gputils-0.13.7/0000777000175000017500000000000011156521352010277 500000000000000gputils-0.13.7/gputils/0000777000175000017500000000000011156521335011767 500000000000000gputils-0.13.7/gputils/gpstrip.c0000644000175000017500000002252711156521262013546 00000000000000/* GNU PIC object symbol strip Copyright (C) 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpstrip.h" struct gpstrip_state state; gp_boolean verbose; void conditional_remove(gp_symbol_type *symbol) { struct symbol *sym; sym = get_symbol(state.symbol_keep, symbol->name); if (sym == NULL) { if (verbose) { gp_message("removing symbol \"%s\"", symbol->name); } gp_coffgen_delsymbol(state.object, symbol); } } void remove_sections(void) { int i; struct symbol *sym; gp_section_type *section; /* FIXME: Check for relocations from other sections. Error out if they exist */ for (i = 0; i < HASH_SIZE; i++) { for (sym = state.section_remove->hash_table[i]; sym; sym = sym->next) { section = gp_coffgen_findsection(state.object, state.object->sections, sym->name); if (section) { if (verbose) { gp_message("removing section \"%s\"", sym->name); } /* remove the sections symbols */ gp_coffgen_delsectionsyms(state.object, section); /* remove the section */ gp_coffgen_delsection(state.object, section); } } } } void remove_symbols(void) { int i; struct symbol *sym; gp_symbol_type *symbol = NULL; for (i = 0; i < HASH_SIZE; i++) { for (sym = state.symbol_remove->hash_table[i]; sym; sym = sym->next) { symbol = gp_coffgen_findsymbol(state.object, sym->name); if (symbol) { if (!gp_coffgen_has_reloc(state.object, symbol)) { conditional_remove(symbol); } } } } } void strip_all(void) { gp_section_type *section = state.object->sections; if (state.object->flags & F_EXEC) { while (section != NULL) { /* remove the line numbers, have too because the symbols will be removed */ section->num_lineno = 0; section->line_numbers = NULL; section->line_numbers_tail = NULL; /* remove the relocations, they should already be removed */ section->num_reloc = 0; section->relocations = NULL; section->relocations_tail = NULL; section = section->next; } /* remove all symbols */ state.object->num_symbols = 0; state.object->symbols = NULL; state.object->symbols_tail = NULL; } else { gp_error("can not strip all symbols because the object file is not executable"); } } void strip_debug(void) { gp_section_type *section = state.object->sections; gp_symbol_type *list = NULL; gp_symbol_type *symbol = NULL; while (section != NULL) { /* remove the line numbers */ section->num_lineno = 0; section->line_numbers = NULL; section->line_numbers_tail = NULL; section = section->next; } list = state.object->symbols; while (list != NULL) { /* remove any debug symbols */ symbol = list; list = list->next; if (symbol->section_number == N_DEBUG) { conditional_remove(symbol); } } } void strip_unneeded(void) { gp_symbol_type *list = NULL; gp_symbol_type *symbol = NULL; list = state.object->symbols; while (list != NULL) { symbol = list; list = list->next; /* if the symbol has a relocation or is global it can't be removed */ if (!gp_coffgen_has_reloc(state.object, symbol) && !gp_coffgen_is_global(symbol)) { conditional_remove(symbol); } } } void discard_all(void) { gp_symbol_type *list = NULL; gp_symbol_type *symbol = NULL; list = state.object->symbols; while (list != NULL) { symbol = list; list = list->next; if (!gp_coffgen_is_global(symbol)) { conditional_remove(symbol); } } } void add_name(struct symbol_table *table, char *name) { struct symbol *sym; sym = get_symbol(table, name); if (sym == NULL) sym = add_symbol(table, name); } void show_usage(void) { printf("Usage: gpstrip [options] file(s)\n"); printf("Options: [defaults in brackets after descriptions]\n"); printf(" -g, --strip-debug Strip debug symbols.\n"); printf(" -h, --help Show this usage message.\n"); printf(" -k SYMBOL, --keep-symbol SYMBOL Keep symbol.\n"); printf(" -n SYMBOL, --strip-symbol SYMBOL Remove symbol.\n"); printf(" -o FILE, --output FILE Alternate name of output file.\n"); printf(" -p, --preserve-dates Preserve dates.\n"); printf(" -r SECTION, --remove-section SECTION Remove section.\n"); printf(" -s, --strip-all Remove all symbols.\n"); printf(" -u, --strip-unneeded Strip symbols not need for relocations.\n"); printf(" -v, --version Show version.\n"); printf(" -V, --verbose Verbose mode.\n"); printf(" -x, --discard-all Remove non-global symbols.\n"); printf("\n"); printf("Report bugs to:\n"); printf("%s\n", PACKAGE_BUGREPORT); exit(0); } #define GET_OPTIONS "?ghk:n:o:pr:suvVx" static struct option longopts[] = { { "strip-debug", 0, 0, 'g' }, { "help", 0, 0, 'h' }, { "keep-symbol", 1, 0, 'k' }, { "strip-symbol", 1, 0, 'n' }, { "output", 1, 0, 'o' }, { "preserve-dates", 0, 0, 'p' }, { "remove-section", 1, 0, 'r' }, { "strip-all", 0, 0, 's' }, { "strip-unneeded", 0, 0, 'u' }, { "version", 0, 0, 'v' }, { "verbose", 0, 0, 'V' }, { "discard-all", 0, 0, 'x' }, { 0, 0, 0, 0 } }; #define GETOPT_FUNC getopt_long(argc, argv, GET_OPTIONS, longopts, 0) int main(int argc, char *argv[]) { extern int optind; int c; int usage = 0; gp_init(); /* initalize */ verbose = false; state.strip_debug = false; state.preserve_dates = false; state.strip_all = false; state.strip_unneeded = false; state.discard_all = false; state.output_file = NULL; state.symbol_keep = push_symbol_table(NULL, false); state.symbol_remove = push_symbol_table(NULL, false); state.section_remove = push_symbol_table(NULL, false); while ((c = GETOPT_FUNC) != EOF) { switch (c) { case '?': case 'h': usage = 1; break; case 'g': state.strip_debug = true; break; case 'k': add_name(state.symbol_keep, optarg); break; case 'n': add_name(state.symbol_remove, optarg); break; case 'o': state.output_file = optarg; break; case 'p': state.preserve_dates = true; break; case 'r': add_name(state.section_remove, optarg); break; case 's': state.strip_all = true; break; case 'u': state.strip_unneeded = true; break; case 'x': state.discard_all = true; break; case 'V': verbose = true; break; case 'v': fprintf(stderr, "%s\n", GPSTRIP_VERSION_STRING); exit(0); } if (usage) break; } if ((optind == argc) || (usage)) { show_usage(); } for ( ; optind < argc; optind++) { state.input_file = argv[optind]; if (gp_identify_coff_file(state.input_file) != object_file_v2 && gp_identify_coff_file(state.input_file) != object_file) { gp_error("\"%s\" is not a valid object file", state.input_file); exit(1); } state.object = gp_read_coff(state.input_file); if (state.object) { remove_sections(); remove_symbols(); if (state.strip_all) { strip_all(); } if (state.strip_debug) { if (state.strip_all) { gp_message("strip debug ignored"); } else { strip_debug(); } } if (state.strip_unneeded) { if (state.strip_all) { gp_message("strip unneeded ignored"); } else { strip_unneeded(); } } if (state.discard_all) { if (state.strip_all) { gp_message("discard all ignored"); } else { discard_all(); } } if (state.output_file) { state.object->filename = state.output_file; } if (!state.preserve_dates) { /* FIXME: need to update the output file dates */ state.object->time = (long)time(NULL); } if (gp_num_errors == 0) { /* no errors have occured so write the file */ if (gp_write_coff(state.object, 0)) gp_error("system error while writing object file"); } else if (state.output_file) { /* a new file is being written, but errors have occurred, delete the file if it exists */ unlink(state.output_file); } /* FIXME: free state.output_file */ } } if (gp_num_errors) return EXIT_FAILURE; else return EXIT_SUCCESS; } gputils-0.13.7/gputils/dump.c0000644000175000017500000003220611156521262013016 00000000000000/* Displays contents of ".COD" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpvc.h" #include "dump.h" #include "block.h" int number_of_source_files = 0; char *substr(char *a, size_t sizeof_a, char *b, size_t n) { strncpy(a, b, sizeof_a); if (n < sizeof_a) a[n] = 0; return a; } /* a little utility routine that's not actually used in the program, but was useful in computing offsets into structures. */ int ptr_offset(char *a, char *b) { return( ( (long int)a) - ((long int)b) ); } /* fget_line - read a line from a file. */ char *fget_line(int line, char *s, int size, FILE *pFile) { static FILE *plastFile=NULL; static int lastline=-1; static long lastPos=-1; if(!pFile) return NULL; /* If we read a line from the same file the last time we were called then see if we can take advantage of the file state: */ if((pFile != plastFile) || /* if the file is the same */ (line < (lastline-1)) || /* and the line is past the previous */ (ftell(pFile) != lastPos) ) { /* and the file hasn't been touched */ plastFile = pFile; lastline = 1; rewind(pFile); lastPos = -1; } while(line >= ++lastline) fgets(s, size, plastFile); fgets(s, size, plastFile); lastPos = ftell(plastFile); return s; } /* */ void dump_hex(char *chunk, int length) { int i,j,all_zero_line; printf("\n"); i = 0; do { for(j=0, all_zero_line=1; j<16; j++) if(chunk[i+j]) all_zero_line = 0; if(all_zero_line) i+=16; else { printf("\n%04x: ",i); for(j=0; j<16; j++) printf("%02x ",(unsigned char)chunk[i+j]); printf(" "); for(j=0; j<16; j++) if(isprint(chunk[i+j])) putchar(chunk[i+j]); else putchar('.'); i+=16; } }while (idir.block[COD_DIR_HIGHADDR]) << 16; start_block = gp_getu16(&dbi->dir.block[COD_DIR_MEMMAP]); if(start_block) { end_block = gp_getu16(&dbi->dir.block[COD_DIR_MEMMAP+2]); if(first) { printf("\n\nROM Usage\n"); printf("--------------------------------\n"); first = 0; } for(j=start_block; j<=end_block; j++) { read_block(temp, j); for(i=0; i< 128; i++) { unsigned short start; unsigned short last; start = gp_getl16(&temp[i*COD_MAPENTRY_SIZE + COD_MAPTAB_START]); last = gp_getl16(&temp[i*COD_MAPENTRY_SIZE + COD_MAPTAB_LAST]); if( !((start == 0) && (last == 0) )) printf("using ROM 0x%06x to 0x%06x\n", (_64k_base+start) >> shift, (_64k_base+last) >> shift); } } } else if(first) printf(" No ROM usage information available.\n"); dbi = dbi->next_dir_block_info; } while(dbi); } /*---------------------------------------------*/ /* * Dump all of the machine code in the .cod file */ void dump_code(void) { unsigned short _64k_base; unsigned short i,j,k,all_zero_line,index; DirBlockInfo *dbi; dump_memmap(); printf("\n\nFormatted Code Dump\n"); printf("-------------------\n"); dbi = &main_dir; do { _64k_base = gp_getu16(&dbi->dir.block[COD_DIR_HIGHADDR]) << 15; for (k = 0; k <= 127; k++) { index = gp_getu16(&dbi->dir.block[2*(COD_DIR_CODE + k)]); if (index != 0) { read_block(temp, index); printf("\n"); i = 0; do { for(j=0, all_zero_line=1; j<8; j++) if( gp_getu16(&temp[(i+j)*2]) ) all_zero_line = 0; if(all_zero_line) i+=8; else { printf("\n%06x: ", (_64k_base+i+k*256) << byte_addr); for(j=0; j<8; j++) printf("%04x ",gp_getu16(&temp[2*i++])); } }while (inext_dir_block_info; } while(dbi); } /*---------------------------------------------*/ /* * Dump all of the (short) Symbol Table stuff in the .cod file */ void dump_symbols( void ) { #define SSYMBOL_SIZE 16 #define SYMBOLS_PER_BLOCK COD_BLOCK_SIZE/SSYMBOL_SIZE #define SR_LEN 0 #define SR_NAME 1 #define SR_TYPE 13 #define SR_VALUE 14 unsigned short i,j,start_block,end_block; char b[16]; start_block = gp_getu16(&directory_block_data[COD_DIR_SYMTAB]); if(start_block) { end_block = gp_getu16(&directory_block_data[COD_DIR_SYMTAB+2]); printf("\nSymbol Table Information\n"); printf("------------------------\n\n"); for(j=start_block; j<=end_block; j++) { read_block(temp, j); for(i=0; i128) type = 0; /* read big endian */ value = gp_getb32(&s[length+3]); printf("%s = %x, type = %s\n", substr(b, sizeof(b), &s[1],length), value, SymbolType4[type]); i += (length + 7); } } }else printf("No long symbol table info\n"); } /*---------------------------------------------*/ /* * Source files */ void dump_source_files( void ) { #define FILE_SIZE 64 #define FILES_PER_BLOCK COD_BLOCK_SIZE/FILE_SIZE unsigned short i,j,start_block,end_block,offset; char b[FILE_SIZE]; start_block = gp_getu16(&directory_block_data[COD_DIR_NAMTAB]); if(start_block) { end_block = gp_getu16(&directory_block_data[COD_DIR_NAMTAB+2]); printf("\nSource File Information\n"); printf("------------------------\n\n"); for(j=start_block; j<=end_block; j++) { read_block(temp, j); for(i=0; i= MAX_SOURCE_FILES) { fprintf(stderr, " too many source files; increase MAX_SOURCE_FILES and recompile\n"); exit(1); } } } } }else printf("No source file info\n"); } char * smod_flags(int smod) { static char f[9]; f[0] = (smod & 0x80) ? 'C':'.'; f[1] = (smod & 0x40) ? 'F':'.'; f[2] = (smod & 0x20) ? 'I':'.'; f[3] = (smod & 0x10) ? 'D':'.'; f[4] = (smod & 0x08) ? 'C':'.'; f[5] = (smod & 0x04) ? 'L':'.'; f[6] = (smod & 0x02) ? 'N':'.'; f[7] = (smod & 0x01) ? 'A':'.'; f[8] = 0; return(f); } /*---------------------------------------------*/ /* * Line number info from the source files */ void dump_line_symbols(void) { static int lst_line_number = 1; static int last_src_line = 0; char buf[2048]; unsigned short i,j,start_block,end_block; LineSymbol *ls; start_block = gp_getu16(&directory_block_data[COD_DIR_LSTTAB]); if(start_block) { end_block = gp_getu16(&directory_block_data[COD_DIR_LSTTAB+2]); printf("\n\nLine Number Information\n"); printf(" LstLn SrcLn Addr Flags FileName\n"); printf(" ----- ----- ---- ----------- ---------------------------------------\n"); for(j=start_block; j<=end_block; j++) { unsigned short sline; unsigned short sloc; read_block(temp, j); ls = (LineSymbol *) temp; for(i=0; i<84; i++) { sline = gp_getl16((char *)&ls[i].sline); sloc = gp_getl16((char *)&ls[i].sloc); if((ls[i].smod & 4) == 0) { assert(ls[i].sfile < number_of_source_files); printf(" %5d %5d %06X %2x %s %-50s\n", lst_line_number++, sline, sloc, ls[i].smod, smod_flags(ls[i].smod), source_file_names[ls[i].sfile]); } if(source_files[ls[i].sfile] && (sline != last_src_line)) { /*fgets(buf, sizeof(buf), source_files[ls[i].sfile]);*/ fget_line(sline, buf, sizeof(buf), source_files[ls[i].sfile]); printf("%s",buf); } last_src_line = sline; } } } else printf("No line number info\n"); } /*---------------------------------------------*/ /* * Debug Message area */ void dump_message_area(void) { #define MAX_STRING_LEN 255 /* Maximum length of a debug message */ char DebugType,DebugMessage[MAX_STRING_LEN]; unsigned short i,j,start_block,end_block, len; unsigned short laddress; start_block = gp_getu16(&directory_block_data[COD_DIR_MESSTAB]); if(start_block) { end_block = gp_getu16(&directory_block_data[COD_DIR_MESSTAB+2]); printf("\n\nDebug Message area\n"); printf(" Addr Cmd Message\n"); printf(" -------- --- -------------------------------------\n"); for(i=start_block; i<=end_block; i++) { read_block(temp, i); j = 0; while (j < 504) { /* read big endian */ laddress = gp_getb32(&temp[j]); j += 4; DebugType = temp[j++]; if (DebugType == 0) { break; } len = temp[j++]; substr(DebugMessage, sizeof(DebugMessage), &temp[j], MAX_STRING_LEN); j += strlen(DebugMessage); printf(" %8x %c %s\n",laddress, DebugType, DebugMessage); } } } else printf(" No Debug Message information available.\n"); } /*---------------------------------------------*/ /* * Display the local symbol table information */ void dump_local_vars(void) { #define SSYMBOL_SIZE 16 #define SYMBOLS_PER_BLOCK COD_BLOCK_SIZE/SSYMBOL_SIZE #if 0 typedef struct symbol_record { char name_strlen; char name[12]; /* Not Symbol Length because */ unsigned char stype; /* this record is 16 bytes */ unsigned short svalue; } symbol_record; typedef struct scope_head { char name_strlen; char name[7]; unsigned int start; unsigned int stop; } scope_head; #endif #define COD_SSYMBOL_NAME 1 #define COD_SSYMBOL_STYPE 13 #define COD_SSYMBOL_SVALUE 14 #define COD_SSYMBOL_START 8 #define COD_SSYMBOL_STOP 12 /* scope_head */ char *sh; unsigned short i,j,start_block,end_block; unsigned char shift; if (byte_addr) shift = 0; else shift = 1; start_block = gp_getu16(&directory_block_data[COD_DIR_LOCALVAR]); if(start_block) { end_block = gp_getu16(&directory_block_data[COD_DIR_LOCALVAR+2]); printf("\n\nLocal Symbol Scoping Information\n"); printf("--------------------------------\n"); for(i=start_block; i<=end_block; i++) { read_block(temp, i); for(j=0; j> shift, stop >> shift); } else { printf("%.12s = 0x%x, type = %s\n", &sh[COD_SSYMBOL_NAME], gp_getl16(&sh[COD_SSYMBOL_SVALUE]), SymbolType4[(int)sh[COD_SSYMBOL_STYPE]]); } } } } }else printf(" No local variable scoping info available.\n"); } gputils-0.13.7/gputils/gpvc.c0000644000175000017500000001616711156313067013022 00000000000000/* Displays contents of ".COD" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpvc.h" #include "dump.h" #include "block.h" FILE *codefile; char filename[BUFFER_LENGTH]; char temp[COD_BLOCK_SIZE]; char *source_file_names[MAX_SOURCE_FILES]; FILE *source_files[MAX_SOURCE_FILES]; DirBlockInfo main_dir; int byte_addr; char directory_block_data[COD_BLOCK_SIZE]; char * SymbolType4[154] = { "a_reg ", "x_reg ", "c_short ", "c_long ", "c_ushort ", "c_ulong ", "c_pointer ", "c_upointer ", "table ", "m_byte ", "m_boolean ", "m_index ", "byte_array ", "u_byte_array ", "word_array ", "u_word_array ", "func_void_none ", "func_void_byte ", "funcVoidTwobyte", "func_void_long ", "func_void_undef", "func_int_none ", "func_int_byte ", "func_int_twobyt", "func_int_long ", "func_int_undef ", "func_long_none ", "func_long_byte ", "funcLongTwobyte", "func_long_long ", "func_long_undef", "pfun_void_none ", "pfun_void_byte ", "pfunVoidTwobyte", "pfun_void_long ", "pfun_void_undef", "pfun_int_none ", "pfun_int_byte ", "pfunIntTwobyte ", "pfun_int_long ", "pfun_int_undef ", "pfun_long_none ", "pfun_long_byte ", "pfun_long_twoby", "pfun_long_long ", "pfun_long_undef", "address ", "constant ", "bad_und ", "br_und ", "upper_und ", "byte_und ", "add_und ", "m_keyword ", "add_mi_und ", "vector ", "port_w ", "port_r ", "port_rw ", "port_rmw ", "endif ", "exundef ", "macro_t ", "macro_s ", "macro_a ", "macro_c ", "c_keyword ", "void ", "c_enum ", "c_typedef1 ", "c_utypedef1 ", "c_typedef2 ", "c_utypedef2 ", "cp_typedef1 ", "cp_utypedef1 ", "cp_typedef2 ", "cp_utypedef2 ", "c_struct ", "i_struct ", "l_const ", "s_short ", "s_ushort ", "s_long ", "s_ulong ", "sa_short ", "sa_ushort ", "sa_long ", "sa_ulong ", "sp_short ", "sp_ushort ", "sp_long ", "sp_ulong ", "FixedPointer ", "PointerFunction", "cc_reg ", "PtrF_void_none ", "PtrF_void_byte ", "PtrF_void_twobyt", "PtrF_void_long ", "PtrF_void_undef", "PtrF_int_none ", "PtrF_int_byte ", "PtrF_int_twobyte", "PtrF_int_long ", "PtrF_int_undef ", "PtrF_long_none ", "PtrF_long_byte ", "PtrF_long_twobyte", "PtrF_long_long ", "PtrF_long_undef", "PfAR_void_none ", "PfAR_void_byte ", "PfAR_void_twobyte", "PfAR_void_long ", "PfAR_void_undef", "PfAR_int_none ", "PfAR_int_byte ", "PfAR_int_twobyte", "PfAR_int_long ", "PfAR_int_undef ", "PfAR_long_none ", "PfAR_long_byte ", "PfAR_long_twobyte", "PfAR_long_long ", "PfAR_long_undef", "FWDlit ", "Pfunc ", "mgoto ", "mcgoto ", "mcgoto2 ", "mcgoto3 ", "mcgoto4 ", "mcgoto74 ", "mcgoto17 ", "mccall17 ", "mcall ", "mc_call ", "res_word ", "local ", "unknown ", "varlabel ", "external ", "global ", "segment ", "Bankaddr ", "bit_0 ", "bit_1 ", "bit_2 ", "bit_3 ", "bit_4 ", "bit_5 ", "bit_6 ", "bit_7 ", "debug " }; void show_usage(void) { printf("Usage: gpvc [options] file\n"); printf("Options: [defaults in brackets after descriptions]\n"); printf(" -a, --all Display all information in .cod file.\n"); printf(" -d, --directory Display directory header.\n"); printf(" -l, --listing Display source listing.\n"); printf(" -m, --message Display debug message area.\n"); printf(" -h, --help Show this usage message.\n"); printf(" -r, --rom Display rom.\n"); printf(" -s, --symbols Display symbols.\n"); printf(" -v, --version Show version.\n"); printf("\n"); printf("Report bugs to:\n"); printf("%s\n", PACKAGE_BUGREPORT); exit(0); } #define GET_OPTIONS "?adhlmrsv" /* Used: adhlmrsv */ static struct option longopts[] = { { "all", 0, 0, 'a' }, { "directory", 0, 0, 'd' }, { "help", 0, 0, 'h' }, { "listing", 0, 0, 'l' }, { "message", 0, 0, 'm' }, { "rom", 0, 0, 'r' }, { "symbols", 0, 0, 's' }, { "version", 0, 0, 'v' }, { 0, 0, 0, 0 } }; #define GETOPT_FUNC getopt_long(argc, argv, GET_OPTIONS, longopts, 0) int main(int argc, char *argv[]) { extern int optind; unsigned int buffer_size; int c,usage=0; int display_flags; Directory *dir; gp_init(); byte_addr = 0; #define DISPLAY_NOTHING 0 #define DISPLAY_DIR 1 #define DISPLAY_SYM 2 #define DISPLAY_ROM 4 #define DISPLAY_SRC 8 #define DISPLAY_MESS 16 #define DISPLAY_ALL 0xff display_flags = DISPLAY_NOTHING; while ((c = GETOPT_FUNC) != EOF) { switch (c) { case '?': case 'h': usage = 1; break; case 'a': display_flags = DISPLAY_ALL; break; case 'd': display_flags |= DISPLAY_DIR; break; case 's': display_flags |= DISPLAY_SYM; break; case 'r': display_flags |= DISPLAY_ROM; break; case 'l': display_flags |= DISPLAY_SRC; break; case 'm': display_flags |= DISPLAY_MESS; break; case 'v': fprintf(stderr, "%s\n", GPVC_VERSION_STRING); exit(0); } if (usage) break; } if ((optind + 1) == argc) strncpy(filename, argv[optind], sizeof(filename)); else usage = 1; if(display_flags == DISPLAY_NOTHING) display_flags = DISPLAY_ALL; if (usage) { show_usage(); } codefile = fopen(filename,"rb"); if(codefile == NULL) { perror(filename); exit(1); } /* Start off by reading the directory block */ read_directory(); fseek(codefile, 0,SEEK_SET); buffer_size = fread(directory_block_data, 1, COD_BLOCK_SIZE, codefile); if(display_flags & DISPLAY_DIR) directory_block(); dir = (Directory *)directory_block_data; if(display_flags & DISPLAY_ROM) dump_code(); if(display_flags & DISPLAY_SYM) { dump_symbols(); dump_lsymbols(); dump_local_vars(); } dump_source_files(); if(display_flags & DISPLAY_SRC) dump_line_symbols(); if(display_flags & DISPLAY_MESS) dump_message_area(); return EXIT_SUCCESS; } gputils-0.13.7/gputils/gpvo.c0000644000175000017500000003644411156521262013034 00000000000000/* GNU PIC view object Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpvo.h" struct gpvo_state state; void print_header(gp_object_type *object) { char *time = ctime(&object->time); char *processor_name = gp_processor_name(object->processor, 2); /* strip the newline from time */ time[strlen(time)-1] = '\0'; printf("COFF File and Optional Headers\n"); printf("Processor Type %s\n", processor_name); printf("Time Stamp %s\n", time); printf("Number of Sections %li\n", object->num_sections); printf("Number of Symbols %li\n", object->num_symbols); printf("Characteristics %#x\n", object->flags); if (object->flags & F_RELFLG) { printf(" Relocation info has been stripped.\n"); } if (object->flags & F_EXEC) { printf(" File is executable.\n"); } if (object->flags & F_LNNO) { printf(" Line numbers have been stripped.\n"); } if (object->flags & L_SYMS) { printf(" Local symbols have been stripped.\n"); } if (object->flags & F_GENERIC) { printf(" Processor independent file for a core.\n"); } printf("\n"); return; } void print_reloc_list(enum proc_class class, gp_reloc_type *relocation) { int word_addr = 1; printf("Relocations Table\n"); printf("Address Offset Type Symbol\n"); if (class == PROC_CLASS_PIC16E) { word_addr = 0; } while (relocation != NULL) { printf("%#-10lx %#-10x %#-6x %-s\n", relocation->address >> word_addr, relocation->offset, relocation->type, relocation->symbol->name); relocation = relocation->next; } printf("\n"); } void print_linenum_list(gp_linenum_type *linenumber) { char *filename; printf("Line Number Table\n"); printf("Line Address Symbol\n"); while (linenumber != NULL) { if (state.suppress_names) { filename = linenumber->symbol->name; } else { filename = linenumber->symbol->aux_list->_aux_symbol._aux_file.filename; } printf("%-8i %#-8lx %s\n", linenumber->line_number, linenumber->address, filename); linenumber = linenumber->next; } printf("\n"); } void print_data(enum proc_class class, gp_section_type *section) { int memory; char buffer[BUFSIZ]; int byte_addr = 0; int org; int num_words = 1; if ((class == PROC_CLASS_PIC16E) && !(section->flags & STYP_DATA)) { org = section->address >> 1; byte_addr = 1; } else { org = section->address; } buffer[0] = '\0'; printf("Data\n"); while (1) { memory = i_memory_get(section->data, org); if ((memory & MEM_USED_MASK) == 0) break; if (section->flags & STYP_TEXT) { num_words = gp_disassemble(section->data, org, class, buffer, sizeof(buffer)); printf("%06x: %04x %s\n", org << byte_addr, memory & 0xffff, buffer); if (num_words != 1) { memory = i_memory_get(section->data, org + 1); assert(memory & MEM_USED_MASK); printf("%06x: %04x\n", (org + 1) << byte_addr, memory & 0xffff); } } else if (section->flags & STYP_DATA_ROM) { printf("%06x: %04x\n", org << byte_addr, memory & 0xffff); } else if (section->flags & STYP_DATA) { printf("%06x: %02x\n", org, memory & 0xff); } org += num_words; } printf("\n"); } void print_sec_header(gp_section_type *section) { printf("Section Header\n"); printf("Name %s\n", section->name); printf("Address %#lx\n", section->address); printf("Size of Section %li\n", section->size); printf("Number of Relocations %i\n", section->num_reloc); printf("Number of Line Numbers %i\n", section->num_lineno); printf("Flags %#lx\n", section->flags); if (section->flags & STYP_TEXT) { printf(" Executable code.\n"); } if (section->flags & STYP_DATA) { printf(" Initialized data.\n"); } if (section->flags & STYP_BSS) { printf(" Uninitialized data.\n"); } if (section->flags & STYP_DATA_ROM) { printf(" Initialized data for ROM.\n"); } if (section->flags & STYP_ABS) { printf(" Absolute.\n"); } if (section->flags & STYP_SHARED) { printf(" Shared across banks.\n"); } if (section->flags & STYP_OVERLAY) { printf(" Overlaid with other sections from different objects modules.\n"); } if (section->flags & STYP_ACCESS) { printf(" Available using access bit.\n"); } if (section->flags & STYP_ACTREC) { printf(" Contains the activation record for a function.\n"); } printf("\n"); } void print_sec_list(gp_object_type *object) { gp_section_type *section = object->sections; while (section != NULL) { print_sec_header(section); if (section->size) { print_data(object->class, section); } if (section->num_reloc) { print_reloc_list(object->class, section->relocations); } if (section->num_lineno) { print_linenum_list(section->line_numbers); } section = section->next; } } void coff_type(int type, char *buffer, size_t sizeof_buffer) { switch (type) { case T_NULL: /* null */ snprintf(buffer, sizeof_buffer, "NULL"); break; case T_VOID: /* void */ snprintf(buffer, sizeof_buffer, "void"); break; case T_CHAR: /* character */ snprintf(buffer, sizeof_buffer, "char"); break; case T_SHORT: /* short integer */ snprintf(buffer, sizeof_buffer, "short"); break; case T_INT: /* integer */ snprintf(buffer, sizeof_buffer, "int"); break; case T_LONG: /* long integer */ snprintf(buffer, sizeof_buffer, "long int"); break; case T_FLOAT: /* floating point */ snprintf(buffer, sizeof_buffer, "float"); break; case T_DOUBLE: /* double length floating point */ snprintf(buffer, sizeof_buffer, "double"); break; case T_STRUCT: /* structure */ snprintf(buffer, sizeof_buffer, "struct"); break; case T_UNION: /* union */ snprintf(buffer, sizeof_buffer, "union"); break; case T_ENUM: /* enumeration */ snprintf(buffer, sizeof_buffer, "enum"); break; case T_MOE: /* member of enumeration */ snprintf(buffer, sizeof_buffer, "enum"); break; case T_UCHAR: /* unsigned character */ snprintf(buffer, sizeof_buffer, "unsigned char"); break; case T_USHORT: /* unsigned short */ snprintf(buffer, sizeof_buffer, "unsigned short"); break; case T_UINT: /* unsigned integer */ snprintf(buffer, sizeof_buffer, "unsigned int"); break; case T_ULONG: /* unsigned long */ snprintf(buffer, sizeof_buffer, "unsigned long"); break; case T_LNGDBL: /* long double floating point */ snprintf(buffer, sizeof_buffer, "long double"); break; case T_SLONG: /* short long */ snprintf(buffer, sizeof_buffer, "short long"); break; case T_USLONG: /* unsigned short long */ snprintf(buffer, sizeof_buffer, "unsigned short long"); break; default: snprintf(buffer, sizeof_buffer, "unknown"); break; } } void print_sym_table (gp_object_type *object) { gp_symbol_type *symbol; gp_aux_type *aux; char *section; int i; char c; symbol = object->symbols; printf("Symbol Table\n"); printf("Name Section Value Type Class NumAux \n"); while (symbol != NULL) { if (symbol->section_number == N_DEBUG) { section = "DEBUG"; } else if (symbol->section_number == N_ABS) { section = "ABSOLUTE"; } else if (symbol->section_number == N_UNDEF) { section = "UNDEFINED"; } else { assert(symbol->section != NULL); section = symbol->section->name; } printf("%-24s %-16s %#-10lx %-4li %-4i %-4i\n", symbol->name, section, symbol->value, symbol->type, symbol->class, symbol->num_auxsym); if (symbol->num_auxsym != 0) { aux = symbol->aux_list; switch (aux->type) { case AUX_DIRECT: printf(" command = \"%c\"\n", aux->_aux_symbol._aux_direct.command); printf(" string = \"%s\"\n", aux->_aux_symbol._aux_direct.string); break; case AUX_FILE: if (!state.suppress_names) { printf(" file = %s\n", aux->_aux_symbol._aux_file.filename); } printf(" line included = %li\n", aux->_aux_symbol._aux_file.line_number); break; case AUX_IDENT: printf(" string = \"%s\"\n", aux->_aux_symbol._aux_ident.string); break; case AUX_SCN: printf(" length = %li\n", aux->_aux_symbol._aux_scn.length); printf(" number of relocations = %i\n", aux->_aux_symbol._aux_scn.nreloc); printf(" number of line numbers = %i\n", aux->_aux_symbol._aux_scn.nlineno); break; default: printf("%ld ", aux->type); for (i = 0; i < object->symbol_size; i++) { printf("%02x", aux->_aux_symbol.data[i]); if (i & 1) { printf(" "); } } for (i = 0; i < object->symbol_size; i++) { c = aux->_aux_symbol.data[i]; putchar( (isprint(c)) ? c : '.'); } } } symbol = symbol->next; } printf("\n"); return; } void export_sym_table(gp_object_type *object) { gp_symbol_type *symbol; char buffer[BUFSIZ]; symbol = object->symbols; while (symbol != NULL) { if ((state.export.enabled) && (symbol->class == C_EXT) && (symbol->section_number > 0)) { coff_type(symbol->type, buffer, sizeof(buffer)); fprintf(state.export.f, " extern %s ; %s\n", symbol->name, buffer); } symbol = symbol->next; } } void print_binary(char *data, long int file_size) { long int i, j; int memory; char c; printf("\nObject file size = %li bytes\n", file_size); printf("\nBinary object file contents:"); for (i = 0; i < file_size; i += 16) { printf("\n%06lx", i); for(j = 0; j < 16; j += 2) { memory = data[i + j]; memory = ((memory << 8) & 0xff00) | (data[i+j+1] & 0xff); if ((i+j) >= file_size) { printf(" "); } else { printf(" %04x", memory); } } printf(" "); for(j = 0; j < 16; j += 2) { if ((i+j) < file_size) { c = data[i + j] & 0xff; putchar( (isprint(c)) ? c : '.'); c = data[i + j + 1] & 0xff; putchar( (isprint(c)) ? c : '.'); } } } printf("\n\n"); return; } void show_usage(void) { printf("Usage: gpvo [options] file\n"); printf("Options: [defaults in brackets after descriptions]\n"); printf(" -b, --binary Print binary data.\n"); printf(" -c, --mnemonics Decode special mnemonics.\n"); printf(" -f, --file File header.\n"); printf(" -h, --help Show this usage message.\n"); printf(" -n, --no-names Suppress filenames.\n"); printf(" -s, --section Section data.\n"); printf(" -t --symbol Symbol table.\n"); printf(" -v, --version Show version.\n"); printf(" -x FILE, --export FILE Export symbols to include file.\n"); printf(" -y, --extended Enable 18xx extended mode.\n"); printf("\n"); printf("Report bugs to:\n"); printf("%s\n", PACKAGE_BUGREPORT); exit(0); } #define GET_OPTIONS "?bcfhnstvx:y" /* Used: himpsv */ static struct option longopts[] = { { "binary", 0, 0, 'b' }, { "mnemonics", 0, 0, 'c' }, { "file", 0, 0, 'f' }, { "help", 0, 0, 'h' }, { "no-names", 0, 0, 'n' }, { "section", 0, 0, 's' }, { "symbol", 0, 0, 't' }, { "version", 0, 0, 'v' }, { "export", 1, 0, 'x' }, { "extended", 0, 0, 'y' }, { 0, 0, 0, 0 } }; #define GETOPT_FUNC getopt_long(argc, argv, GET_OPTIONS, longopts, 0) int main(int argc, char *argv[]) { extern int optind; int c; int usage = 0; char buffer[BUFSIZ]; gp_init(); /* initalize */ state.dump_flags = 0; state.suppress_names = false; state.export.enabled = false; while ((c = GETOPT_FUNC) != EOF) { switch (c) { case '?': case 'h': usage = 1; break; case 'b': state.dump_flags |= PRINT_BINARY; break; case 'c': gp_decode_mnemonics = true; break; case 'f': state.dump_flags |= PRINT_HEADER; break; case 'n': state.suppress_names = true; break; case 's': state.dump_flags |= PRINT_SECTIONS; break; case 't': state.dump_flags |= PRINT_SYMTBL; break; case 'y': gp_decode_extended = true; break; case 'x': state.export.enabled = true; state.export.filename = optarg; break; case 'v': fprintf(stderr, "%s\n", GPVO_VERSION_STRING); exit(0); } if (usage) break; } if ((optind + 1) == argc) { state.filename = argv[optind]; } else { usage = 1; } if (usage) { show_usage(); } if (!state.dump_flags) { /* no command line flags were set so print everything */ state.dump_flags = PRINT_HEADER | PRINT_SECTIONS | PRINT_SYMTBL; } if (gp_identify_coff_file(state.filename) != object_file_v2 && gp_identify_coff_file(state.filename) != object_file) { gp_error("\"%s\" is not a valid object file", state.filename); exit(1); } state.object = gp_read_coff(state.filename); state.file = gp_read_file(state.filename); if (state.export.enabled) { state.export.f = fopen(state.export.filename, "w"); if (state.export.f == NULL) { perror(state.export.filename); exit(1); } gp_date_string(buffer, sizeof(buffer)); fprintf(state.export.f, "; %s\n", state.export.filename); fprintf(state.export.f, "; generated by %s on %s\n", GPVO_VERSION_STRING, buffer); fprintf(state.export.f, "; from %s\n\n", state.filename); export_sym_table(state.object); fclose(state.export.f); /* suppress normal output */ state.dump_flags = 0; } if (state.dump_flags & PRINT_HEADER) { print_header(state.object); } if (state.dump_flags & PRINT_SECTIONS) { print_sec_list(state.object); } if (state.dump_flags & PRINT_SYMTBL) { print_sym_table(state.object); } if (state.dump_flags & PRINT_BINARY) { print_binary(state.file->file, state.file->size); } return EXIT_SUCCESS; } gputils-0.13.7/gputils/gpvc.h0000644000175000017500000000243611156521262013017 00000000000000/* Displays contents of ".COD" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPVC_H__ #define __GPVC_H__ #include "gpcod.h" #define GPVC_VERSION_STRING ("gpvc-" VERSION " beta") #define BUFFER_LENGTH 256 #define MAX_SOURCE_FILES 100 extern FILE *codefile; extern char filename[BUFFER_LENGTH]; extern char temp[COD_BLOCK_SIZE]; extern char *source_file_names[MAX_SOURCE_FILES]; extern FILE *source_files[MAX_SOURCE_FILES]; extern DirBlockInfo main_dir; extern int byte_addr; extern char directory_block_data[COD_BLOCK_SIZE]; extern char * SymbolType4[154]; #endif gputils-0.13.7/gputils/block.h0000644000175000017500000000172211156313067013151 00000000000000/* Displays contents of ".COD" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __BLOCK_H__ #define __BLOCK_H__ #include "stdhdr.h" void directory_block(void); void read_block(char * block, int block_number); void read_directory(void); #endif gputils-0.13.7/gputils/gplib.h0000644000175000017500000000256211156521262013155 00000000000000/* gplib - GNU PIC librarian Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef GPLIB_H #define GPLIB_H enum lib_modes { ar_create, ar_delete, ar_extract, ar_list, ar_replace, ar_symbols, ar_null }; #define GPLIB_VERSION_STRING ("gplib-" VERSION " beta") #define MAX_OBJ_NAMES 256 extern struct gplib_state { enum lib_modes mode; /* operating mode */ int numobjects; /* number of objects in the list */ char *filename; /* library file name */ char *objectname[MAX_OBJ_NAMES]; /* the list of object filenames */ gp_archive_type *archive; /* internal archive format */ } state; #endif gputils-0.13.7/gputils/gpdasm.h0000644000175000017500000000312511156521262013327 00000000000000/* Disassembles ".HEX" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPDASM_H__ #define __GPDASM_H__ #define GPDASM_VERSION_STRING ("gpdasm-" VERSION " beta") extern struct gpdasm_state { pic_processor_t processor; /* selected processor */ enum proc_class class; /* processor class */ int format; /* format of the output */ int pass; /* 1 or 2 */ MemBlock *i_memory; /* Instruction memory linked list */ char *srcfilename, /* Source (.asm) file name */ basefilename[BUFSIZ], /* basename for generating hex,list,symbol filenames */ hexfilename[BUFSIZ]; /* Hex (.hex) file name */ struct hex_data *hex_info; /* information on input hex file */ struct { /* Totals for errors, warnings, messages */ int errors; int warnings; int messages; } num; } state; #endif gputils-0.13.7/gputils/gplib.c0000644000175000017500000002046111156521262013146 00000000000000/* GNU PIC Librarian Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gplib.h" struct gplib_state state = { ar_null, /* default mode, do nothing */ 0, /* number of objects */ }; struct symbol_table *definition_tbl = NULL; struct symbol_table *symbol_index = NULL; void select_mode(enum lib_modes mode) { if (state.mode == ar_null) { state.mode = mode; } else { gp_error("multiple library operations selected"); } } /* return the object name without the path */ static char * object_name(char *file_name) { char *name; #ifdef HAVE_DOS_BASED_FILE_SYSTEM for (name = file_name + strlen(file_name) - 1; name >= file_name; --name) { if (*name == UNIX_PATH_CHAR || *name == PATH_CHAR) { return ++name; } } return file_name; #else name = strrchr(file_name, PATH_CHAR); if (name) { return ++name; } else { return file_name; } #endif } static gp_boolean has_path(char *file_name) { char *name; name = strrchr(file_name, PATH_CHAR); #ifdef HAVE_DOS_BASED_FILE_SYSTEM if (!name) name = strrchr(file_name, UNIX_PATH_CHAR); #endif if (name) { return true; } else { return false; } } void show_usage(void) { printf("Usage: gplib [options] library [member]\n"); printf("Options: [defaults in brackets after descriptions]\n"); printf(" -c, --create Create a new library.\n"); printf(" -d, --delete Delete member from library.\n"); printf(" -h, --help Show this usage message.\n"); printf(" -n, --no-index Don't add symbol index.\n"); printf(" -q, --quiet Quiet mode.\n"); printf(" -r, --replace Add or replace member from library.\n"); printf(" -s, --symbols List global symbols in library.\n"); printf(" -t, --list List members in library.\n"); printf(" -v, --version Show version.\n"); printf(" -x, --extract Extract member from library.\n"); printf("\n"); printf("Report bugs to:\n"); printf("%s\n", PACKAGE_BUGREPORT); exit(0); } #define GET_OPTIONS "?cdhnqrstvx" static struct option longopts[] = { { "create", 0, 0, 'c' }, { "delete", 0, 0, 'd' }, { "extract", 0, 0, 'x' }, { "help", 0, 0, 'h' }, { "no-index", 0, 0, 'n' }, { "quiet", 0, 0, 'q' }, { "replace", 0, 0, 'r' }, { "symbols", 0, 0, 's' }, { "list", 0, 0, 't' }, { "version", 0, 0, 'v' }, { 0, 0, 0, 0 } }; #define GETOPT_FUNC getopt_long(argc, argv, GET_OPTIONS, longopts, 0) int main(int argc, char *argv[]) { extern int optind; int i = 0; int c; gp_boolean usage = false; gp_boolean update_archive = false; gp_boolean no_index = false; gp_archive_type *object = NULL; gp_init(); /* symbols are case sensitive */ definition_tbl = push_symbol_table(NULL, false); symbol_index = push_symbol_table(NULL, false); while ((c = GETOPT_FUNC) != EOF) { switch (c) { case '?': case 'h': usage = true; break; case 'c': select_mode(ar_create); break; case 'd': select_mode(ar_delete); break; case 'n': no_index = true; break; case 'q': gp_quiet = true; break; case 'r': select_mode(ar_replace); break; case 's': select_mode(ar_symbols); break; case 't': select_mode(ar_list); break; case 'v': fprintf(stderr, "%s\n", GPLIB_VERSION_STRING); exit(0); break; case 'x': select_mode(ar_extract); break; } if (usage) break; } if (optind < argc) { /* fetch the library name */ state.filename = argv[optind++]; /* some operations require object filenames or membernames */ for ( ; optind < argc; optind++) { state.objectname[state.numobjects] = argv[optind]; if (state.numobjects >= MAX_OBJ_NAMES) { gp_error("exceeded maximum number of object files"); break; } state.numobjects++; } } else { usage = true; } /* User did not select an operation */ if (state.mode == ar_null) { usage = true; } /* User did not provide object names */ if ((state.mode != ar_list) && (state.mode != ar_symbols) && (state.numobjects == 0)) { usage = true; } if (usage) { show_usage(); } /* if we are not creating a new archive, we have to read an existing one */ if (state.mode != ar_create) { if (gp_identify_coff_file(state.filename) != archive_file) { gp_error("\"%s\" is not a valid archive file", state.filename); exit(1); } else { state.archive = gp_archive_read(state.filename); } } /* process the option */ i = 0; switch (state.mode) { case ar_create: case ar_replace: while (i < state.numobjects) { if (gp_identify_coff_file(state.objectname[i]) != object_file_v2 && gp_identify_coff_file(state.objectname[i]) != object_file) { gp_error("\"%s\" is not a valid object file", state.objectname[i]); break; } else { state.archive = gp_archive_add_member(state.archive, state.objectname[i], object_name(state.objectname[i])); } i++; } update_archive = true; break; case ar_delete: while (i < state.numobjects) { if (has_path(state.objectname[i])) { gp_error("invalid object name \"%s\"", state.objectname[i]); break; } object = gp_archive_find_member(state.archive, state.objectname[i]); if (object == NULL) { gp_error("object \"%s\" not found", state.objectname[i]); break; } else { state.archive = gp_archive_delete_member(state.archive, state.objectname[i]); } i++; } update_archive = true; break; case ar_extract: while (i < state.numobjects) { if (has_path(state.objectname[i])) { gp_error("invalid object name \"%s\"", state.objectname[i]); break; } object = gp_archive_find_member(state.archive, state.objectname[i]); if (object == NULL) { gp_error("object \"%s\" not found", state.objectname[i]); break; } else { if (gp_archive_extract_member(state.archive, state.objectname[i])) { gp_error("can't write file \"%s\"", state.objectname[i]); break; } } i++; } break; case ar_list: gp_archive_list_members(state.archive); break; case ar_symbols: if (gp_archive_have_index(state.archive) == 0) { gp_error("this archive has no symbol index"); } else { gp_archive_read_index(symbol_index, state.archive); gp_archive_print_table(symbol_index); } break; case ar_null: default: assert(0); } /* If the archive is being modified remove the old symbol index */ if (update_archive) { state.archive = gp_archive_remove_index(state.archive); } /* check for duplicate symbols */ gp_archive_make_index(state.archive, definition_tbl); /* add the symbol index to the archive */ if (update_archive && (!no_index)) { state.archive = gp_archive_add_index(definition_tbl, state.archive); } /* write the new or modified archive */ if (update_archive && (gp_num_errors == 0)) { if (gp_archive_write(state.archive, state.filename)) gp_error("can't write the new archive file"); } if (gp_num_errors > 0) return EXIT_FAILURE; else return EXIT_SUCCESS; } gputils-0.13.7/gputils/dump.h0000644000175000017500000000230111156313067013016 00000000000000/* Displays contents of ".COD" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __DUMP_H__ #define __DUMP_H__ void dump_hex(char *chunk, int length); void dump_memmap( void); void dump_code(void); void dump_symbols( void ); void dump_lsymbols( void ); void dump_source_files( void ); void dump_line_symbols(void); void dump_message_area(void); void dump_local_vars(void); unsigned short get_short_int( char * buff); char *substr(char *a, size_t sizeof_a, char *b, size_t n); #endif gputils-0.13.7/gputils/gpvo.h0000644000175000017500000000273311156521262013033 00000000000000/* gpvo - GNU PIC view object Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef GPVO_H #define GPVO_H #define GPVO_VERSION_STRING ("gpvo-" VERSION " beta") /* Dump Flags */ #define PRINT_HEADER 1 << 1 #define PRINT_SECTIONS 1 << 2 #define PRINT_SYMTBL 1 << 3 #define PRINT_BINARY 1 << 4 extern struct gpvo_state { int dump_flags; /* when bit set then print that section */ gp_boolean suppress_names; /* suppress filenames when 1 */ char *filename; /* object file name */ struct { FILE *f; /* include file output */ gp_boolean enabled; /* include file enable */ char *filename; /* include file name */ } export; gp_object_type *object; /* formatted object file */ gp_binary_type *file; /* binary object file */ } state; #endif gputils-0.13.7/gputils/gpdasm.c0000644000175000017500000001530111156521262013321 00000000000000/* Disassembles ".HEX" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpdasm.h" char *processor_name = NULL; struct gpdasm_state state = { no_processor, /* processor type */ PROC_CLASS_GENERIC, /* 12 bit device */ 1 /* output format */ }; void select_processor(void) { struct px *found = NULL; if (processor_name == NULL) { printf("error: must select processor\n"); exit(1); } found = gp_find_processor(processor_name); if (found) { state.processor = found; } else { printf("Didn't find any processor named: %s\nHere are the supported processors:\n", processor_name); gp_dump_processor_list(true, 0); exit(1); } state.class = gp_processor_class(state.processor); switch (state.class) { case PROC_CLASS_EEPROM8: case PROC_CLASS_EEPROM16: case PROC_CLASS_GENERIC: fprintf(stderr, "error: unsupported processor class\n"); exit(1); break; case PROC_CLASS_PIC12: case PROC_CLASS_SX: case PROC_CLASS_PIC14: case PROC_CLASS_PIC16: case PROC_CLASS_PIC16E: break; default: assert(0); } return; } void writeheader() { if (!state.format) { printf("\n"); printf(" processor %s\n", processor_name); } } void closeasm() { if (!state.format) { printf(" end\n"); } } void writeorg(int address) { if (!state.format) { printf("\n"); printf(" org\t%#x\n", address); } } void dasm(MemBlock *memory) { MemBlock *m = memory; int i, maximum; int last_loc = 0; int num_words; char buffer[80]; int byte_addr = 0; if (state.class == PROC_CLASS_PIC16E) { byte_addr = 1; } writeheader(); while(m) { i = m->base << I_MEM_BITS; maximum = i + MAX_I_MEM; while (i < maximum) { if (((i_memory_get(memory, i)) & MEM_USED_MASK) == 0) { i++; } else { if (last_loc != i - 1){ writeorg(i << byte_addr); } last_loc = i; if (state.format) { printf("%06x: %04x ", i << byte_addr, (i_memory_get(memory, i) & 0xffff)); } else { printf(" "); } num_words = gp_disassemble(memory, i, state.class, buffer, sizeof(buffer)); printf("%s\n", buffer); i++; if (num_words != 1) { /* some 18xx instructions use two words */ if (state.format) { printf("%06x: %04x\n", i << byte_addr, (i_memory_get(memory, i) & 0xffff)); } i++; } } } m = m->next; } closeasm(); } void show_usage(void) { printf("Usage: gpdasm [options] file\n"); printf("Options: [defaults in brackets after descriptions]\n"); printf(" -c, --mnemonics Decode special mnemonics.\n"); printf(" -h, --help Show this usage message.\n"); printf(" -i, --hex-info Information on input hex file.\n"); printf(" -l, --list-chips List supported processors.\n"); printf(" -m, --dump Memory dump hex file.\n"); printf(" -p PROC, --processor PROC Select processor.\n"); printf(" -s, --short Print short format.\n"); printf(" -v, --version Show version.\n"); printf(" -y, --extended Enable 18xx extended mode.\n"); printf("\n"); printf("Report bugs to:\n"); printf("%s\n", PACKAGE_BUGREPORT); exit(0); } #define GET_OPTIONS "?chilmp:svy" /* Used: himpsv */ static struct option longopts[] = { { "mnemonics", 0, 0, 'c' }, { "help", 0, 0, 'h' }, { "hex-info", 0, 0, 'i' }, { "list-chips", 0, 0, 'l' }, { "dump", 0, 0, 'm' }, { "processor", 1, 0, 'p' }, { "short", 0, 0, 's' }, { "version", 0, 0, 'v' }, { "extended", 0, 0, 'y' }, { 0, 0, 0, 0 } }; #define GETOPT_FUNC getopt_long(argc, argv, GET_OPTIONS, longopts, 0) int main(int argc, char *argv[]) { extern char *optarg; extern int optind; int c; int print_hex_info = 0; int usage = 0; int memory_dump = 0; char *filename = 0; gp_init(); state.i_memory = i_memory_create(); while ((c = GETOPT_FUNC) != EOF) { switch (c) { case '?': case 'h': usage = 1; break; case 'c': gp_decode_mnemonics = true; break; case 'i': print_hex_info = 1; break; case 'l': gp_dump_processor_list(true, 0); exit(0); break; case 'm': memory_dump = 1; break; case 'p': processor_name = optarg; break; case 's': state.format = 0; break; case 'y': gp_decode_extended = true; break; case 'v': fprintf(stderr, "%s\n", GPDASM_VERSION_STRING); exit(0); } if (usage) break; } if ((optind + 1) == argc) { filename = argv[optind]; } else { usage = 1; } if (usage) { show_usage(); } select_processor(); state.hex_info = readhex(filename, state.i_memory); if (state.hex_info->error) { state.num.errors++; } if (print_hex_info) { printf("hex file name: %s\n", filename); printf("hex file format: "); if (state.hex_info->hex_format == inhx8m) { printf("inhx8m\n"); } else if (state.hex_info->hex_format == inhx16) { printf("inhx16\n"); } else if (state.hex_info->hex_format == inhx32) { printf("inhx32\n"); } else { printf("UNKNOWN\n"); } printf("number of bytes: %i\n", state.hex_info->size); printf("\n"); } if (state.num.errors == 0) { if(memory_dump) { print_i_memory(state.i_memory, state.class == PROC_CLASS_PIC16E ? 1 : 0); } else { dasm(state.i_memory); } } i_memory_free(state.i_memory); if (state.num.errors > 0) return EXIT_FAILURE; else return EXIT_SUCCESS; } gputils-0.13.7/gputils/Makefile.am0000644000175000017500000000070611156521262013741 00000000000000## Process this file with automake to produce Makefile.in bin_PROGRAMS = gpdasm gplib gpstrip gpvc gpvo AM_CPPFLAGS = -I${top_srcdir}/libgputils -I${top_srcdir}/include LDADD = ${top_builddir}/@LIBGPUTILS@ ${top_builddir}/@LIBIBERTY@ gpdasm_SOURCES=\ gpdasm.c\ gpdasm.h gplib_SOURCES=\ gplib.c \ gplib.h gpstrip_SOURCES=\ gpstrip.c \ gpstrip.h gpvc_SOURCES=\ block.c dump.c gpvc.c \ block.h dump.h gpvc.h gpvo_SOURCES=\ gpvo.c \ gpvo.h gputils-0.13.7/gputils/block.c0000644000175000017500000001260611156521262013145 00000000000000/* Displays contents of ".COD" files Copyright (C) 2001, 2002, 2003, 2004, 2005 Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpvc.h" #include "dump.h" #include "block.h" void directory_block(void) { char temp_buf[256]; char *block; char *processor_name; struct px *processor_info; enum proc_class processor_class; int time; int bytes_for_address; block = main_dir.dir.block; printf("directory block \n"); printf("COD file version %d\n", gp_getl16(&block[COD_DIR_CODTYPE])); printf("Source file %s\n", &block[COD_DIR_SOURCE]); printf("Date %s\n", substr(temp_buf, sizeof(temp_buf), &block[COD_DIR_DATE],7)); time = gp_getl16(&block[COD_DIR_TIME]); printf("Time %02d:%02d\n", time / 100, time % 100); printf("Compiler version %s\n", substr(temp_buf, sizeof(temp_buf), &block[COD_DIR_VERSION],19)); printf("Compiler %s\n", substr(temp_buf, sizeof(temp_buf), &block[COD_DIR_COMPILER],12)); printf("Notice %s\n", substr(temp_buf, sizeof(temp_buf), &block[COD_DIR_NOTICE],64)); processor_name = substr(temp_buf, sizeof(temp_buf), &block[COD_DIR_PROCESSOR], 8); printf("Processor %s\n", processor_name); processor_info = gp_find_processor(processor_name); processor_class = gp_processor_class(processor_info); if (processor_class == PROC_CLASS_PIC16E) { byte_addr = 1; } else { byte_addr = 0; } bytes_for_address = gp_getl16(&block[COD_DIR_ADDRSIZE]); printf("Bytes for address: %d\n", bytes_for_address); if (bytes_for_address != 4) { printf("WARNING: address size looks suspicious\n"); } printf("High word of 64k address %04x\n", gp_getl16(&block[COD_DIR_HIGHADDR])); printf("Short symbol table start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_SYMTAB]), gp_getl16(&block[COD_DIR_SYMTAB+2])); printf("Long symbol table start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_LSYMTAB]), gp_getl16(&block[COD_DIR_LSYMTAB+2])); printf("File name table start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_NAMTAB]), gp_getl16(&block[COD_DIR_NAMTAB+2])); printf("Source info table start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_LSTTAB]), gp_getl16(&block[COD_DIR_LSTTAB+2])); printf("Rom table start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_MEMMAP]), gp_getl16(&block[COD_DIR_MEMMAP+2])); printf("Local scope table start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_LOCALVAR]), gp_getl16(&block[COD_DIR_LOCALVAR+2])); printf("Debug messages start block: 0x%04x end block: 0x%04x\n", gp_getl16(&block[COD_DIR_MESSTAB]), gp_getl16(&block[COD_DIR_MESSTAB+2])); printf("\nNext directory block"); if(gp_getl16(&block[COD_DIR_NEXTDIR])) printf(": %d\n",gp_getl16(&block[COD_DIR_NEXTDIR])); else printf(" is empty\n"); /* Uncomment this section to get the address offsets within the directory structure NOTE: the offsets are compiler dependent. For gcc, use the -fpack-struct option to pack the structures with no gaps. printf("notice_strlen address %d\n",ptr_offset((char *)&dir->notice_strlen,block) ); printf("notice address %d\n",ptr_offset((char *)&dir->notice,block) ); printf("symtab address %d\n",ptr_offset((char *)&dir->symtab,block) ); printf("processor address %d\n",ptr_offset((char *)&dir->processor,block) ); printf("AddrSize address %d\n",ptr_offset((char *)&dir->AddrSize,block) ); printf("HighAddr address %d\n",ptr_offset((char *)&dir->HighAddr,block) ); printf("NextDir address %d\n",ptr_offset((char *)&dir->NextDir,block) ); printf("memmap address %d\n",ptr_offset((char *)&dir->MemMapOFS,block) ); printf("lsymtab address %d\n",ptr_offset((char *)&dir->Lsymtab,block) ); */ } void read_block(char * block, int block_number) { fseek(codefile, block_number * COD_BLOCK_SIZE, SEEK_SET); fread(block, COD_BLOCK_SIZE, 1, codefile); } void create_block(Block *b) { assert(b != NULL); b->block = malloc(COD_BLOCK_SIZE); gp_cod_clear(b); } void read_directory(void) { DirBlockInfo *dbi; create_block(&main_dir.dir); read_block(main_dir.dir.block, 0); dbi = &main_dir; do { int next_dir_block = gp_getl16(&dbi->dir.block[COD_DIR_NEXTDIR]); if(next_dir_block) { dbi->next_dir_block_info = (DirBlockInfo *)malloc(sizeof(DirBlockInfo)); dbi = dbi->next_dir_block_info; create_block(&dbi->dir); read_block(dbi->dir.block, next_dir_block); } else { dbi->next_dir_block_info = NULL; return; } } while(1); } gputils-0.13.7/gputils/Makefile.in0000644000175000017500000003612511156521262013756 00000000000000# Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ top_builddir = .. am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd INSTALL = @INSTALL@ install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ bin_PROGRAMS = gpdasm$(EXEEXT) gplib$(EXEEXT) gpstrip$(EXEEXT) \ gpvc$(EXEEXT) gpvo$(EXEEXT) subdir = gputils DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 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published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef GPSTRIP_H #define GPSTRIP_H #define GPSTRIP_VERSION_STRING ("gpstrip-" VERSION " beta") extern struct gpstrip_state { gp_boolean strip_debug; /* strip debug symbols */ gp_boolean preserve_dates; /* preserve dates */ gp_boolean strip_all; /* remove all symbols */ gp_boolean strip_unneeded; /* Strip symbols not need for relocations */ gp_boolean discard_all; /* Remove non-global symbols */ char *input_file; /* input file name */ char *output_file; /* output file name */ struct symbol_table *symbol_keep; /* force these symbols to be keep */ struct symbol_table *symbol_remove; /* force these symbols to be removed */ struct symbol_table *section_remove; /* remove these sections */ gp_object_type *object; /* formatted object file */ } state; #endif gputils-0.13.7/man/0000777000175000017500000000000011156521351011051 500000000000000gputils-0.13.7/man/gpvo.10000644000175000017500000000400211156521302012012 00000000000000.TH GPVO 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gpvo \- GNU PIC object file viewer .SH SYNOPSIS .B gpvo [options] file .SH WARNING The information in this man page is an extract from the full documentation of gputils and is limited to the meaning of the options. For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gpvo is an COFF object file viewer for Microchip (TM) PIC (TM) micro-controllers. COFF files are relocatable objects output from gpasm. .B gpvo is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS .TP .BR \-b ", "\-\-binary Display binary data. .TP .BR \-c ", "\-\-mnemonics Decode special mnemonics. .TP .BR \-f ", "\-\-file Display file header. .TP .BR \-h ", "\-\-help Show the usage message. .TP .BR \-o ", "\-\-optional Display optional header. .TP .BR \-r ", "\-\-string Display the string table. .TP .BR \-s ", "\-\-section Display sections. .TP .BR \-t ", "\-\-symbol Display symbol table. .TP .BR \-v ", "\-\-version Show the version. .TP .BR "\-x FILE" , " \-\-export FILE Export the external symbols. .TP .BR \-y ", "\-\-extended Enable 18xx extended mode. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/gputils.10000644000175000017500000000231111156521302012527 00000000000000.TH GPUTILS 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gputils \- GNU PIC utilities .SH DESCRIPTION .B gputils is a collection of development tools for Microchip (TM) PIC (TM) microcontrollers. It's intended to be compatible with the manufacturer's tools, MPASM, MPLINK and MPLIB. .SH SEE ALSO .BR gpasm (1), .BR gpdasm (1), .BR gplib (1), .BR gplink (1), .BR gpstrip (1), .BR gpvc (1), .BR gpvo (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/gpvc.10000644000175000017500000000356111156521302012007 00000000000000.TH GPVC 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gpvc \- GNU PIC COD file viewer .SH SYNOPSIS .B gpvc [options] file .SH WARNING The information in this man page is an extract from the full documentation of gputils and is limited to the meaning of the options. For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gpvc is an COD file viewer for Microchip (TM) PIC (TM) micro-controllers. COD files are and output from gpasm. They contain information used for simulation. .B gpvc is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS .TP .BR \-a ", "\-\-all Display all information in the COD file. .TP .BR \-d ", "\-\-directory Display directory header. .TP .BR \-l ", "\-\-listing Display source listing. .TP .BR \-m ", "\-\-message Display debug message area. .TP .BR \-h ", "\-\-help Show the usage message. .TP .BR \-r ", "\-\-rom Display ROM. .TP .BR \-s ", "\-\-symbols Display symbols. .TP .BR \-v ", "\-\-version Show the version. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Scott Dattalo This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/0000777000175000017500000000000011156521351011460 500000000000000gputils-0.13.7/man/fr/gpvo.10000644000175000017500000000536011156521302012431 00000000000000.TH GPVO 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gpvo \- Visualiseur GNU de fichiers objets pour PIC .SH SYNOPSIS .B gpvo [options] fichier .SH AVERTISSEMENT Les informations de cette page de manuel sont extraites de la documentation complète de gputils et sont limitées à la signification des options. Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gpvo est un visualiseur de fichiers objets COFF pour les microcontrôleurs PIC (TM) de Microchip (TM). Les fichiers COFF sont des objets relogeables produit par gpasm. .B gpvo est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS .TP .BR \-b ", "\-\-binary Afficher les données binaires. .TP .BR \-c ", "\-\-mnemonics Décoder les mnémoniques spéciales. .TP .BR \-f ", "\-\-file Afficher l'en-tête du fichier. .TP .BR \-h ", "\-\-help Afficher un message d'usage. .TP .BR \-o ", "\-\-optional Afficher l'en-tête optionnel. .TP .BR \-r ", "\-\-string Afficher la table des chaînes. .TP .BR \-s ", "\-\-section Afficher les sections. .TP .BR \-t ", "\-\-symbol Afficher la tables des symboles. .TP .BR \-v ", "\-\-version Afficher la version. .TP .BR "\-x FICHIER" , " \-\-export FICHIER Exporter les symboles externes. .TP .BR \-y ", "\-\-extended Activer le mode étendu 18xx. .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 27\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=en\ man\ 1\ gpvo\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/gputils.10000644000175000017500000000336311156521302013146 00000000000000.TH GPASM 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gputils \- Utilitaires GNU pour PIC .SH DESCRIPTION .B gputils est une collection d'outils de développement pour les microcontrôleurs PIC (TM) de Microchip (TM). Son objectif est d'être compatible avec les outils du fabricant, MPASM, MPLINK et MPLIB. .SH VOIR AUSSI .BR gpasm (1), .BR gpdasm (1), .BR gplib (1), .BR gplink (1), .BR gpstrip (1), .BR gpvc (1), .BR gpvo (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 27\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gputils\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 James Bowman, Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/gpvc.10000644000175000017500000000510511156521302012412 00000000000000.TH GPASM 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gpvc \- Visualiseur GNU de fichiers COD pour PIC .SH SYNOPSIS .B gpvc [options] fichier .SH AVERTISSEMENT Les informations de cette page de manuel sont extraites de la documentation complète de gputils et sont limitées à la signification des options. Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gpvc est un visualiseur de fichiers COD pour les microcontrôleurs PIC (TM) de Microchip (TM). Ces fichiers contiennent des informations utilisées pour la simulation. .B gpvc est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS .TP .BR \-a ", "\-\-all Afficher toutes les informations présentes dans le fichier COD. .TP .BR \-d ", "\-\-directory Afficher le répertoire des en-têtes. .TP .BR \-l ", "\-\-listing Afficher le listage des sources. .TP .BR \-m ", "\-\-message Afficher la zone de messages de débogage. .TP .BR \-h ", "\-\-help Afficher un message d'usage. .TP .BR \-r ", "\-\-rom Afficher la ROM. .TP .BR \-s ", "\-\-symbols Afficher les symboles. .TP .BR \-v ", "\-\-version Afficher la version. .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 27\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gpvc\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Scott Dattalo Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/gplink.10000644000175000017500000000671011156521302012742 00000000000000.TH GPLINK 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gplink \- Éditeur de liens GNU pour PIC .SH SYNOPSIS .B gplink [options] [objets] [bibliothèques] .SH AVERTISSEMENT Les informations de cette page de manuel sont extraites de la documentation complète de gputils et sont limitées à la signification des options. Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gplink conbine un nombre de fichiers objets et archives, reloge leurs données, et lie leurs références symboles. Il produit en sortie un exécutable pour les microcontrôleurs PIC (TM) de Microchip (TM). .B gplink est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS .TP .BR "\-a FMT" , " \-\-hex\-format FMT gplink reconnaît les formats de fichiers hexadécimaux inhx8m, inhx8s, inhx16, et inhx32. Cette option contrôle quel format de fichier hexadécimal est utilisé. La valeur par défaut est inhx32. .TP .BR \-c ", "\-\-object Produire en sortie un objet exécutable. .TP .BR \-d ", "\-\-debug Produire des messages de débogage. .TP .BR "\-f VALEUR" , " \--fill VALEUR Remplir la mémoire programme inutilisée et non protégée avec VALEUR. VALEUR supplante la valeur de remplissage du script éditeur de liens. VALEUR ne doit pas être supérieure à 0xffff. VALEUR est en hexadécimal et doit être précédée par «\ 0x\ ». .TP .BR \-h ", "\-\-help Afficher un message d'usage. .TP .BR "\-I RÉP" , " \-\-include RÉP Spécifier le répertoire d'inclusion d'en-têtes. .TP .BR \-m ", "\-\-map Produire en sortie un fichier d'équivalence. .TP .BR "\-o FICHIER" , " \-\-output FICHIER Nom alternatif du fichier de sortie. .TP .BR \-q ", "\-\-quiet Supprimer tout ce qui est envoyé sur la sortie standard. .TP .BR \-r ", "\-\-use\-shared Essayer de reloger des sections de données non partagées vers la mémoire partagée si la translation échoue. .TP .BR "\-s FICHIER" , " \-\-script FICHIER Choisir le script éditeur de lien. .TP .BR \-v ", "\-\-version Afficher la version. .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 28\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gplink\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/gplib.10000644000175000017500000000531311156521302012551 00000000000000.TH GPLIB 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gplib - Bibliothécaire GNU pour PIC .SH SYNOPSIS .B gplib [options] bibliothèque [membre] .SH AVERTISSEMENT Les informations de cette page de manuel sont extraites de la documentation complète de gputils et sont limitées à la signification des options. Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gplib crée, modifie et extrait des archives COFF pour les microcontrôleurs PIC (TM) de Microchip (TM). .B gplib est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS .TP .BR \-c ", "\-\-create Créer une nouvelle bibliothèque. .TP .BR \-d ", "\-\-delete Supprimer «\ membre\ » de «\ bibliothèque\ ». .TP .BR \-h ", "\-\-help Afficher un message d'usage. .TP .BR \-n ", "\-\-no-index Ne pas ajouter l'index des symboles. .TP .BR \-q ", "\-\-quiet Mode silencieux. .TP .BR \-r ", "\-\-replace Ajouter ou remplacer «\ membre\ » de «\ bibliothèque\ ». .TP .BR \-s ", "\-\-symbols Afficher les symboles globaux de «\ bibliothèque\ ». .TP .BR \-t ", "\-\-list Afficher les membres de «\ bibliothèque\ ». .TP .BR \-v ", "\-\-version Afficher la version. .TP .BR \-x ", "\-\-extract Extraire «\ membre\ » de «\ bibliothèque\ ». .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 28\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gplib\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/gpdasm.10000644000175000017500000000536311156521302012734 00000000000000.TH GPDASM 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gpdasm \- Désassembleur GNU pour PIC .SH SYNOPSIS .B gpdasm [options] fichier .SH AVERTISSEMENT Les informations de cette page de manuel sont extraites de la documentation complète de gputils et sont limitées à la signification des options. Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gpdasm est un désassembleur pour les microcontrôleurs PIC (TM) de Microchip (TM). .B gpdasm est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS .TP .BR \-c ", " \-\-mnemonics Décoder les mnémoniques spéciales. .TP .BR \-h ", "\-\-help Afficher un message d'usage. .TP .BR \-i ", "\-\-hex-info Produire des informations supplémentaires concernant le fichier hexadécimal d'entrée. Ces informations incluent la taille du fichier et le format hexadécimal. .TP .BR \-l ", "\-\-list-chips Afficher la liste des processeurs reconnus. .TP .BR \-m ", "\-\-dump Afficher le contenu de la mémoire programme. .TP .BR "\-p PROC" , " \-\-processor PROC Sélectionner le processeur. .TP .BR \-s ", "\-\-short Produire en sortie le format court. Ce format peut être réassemblé par gpasm. .TP .BR \-v ", "\-\-version Afficher la version. .TP .BR \-y ", "\-\-extended Activer le mode étendu 18xx. .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 28\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gpdasm\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. 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Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gpasm est un assembleur pour les microcontrôleurs PIC (TM) de Microchip (TM). Son objectif est d'être compatible avec l'assembleur MPASM du fabricant. .B gpasm est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS Voici un résumé des options .BR gpasm . Les options de .B gpasm supplantent toujours toute configuration contenue dans le code source. .TP .BR "\-a FMT" , " \-\-hex-format FMT GPASM reconnaît les formats de fichiers hexadécimaux inhx8m, inhx8s, inhx16 et inhx32. Cette option contrôle quel format de fichier hexadécimal est utilisé. La valeur par défaut est inhx32. .TP .BR \-c ", "\-\-object Produire en sortie un objet relogeable (ancien format COFF). .TP .BR \-C ", "\-\-new-coff Produire en sortie un objet relogeable (nouveau format COFF). .TP .BR \-d ", " \-\-debug Afficher les messages de débogage. .TP .BR "\-D SYM=VAL" , " \-\-define SYM=VAL" Définir SYM avec la valeur VAL. Ceci est équivalent à placer «\ #define SYM VAL\ » dans le code source. .TP .BR "\-e [ON|OFF]" , " \-\-expand [ON|OFF]" Le développement des macros dans le fichier listage est contrôlé en utilisant les directives EXPAND et NOEXPAND. Cette option permet d'ignorer l'une ou l'autre directive. Lorsque «\ ON\ » est sélectionné, les macros sont toujours développées sans se soucier de la présence de NOEXPAND. De la même manière, «\ OFF\ » forcera les macros à ne pas être développées. .TP .BR \-g ", " \-\-debug-info Utiliser les directives de débogage pour COFF. .TP .BR \-h ", " \-\-help Afficher un message d'usage. .TP .BR \-i ", " \-\-ignore-case Tous les symboles et macros définis par l'utilisateur sont sensibles à la casse. Cette option permet de les rendre insensibles à la casse. .TP .BR "\-I RÉP" , " \-\-include RÉP" Le fichier d'assemblage de plus haut niveau hiérarchique est passé comme argument à gpasm. Ce fichier peut contenir des directives INCLUDE. Ces directives ouvrent les fichiers spécifiés et leurs contenus sont alors assemblés. GPASM recherche ces fichiers dans le répertoire courant. Si le fichier n'est pas localisé, le chemin par défaut des en-têtes est parcouru. Enfin, tous les chemins spécifiés par cet argument sont parcourus. .TP .BR \-L ", "\-\-force-list Ignorer les directives NOLIST. Ceci force gpasm à afficher chaque ligne assemblée dans le fichier listage de sortie. .TP .BR \-l ", "\-\-list-chips Afficher la liste des processeurs reconnus. .TP .BR \-m ", "\-\-dump À la fin de la dernière étape d'assemblage, afficher le contenu de la mémoire programme. .TP .BR \-M ", "\-\-deps Produire un fichier des dépendances. .TP .BR \-n ", "\-\-dos Par défaut, gpasm génère des fichiers hexadécimaux au format ISO. Toutefois, certains programmateurs de composants requièrent un fichier au format DOS. Cette option fait que gpasm génèrera un fichier au format DOS. .TP .BR "\-o FICHIER" , " \-\-output FICHIER" Nom alternatif du fichier de sortie. .TP .BR "\-p PROC" , " \-\-processor PROC" Sélectionner le processeur. .TP .BR \-q ", "\-\-quiet Supprimer tout ce qui est envoyé sur la sortie standard. .TP .BR "\-r BASE" , " \-\-radix BASE" Les bases reconnues sont BIN, DEC, OCT, et HEX. La base par défaut est HEX. .TP .BR \-v ", "\-\-version Afficher la version. .TP .BR "\-w [0|1|2]" , " \-\-warning [0|1|2]" Cette option configure le niveau d'affichage des messages. La valeur par défaut est «\ 0\ ». Elle permet l'affichage des messages, des avertissements et des erreurs. «\ 1\ » supprimera les messages. «\ 2\ » supprimera les messages et les avertissements. .TP .BR \-y ", "\-\-extended Activer le mode étendu 18xx. .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 14\ octobre\ 2004 et révisée le 13\ mai\ 2008. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gpasm\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 James Bowman, Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/fr/gpstrip.10000644000175000017500000000541311156521302013145 00000000000000.TH GPSTRIP 1 "27 octobre 2007" "gputils-0.13.7" "Manuel de l'utilisateur Linux" .SH NOM gpstrip \- Retirer les symboles d'un fichier objet .SH SYNOPSIS .B gpstrip [options] [fichier] .SH AVERTISSEMENT Les informations de cette page de manuel sont extraites de la documentation complète de gputils et sont limitées à la signification des options. Pour une documentation complète, reportez-vous au fichier «\ gputils.ps\ » (en anglais) situé dans le répertoire doc de gputils. .SH DESCRIPTION .B gpstrip retire les symboles des fichiers objet GNU PIC .B gpstrip est une partie de gputils. Consultez la page manuel .BR gputils (1) pour avoir des détails sur les autres utilitaires GNU PIC. .SH OPTIONS .TP .BR \-g ", "\-\-strip\-debug Éliminer les symboles de débogage. .TP .BR \-h ", "\-\-help Afficher ce message d'usage. .TP .BR "\-k SYMBOLE" , " \-\-keep\-symbol SYMBOLE Conserver le symbole SYMBOLE. .TP .BR "\-n SYMBOLE" , " \-\-strip\-symbol SYMBOLE Supprimer le symbole SYMBOLE. .TP .BR "\-o FICHIER" , " \-\-output FICHIER Nom alternatif du fichier de sortie. .TP .BR \-p ", "\-\-preserve\-dates Préserver les dates. .TP .BR "\-r SECTION" , " \-\-remove-section SECTION Retirer la section SECTION. .TP .BR \-s ", "\-\-strip\-all Retirer tous les symboles. .TP .BR \-u ", "\-\-strip\-unneeded Retirer les symboles qui ne sont pas nécessaires à la translation (Ndt\ : relocation). .TP .BR \-v ", "\-\-version Afficher la version. .TP .BR \-x ", "\-\-discard-all Retirer les symboles non globaux. .SH VOIR AUSSI .BR gputils (1) .SH AUTEUR Craig Franklin .SH TRADUCTION .PP Ce document est une traduction réalisée par Alain Portal le 24\ mai\ 2005 et révisée le 28\ octobre\ 2007. .PP L'équipe de traduction a fait le maximum pour réaliser une adaptation française de qualité. La version anglaise la plus à jour de ce document est toujours consultable via la commande\ : «\ \fBLANG=C\ man\ 1\ gpstrip\fR\ ». N'hésitez pas à signaler à l'auteur ou au traducteur, selon le cas, toute erreur dans cette page de manuel. .SH COPYRIGHT Copyright (C) 2005 Craig Franklin Ce programme est un logiciel libre\ ; vous pouvez le redistribuer et/ou le modifier sous les termes de la licence GNU GPL telle que publiée par la Free Software Foundation\ ; soit la version 2, soit (à votre convenance) toute version ultérieure. Ce programme est distribué dans l'espoir qu'il soit utile, mais SANS AUCUNE GARANTIE\ ; même sans la garantie implicite d'UTILISABILITÉ ou d'ADAPTATION À UN USAGE PRÉCIS. Lisez la licence GNU GPL pour plus de détails. Vous devriez avoir reçu une copie de la licence GNU GPL avec ce programme\ ; si ce n'est pas le cas, écrivez à Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/gplink.10000644000175000017500000000515511156521302012335 00000000000000.TH GPLINK 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gplink \- GNU PIC linker .SH SYNOPSIS .B gplink [options] [objects] [libraries] .SH WARNING The information in this man page is an extract from the full documentation of gputils and is limited to the meaning of the options. For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gplink combines a number of object and archive files, relocates their data, and ties up their symbol references. It outputs an executable for Microchip (TM) PIC (TM) micro-controllers. .B gplink is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS .TP .BR "\-a FMT" , " \-\-hex\-format FMT gplink supports inhx8m, inhx8s, inhx16, and inhx32 hex file formats. This option controls which hex file format is used. The default is inhx32. .TP .BR \-c ", "\-\-object Output an executable object. .TP .BR \-d ", "\-\-debug Display debug messages. .TP .BR "\-f VALUE" , " \--fill VALUE Fill unused unprotected program memory with value. The value supercedes the linker script fill value. The value must not be greater than 0xffff. The value is hex. The value may be preceeded by "0x". .TP .BR \-h ", "\-\-help Show the usage message. .TP .BR "\-I DIR" , " \-\-include DIR Specify include directory. .TP .BR \-m ", "\-\-map Output a map file. .TP .BR "\-o FILE" , " \-\-output FILE Alternate name of the output file. .TP .BR \-q ", "\-\-quiet Suppress anything sent to standard output. .TP .BR \-r ", "\-\-use\-shared Attempt to relocate unshared data sections to shared memory if relocation fails. .TP .BR "\-s FILE" , " \-\-script FILE Linker script. .TP .BR \-v ", "\-\-version Show the version. .TP .BR \-w ", "\-\-processor\-mismatch Disable "processor mismatch" warning. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/gplib.10000644000175000017500000000366711156521302012154 00000000000000.TH GPLIB 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gplib \- GNU PIC librarian .SH SYNOPSIS .B gplib [options] library [member] .SH WARNING The information in this man page is an extract from the full documentation of gputils and is limited to the meaning of the options. For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gplib creates, modifies, and extracts from COFF archives for Microchip (TM) PIC (TM) micro-controllers. .B gplib is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS .TP .BR \-c ", "\-\-create Create a new library. .TP .BR \-d ", "\-\-delete Delete member from library. .TP .BR \-h ", "\-\-help Show the usage message. .TP .BR \-n ", "\-\-no-index Don't add symbol index. .TP .BR \-q ", "\-\-quiet Quiet mode. .TP .BR \-r ", "\-\-replace Add or replace member from library. .TP .BR \-s ", "\-\-symbols List global symbols in library. .TP .BR \-t ", "\-\-list List members in library. .TP .BR \-v ", "\-\-version Show the version. .TP .BR \-x ", "\-\-extract Extract member from library. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/gpdasm.10000644000175000017500000000377311156521302012330 00000000000000.TH GPDASM 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gpdasm \- GNU PIC disassembler .SH SYNOPSIS .B gpdasm [options] file .SH WARNING The information in this man page is an extract from the full documentation of gputils and is limited to the meaning of the options. For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gpdasm is an disassembler for Microchip (TM) PIC (TM) micro-controllers. .B gpdasm is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS .TP .BR \-c ", " \-\-mnemonics Decode special mnemonics. .TP .BR \-h ", "\-\-help Show the usage message. .TP .BR \-i ", "\-\-hex-info Report extra information about input hex file. This information includes file size and hex format. .TP .BR \-l ", "\-\-list-chips List the supported processors. .TP .BR \-m ", "\-\-dump Display the contents of instruction memory. .TP .BR "\-p PROC" , " \-\-processor PROC Select the processor. .TP .BR \-s ", "\-\-short Output the short format. This format can be reassembled by gpasm. .TP .BR \-v ", "\-\-version Show the version. .TP .BR \-y ", "\-\-extended Enable 18xx extended mode. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. 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For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gpasm is an assembler for Microchip (TM) PIC (TM) micro-controllers. It's intended to be compatible with the manufacturer's MPASM assembler. .B gpasm is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS Below is a summary of the .B gpasm options. .B gpasm options always supersede any settings in the source code. .TP .BR "\-a FMT" , " \-\-hex\-format FMT GPASM supports inhx8m, inhx8s, inhx16, and inhx32 hex file formats. This option controls which hex file format is used. The default is inhx32. .TP .BR \-c ", "\-\-object Output a relocatable object (old COFF format). .TP .BR \-C ", "\-\-new\-coff Output a relocatable object (new COFF format). .TP .BR \-d ", " \-\-debug Output debug messages. .TP .BR "\-D SYM=VAL" , " \-\-define SYM=VAL" Define SYM with value VAL. This is equivalent to placing "#define SYM VAL" in the source. .TP .BR "\-e [ON|OFF]" , " \-\-expand [ON|OFF]" Macro expansion in the listing file is controlled using the EXPAND and NOEXPAND directives. This option can force either directive to be ignored. When "ON" is selected the macros are always expanded regardless of the presence of NOEXPAND. Likewise, "OFF" will force macros not to be expanded. .TP .BR \-g ", " \-\-debug-info Use debug directives for COFF. .TP .BR \-h ", " \-\-help Show the usage message. .TP .BR \-i ", " \-\-ignore\-case All user defined symbols and macros are case sensitive. This option makes them case insensitive. .TP .BR "\-I DIR" , " \-\-include DIR" The top level assembly file is passed to gpasm as an argument. This file can contain INCLUDE directives. These directives open the specified file and then its contents are assembled. GPASM searches for these files in the local directory. If the file is not located, the default header path is checked. Finally, all paths specified using this argument are searched. .TP .BR \-L ", "\-\-force-list Ignore NOLIST directives. This forces gpasm to print every line assembled in the list file output. .TP .BR \-l ", "\-\-list\-chips List the supported processors. .TP .BR \-m ", "\-\-dump Upon completion of the final pass of assembly, display the contents of instruction memory. .TP .BR \-M ", "\-\-deps Output a dependency file. .TP .BR \-n ", "\-\-dos By default, gpasm generates hex files using ISO format. However, some device programmers required a DOS formatted file. This option will cause gpasm to generate a DOS formatted hex file. .TP .BR "\-o FILE" , " \-\-output FILE" Alternate name of the output file. .TP .BR "\-p PROC" , " \-\-processor PROC" Select the processor. .TP .BR \-q ", "\-\-quiet Suppress anything sent to standard output. .TP .BR "\-r RADIX" , " \-\-radix RADIX" The supported radices are BIN, DEC, OCT, and HEX. The default is HEX. .TP .BR \-v ", "\-\-version Show the version. .TP .BR "\-w [0|1|2]" , " \-\-warning [0|1|2]" This option sets the message level. "0" is the default. It will allow all messages, warnings, and errors to be reported. "1" will suppress the messages. "2" will suppress the messages and warnings. .TP .BR \-y ", "\-\-extended Enable 18xx extended mode. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/man/gpstrip.10000644000175000017500000000400411156521302012531 00000000000000.TH GPSTRIP 1 "2007-10-27" "gputils-0.13.7" "Linux user's manual" .SH NAME gpstrip \- discard symbols from object file .SH SYNOPSIS .B gpstrip [options] [file(s)] .SH WARNING The information in this man page is an extract from the full documentation of gputils and is limited to the meaning of the options. For complete and current documentation, refer to "gputils.ps" located in the gputils docs directory. .SH DESCRIPTION .B gpstrip discards symbols from GNU PIC object files. .B gpstrip is part of gputils. Check the .BR gputils (1) manpage for details on other GNU PIC utilities. .SH OPTIONS .TP .BR \-g ", "\-\-strip\-debug Strip debug symbols. .TP .BR \-h ", "\-\-help Show this usage message. .TP .BR "\-k SYMBOL" , " \-\-keep\-symbol SYMBOL Keep symbol. .TP .BR "\-n SYMBOL" , " \-\-strip\-symbol SYMBOL Remove symbol. .TP .BR "\-o FILE" , " \-\-output FILE Alternate name of output file. .TP .BR \-p ", "\-\-preserve\-dates Preserve dates. .TP .BR "\-r SECTION" , " \-\-remove-section SECTION Remove section. .TP .BR \-s ", "\-\-strip\-all Remove all symbols. .TP .BR \-u ", "\-\-strip\-unneeded Strip symbols not need for relocations. .TP .BR \-v ", "\-\-version Show version. .TP .BR \-x ", "\-\-discard-all Remove non-global symbols. .SH SEE ALSO .BR gputils (1) .SH AUTHOR Craig Franklin .SH COPYRIGHT Copyright (C) 2005 Craig Franklin This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. gputils-0.13.7/depcomp0000755000175000017500000003554511156313233011601 00000000000000#! /bin/sh # depcomp - compile a program generating dependencies as side-effects scriptversion=2004-05-31.23 # Copyright (C) 1999, 2000, 2003, 2004 Free Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2, or (at your option) # any later version. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA # 02111-1307, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Alexandre Oliva . case $1 in '') echo "$0: No command. Try \`$0 --help' for more information." 1>&2 exit 1; ;; -h | --h*) cat <<\EOF Usage: depcomp [--help] [--version] PROGRAM [ARGS] Run PROGRAMS ARGS to compile a file, generating dependencies as side-effects. Environment variables: depmode Dependency tracking mode. source Source file read by `PROGRAMS ARGS'. object Object file output by `PROGRAMS ARGS'. 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exit 1; }; } fi { echo "$as_me:$LINENO: result: $ac_cv_build" >&5 echo "${ECHO_T}$ac_cv_build" >&6; } case $ac_cv_build in *-*-*) ;; *) { { echo "$as_me:$LINENO: error: invalid value of canonical build" >&5 echo "$as_me: error: invalid value of canonical build" >&2;} { (exit 1); exit 1; }; };; esac build=$ac_cv_build ac_save_IFS=$IFS; IFS='-' set x $ac_cv_build shift build_cpu=$1 build_vendor=$2 shift; shift # Remember, the first character of IFS is used to create $*, # except with old shells: build_os=$* IFS=$ac_save_IFS case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac { echo "$as_me:$LINENO: checking host system type" >&5 echo $ECHO_N "checking host system type... $ECHO_C" >&6; } if test "${ac_cv_host+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test "x$host_alias" = x; then ac_cv_host=$ac_cv_build else ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || { { echo "$as_me:$LINENO: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&5 echo "$as_me: error: $SHELL $ac_aux_dir/config.sub $host_alias failed" >&2;} { (exit 1); exit 1; }; } fi fi { echo "$as_me:$LINENO: result: $ac_cv_host" >&5 echo "${ECHO_T}$ac_cv_host" >&6; } case $ac_cv_host in *-*-*) ;; *) { { echo "$as_me:$LINENO: error: invalid value of canonical host" >&5 echo "$as_me: error: invalid value of canonical host" >&2;} { (exit 1); exit 1; }; };; esac host=$ac_cv_host ac_save_IFS=$IFS; IFS='-' set x $ac_cv_host shift host_cpu=$1 host_vendor=$2 shift; shift # Remember, the first character of IFS is used to create $*, # except with old shells: host_os=$* IFS=$ac_save_IFS case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac # Defaults GPUTILS_HEADER_PATH="\$(datadir)/gputils/header" GPUTILS_LKR_PATH="\$(datadir)/gputils/lkr" GPUTILS_LIB_PATH="\$(datadir)/gputils/lib" LIBGPUTILS=libgputils/libgputils.a LIBIBERTY=libiberty/libiberty.a MAKE_SUBDIRS="libgputils libiberty gpasm gplink gputils header lkr doc man" # Check for additional parameters # Check whether --enable-debug was given. if test "${enable_debug+set}" = set; then enableval=$enable_debug; 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echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } { echo "$as_me:$LINENO: checking lex output file root" >&5 echo $ECHO_N "checking lex output file root... $ECHO_C" >&6; } if test "${ac_cv_prog_lex_root+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -f lex.yy.c; then ac_cv_prog_lex_root=lex.yy elif test -f lexyy.c; then ac_cv_prog_lex_root=lexyy else { { echo "$as_me:$LINENO: error: cannot find output from $LEX; giving up" >&5 echo "$as_me: error: cannot find output from $LEX; giving up" >&2;} { (exit 1); exit 1; }; } fi fi { echo "$as_me:$LINENO: result: $ac_cv_prog_lex_root" >&5 echo "${ECHO_T}$ac_cv_prog_lex_root" >&6; } LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root if test -z "${LEXLIB+set}"; then { echo "$as_me:$LINENO: checking lex library" >&5 echo $ECHO_N "checking lex library... $ECHO_C" >&6; } if test "${ac_cv_lib_lex+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_save_LIBS=$LIBS ac_cv_lib_lex='none needed' for ac_lib in '' -lfl -ll; do LIBS="$ac_lib $ac_save_LIBS" cat >conftest.$ac_ext <<_ACEOF `cat $LEX_OUTPUT_ROOT.c` _ACEOF rm -f conftest.$ac_objext conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && $as_test_x conftest$ac_exeext; then ac_cv_lib_lex=$ac_lib else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 fi rm -f core conftest.err conftest.$ac_objext conftest_ipa8_conftest.oo \ conftest$ac_exeext conftest.$ac_ext test "$ac_cv_lib_lex" != 'none needed' && break done LIBS=$ac_save_LIBS fi { echo "$as_me:$LINENO: result: $ac_cv_lib_lex" >&5 echo "${ECHO_T}$ac_cv_lib_lex" >&6; } test "$ac_cv_lib_lex" != 'none needed' && LEXLIB=$ac_cv_lib_lex fi { echo "$as_me:$LINENO: checking whether yytext is a pointer" >&5 echo $ECHO_N "checking whether yytext is a pointer... $ECHO_C" >&6; } if test "${ac_cv_prog_lex_yytext_pointer+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # POSIX says lex can declare yytext either as a pointer or an array; the # default is implementation-dependent. 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INSTALL=$ac_install_sh fi fi { echo "$as_me:$LINENO: result: $INSTALL" >&5 echo "${ECHO_T}$INSTALL" >&6; } # Use test -z because SunOS4 sh mishandles braces in ${var-val}. # It thinks the first close brace ends the variable substitution. test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' # append the host alias to the tools for cross compiling if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$RANLIB"; then ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi RANLIB=$ac_cv_prog_RANLIB if test -n "$RANLIB"; then { echo "$as_me:$LINENO: result: $RANLIB" >&5 echo "${ECHO_T}$RANLIB" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi fi if test -z "$ac_cv_prog_RANLIB"; then ac_ct_RANLIB=$RANLIB # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$ac_ct_RANLIB"; then ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_RANLIB="ranlib" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB if test -n "$ac_ct_RANLIB"; then { echo "$as_me:$LINENO: result: $ac_ct_RANLIB" >&5 echo "${ECHO_T}$ac_ct_RANLIB" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi if test "x$ac_ct_RANLIB" = x; then RANLIB=":" else case $cross_compiling:$ac_tool_warned in yes:) { echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&5 echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&2;} ac_tool_warned=yes ;; esac RANLIB=$ac_ct_RANLIB fi else RANLIB="$ac_cv_prog_RANLIB" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_AR+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$AR"; then ac_cv_prog_AR="$AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_AR="${ac_tool_prefix}ar" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi AR=$ac_cv_prog_AR if test -n "$AR"; then { echo "$as_me:$LINENO: result: $AR" >&5 echo "${ECHO_T}$AR" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi fi if test -z "$ac_cv_prog_AR"; then ac_ct_AR=$AR # Extract the first word of "ar", so it can be a program name with args. set dummy ar; ac_word=$2 { echo "$as_me:$LINENO: checking for $ac_word" >&5 echo $ECHO_N "checking for $ac_word... $ECHO_C" >&6; } if test "${ac_cv_prog_ac_ct_AR+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if test -n "$ac_ct_AR"; then ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_AR="ar" echo "$as_me:$LINENO: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_AR=$ac_cv_prog_ac_ct_AR if test -n "$ac_ct_AR"; then { echo "$as_me:$LINENO: result: $ac_ct_AR" >&5 echo "${ECHO_T}$ac_ct_AR" >&6; } else { echo "$as_me:$LINENO: result: no" >&5 echo "${ECHO_T}no" >&6; } fi if test "x$ac_ct_AR" = x; then AR=":" else case $cross_compiling:$ac_tool_warned in yes:) { echo "$as_me:$LINENO: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&5 echo "$as_me: WARNING: In the future, Autoconf will not detect cross-tools whose name does not start with the host triplet. If you think this configuration is useful to you, please write to autoconf@gnu.org." >&2;} ac_tool_warned=yes ;; esac AR=$ac_ct_AR fi else AR="$ac_cv_prog_AR" fi # Checks for header files. ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu { echo "$as_me:$LINENO: checking how to run the C preprocessor" >&5 echo $ECHO_N "checking how to run the C preprocessor... $ECHO_C" >&6; } # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= fi if test -z "$CPP"; then if test "${ac_cv_prog_CPP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Double quotes because CPP needs to be expanded for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" do ac_preproc_ok=false for ac_c_preproc_warn_flag in '' yes do # Use a header file that comes with gcc, so configuring glibc # with a fresh cross-compiler works. # Prefer to if __STDC__ is defined, since # exists even on freestanding compilers. # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #ifdef __STDC__ # include #else # include #endif Syntax error _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 # Broken: fails on valid input. continue fi rm -f conftest.err conftest.$ac_ext # OK, works on sane cases. Now check whether nonexistent headers # can be detected and how. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then # Broken: success on invalid input. continue else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 # Passes both tests. ac_preproc_ok=: break fi rm -f conftest.err conftest.$ac_ext done # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. rm -f conftest.err conftest.$ac_ext if $ac_preproc_ok; then break fi done ac_cv_prog_CPP=$CPP fi CPP=$ac_cv_prog_CPP else ac_cv_prog_CPP=$CPP fi { echo "$as_me:$LINENO: result: $CPP" >&5 echo "${ECHO_T}$CPP" >&6; } ac_preproc_ok=false for ac_c_preproc_warn_flag in '' yes do # Use a header file that comes with gcc, so configuring glibc # with a fresh cross-compiler works. # Prefer to if __STDC__ is defined, since # exists even on freestanding compilers. # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #ifdef __STDC__ # include #else # include #endif Syntax error _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then : else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 # Broken: fails on valid input. continue fi rm -f conftest.err conftest.$ac_ext # OK, works on sane cases. Now check whether nonexistent headers # can be detected and how. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then # Broken: success on invalid input. continue else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 # Passes both tests. ac_preproc_ok=: break fi rm -f conftest.err conftest.$ac_ext done # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. rm -f conftest.err conftest.$ac_ext if $ac_preproc_ok; then : else { { echo "$as_me:$LINENO: error: C preprocessor \"$CPP\" fails sanity check See \`config.log' for more details." >&5 echo "$as_me: error: C preprocessor \"$CPP\" fails sanity check See \`config.log' for more details." >&2;} { (exit 1); exit 1; }; } fi ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu { echo "$as_me:$LINENO: checking for grep that handles long lines and -e" >&5 echo $ECHO_N "checking for grep that handles long lines and -e... $ECHO_C" >&6; } if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else # Extract the first word of "grep ggrep" to use in msg output if test -z "$GREP"; then set dummy grep ggrep; ac_prog_name=$2 if test "${ac_cv_path_GREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_GREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in grep ggrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue # Check for GNU ac_path_GREP and select it if it is found. # Check for GNU $ac_path_GREP case `"$ac_path_GREP" --version 2>&1` in *GNU*) ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'GREP' >> "conftest.nl" "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_GREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_GREP_found && break 3 done done done IFS=$as_save_IFS fi GREP="$ac_cv_path_GREP" if test -z "$GREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_GREP=$GREP fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_GREP" >&5 echo "${ECHO_T}$ac_cv_path_GREP" >&6; } GREP="$ac_cv_path_GREP" { echo "$as_me:$LINENO: checking for egrep" >&5 echo $ECHO_N "checking for egrep... $ECHO_C" >&6; } if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 then ac_cv_path_EGREP="$GREP -E" else # Extract the first word of "egrep" to use in msg output if test -z "$EGREP"; then set dummy egrep; ac_prog_name=$2 if test "${ac_cv_path_EGREP+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else ac_path_EGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in egrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue # Check for GNU ac_path_EGREP and select it if it is found. # Check for GNU $ac_path_EGREP case `"$ac_path_EGREP" --version 2>&1` in *GNU*) ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; *) ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" echo 'EGREP' >> "conftest.nl" "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break ac_count=`expr $ac_count + 1` if test $ac_count -gt ${ac_path_EGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_EGREP_found && break 3 done done done IFS=$as_save_IFS fi EGREP="$ac_cv_path_EGREP" if test -z "$EGREP"; then { { echo "$as_me:$LINENO: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&5 echo "$as_me: error: no acceptable $ac_prog_name could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" >&2;} { (exit 1); exit 1; }; } fi else ac_cv_path_EGREP=$EGREP fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_path_EGREP" >&5 echo "${ECHO_T}$ac_cv_path_EGREP" >&6; } EGREP="$ac_cv_path_EGREP" { echo "$as_me:$LINENO: checking for ANSI C header files" >&5 echo $ECHO_N "checking for ANSI C header files... $ECHO_C" >&6; } if test "${ac_cv_header_stdc+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #include #include int main () { ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_header_stdc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_header_stdc=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "memchr" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "free" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. if test "$cross_compiling" = yes; then : else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include #if ((' ' & 0x0FF) == 0x020) # define ISLOWER(c) ('a' <= (c) && (c) <= 'z') # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ (('a' <= (c) && (c) <= 'i') \ || ('j' <= (c) && (c) <= 'r') \ || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF rm -f conftest$ac_exeext if { (ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_link") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { ac_try='./conftest$ac_exeext' { (case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_try") 2>&5 ac_status=$? echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); }; }; then : else echo "$as_me: program exited with status $ac_status" >&5 echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ( exit $ac_status ) ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext conftest.$ac_objext conftest.$ac_ext fi fi fi { echo "$as_me:$LINENO: result: $ac_cv_header_stdc" >&5 echo "${ECHO_T}$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then cat >>confdefs.h <<\_ACEOF #define STDC_HEADERS 1 _ACEOF fi # On IRIX 5.3, sys/types and inttypes.h are conflicting. for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ inttypes.h stdint.h unistd.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then eval "$as_ac_Header=yes" else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 eval "$as_ac_Header=no" fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_header in libintl.h malloc.h stdlib.h string.h strings.h unistd.h windows.h do as_ac_Header=`echo "ac_cv_header_$ac_header" | $as_tr_sh` if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } else # Is the header compilable? { echo "$as_me:$LINENO: checking $ac_header usability" >&5 echo $ECHO_N "checking $ac_header usability... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default #include <$ac_header> _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_header_compiler=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_compiler=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_compiler" >&5 echo "${ECHO_T}$ac_header_compiler" >&6; } # Is the header present? { echo "$as_me:$LINENO: checking $ac_header presence" >&5 echo $ECHO_N "checking $ac_header presence... $ECHO_C" >&6; } cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include <$ac_header> _ACEOF if { (ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } >/dev/null && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then ac_header_preproc=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_header_preproc=no fi rm -f conftest.err conftest.$ac_ext { echo "$as_me:$LINENO: result: $ac_header_preproc" >&5 echo "${ECHO_T}$ac_header_preproc" >&6; } # So? What about this header? case $ac_header_compiler:$ac_header_preproc:$ac_c_preproc_warn_flag in yes:no: ) { echo "$as_me:$LINENO: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&5 echo "$as_me: WARNING: $ac_header: accepted by the compiler, rejected by the preprocessor!" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the compiler's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the compiler's result" >&2;} ac_header_preproc=yes ;; no:yes:* ) { echo "$as_me:$LINENO: WARNING: $ac_header: present but cannot be compiled" >&5 echo "$as_me: WARNING: $ac_header: present but cannot be compiled" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: check for missing prerequisite headers?" >&5 echo "$as_me: WARNING: $ac_header: check for missing prerequisite headers?" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: see the Autoconf documentation" >&5 echo "$as_me: WARNING: $ac_header: see the Autoconf documentation" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&5 echo "$as_me: WARNING: $ac_header: section \"Present But Cannot Be Compiled\"" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: proceeding with the preprocessor's result" >&5 echo "$as_me: WARNING: $ac_header: proceeding with the preprocessor's result" >&2;} { echo "$as_me:$LINENO: WARNING: $ac_header: in the future, the compiler will take precedence" >&5 echo "$as_me: WARNING: $ac_header: in the future, the compiler will take precedence" >&2;} ( cat <<\_ASBOX ## ---------------------------------------------------- ## ## Report this to ## ## ---------------------------------------------------- ## _ASBOX ) | sed "s/^/$as_me: WARNING: /" >&2 ;; esac { echo "$as_me:$LINENO: checking for $ac_header" >&5 echo $ECHO_N "checking for $ac_header... $ECHO_C" >&6; } if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else eval "$as_ac_Header=\$ac_header_preproc" fi ac_res=`eval echo '${'$as_ac_Header'}'` { echo "$as_me:$LINENO: result: $ac_res" >&5 echo "${ECHO_T}$ac_res" >&6; } fi if test `eval echo '${'$as_ac_Header'}'` = yes; then cat >>confdefs.h <<_ACEOF #define `echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done { echo "$as_me:$LINENO: checking whether asprintf is declared" >&5 echo $ECHO_N "checking whether asprintf is declared... $ECHO_C" >&6; } if test "${ac_cv_have_decl_asprintf+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { #ifndef asprintf (void) asprintf; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_have_decl_asprintf=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_have_decl_asprintf=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_have_decl_asprintf" >&5 echo "${ECHO_T}$ac_cv_have_decl_asprintf" >&6; } if test $ac_cv_have_decl_asprintf = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_DECL_ASPRINTF 1 _ACEOF else cat >>confdefs.h <<_ACEOF #define HAVE_DECL_ASPRINTF 0 _ACEOF fi { echo "$as_me:$LINENO: checking whether basename is declared" >&5 echo $ECHO_N "checking whether basename is declared... $ECHO_C" >&6; } if test "${ac_cv_have_decl_basename+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { #ifndef basename (void) basename; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_have_decl_basename=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_have_decl_basename=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_have_decl_basename" >&5 echo "${ECHO_T}$ac_cv_have_decl_basename" >&6; } if test $ac_cv_have_decl_basename = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_DECL_BASENAME 1 _ACEOF else cat >>confdefs.h <<_ACEOF #define HAVE_DECL_BASENAME 0 _ACEOF fi { echo "$as_me:$LINENO: checking whether getopt is declared" >&5 echo $ECHO_N "checking whether getopt is declared... $ECHO_C" >&6; } if test "${ac_cv_have_decl_getopt+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { #ifndef getopt (void) getopt; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_have_decl_getopt=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_have_decl_getopt=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_have_decl_getopt" >&5 echo "${ECHO_T}$ac_cv_have_decl_getopt" >&6; } if test $ac_cv_have_decl_getopt = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_DECL_GETOPT 1 _ACEOF else cat >>confdefs.h <<_ACEOF #define HAVE_DECL_GETOPT 0 _ACEOF fi { echo "$as_me:$LINENO: checking whether vasprintf is declared" >&5 echo $ECHO_N "checking whether vasprintf is declared... $ECHO_C" >&6; } if test "${ac_cv_have_decl_vasprintf+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default int main () { #ifndef vasprintf (void) vasprintf; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_have_decl_vasprintf=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_have_decl_vasprintf=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_have_decl_vasprintf" >&5 echo "${ECHO_T}$ac_cv_have_decl_vasprintf" >&6; } if test $ac_cv_have_decl_vasprintf = yes; then cat >>confdefs.h <<_ACEOF #define HAVE_DECL_VASPRINTF 1 _ACEOF else cat >>confdefs.h <<_ACEOF #define HAVE_DECL_VASPRINTF 0 _ACEOF fi # Checks for typedefs, structures, and compiler characteristics. { echo "$as_me:$LINENO: checking for an ANSI C-conforming const" >&5 echo $ECHO_N "checking for an ANSI C-conforming const... $ECHO_C" >&6; } if test "${ac_cv_c_const+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ int main () { /* FIXME: Include the comments suggested by Paul. */ #ifndef __cplusplus /* Ultrix mips cc rejects this. */ typedef int charset[2]; const charset cs; /* SunOS 4.1.1 cc rejects this. */ char const *const *pcpcc; char **ppc; /* NEC SVR4.0.2 mips cc rejects this. */ struct point {int x, y;}; static struct point const zero = {0,0}; /* AIX XL C 1.02.0.0 rejects this. It does not let you subtract one const X* pointer from another in an arm of an if-expression whose if-part is not a constant expression */ const char *g = "string"; pcpcc = &g + (g ? g-g : 0); /* HPUX 7.0 cc rejects these. */ ++pcpcc; ppc = (char**) pcpcc; pcpcc = (char const *const *) ppc; { /* SCO 3.2v4 cc rejects this. */ char *t; char const *s = 0 ? (char *) 0 : (char const *) 0; *t++ = 0; if (s) return 0; } { /* Someone thinks the Sun supposedly-ANSI compiler will reject this. */ int x[] = {25, 17}; const int *foo = &x[0]; ++foo; } { /* Sun SC1.0 ANSI compiler rejects this -- but not the above. */ typedef const int *iptr; iptr p = 0; ++p; } { /* AIX XL C 1.02.0.0 rejects this saying "k.c", line 2.27: 1506-025 (S) Operand must be a modifiable lvalue. */ struct s { int j; const int *ap[3]; }; struct s *b; b->j = 5; } { /* ULTRIX-32 V3.1 (Rev 9) vcc rejects this */ const int foo = 10; if (!foo) return 0; } return !cs[0] && !zero.x; #endif ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_c_const=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_c_const=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_c_const" >&5 echo "${ECHO_T}$ac_cv_c_const" >&6; } if test $ac_cv_c_const = no; then cat >>confdefs.h <<\_ACEOF #define const _ACEOF fi { echo "$as_me:$LINENO: checking for size_t" >&5 echo $ECHO_N "checking for size_t... $ECHO_C" >&6; } if test "${ac_cv_type_size_t+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ $ac_includes_default typedef size_t ac__type_new_; int main () { if ((ac__type_new_ *) 0) return 0; if (sizeof (ac__type_new_)) return 0; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_type_size_t=yes else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_type_size_t=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_type_size_t" >&5 echo "${ECHO_T}$ac_cv_type_size_t" >&6; } if test $ac_cv_type_size_t = yes; then : else cat >>confdefs.h <<_ACEOF #define size_t unsigned int _ACEOF fi { echo "$as_me:$LINENO: checking whether struct tm is in sys/time.h or time.h" >&5 echo $ECHO_N "checking whether struct tm is in sys/time.h or time.h... $ECHO_C" >&6; } if test "${ac_cv_struct_tm+set}" = set; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ #include #include int main () { struct tm tm; int *p = &tm.tm_sec; return !p; ; return 0; } _ACEOF rm -f conftest.$ac_objext if { (ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval "echo \"\$as_me:$LINENO: $ac_try_echo\"") >&5 (eval "$ac_compile") 2>conftest.er1 ac_status=$? grep -v '^ *+' conftest.er1 >conftest.err rm -f conftest.er1 cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 (exit $ac_status); } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then ac_cv_struct_tm=time.h else echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_cv_struct_tm=sys/time.h fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { echo "$as_me:$LINENO: result: $ac_cv_struct_tm" >&5 echo "${ECHO_T}$ac_cv_struct_tm" >&6; } if test $ac_cv_struct_tm = sys/time.h; then cat >>confdefs.h <<\_ACEOF #define TM_IN_SYS_TIME 1 _ACEOF fi # Checks for library functions. for ac_func in strcasecmp stricmp do as_ac_var=`echo "ac_cv_func_$ac_func" | $as_tr_sh` { echo "$as_me:$LINENO: checking for $ac_func" >&5 echo $ECHO_N "checking for $ac_func... $ECHO_C" >&6; } if { as_var=$as_ac_var; eval "test \"\${$as_var+set}\" = set"; }; then echo $ECHO_N "(cached) $ECHO_C" >&6 else cat >conftest.$ac_ext <<_ACEOF /* confdefs.h. */ _ACEOF cat confdefs.h >>conftest.$ac_ext cat >>conftest.$ac_ext <<_ACEOF /* end confdefs.h. */ /* Define $ac_func to an innocuous variant, in case declares $ac_func. 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See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __DEPS_H__ #define __DEPS_H__ void deps_init(void); void deps_add(char *file_name); void deps_close(void); #endif gputils-0.13.7/gpasm/directive.c0000644000175000017500000032045211156521302013445 00000000000000/* Implements directives, pseudo-ops and processor opcodes Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "directive.h" #include "evaluate.h" #include "parse.h" #include "processor.h" #include "lst.h" #include "macro.h" #include "coff.h" #include "gperror.h" #include "special.h" #include "gpcfg.h" /* Forward declarations */ void execute_body(struct macro_head *h); #define ATTRIB_COND 1 /************************************************************************/ /* create flags that control the behavior of the table macros like data, * dt,de, and dw */ #define DEFAULT_LIT_MASK 0xffff #define ENDIAN_SWAP (1<<31) #define PACKING_BYTES (1<<30) #define SPLIT_PACK (1<<29) struct sllist { struct pnode *p; struct sllist *next; }; extern struct pnode *mk_constant(int value); /************************************************************************/ int _16bit_core = 0; /* The 16bit core is handled differently in * some instances. */ int _17cxx_core = 0; /* 17cxx is different from 18cxx */ /************************************************************************/ /* Write a word into the memory image at the current location */ static void emit(unsigned int value) { long byte_org = (state.org << _16bit_core); /* only write the program data to memory on the second pass */ if (state.pass == 2) { if ((state.mode == relocatable) && (state.obj.section == NULL)) { gperror(GPE_WRONG_SECTION, NULL); } if (_17cxx_core && (state.org > 0xffff)) { gperror(GPE_ADDROVF, NULL); } if(value > state.device.core_size) { gpmessage(GPM_RANGE,NULL); value &= state.device.core_size; } if (i_memory_get(state.i_memory, state.org) & MEM_USED_MASK) { gperror(GPE_ADDROVR, NULL); } if ((SECTION_FLAGS & STYP_TEXT) && (state.maxrom >= 0)) { if (byte_org > state.maxrom) { gpwarning(GPW_EXCEED_ROM, NULL); } else { /* check if current org is within a bad address range */ struct range_pair *cur_badrom; for (cur_badrom = state.badrom; cur_badrom != NULL; cur_badrom = cur_badrom->next) { if ((byte_org >= cur_badrom->start) && (byte_org <= cur_badrom->end)) { gpwarning(GPW_EXCEED_ROM, NULL); break; } } } } i_memory_put(state.i_memory, state.org, MEM_USED_MASK | value); } state.org++; } int endian_swap_word(int x) { return ( ( (x>>8) & 0xff) | ( (x<<8) & 0xff00)); } /* Write a word to memory unless we're packing successive bytes into a word * * The static variable 'packed_hi_lo' acts both as a flag and a shift amount. * when it's zero, the next byte to be emitted is packed into the low byte * of the word. When it is 8, the next byte is packed into high byte of the * word. This variable is used in conjunction with the data( ) routine. * * The static variable 'packed_byte' is the word into which two bytes are * packed. When two bytes are packed, then the word is emitted. */ int packed_hi_lo = 0; static int packed_byte = 0; gp_boolean _16packed_byte_acc; static void emit_packed(unsigned int value, unsigned int mode) { if(value > 255) { gpwarning(GPW_RANGE,NULL); value &= 0xff; } packed_byte |= (value << packed_hi_lo); if(packed_hi_lo) { if(mode & ENDIAN_SWAP) packed_byte = endian_swap_word(packed_byte); emit( packed_byte); packed_hi_lo = packed_byte = 0; } else packed_hi_lo = 8; } static int off_or_on(struct pnode *p) { int had_error = 0, ret = 0; if (p->tag != symbol) had_error = 1; else if (strcasecmp(p->value.symbol, "OFF") == 0) ret = 0; else if (strcasecmp(p->value.symbol, "ON") == 0) ret = 1; else had_error = 1; if (had_error) gperror(GPE_EXPECTED, "Expected \"ON\" or \"OFF\"."); return ret; } static void data(struct sllist *L, int flavor, int lit_mask) { if(state.obj.section) state.obj.section->emitted_pack_byte = false; if (L) { struct sllist *list,*previous; int value; list = L->next; while(list) { value = reloc_evaluate(list->p, RELOCT_ALL); if(lit_mask & PACKING_BYTES) { if(!_16packed_byte_acc) emit_packed(value | flavor, lit_mask); else { if (state.pass == 2) { /* read what's in the current org - pack our byte with it using emit() directly */ i_memory_put(state.i_memory, state.org - 1, (i_memory_get(state.i_memory, state.org - 1) & ~0xff00) | (value << 8)); } /* reset status */ _16packed_byte_acc = false; if(state.obj.section) { state.obj.section->have_pack_byte = false; state.obj.section->emitted_pack_byte = true; } } } else { if((value > lit_mask) || (value < 0)) { gpwarning(GPW_RANGE,NULL); } if(lit_mask & SPLIT_PACK) { emit(value & 0xff); emit((value >> 8) & 0xff); } else { emit((value & lit_mask) | flavor); } } previous = list; list = list->next; free(previous); } } if(packed_hi_lo) { if(!(state.obj.new_sec_flags & STYP_BPACK)) { emit_packed(flavor, lit_mask); } else { /* * still pad, but do so with 0xff (to match mplab), it will be * overwritten if there is more db data. */ emit_packed(flavor | 0xff, lit_mask); _16packed_byte_acc = true; if(state.obj.section) state.obj.section->have_pack_byte = true; } } } /* If we convert to glib, we can use the built in library call g_slist_append */ struct sllist *sllist_append(struct sllist *list, struct pnode *p) { struct sllist *new; new = malloc(sizeof(*new)); new->p = p; new->next = NULL; list->next = new; return(new); } /* convert an expression list which may consist of strings, constants, labels, * etc. into a singly linked list of integers. * This is called by the db,dw,dt,de, and data directives. * * pnode *L - A pointer to a doubly-linked list containing all of the * expressions. * sllist *list - A pointer to a singly-linked list into which we will place * the integer values of the expressions. * packing_strings - A flag indicating that char strings should be packed two to * a word. Note that this applies to only the da, dw, and data * directives. The db directive does the byte packing later. */ static void simplify_data(struct pnode *L, struct sllist *list, int packing_strings) { if (L) { struct pnode *p; unsigned int v = 0; unsigned int shift; int value; p = HEAD(L); if (p->tag == string) { char *pc = p->value.string; if(packing_strings == 2) { shift = 7; } else { shift = 8; } while (*pc) { pc = convert_escape_chars(pc, &value); if(packing_strings) { if(v>= (1<<31) ) { v = (v<= 1<<31 ) { v = v <mode = in_then; new->prev = state.astack; if (state.astack == NULL) new->prev_enabled = 1; else new->prev_enabled = state.astack->enabled && state.astack->prev_enabled; new->enabled = 0; /* Only the default */ state.astack = new; } /* Checking that a macro definition's parameters are correct */ static int macro_parms_simple(struct pnode *parms) { if (parms == NULL) { return 1; } else if (HEAD(parms)->tag != symbol) { gperror(GPE_ILLEGAL_ARGU, NULL); return 0; } else { return (macro_parms_simple(TAIL(parms))); } } static int list_symbol_member(struct pnode *M, struct pnode *L) { if (L == NULL) { return 0; } else if (STRCMP(M->value.symbol, HEAD(L)->value.symbol) == 0) { char buf[BUFSIZ]; snprintf(buf, sizeof(buf), "Duplicate macro parameter (%s).", HEAD(L)->value.symbol); gperror(GPE_UNKNOWN, buf); return 1; } else { return list_symbol_member(M, TAIL(L)); } } static int macro_parms_unique(struct pnode *parms) { if (parms == NULL) return 1; else return (!list_symbol_member(HEAD(parms), TAIL(parms)) && macro_parms_unique(TAIL(parms))); } static int macro_parms_ok(struct pnode *parms) { return (macro_parms_simple(parms) && macro_parms_unique(parms)); } typedef gpasmVal opfunc(gpasmVal r, char *name, int arity, struct pnode *parms); /************************************************************************/ static gpasmVal do_badram(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; for (; parms != NULL; parms = TAIL(parms)) { p = HEAD(parms); if ((p->tag == binop) && (p->value.binop.op == '-')) { int start, end; if (can_evaluate(p->value.binop.p0) && can_evaluate(p->value.binop.p1)) { start = evaluate(p->value.binop.p0); end = evaluate(p->value.binop.p1); if ((end < start) || (start < 0) || (MAX_RAM <= end)) { gpwarning(GPW_INVALID_RAM, NULL); } else { for (; start <= end; start++) state.badram[start] = 1; } } } else { if (can_evaluate(p)) { int loc; loc = evaluate(p); if ((loc < 0) || (MAX_RAM <= loc)) { gpwarning(GPW_INVALID_RAM, NULL); } else state.badram[loc] = 1; } } } return r; } static gpasmVal do_badrom(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; /* FIXME: implement this directive */ gpwarning(GPW_UNKNOWN, "gpasm doesn't support the badrom directive yet"); return r; } static void set_bankisel(int address) { if (state.device.class == PROC_CLASS_PIC14) { if (address < 0x100) { /* bcf 0x3, 0x7 */ emit(0x1383); } else { /* bsf 0x3, 0x7 */ emit(0x1783); } } else { /* movlb bank */ emit(0xb800 | gp_processor_check_bank(state.device.class, address)); } } static gpasmVal do_bankisel(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int num_reloc; if ((state.device.class != PROC_CLASS_PIC14) && (state.device.class != PROC_CLASS_PIC16)) { gpmessage(GPM_EXTPAGE, NULL); return r; } if (enforce_arity(arity, 1)) { p = HEAD(parms); if (state.mode == absolute) { set_bankisel(maybe_evaluate(p)); } else { num_reloc = count_reloc(p); if (num_reloc == 0) { /* it is an absolute address, generate the bankisel but no relocation */ set_bankisel(maybe_evaluate(p)); } else if (num_reloc != 1) { gperror(GPE_UNRESOLVABLE, NULL); } else { reloc_evaluate(p, RELOCT_IBANKSEL); emit(0); } } } return r; } static gpasmVal do_banksel(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int address; int bank; int num_reloc; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (state.mode == absolute) { address = maybe_evaluate(p); bank = gp_processor_check_bank(state.device.class, address); state.org += gp_processor_set_bank(state.device.class, state.processor_info->num_banks, bank, state.i_memory, state.org); } else { num_reloc = count_reloc(p); if (num_reloc == 0) { /* it is an absolute address, generate the banksel but no relocation */ address = maybe_evaluate(p); bank = gp_processor_check_bank(state.device.class, address); state.org += gp_processor_set_bank(state.device.class, state.processor_info->num_banks, bank, state.i_memory, state.org); } else if (num_reloc != 1) { gperror(GPE_UNRESOLVABLE, NULL); } else if (state.device.class == PROC_CLASS_PIC16) { reloc_evaluate(p, RELOCT_BANKSEL); emit(0); } else if (state.device.class == PROC_CLASS_PIC16E) { reloc_evaluate(p, RELOCT_BANKSEL); emit(0); } else { switch (state.processor_info->num_banks) { case 2: reloc_evaluate(p, RELOCT_BANKSEL); emit(0); break; case 4: reloc_evaluate(p, RELOCT_BANKSEL); emit(0); emit(0); break; } } } } return r; } static gpasmVal do_code(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = sec; state.next_state = state_section; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".code", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_TEXT; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".code", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p) >> _16bit_core; state.obj.new_sec_flags = STYP_TEXT | STYP_ABS; break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_code_pack(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; if(!_16bit_core) gperror(GPE_UNKNOWN, "code_pack is only supported on 16bit cores"); else { state.lst.line.linetype = sec; state.next_state = state_section; _16packed_byte_acc = false; if(state.obj.section) { state.obj.section->have_pack_byte = false; state.obj.section->emitted_pack_byte = false; } if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".code", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_TEXT | STYP_BPACK; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".code", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p) >> _16bit_core; state.obj.new_sec_flags = STYP_TEXT | STYP_ABS | STYP_BPACK; break; default: enforce_arity(arity, 1); } } } return r; } static gpasmVal do_constant(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int value; state.lst.line.linetype = dir; for (; parms; parms = TAIL(parms)) { p = HEAD(parms); if ((p->tag == binop) && (p->value.binop.op == '=')) { if (enforce_simple(p->value.binop.p0)) { char *lhs; /* fetch the symbol */ lhs = p->value.binop.p0->value.symbol; /* constants must be assigned a value at declaration */ value = maybe_evaluate(p->value.binop.p1); /* put the symbol and value in the table*/ set_global(lhs, value, PERMANENT, gvt_constant); } } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } /*------------------------------------------------------------------------- * * configuration memory * * In addition to memory for storing instructions, each pic has memory for * storing configuration data (e.g. code protection, wdt enable, etc.). Each * family of the pic microcontrollers treats this memory slightly different. * * do_config( ) - Called by the parser when a __CONFIG assembler directive * is encountered. * * do_16_config( ) - Called by the parser to process MPASM style CONFIG xx=yy * directives for 16 bit devices. */ static gp_boolean config_us_used; static gp_boolean config_16_used; /* * creates the configuration or device id COFF section for do_config and * do_16_config. returns true when a section is created. */ static gp_boolean config_add_section(int ca) { if (state.mode == relocatable) { if ((!state.found_devid) && ((ca == DEVID1) || (ca == DEVID2))) { coff_new_section(".devid", ca >> _16bit_core, STYP_ABS | STYP_TEXT); state.found_devid = true; return true; } else if (!state.found_config) { coff_new_section(".config", state.processor_info->config_addrs[0] >> _16bit_core, STYP_ABS | STYP_TEXT); state.found_config = true; return true; } } return false; } static gpasmVal do_config(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int ca; int value; config_us_used = true; if(config_16_used) { gperror(GPE_CONFIG_usCONFIG, NULL); return r; } state.lst.line.linetype = config; switch(arity) { case 1: if(_16bit_core) { gpwarning(GPW_EXPECTED,"18cxxx devices should specify __CONFIG address"); } ca = state.processor_info->config_addrs[0]; p = HEAD(parms); break; case 2: ca = maybe_evaluate(HEAD(parms)); p = HEAD(TAIL(parms)); break; default: enforce_arity(arity,2); return r; } state.lst.config_address = ca; config_add_section(ca); if ((can_evaluate(p)) && (state.pass == 2)) { value = evaluate(p); if(_16bit_core) { int curval = i_memory_get(state.c_memory, ca>>1); int mask = 0xff <<((ca&1) ? 0 : 8); if(value > 0xff) { gpwarning(GPW_RANGE,0); } /* If the config address is even, then this byte goes in LSB position */ value = (value & 0xff) << ((ca&1) ? 8 : 0) | MEM_USED_MASK; if(curval & MEM_USED_MASK) curval &= mask; else curval |= mask; i_memory_put(state.c_memory, ca>>1, curval | value); } else { if(value > state.device.core_size) { gpmessage(GPM_RANGE,NULL); value &= state.device.core_size; } if (i_memory_get(state.c_memory, ca) & MEM_USED_MASK) { gperror(GPE_ADDROVR, NULL); } i_memory_put(state.c_memory, ca, MEM_USED_MASK | value); /* FIXME: need line_number? this one will be wrong coff_linenum(1) */ } /* force the section to end */ state.obj.section = NULL; } return r; } /* helper to write configuration data, grabbing defaults when necessary */ static void config_16_set_mem(const struct gp_cfg_device *p_dev, int ca, unsigned char byte, unsigned char mask) { int new_val, cur_val = i_memory_get(state.c_memory, ca / 2); unsigned char cd = gp_cfg_get_default(p_dev, ca); if (ca & 1) { unsigned char fill_val = gp_cfg_get_default(p_dev, ca - 1); if (!(cur_val & MEM_USED_MASK)) cur_val = (cd << 8) | fill_val; new_val = (cur_val & ~((int)mask << 8)) | (byte << 8) | MEM_USED_MASK; } else { unsigned char fill_val = gp_cfg_get_default(p_dev, ca + 1); if (!(cur_val & MEM_USED_MASK)) cur_val = (fill_val << 8) | cd; new_val = (cur_val & ~((int)mask)) | (byte) | MEM_USED_MASK; } /* write the new config word */ i_memory_put(state.c_memory, ca / 2, new_val); } /* Sets defaults over unused portions of configuration memory. */ static void config_16_check_defaults(const struct gp_cfg_device *p_dev) { const struct gp_cfg_addr *addrs = p_dev->config_addrs; int t; /* * if we don't set defaults here, then MPLINK (I'm assuming) will pad the * entire section with 0xff. That puts the 0xff's in the hex file. MPASM puts * nothing in the hex file for unspecified bytes. I'm not sure the best * approach here - defaults or nothing. going to go with defaults. * * if this is commented out, the calls to config_16_set_mem below _will_ * use defaults for adjacent values. */ for(t=0; taddr_count; addrs++, t++) { if(!(i_memory_get(state.c_memory, addrs->addr / 2) & MEM_USED_MASK)) { config_16_set_mem(p_dev, addrs->addr, addrs->defval, 0xff); } } } /* Support MPASM style CONFIG xxx = yyy syntax. */ static gpasmVal _do_16_config(gpasmVal r, char *name, int arity, struct pnode *parms) { static unsigned char double_mask[64]; const struct gp_cfg_device *p_dev; const struct gp_cfg_directive *p_dir; const struct gp_cfg_option *p_opt; const char *k_str, *v_str; struct pnode *k, *v; char v_buff[64]; int ca; state.lst.line.linetype = config; config_16_used = true; if (config_us_used) { gperror(GPE_CONFIG_usCONFIG, NULL); return r; } /* make sure we an find our device in the config DB */ p_dev = gp_cfg_find_pic_multi(sizeof(state.processor_info->names) / sizeof(*state.processor_info->names), state.processor_info->names); if (!p_dev) { gperror(GPE_UNKNOWN, "the selected processor has no entries in the config db. CONFIG cannot be used."); return r; } /* validate argument format */ if (!parms || parms->tag != binop || parms->value.binop.op != '=') { gperror(GPE_CONFIG_UNKNOWN, "incorrect syntax. use `CONFIG KEY = VALUE'"); return r; } /* validate parameter types */ k = parms->value.binop.p0; v = parms->value.binop.p1; if (k->tag != symbol || (v->tag != symbol && v->tag != constant)) { gperror(GPE_CONFIG_UNKNOWN, "incorrect syntax. use `CONFIG KEY = VALUE'"); return r; } /* grab string representations */ k_str = k->value.symbol; if (v->tag != constant) v_str = v->value.symbol; else { int value = v->value.constant; if (state.radix != 10) { if (state.radix == 16) { snprintf(v_buff, sizeof(v_buff), "%x", value); } else { gperror(GPE_CONFIG_UNKNOWN, "CONFIG can't be used in source files with a radix other than 10 or 16"); } } else { snprintf(v_buff, sizeof(v_buff), "%d", value); } v_str = v_buff; } /* find the directive */ p_dir = gp_cfg_find_directive(p_dev, k_str, &ca, NULL); if (!p_dir) { gperror(GPE_CONFIG_UNKNOWN, "CONFIG Directive Error: (setting not found for selected processor)"); return r; } /* note address to lister, though it doesn't seem to use it */ state.lst.config_address = ca; /* find the option */ p_opt = gp_cfg_find_option(p_dir, v_str); if (!p_opt) { gperror(GPE_CONFIG_UNKNOWN, "CONFIG Directive Error: (specified value not valid for directive)"); return r; } /* make sure the section exists ... */ config_add_section(ca); config_16_check_defaults(p_dev); /* emit the bytes if appropriate */ if (state.pass == 2) { unsigned char dm_addr = (unsigned char)(ca - p_dev->config_addrs->addr); /* make sure we've not written here yet */ if (dm_addr < sizeof(double_mask)) { if (double_mask[dm_addr] & p_dir->mask) { gperror(GPE_CONFIG_UNKNOWN, "CONFIG Directive Error: (multiple definitions found for setting)"); return r; } double_mask[dm_addr] |= p_dir->mask; } else { gpwarning(GPW_UNKNOWN, "double_mask in do_16_config() needs to be adjusted to account for larger config ranges"); } /* let the helper set the data. */ config_16_set_mem(p_dev, ca, p_opt->byte, p_dir->mask); } return r; } static gpasmVal do_16_config(gpasmVal r, char *name, int arity, struct pnode *parms) { for (; parms != NULL; parms = TAIL(parms)) { struct pnode *p = HEAD(parms); _do_16_config(r, name, arity, p); } return r; } /*------------------------------------------------------------------------- * do_da - The 'da' directive. Generates a number representing two * 7 bit ascii characters. It can be used in place of the DATA * directive for 14 bit cores to pack two characters into one * word. */ static gpasmVal do_da(gpasmVal r, char *name, int arity, struct pnode *parms) { struct sllist list; list.next = NULL; if(_16bit_core || state.device.core_size == CORE_12BIT_MASK) { simplify_data(parms, &list, 1); } else { simplify_data(parms, &list, 2); } data(&list, 0, DEFAULT_LIT_MASK); return r; } /*------------------------------------------------------------------------- * do_data - The 'data' directive. Initialize one or more words of program * memory with data. On all families except the pic18cxxx, the * first character is in the most significant byte of the word. */ static gpasmVal do_data(gpasmVal r, char *name, int arity, struct pnode *parms) { struct sllist list; list.next = NULL; simplify_data(parms, &list, 1); if ((state.mode == relocatable) && !(SECTION_FLAGS & STYP_TEXT)) { /* This is a data memory not program */ state.lst.line.linetype = res; /* data memory is byte sized so split the data */ data(&list, 0, SPLIT_PACK); } else { data(&list, 0, DEFAULT_LIT_MASK); } return r; } /*------------------------------------------------------------------------- * do_db - Reserve program memory words with packed 8-bit values. On the * 18cxxx families, dw and db are the same. For the 12 and 14 bit * cores, the upper bits are masked (e.g. the 14-bit core can only * store 14bits at a given program memory address, so the upper 2 * in a db directive are meaningless. */ static gpasmVal do_db(gpasmVal r, char *name, int arity, struct pnode *parms) { struct sllist list; list.next = NULL; simplify_data(parms, &list,0); if ((state.mode == relocatable) && !(SECTION_FLAGS & STYP_TEXT)) { /* This is a data memory not program */ state.lst.line.linetype = res; /* only valid in initialized data sections */ if (SECTION_FLAGS & STYP_BSS) gperror(GPE_WRONG_SECTION, NULL); data(&list, 0, 0xff); } else { if(_16bit_core) { data(&list, 0, PACKING_BYTES); } else { data(&list, 0, ENDIAN_SWAP | PACKING_BYTES); } } return r; } static gpasmVal do_de(gpasmVal r, char *name, int arity, struct pnode *parms) { struct sllist list; list.next = NULL; simplify_data(parms, &list,0); if(_16bit_core) { data(&list, 0, PACKING_BYTES); } else { data(&list, 0, 0xff); } return r; } static gpasmVal do_def(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; char *symbol_name = NULL; gp_symbol_type *coff_symbol = NULL; int shift = 0; int eval; int value = 0; gp_boolean new_class = false; int coff_class = C_NULL; gp_boolean new_type = false; int coff_type = T_NULL; enum gpasmValTypes type = gvt_debug; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { if (arity < 2) { enforce_arity(arity, 2); return r; } /* the first argument is the symbol name */ p = HEAD(parms); if (enforce_simple(p)) { symbol_name = p->value.symbol; } else { return r; } parms = TAIL(parms); if ((SECTION_FLAGS & STYP_TEXT) && _16bit_core) { shift = 1; } /* update the properties */ for (; parms; parms = TAIL(parms)) { p = HEAD(parms); if ((p->tag == binop) && (p->value.binop.op == '=')) { if (enforce_simple(p->value.binop.p0)) { char *lhs; lhs = p->value.binop.p0->value.symbol; if (strcasecmp(lhs, "value") == 0) { value = maybe_evaluate(p->value.binop.p1); } else if (strcasecmp(lhs, "size") == 0) { state.org += (maybe_evaluate(p->value.binop.p1) >> shift); } else if (strcasecmp(lhs, "type") == 0) { eval = maybe_evaluate(p->value.binop.p1); if ((eval < 0) || (eval > 0xffff)) { gperror(GPE_RANGE, NULL); } else { new_type = true; coff_type = eval; } } else if (strcasecmp(lhs, "class") == 0) { eval = maybe_evaluate(p->value.binop.p1); if ((eval < -128) || (eval > 127)) { gperror(GPE_RANGE, NULL); } else { new_class = true; coff_class = eval; } } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } } else { if (enforce_simple(p)) { if (strcasecmp(p->value.symbol, "absolute") == 0) { type = gvt_absolute; value = 0; } else if (strcasecmp(p->value.symbol, "debug") == 0) { type = gvt_debug; value = 0; } else if (strcasecmp(p->value.symbol, "extern") == 0) { type = gvt_extern; value = 0; } else if (strcasecmp(p->value.symbol, "global") == 0) { type = gvt_global; value = state.org << shift; } else if (strcasecmp(p->value.symbol, "static") == 0) { type = gvt_static; value = state.org << shift; } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } } } } set_global(symbol_name, value, PERMANENT, type); /* update the symbol with the values */ if ((state.pass == 2) && (new_class || new_type)) { coff_symbol = gp_coffgen_findsymbol(state.obj.object, symbol_name); assert(coff_symbol != NULL); if (new_class) coff_symbol->class = coff_class; if (new_type) coff_symbol->type = coff_type; } return r; } static gpasmVal do_define(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; struct symbol *current_definition; if (arity < 1) { /* FIXME: find a more elegant way to do this */ state.pass = 2; gperror(GPE_MISSING_ARGU, NULL); exit(1); } assert(arity <= 2); p = HEAD(parms); if (p->tag == string) { if((asm_enabled()) && (!state.mac_prev)) { if ((get_symbol(state.stDefines, p->value.string) != NULL) && (state.pass == 1)) { /* FIXME: find a more elegant way to do this */ state.pass = 2; gperror(GPE_DUPLAB, NULL); exit(1); } current_definition = add_symbol(state.stDefines, p->value.string); if (TAIL(parms)) { struct pnode *p2 = HEAD(TAIL(parms)); assert(p2->tag == string); annotate_symbol(current_definition, strdup(p2->value.string)); } } } return r; } static gpasmVal do_dim(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; char *symbol_name = NULL; gp_symbol_type *coff_symbol = NULL; int number_symbols; gp_aux_type *aux_list; struct sllist first_list; struct sllist *list = &first_list; struct sllist *previous; int i; int value; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { if (arity < 3) { enforce_arity(arity, 1); return r; } /* the first argument is the symbol name */ p = HEAD(parms); if (enforce_simple(p)) { /* lookup the symbol */ symbol_name = p->value.symbol; coff_symbol = gp_coffgen_findsymbol(state.obj.object, symbol_name); if (coff_symbol == NULL) { gperror(GPE_NOSYM, NULL); return r; } } else { return r; } parms = TAIL(parms); /* the second argument must be the number of aux symbols */ p = HEAD(parms); number_symbols = maybe_evaluate(p); if ((number_symbols < 0) || (number_symbols > 127)) { gperror(GPE_UNKNOWN, "number of auxiliary symbols must be less then 128 and positive"); return r; } state.obj.symbol_num += number_symbols; parms = TAIL(parms); /* create the symbols */ aux_list = gp_coffgen_blockaux(number_symbols); coff_symbol->num_auxsym = number_symbols; coff_symbol->aux_list = aux_list; /* convert the arguments into a list of values */ list->next = NULL; simplify_data(parms, list, 0); /* write the data to the auxiliary symbols */ list = list->next; i = 0; while(list) { value = maybe_evaluate(list->p); if (value & (~0xff)) { gperror(GPE_RANGE, NULL); return r; } if (aux_list == NULL) { gperror(GPE_UNKNOWN, "insufficent number of auxiliary symbols"); return r; } if (i == (state.obj.newcoff ? SYMBOL_SIZE_v2 : SYMBOL_SIZE_v1)) { i = 0; aux_list = aux_list->next; } else { aux_list->_aux_symbol.data[i++] = value; } previous = list; list = list->next; free(previous); } } return r; } static gpasmVal do_direct(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int value; unsigned char direct_command = 0; char *direct_string = NULL; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else if (enforce_arity(arity, 2)) { p = HEAD(parms); coerce_str1(p); value = maybe_evaluate(p); if ((value < 0) || (value > 255)) { gperror(GPE_RANGE, NULL); } else { direct_command = value; } p= HEAD(TAIL(parms)); if (p->tag == string) { if (strlen(p->value.string) < 255) { direct_string = convert_escaped_char(p->value.string,'"'); } else { gperror(GPE_UNKNOWN, "string must be less than 255 bytes long"); } } else { gperror(GPE_ILLEGAL_ARGU, NULL); } if (direct_string == NULL) { return r; } if (SECTION_FLAGS & STYP_TEXT) { coff_add_directsym(direct_command, direct_string); } else { gperror(GPE_WRONG_SECTION, NULL); } } return r; } static gpasmVal do_dt(gpasmVal r, char *name, int arity, struct pnode *parms) { struct symbol *s; struct insn *i; struct sllist list; s = get_symbol(state.stBuiltin, "RETLW"); assert(s != NULL); /* Every PIC has a RETLW instruction */ i = get_symbol_annotation(s); list.next = NULL; simplify_data(parms, &list, 0); data(&list, i->opcode, 0xff); return r; } /*------------------------------------------------------------------------- * do_dw - The 'dw' directive. On all families except for the p18cxxx, the * dw directive is the same as the 'data' directive. For the p18cxxx * it's the same as the 'db' directive. (That's strange, but it's * also the way mpasm does it). */ static gpasmVal do_dw(gpasmVal r, char *name, int arity, struct pnode *parms) { struct sllist list; list.next = NULL; simplify_data(parms, &list, 1); if ((state.mode == relocatable) && !(SECTION_FLAGS & STYP_TEXT)) { /* This is a data memory not program */ state.lst.line.linetype = res; /* only valid in initialized data sections */ if (SECTION_FLAGS & STYP_BSS) gperror(GPE_WRONG_SECTION, NULL); /* data memory is byte sized so split the data */ data(&list, 0, SPLIT_PACK); } else { data(&list, 0, DEFAULT_LIT_MASK); } return r; } static gpasmVal do_else(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (state.astack == NULL) gperror(GPE_ILLEGAL_COND, NULL); else if ((state.astack->mode != in_then)) gperror(GPE_ILLEGAL_COND, NULL); else state.astack->enabled = !state.astack->enabled; return r; } static gpasmVal do_endif(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (state.astack == NULL) { gperror(GPE_ILLEGAL_COND, "Illegal condition (ENDIF)."); } else if ((state.astack->mode != in_then) && (state.astack->mode != in_else)) { gperror(GPE_ILLEGAL_COND, "Illegal condition (ENDIF)."); } else { struct amode *old; old = state.astack; state.astack = state.astack->prev; free(old); } return r; } static gpasmVal do_endm(gpasmVal r, char *name, int arity, struct pnode *parms) { assert(!state.mac_head); state.lst.line.linetype = dir; if (state.mac_prev == NULL) gperror(GPE_UNMATCHED_ENDM, NULL); else state.mac_prev = NULL; state.mac_body = NULL; return r; } static gpasmVal do_endw(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; assert(!state.mac_head); if (state.mac_prev == NULL) { gperror(GPE_ILLEGAL_COND, "Illegal condition (ENDW)."); } else if (maybe_evaluate(state.while_head->parms)) { state.next_state = state_while; state.next_buffer.macro = state.while_head; } state.mac_body = NULL; state.mac_prev = NULL; state.while_head = NULL; return r; } static gpasmVal do_eof(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else if (enforce_arity(arity, 0)) { if (state.debug_info) { coff_add_eofsym(); } else { gpwarning(GPW_UNKNOWN, "directive ignored when debug info is disabled"); } } return r; } static gpasmVal do_equ(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = equ; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (can_evaluate(p)) r = evaluate(p); else r = 0; } return r; } static gpasmVal do_error(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == string) { gperror(GPE_USER, p->value.string); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } /************************************************************************ * do_errlvl - parse the ERRORLEVEL directive * * If the file gpasm is assembling contains a ERRORLEVEL directive, then scan * the comma delimited list of options in *parms * * Inputs: * gpasmVal r - not used, but is returned * char *name - not used, but contains the directive name 'list'. * int arity - not used, but should contain '1' * struct pnode *parms - a linked list of the parsed parameters * * * ************************************************************************/ static gpasmVal do_errlvl(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (state.pass == 2) { for (; parms; parms = TAIL(parms)) { p = HEAD(parms); if (p->tag == unop) { gpasmVal value = evaluate(p->value.unop.p0); if (p->value.unop.op == '-') { add_code(-value); } else if (p->value.unop.op == '+') { add_code(value); } else { gperror(GPE_ILLEGAL_ARGU, "Expected 0, 1, 2, +|-"); } } else if (p->tag == constant) { select_errorlevel(p->value.constant); } else { gperror(GPE_ILLEGAL_ARGU, "Expected 0, 1, 2, +|-"); } } } return r; } static gpasmVal do_exitm(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (enforce_arity(arity, 0)) { if (state.stGlobal == state.stTop) { gperror(GPE_UNKNOWN, "Attempt to use \"exitm\" outside of macro"); } else { state.next_state = state_exitmacro; } } return r; } static gpasmVal do_expand(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (state.cmd_line.macro_expand) { gpmessage(GPM_SUPLIN, NULL); } else { if (enforce_arity(arity, 0)) { state.lst.expand = true; } } return r; } static gpasmVal do_extern(gpasmVal r, char *name, int arity, struct pnode *parms) { char *p; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { for (; parms; parms = TAIL(parms)) { p = maybe_evaluate_concat(HEAD(parms)); if (p) { set_global(p, 0, PERMANENT, gvt_extern); } } } return r; } static gpasmVal do_file(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else if (enforce_arity(arity, 1)) { if (state.debug_info) { p = HEAD(parms); if (p->tag == string) { state.obj.debug_file = coff_add_filesym(p->value.string, 0); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } else { gpwarning(GPW_UNKNOWN, "directive ignored when debug info is disabled"); } } return r; } /* Filling constants is handled here. Filling instructions is handled in the parser. */ static gpasmVal do_fill(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *h; int number; int i; if (enforce_arity(arity, 2)) { h = HEAD(parms); number = eval_fill_number(HEAD(TAIL(parms))); for (i = 1; i <= number ; i += 1) { /* we must evaluate each loop, because some symbols change (i.e. $) */ emit(maybe_evaluate(h)); } } return r; } static gpasmVal do_global(gpasmVal r, char *name, int arity, struct pnode *parms) { char *p; char buf[BUFSIZ]; struct symbol *s; struct variable *var; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { for (; parms; parms = TAIL(parms)) { p = maybe_evaluate_concat(HEAD(parms)); if (p) { s = get_symbol(state.stTop, p); if (s == NULL) { snprintf(buf, sizeof(buf), "Symbol not previously defined (%s).", p); gperror(GPE_NOSYM, buf); } else { var = get_symbol_annotation(s); if (var == NULL) { snprintf(buf, sizeof(buf), "Symbol not assigned a value (%s).", p); gpwarning(GPW_UNKNOWN, buf); } else { if ((var->previous_type == gvt_address) || (var->previous_type == gvt_global) || (var->previous_type == gvt_static)) { /* make the symbol global */ var->type = gvt_global; } else if (var->previous_type == gvt_extern) { gperror(GPE_DUPLAB, NULL); } else { snprintf(buf, sizeof(buf), "Operand must be an address label (%s).", p); gperror(GPE_MUST_BE_LABEL, buf); } } } } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } } return r; } static gpasmVal do_idata(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = sec; state.next_state = state_section; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".idata", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_DATA; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".idata", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p); state.obj.new_sec_flags = STYP_DATA | STYP_ABS; break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_ident(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == string) { coff_add_identsym(p->value.string); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_idlocs(gpasmVal r, char *name, int arity, struct pnode *parms) { int value; int idreg; int curvalue; int mask; if (_17cxx_core) { gperror(GPE_ILLEGAL_DIR, NULL); return r; } if (_16bit_core) { if (enforce_arity(arity,2)) { idreg = maybe_evaluate(HEAD(parms)); value = maybe_evaluate(HEAD(TAIL(parms))); } else { gperror(GPW_EXPECTED,"18cxxx devices should specify __IDLOC address"); return r; } } else { if (enforce_arity(arity,1)) { idreg = state.device.id_location; value = maybe_evaluate(HEAD(parms)); } else { return r; } } if ((state.mode == relocatable) && (!state.found_idlocs)) { coff_new_section(".idlocs", idreg >> _16bit_core, STYP_ABS | STYP_TEXT); state.found_idlocs = true; } state.lst.config_address = idreg; state.device.id_location = idreg; if (state.pass == 2) { if (_16bit_core) { state.lst.line.linetype = config; if (idreg > IDLOC7 || idreg < IDLOC0) { gperror(GPE_RANGE,NULL); } else { if(value > 0xff) { gpwarning(GPW_RANGE, NULL); } curvalue = i_memory_get(state.c_memory, idreg>>1); mask = 0xff <<((idreg&1) ? 0 : 8); /* If the address is even, then this byte goes in LSB position */ value = (value & 0xff) << ((idreg&1) ? 8 : 0) | MEM_USED_MASK; if(curvalue & MEM_USED_MASK) curvalue &= mask; else curvalue |= mask; i_memory_put(state.c_memory, idreg>>1, curvalue | value); } } else { state.lst.line.linetype = idlocs; if (value > 0xffff) { gpmessage(GPM_IDLOC, NULL); value &= 0xffff; } if (i_memory_get(state.c_memory, idreg) & MEM_USED_MASK) { gperror(GPE_ADDROVR, NULL); } i_memory_put(state.c_memory, idreg, ((value & 0xf000) >> 12) | MEM_USED_MASK); i_memory_put(state.c_memory, idreg + 1, ((value & 0x0f00) >> 8) | MEM_USED_MASK); i_memory_put(state.c_memory, idreg + 2, ((value & 0x00f0) >> 4) | MEM_USED_MASK); i_memory_put(state.c_memory, idreg + 3, (value & 0x000f) | MEM_USED_MASK); } } return r; } static gpasmVal do_if(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; enter_if(); /* Only evaluate the conditional if it matters... */ if (state.astack->prev_enabled) { if (enforce_arity(arity, 1)) { p = HEAD(parms); state.astack->enabled = maybe_evaluate(p); } } return r; } static gpasmVal do_ifdef(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; enter_if(); /* Only evaluate the conditional if it matters... */ if (state.astack->prev_enabled) { if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag != symbol) { gperror(GPE_ILLEGAL_LABEL, NULL); } else { if ((get_symbol(state.stDefines, p->value.symbol)) || (get_symbol(state.stTop, p->value.symbol))) state.astack->enabled = 1; } } } return r; } static gpasmVal do_ifndef(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; enter_if(); /* Only evaluate the conditional if it matters... */ if (state.astack->prev_enabled) { if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag != symbol) { gperror(GPE_ILLEGAL_LABEL, NULL); } else { if ((!get_symbol(state.stDefines, p->value.symbol)) && (!get_symbol(state.stTop, p->value.symbol))) state.astack->enabled = 1; } } } return r; } static gpasmVal do_include(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == string) { state.next_state = state_include; state.next_buffer.file = strdup(p->value.string); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_line(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else if (enforce_arity(arity, 1)) { if (state.debug_info) { p = HEAD(parms); state.obj.debug_line = maybe_evaluate(p); } else { gpwarning(GPW_UNKNOWN, "directive ignored when debug info is disabled"); } } return r; } /************************************************************************ * do_list - parse the LIST directive * * If the file gpasm is assembling contains a LIST directive, then scan * and parse will call do_list and pass the comma delimited list of LIST * options in *parms * * Inputs: * gpasmVal r - not used, but is returned * char *name - not used, but contains the directive name 'list'. * int arity - not used, but should contain '1' * struct pnode *parms - a linked list of the parsed parameters * * * ************************************************************************/ static gpasmVal do_list(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.enabled = true; state.lst.line.linetype = dir; for (; parms; parms = TAIL(parms)) { p = HEAD(parms); if ((p->tag == binop) && (p->value.binop.op == '=')) { if (enforce_simple(p->value.binop.p0)) { char *lhs; lhs = p->value.binop.p0->value.symbol; if (strcasecmp(lhs, "b") == 0) { int b; b = maybe_evaluate(p->value.binop.p1); if (b != 0) state.lst.tabstop = b; } else if (strcasecmp(lhs, "c") == 0) { ; /* Ignore this for now: column width not used */ } else if (strcasecmp(lhs, "f") == 0) { if (enforce_simple(p->value.binop.p1)) select_hexformat(p->value.binop.p1->value.symbol); } else if (strcasecmp(lhs, "l") == 0) { ; /* Ignore this for now: page length */ } else if (strcasecmp(lhs, "m") == 0) { /* Undocumented, only found in MEMORY.INC and MCP250XX.INC. */ if (can_evaluate(p->value.binop.p1)) { int value = evaluate(p->value.binop.p1); if (value < state.maxrom) { char message[BUFSIZ]; snprintf(message, sizeof(message), "Argument out of range (must be greater than or equal to %ld)", state.maxrom); gperror(GPE_RANGE, message); } else state.maxrom = value; } } else if (strcasecmp(lhs, "mm") == 0) { state.lst.memorymap = off_or_on(p->value.binop.p1); } else if (strcasecmp(lhs, "n") == 0) { if (can_evaluate(p->value.binop.p1)) { int number = evaluate(p->value.binop.p1); if ((number > 6) || (number == 0)) { state.lst.linesperpage = number; } else { gperror(GPE_RANGE, NULL); } } } else if (strcasecmp(lhs, "p") == 0) { if (enforce_simple(p->value.binop.p1)) select_processor(p->value.binop.p1->value.symbol); } else if (strcasecmp(lhs, "pe") == 0) { state.extended_pic16e = true; if (enforce_simple(p->value.binop.p1)) select_processor(p->value.binop.p1->value.symbol); } else if (strcasecmp(lhs, "r") == 0) { if (enforce_simple(p->value.binop.p1)) select_radix(p->value.binop.p1->value.symbol); } else if (strcasecmp(lhs, "st") == 0) { state.lst.symboltable = off_or_on(p->value.binop.p1); } else if (strcasecmp(lhs, "t") == 0) { ; /* Ignore this for now: always wrap long list lines */ } else if (strcasecmp(lhs, "w") == 0) { select_errorlevel(maybe_evaluate(p->value.binop.p1)); } else if (strcasecmp(lhs, "x") == 0) { if (enforce_simple(p->value.binop.p1)) select_expand(p->value.binop.p1->value.symbol); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } } else { if (enforce_simple(p)) { if (strcasecmp(p->value.symbol, "free") == 0) { ; /* Ignore this directive */ } else if (strcasecmp(p->value.symbol, "fixed") == 0) { ; /* Ignore this directive */ } else if (strcasecmp(p->value.symbol, "nowrap") == 0) { ; /* Ignore this directive */ } else if (strcasecmp(p->value.symbol, "wrap") == 0) { ; /* Ignore this directive */ } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } } } /* The .list symbol is only added to the COFF file if its only action is to turn on the listing */ if (arity == 0) coff_add_listsym(); return r; } static gpasmVal do_local(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; /* like variable except it is put in TOP instead of GLOBAL */ if (state.stGlobal == state.stTop) { gperror(GPE_UNKNOWN, "Attempt to use \"local\" outside of macro"); } else { for (; parms; parms = TAIL(parms)) { p = HEAD(parms); if ((p->tag == binop) && (p->value.binop.op == '=')) { if (enforce_simple(p->value.binop.p0)) { char *lhs; gpasmVal value; /* fetch the symbol */ lhs = p->value.binop.p0->value.symbol; value = maybe_evaluate(p->value.binop.p1); /* put the symbol and value in the TOP table*/ add_symbol(state.stTop, lhs); set_global(lhs, value, TEMPORARY, gvt_constant); } } else if (p->tag == symbol) { /* put the symbol in the Top table */ add_symbol(state.stTop, p->value.symbol); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } } return r; } static gpasmVal do_noexpand(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (state.cmd_line.macro_expand) { gpmessage(GPM_SUPLIN, NULL); } else { if (enforce_arity(arity, 0)) { state.lst.expand = false; } } return r; } static gpasmVal do_nolist(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (!state.lst.force) state.lst.enabled = false; coff_add_nolistsym(); return r; } static gpasmVal do_maxram(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (can_evaluate(p)) state.maxram = evaluate(p); } return r; } static gpasmVal do_maxrom(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (can_evaluate(p)) state.maxrom = evaluate(p); } return r; } static gpasmVal do_macro(gpasmVal r, char *name, int arity, struct pnode *parms) { struct macro_head *head = malloc(sizeof(*head)); head->parms = parms; head->body = NULL; head->defined = 0; /* Record data for the list, cod, and coff files */ head->line_number = state.src->line_number; head->file_symbol = state.src->file_symbol; head->src_name = strdup(state.src->name); state.lst.line.linetype = dir; if (macro_parms_ok(parms)) state.mac_head = head; state.mac_prev = &(head->body); state.mac_body = NULL; return r; } static gpasmVal do_messg(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == string) { gpmessage(GPM_USER, p->value.string); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_org(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = org; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (can_evaluate(p)) { gpasmVal new_org = evaluate(p); if (_16bit_core && (new_org & 0x1)) gperror(GPE_ORG_ODD, NULL); r = new_org >> _16bit_core; if (state.mode == absolute) { state.org = r; } else { /* Default section name, this will be overwritten if a label is present. */ snprintf(state.obj.new_sec_name, sizeof(state.obj.new_sec_name), ".org_%x", r); state.obj.new_sec_addr = r; state.obj.new_sec_flags = STYP_TEXT | STYP_ABS; state.lst.line.linetype = sec; state.next_state = state_section; } } else r = 0; } return r; } static gpasmVal do_page(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (enforce_arity(arity, 0)) lst_throw(); return r; } /* Called by both do_pagesel and do_pageselw, which have a very slight * difference between them */ static gpasmVal _do_pagesel(gpasmVal r, char *name, int arity, struct pnode *parms, unsigned short reloc_type) { struct pnode *p; int address; int page; int num_reloc; int use_wreg = 0; if ((reloc_type == RELOCT_PAGESEL_WREG) || (state.device.class == PROC_CLASS_PIC16)) { use_wreg = 1; } if ((state.device.class == PROC_CLASS_EEPROM8) || (state.device.class == PROC_CLASS_EEPROM16) || (state.device.class == PROC_CLASS_PIC16E)) { /* do nothing */ return r; } else if (state.device.class == PROC_CLASS_PIC16) { gpmessage(GPM_W_MODIFIED, NULL); } if (enforce_arity(arity, 1)) { p = HEAD(parms); if (state.mode == absolute) { address = maybe_evaluate(p); page = gp_processor_check_page(state.device.class, address); state.org += gp_processor_set_page(state.device.class, state.processor_info->num_pages, page, state.i_memory, state.org, use_wreg); } else { num_reloc = count_reloc(p); if (num_reloc == 0) { /* it is an absolute address, generate the pagesel but no relocation */ address = maybe_evaluate(p); page = gp_processor_check_page(state.device.class, address); state.org += gp_processor_set_page(state.device.class, state.processor_info->num_pages, page, state.i_memory, state.org, use_wreg); } else if (num_reloc != 1) { gperror(GPE_ILLEGAL_LABEL, NULL); } else if (state.device.class == PROC_CLASS_PIC16) { reloc_evaluate(p, RELOCT_PAGESEL_WREG); emit(0); emit(0); } else { if ((use_wreg == 0) && (state.processor_info->num_pages == 2)) { reloc_evaluate(p, RELOCT_PAGESEL_BITS); emit(0); } else if ((state.processor_info->num_pages == 2) || (state.processor_info->num_pages == 4)) { reloc_evaluate(p, reloc_type); emit(0); emit(0); } } } } return r; } static gpasmVal do_pagesel(gpasmVal r, char *name, int arity, struct pnode *parms) { return _do_pagesel(r, name, arity, parms, RELOCT_PAGESEL_BITS); } static gpasmVal do_pageselw(gpasmVal r, char *name, int arity, struct pnode *parms) { return _do_pagesel(r, name, arity, parms, RELOCT_PAGESEL_WREG); } static gpasmVal do_processor(gpasmVal r, char *name, int arity, struct pnode *parms) { state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { struct pnode *p = HEAD(parms); if (enforce_simple(p)) select_processor(p->value.symbol); } return r; } static gpasmVal do_radix(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (enforce_simple(p)) { select_radix(p->value.symbol); } } return r; } static gpasmVal do_res(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int count; int i; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (can_evaluate(p)) { count = evaluate(p); r = state.org; if (state.mode == absolute) { state.lst.line.linetype = equ; /* FIXME: in absolute mode, MPASM will reserve single bytes for * PIC18's, but that will require significant changes for gpasm */ if ((count >> _16bit_core) == 0) gpwarning(GPW_UNKNOWN, "No memory has been reserved by this instruction."); state.org += (count >> _16bit_core); } else { state.lst.line.linetype = res; if (SECTION_FLAGS & STYP_TEXT) count >>= _16bit_core; if (count == 0) gpwarning(GPW_UNKNOWN, "No memory has been reserved by this instruction."); for (i = 0; i < count; i++) { if (SECTION_FLAGS & STYP_TEXT) { /* For some reason program memory is filled with a different value. */ emit(state.device.core_size); } else { emit(0); } } } } } return r; } static gpasmVal do_set(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = set; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (can_evaluate(p)) r = evaluate(p); else r = 0; } return r; } static gpasmVal do_space(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (state.pass == 2) { switch (arity) { case 0: /* do nothing */ break; case 1: p = HEAD(parms); if (can_evaluate(p)) { int i; for (i = evaluate(p); i > 0; i--) lst_line(""); } break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_subtitle(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == string) { #define LEN sizeof(state.lst.subtitle_name) strncpy(state.lst.subtitle_name, p->value.string, LEN); #undef LEN } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_title(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == string) { #define LEN sizeof(state.lst.title_name) strncpy(state.lst.title_name, p->value.string, LEN); #undef LEN } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_type(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; char *symbol_name = NULL; gp_symbol_type *coff_symbol = NULL; int value; state.lst.line.linetype = dir; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else if (enforce_arity(arity, 2)) { /* the first argument is the symbol name */ p = HEAD(parms); if (enforce_simple(p)) { symbol_name = p->value.symbol; coff_symbol = gp_coffgen_findsymbol(state.obj.object, symbol_name); if (coff_symbol == NULL) { gperror(GPE_NOSYM, NULL); } else { p = HEAD(TAIL(parms)); value = maybe_evaluate(p); if ((value < 0) || (value > 0xffff)) { gperror(GPE_RANGE, NULL); } else { coff_symbol->type = value; } } } } return r; } static gpasmVal do_udata(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = sec; state.next_state = state_section; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".udata", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_BSS; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".udata", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p); state.obj.new_sec_flags = STYP_BSS | STYP_ABS; break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_udata_acs(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = sec; state.next_state = state_section; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".udata_acs", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_BSS | STYP_ACCESS; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".udata_acs", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p); state.obj.new_sec_flags = STYP_BSS | STYP_ABS | STYP_ACCESS; break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_udata_ovr(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = sec; state.next_state = state_section; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".udata_ovr", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_BSS | STYP_OVERLAY; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".udata_ovr", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p); state.obj.new_sec_flags = STYP_BSS | STYP_ABS | STYP_OVERLAY; break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_udata_shr(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = sec; state.next_state = state_section; if (state.mode == absolute) { gperror(GPE_OBJECT_ONLY, NULL); } else { switch (arity) { case 0: /* new relocatable section */ strncpy(state.obj.new_sec_name, ".udata_shr", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = 0; state.obj.new_sec_flags = STYP_BSS | STYP_SHARED; break; case 1: /* new absolute section */ p = HEAD(parms); strncpy(state.obj.new_sec_name, ".udata_shr", sizeof(state.obj.new_sec_name)); state.obj.new_sec_addr = maybe_evaluate(p); state.obj.new_sec_flags = STYP_BSS | STYP_ABS | STYP_SHARED; break; default: enforce_arity(arity, 1); } } return r; } static gpasmVal do_undefine(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); if (p->tag == symbol) { if (remove_symbol(state.stDefines, p->value.symbol) == 0) gpwarning(GPW_NOT_DEFINED, NULL); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_variable(gpasmVal r, char *name, int arity, struct pnode *parms) { struct pnode *p; int value; state.lst.line.linetype = dir; for (; parms; parms = TAIL(parms)) { p = HEAD(parms); if ((p->tag == binop) && (p->value.binop.op == '=')) { if (enforce_simple(p->value.binop.p0)) { char *lhs; /* fetch the symbol */ lhs = p->value.binop.p0->value.symbol; value = maybe_evaluate(p->value.binop.p1); /* put the symbol and value in the table*/ set_global(lhs, value, TEMPORARY, gvt_constant); } } else if (p->tag == symbol) { /* put the symbol with a 0 value in the table*/ set_global(p->value.symbol, 0, TEMPORARY, gvt_constant); } else { gperror(GPE_ILLEGAL_ARGU, NULL); } } return r; } static gpasmVal do_while(gpasmVal r, char *name, int arity, struct pnode *parms) { struct macro_head *head = malloc(sizeof(*head)); struct pnode *p; if (state.src->type == src_while) { state.pass = 2; /* Ensure error actually gets displayed */ gperror(GPE_UNKNOWN, "gpasm does not yet support nested while loops"); exit (1); } state.lst.line.linetype = dir; if (enforce_arity(arity, 1)) { p = HEAD(parms); head->parms = p; } else { head->parms = NULL; } head->body = NULL; /* Record data for the list, cod, and coff files */ head->line_number = state.src->line_number; head->file_symbol = state.src->file_symbol; head->src_name = strdup(state.src->name); /* DON'T set up state.mac_head; this isn't a macro head. */ state.while_head = head; state.mac_prev = &(head->body); state.mac_body = NULL; return r; } int asm_enabled(void) { return ((state.astack == NULL) || (state.astack->enabled && state.astack->prev_enabled)); } /* Check that a register file address is ok */ void file_ok(unsigned int file) { /* don't check address, the linker takes care of it */ if (state.mode == relocatable) return; if ((file > state.maxram) || (state.badram[file])) { gpwarning(GPW_INVALID_RAM, NULL); } /* Issue bank message if necessary */ switch (state.device.class) { case PROC_CLASS_EEPROM8: case PROC_CLASS_EEPROM16: /* do nothing */ break; case PROC_CLASS_GENERIC: case PROC_CLASS_PIC12: case PROC_CLASS_SX: if (file & (~0x1f)) gpmessage(GPM_BANK, NULL); break; case PROC_CLASS_PIC14: if (file & (~0x7f)) gpmessage(GPM_BANK, NULL); break; case PROC_CLASS_PIC16: if (file & (~0xff)) gpmessage(GPM_BANK, NULL); break; case PROC_CLASS_PIC16E: /* do nothing */ break; default: assert(0); } return; } static void emit_check(int insn, int argument, int mask) { int test = argument; if (test < 0) test = -test; /* If there are bits that shouldn't be set then issue a warning */ if (test & (~mask)) { gpwarning(GPW_RANGE, NULL); } emit(insn | (argument & mask)); return; } /* For relative branches, issue a warning if the absolute value of argument is greater than range */ static void emit_check_relative(int insn, int argument, int mask, int range) { char full_message[BUFSIZ]; /* If the branch is too far then issue an error */ if ((argument > range) || (argument < -(range+1))) { snprintf(full_message, sizeof(full_message), "Argument out of range (%d not between %d and %d)\n", argument, -(range+1), range); gperror(GPE_RANGE, full_message); } emit(insn | (argument & mask)); return; } static int check_flag(int flag) { if ((flag != 0) && (flag != 1)) gpwarning(GPW_RANGE, NULL); return flag & 0x1; } gpasmVal do_insn(char *name, struct pnode *parms) { struct symbol *s; int arity; struct pnode *p; int file; /* register file address, if applicable */ gpasmVal r; /* Return value */ r = state.org; arity = list_length(parms); s = get_symbol(state.stBuiltin, name); if (s) { struct insn *i; i = get_symbol_annotation(s); /* Interpret the instruction if assembly is enabled, or if it's a conditional. */ if (asm_enabled() || (i->attribs & ATTRIB_COND)) { state.lst.line.linetype = insn; switch (i->class) { case INSN_CLASS_LIT3_BANK: if (enforce_arity(arity, 1)) { p = HEAD(parms); emit_check(i->opcode, (reloc_evaluate(p, RELOCT_F) >> 5), 0x07); } break; case INSN_CLASS_LIT3_PAGE: if (enforce_arity(arity, 1)) { p = HEAD(parms); emit_check(i->opcode, (reloc_evaluate(p, RELOCT_F) >> 9), 0x07); } break; case INSN_CLASS_LIT1: { int s = 0; switch (arity) { case 1: s = check_flag(reloc_evaluate(HEAD(parms), RELOCT_F)); case 0: emit(i->opcode | s); break; default: enforce_arity(arity, 1); } } break; case INSN_CLASS_LIT4: if (enforce_arity(arity, 1)) { p = HEAD(parms); emit_check(i->opcode, reloc_evaluate(p, RELOCT_F), 0x0f); } break; case INSN_CLASS_LIT4S: if (enforce_arity(arity, 1)) { p = HEAD(parms); emit_check(i->opcode, (reloc_evaluate(p, RELOCT_MOVLR) << 4), 0xf0); } break; case INSN_CLASS_LIT6: if (enforce_arity(arity, 1)) { p = HEAD(parms); /* The literal cannot be a relocatable address */ emit_check(i->opcode, maybe_evaluate(p), 0x3f); } break; case INSN_CLASS_LIT8: if (enforce_arity(arity, 1)) { p = HEAD(parms); coerce_str1(p); /* literal instructions can coerce string literals */ if (strcasecmp(i->name, "movlb") == 0) { emit_check(i->opcode, reloc_evaluate(p, RELOCT_MOVLB), 0xf); } else { emit_check(i->opcode, reloc_evaluate(p, RELOCT_LOW), 0xff); } } break; case INSN_CLASS_LIT8C12: if (enforce_arity(arity, 1)) { int value; p = HEAD(parms); value = reloc_evaluate(p, RELOCT_CALL); /* PC is 11 bits. mpasm checks the maximum device address. */ if (value & (~0x7ff)) gperror(GPE_RANGE, NULL); if ((value & 0x600) != (state.org & 0x600)) gpmessage(GPM_PAGE, NULL); if (value & 0x100) gperror(GPE_BAD_CALL_ADDR, NULL); emit(i->opcode | (value & 0xff)); } break; case INSN_CLASS_LIT8C16: if (enforce_arity(arity, 1)) { int value; p = HEAD(parms); value = reloc_evaluate(p, RELOCT_LOW); /* PC is 16 bits. mpasm checks the maximum device address. */ if (value & (~0xffff)) gperror(GPE_RANGE, NULL); emit(i->opcode | (value & 0xff)); } break; case INSN_CLASS_LIT9: if (enforce_arity(arity, 1)) { int value; p = HEAD(parms); value = reloc_evaluate(p, RELOCT_GOTO); /* PC is 11 bits. mpasm checks the maximum device address. */ if (value & (~0x7ff)) gperror(GPE_RANGE, NULL); if ((value & 0x600) != (state.org & 0x600)) gpmessage(GPM_PAGE, NULL); emit(i->opcode | (value & 0x1ff)); } break; case INSN_CLASS_LIT11: if (enforce_arity(arity, 1)) { int value; p = HEAD(parms); if (strcasecmp(i->name, "goto") == 0) { value = reloc_evaluate(p, RELOCT_GOTO); } else { value = reloc_evaluate(p, RELOCT_CALL); } /* PC is 13 bits. mpasm checks the maximum device address. */ if (value & (~0x1fff)) gperror(GPE_RANGE, NULL); if ((value & 0x1800) != (state.org & 0x1800)) gpmessage(GPM_PAGE, NULL); emit(i->opcode | (value & 0x7ff)); } break; case INSN_CLASS_LIT13: if (enforce_arity(arity, 1)) { int value; p = HEAD(parms); if (strcasecmp(i->name, "goto") == 0) { value = reloc_evaluate(p, RELOCT_GOTO); } else { value = reloc_evaluate(p, RELOCT_CALL); } /* PC is 16 bits. mpasm checks the maximum device address. */ if (value & (~0xffff)) gperror(GPE_RANGE, NULL); if ((value & 0xe000) != (state.org & 0xe000)) gpmessage(GPM_PAGE, NULL); emit(i->opcode | (value & 0x1fff)); } break; case INSN_CLASS_LITFSR: if (enforce_arity(arity, 2)) { int value; int fsr; p = HEAD(parms); fsr = maybe_evaluate(p); if ((fsr < 0) || (fsr > 2)) gperror(GPE_RANGE, NULL); p = HEAD(TAIL(parms)); /* the offset cannot be a relocatable address */ value = maybe_evaluate(p); if (value & (~0x3f)) gperror(GPE_RANGE, NULL); emit(i->opcode | ((fsr & 0x3) << 6) | (value & 0x3f)); } break; case INSN_CLASS_RBRA8: if (enforce_arity(arity, 1)) { int offset; p = HEAD(parms); if (count_reloc(p) == 0) { offset = maybe_evaluate(p) - ((state.org + 1)<<_16bit_core); offset >>= _16bit_core; } else { offset = reloc_evaluate(p, RELOCT_CONDBRA); } /* The offset for the relative branch must be between -127 <= offset <= 127. */ emit_check_relative(i->opcode, offset, 0xff, 127); } break; case INSN_CLASS_RBRA11: if (enforce_arity(arity, 1)) { int offset; p = HEAD(parms); if (count_reloc(p) == 0) { offset = maybe_evaluate(p) - ((state.org + 1)<<_16bit_core); offset >>= _16bit_core; } else { offset = reloc_evaluate(p, RELOCT_BRA); } emit_check_relative(i->opcode, offset, 0x7ff, 0x3ff); } break; case INSN_CLASS_LIT20: if (enforce_arity(arity, 1)) { int dest; p = HEAD(parms); dest = reloc_evaluate(p, RELOCT_GOTO) >> _16bit_core; emit(i->opcode | (dest & 0xff)); reloc_evaluate(p, RELOCT_GOTO2); /* add the second relocation */ emit_check(0xf000, dest>>8, 0xfff); } break; case INSN_CLASS_CALL20: { int dest; int s = 0; /* By default, fast push is not used */ struct pnode *p2; /* second parameter */ if (arity < 1) { enforce_arity(arity, 2); } else { p = HEAD(parms); switch (arity) { case 2: p2 = HEAD(TAIL(parms)); /* Allow "s" for fast push */ if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "s") == 0)) s = 1; else s = check_flag(maybe_evaluate(p2)); break; case 1: s = 0; break; default: enforce_arity(arity, 2); } dest = reloc_evaluate(p, RELOCT_CALL) >> _16bit_core; emit(i->opcode | (s<<8) | (dest & 0xff)); reloc_evaluate(p, RELOCT_CALL2); /* add the second relocation */ emit_check(0xf000, (dest>>8), 0xfff); } } break; case INSN_CLASS_FLIT12: { int k; if (enforce_arity(arity, 2)) { p = HEAD(parms); file = maybe_evaluate(p); if(file > 3) gperror(GPE_UNKNOWN, "FSR is out of range"); p = HEAD(TAIL(parms)); k = reloc_evaluate(p, RELOCT_LFSR1); emit_check(i->opcode | ((file & 3) << 4), (k>>8), 0xf); reloc_evaluate(p, RELOCT_LFSR2); /* add the second relocation */ emit(0xf000 | (k & 0xff)); } } break; case INSN_CLASS_FF: if (enforce_arity(arity, 2)) { int dest = maybe_evaluate(HEAD(TAIL(parms))); /* destination can't be PCL, TOSU, TOSH, TOSL */ if ((dest == 0xff9) || (dest == 0xfff) || (dest == 0xffe) || (dest == 0xffd)) { gperror(GPE_UNKNOWN, "Invalid destination"); } emit_check(i->opcode, reloc_evaluate(HEAD(parms), RELOCT_FF1), 0xfff); emit_check(0xf000, reloc_evaluate(HEAD(TAIL(parms)), RELOCT_FF2), 0xfff); } break; case INSN_CLASS_FP: if (enforce_arity(arity, 2)) { int reg=0; file=reloc_evaluate(HEAD(parms), RELOCT_F); reg=reloc_evaluate(HEAD(TAIL(parms)), RELOCT_P); file_ok(file); if (reg & ~0xf1f) { gpwarning(GPW_RANGE, NULL); } emit(i->opcode | ( (reg & 0x1f) << 8) | (file & 0xff) ); } break; case INSN_CLASS_PF: if (enforce_arity(arity, 2)) { int reg=0; file=reloc_evaluate(HEAD(TAIL(parms)), RELOCT_F); reg=reloc_evaluate(HEAD(parms), RELOCT_P); file_ok(file); if (reg & ~0xf1f) { gpwarning(GPW_RANGE, NULL); } emit(i->opcode | ( (reg & 0x1f) << 8) | (file & 0xff) ); } break; case INSN_CLASS_SF: if (enforce_arity(arity, 2)) { int source; int dest; p = HEAD(parms); if (p->tag != offset) gperror(GPE_MISSING_BRACKET, NULL); source = maybe_evaluate(p); p = HEAD(TAIL(parms)); dest = maybe_evaluate(p); /* destination can't be PCL, TOSU, TOSH, TOSL */ if ((dest == 0xff9) || (dest == 0xfff) || (dest == 0xffe) || (dest == 0xffd)) { gperror(GPE_UNKNOWN, "Invalid destination"); } emit_check(i->opcode, source, 0x7f); emit_check(0xf000, reloc_evaluate(HEAD(TAIL(parms)), RELOCT_FF2), 0xfff); } break; case INSN_CLASS_SS: if (enforce_arity(arity, 2)) { int source; int dest; p = HEAD(parms); if (p->tag != offset) gperror(GPE_MISSING_BRACKET, NULL); source = maybe_evaluate(p); p = HEAD(TAIL(parms)); if (p->tag != offset) gperror(GPE_MISSING_BRACKET, NULL); dest = maybe_evaluate(p); emit_check(i->opcode, source, 0x7f); emit_check(0xf000, dest, 0x7f); } break; case INSN_CLASS_OPF5: if (enforce_arity(arity, 1)) { p = HEAD(parms); if (strcasecmp(i->name, "tris") == 0) { file = reloc_evaluate(p, RELOCT_TRIS); } else { file = reloc_evaluate(p, RELOCT_F); } file_ok(file); emit(i->opcode | (file & 0x1f)); } break; case INSN_CLASS_OPWF5: { int d = 1; /* Default destination of 1 (file) */ struct pnode *p2; /* second parameter */ if(arity == 0) { enforce_arity(arity, 2); break; } p = HEAD(parms); switch (arity) { case 2: p2 = HEAD(TAIL(parms)); /* Allow "w" and "f" as destinations */ if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "f") == 0)) d = 1; else if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "w") == 0)) d = 0; else d = check_flag(maybe_evaluate(p2)); break; case 1: d = 1; gpmessage(GPM_NOF,NULL); break; default: enforce_arity(arity, 2); } file = reloc_evaluate(p, RELOCT_F); file_ok(file); emit(i->opcode | (d << 5) | (file & 0x1f)); } break; case INSN_CLASS_B5: { struct pnode *f, *b; int bit; if (enforce_arity(arity, 2)) { f = HEAD(parms); b = HEAD(TAIL(parms)); file = reloc_evaluate(f, RELOCT_F); bit = maybe_evaluate(b); if (!((0 <= bit) && (bit <= 7))) gpwarning(GPW_RANGE, NULL); file_ok(file); emit(i->opcode | ((bit & 7) << 5) |(file & 0x1f)); } } break; case INSN_CLASS_B8: { struct pnode *f, *b; int bit; if (enforce_arity(arity, 2)) { f = HEAD(parms); b = HEAD(TAIL(parms)); file = reloc_evaluate(f, RELOCT_F); bit = maybe_evaluate(b); if (!((0 <= bit) && (bit <= 7))) gpwarning(GPW_RANGE, NULL); file_ok(file); emit(i->opcode | ((bit & 7) << 8) | (file & 0xff)); } } break; case INSN_CLASS_OPF7: if (enforce_arity(arity, 1)) { p = HEAD(parms); if (strcasecmp(i->name, "tris") == 0) { gpwarning(GPW_NOT_RECOMMENDED, NULL); file = reloc_evaluate(p, RELOCT_TRIS); } else { file = reloc_evaluate(p, RELOCT_F); } file_ok(file); emit(i->opcode | (file & 0x7f)); } break; case INSN_CLASS_OPF8: if (enforce_arity(arity, 1)) { p = HEAD(parms); file = reloc_evaluate(p, RELOCT_F); file_ok(file); emit(i->opcode | (file & 0xff)); } break; case INSN_CLASS_OPWF7: { int d = 1; /* Default destination of 1 (file) */ struct pnode *p2; /* second parameter */ if(arity == 0) { enforce_arity(arity, 2); break; } p = HEAD(parms); switch (arity) { case 2: p2 = HEAD(TAIL(parms)); /* Allow "w" and "f" as destinations */ if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "f") == 0)) d = 1; else if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "w") == 0)) d = 0; else d = check_flag(maybe_evaluate(p2)); break; case 1: d = 1; gpmessage(GPM_NOF,NULL); break; default: enforce_arity(arity, 2); } file = reloc_evaluate(p, RELOCT_F); file_ok(file); emit(i->opcode | (d << 7) | (file & 0x7f)); } break; case INSN_CLASS_OPWF8: { int d = 1; /* Default destination of 1 (file) */ struct pnode *p2; /* second parameter */ if(arity == 0) { enforce_arity(arity, 2); break; } p = HEAD(parms); switch (arity) { case 2: p2 = HEAD(TAIL(parms)); /* Allow "w" and "f" as destinations */ if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "f") == 0)) d = 1; else if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "w") == 0)) d = 0; else d = check_flag(maybe_evaluate(p2)); break; case 1: d = 1; gpmessage(GPM_NOF,NULL); break; default: enforce_arity(arity, 2); } file = reloc_evaluate(p, RELOCT_F); file_ok(file); emit(i->opcode | (d << 8) | (file & 0xff)); } break; case INSN_CLASS_B7: { struct pnode *f, *b; int bit; if (enforce_arity(arity, 2)) { f = HEAD(parms); b = HEAD(TAIL(parms)); file = reloc_evaluate(f, RELOCT_F); bit = maybe_evaluate(b); if (!((0 <= bit) && (bit <= 7))) gpwarning(GPW_RANGE, NULL); file_ok(file); emit(i->opcode | ((bit & 7) << 7) | (file & 0x7f)); } } break; case INSN_CLASS_OPFA8: { int a = 0; struct pnode *p2; /* second parameter */ if(arity == 0) { enforce_arity(arity, 2); break; } p = HEAD(parms); file = reloc_evaluate(p, RELOCT_F); file_ok(file); /* add relocation for the access bit, if necessary */ reloc_evaluate(p, RELOCT_ACCESS); /* Default access (use the BSR unless access is to special registers) */ /* If extended instructions are enabled, access bit should default to 1 for low-end */ /* of Access Memory unless the file is explicitly an offset (e.g. [foo]) */ if ((state.extended_pic16e == true) && (file <= 0x5f)) { if (p->tag == offset) { a = 0; } else { a = 1; } } else if ((file < state.device.bsr_boundary) || (file >= (0xf00 + state.device.bsr_boundary))) { a = 0; } else { a = 1; } switch (arity) { case 2: p2 = HEAD(TAIL(parms)); /* Allow "w" and "f" as destinations */ if ((p2->tag == symbol) && (strcasecmp(p2->value.symbol, "b") == 0)) a = 1; else a = check_flag(maybe_evaluate(p2)); break; case 1: /* use default a */ break; default: enforce_arity(arity, 2); } emit(i->opcode | (a << 8) | (file & 0xff)); } break; case INSN_CLASS_BA8: { struct pnode *f, *b,*par; int bit,a=0; if ((arity != 2) && (arity != 3)) { enforce_arity(arity, 3); break; } f = HEAD(parms); file = reloc_evaluate(f, RELOCT_F); if (arity == 3) { par = HEAD(TAIL(TAIL(parms))); if ((par->tag == symbol) && (strcasecmp(par->value.symbol, "b") == 0)) a = 1; else a = check_flag(maybe_evaluate(par)); } else { /* Default access (use the BSR unless access is to special registers) */ /* If extended instructions are enabled, access bit should default to 1 for low-end */ /* of Access Memory unless the file is explicitly an offset (e.g. [foo]) */ if ((state.extended_pic16e == true) && (file <= 0x5f)) { if (f->tag == offset) { a = 0; } else { a = 1; } } else if ((file < state.device.bsr_boundary) || (file >= (0xf00 + state.device.bsr_boundary))) { a = 0; } else { a = 1; } } /* add relocation for the access bit, if necessary */ reloc_evaluate(f, RELOCT_ACCESS); b = HEAD(TAIL(parms)); bit = maybe_evaluate(b); if (!((0 <= bit) && (bit <= 7))) gpwarning(GPW_RANGE, NULL); file_ok(file); emit(i->opcode | ( a << 8) | ((bit & 7) << 9) | (file & 0xff)); } break; case INSN_CLASS_OPWFA8: { int d = 1; /* Default destination of 1 (file) */ int a = 0; struct pnode *par; /* second parameter */ if(arity == 0) { enforce_arity(arity, 2); break; } p = HEAD(parms); file = reloc_evaluate(p, RELOCT_F); file_ok(file); /* add relocation for the access bit, if necessary */ reloc_evaluate(p, RELOCT_ACCESS); /* Default access (use the BSR unless access is to special registers) */ /* If extended instructions are enabled, access bit should default to 1 for low-end */ /* of Access Memory */ if ((state.extended_pic16e == true) && (file <= 0x5f)) { if (p->tag == offset) { a = 0; } else { a = 1; } } else if ((file < state.device.bsr_boundary) || (file >= (0xf00 + state.device.bsr_boundary))) { a = 0; } else { a = 1; } switch (arity) { case 3: par = HEAD(TAIL(TAIL(parms))); if ((par->tag == symbol) && (strcasecmp(par->value.symbol, "b") == 0)) a = 1; else a = check_flag(maybe_evaluate(par)); /* fall through */ case 2: par = HEAD(TAIL(parms)); /* Allow "w" and "f" as destinations */ if ((par->tag == symbol) && (strcasecmp(par->value.symbol, "f") == 0)) d = 1; else if ((par->tag == symbol) && (strcasecmp(par->value.symbol, "w") == 0)) d = 0; else d = check_flag(maybe_evaluate(par)); break; case 1: /* use default a and d */ gpmessage(GPM_NOF,NULL); break; default: enforce_arity(arity, 3); } emit(i->opcode | (d << 9) | (a << 8) | (file & 0xff)); } break; case INSN_CLASS_IMPLICIT: if (arity != 0) { gpwarning(GPW_EXTRANEOUS, NULL); } if ((strcasecmp(i->name, "option") == 0) && (state.device.core_size != CORE_12BIT_MASK)){ gpwarning(GPW_NOT_RECOMMENDED, NULL); } emit(i->opcode); break; case INSN_CLASS_TBL: if (enforce_arity(arity, 1)) { p = HEAD(parms); switch(maybe_evaluate(p)) { case TBL_NO_CHANGE: emit(i->opcode); break; case TBL_POST_INC: emit(i->opcode | 1); break; case TBL_POST_DEC: emit(i->opcode | 2); break; case TBL_PRE_INC: emit(i->opcode | 3); break; default: gperror(GPE_ILLEGAL_ARGU, NULL); } } break; case INSN_CLASS_TBL2: if (enforce_arity(arity, 2)) { int t=0; /* read low byte by default */ struct pnode *p2; /* second parameter */ /* "0" (lower byte) and "1" (upper byte) */ p = HEAD(parms); t = check_flag(maybe_evaluate(p)); p2 = HEAD(TAIL(parms)); file = reloc_evaluate(p2, RELOCT_F); file_ok(file); emit(i->opcode | (t << 9) | (file & 0xff)); } break; case INSN_CLASS_TBL3: if (enforce_arity(arity, 3)) { int inc=0,t=0; struct pnode *p2; /* second parameter */ struct pnode *p3; /* third parameter */ /* "0" (lower byte) and "1" (upper byte) */ p = HEAD(parms); t = check_flag(maybe_evaluate(p)); /* "0" (no change) and "1" (postincrement) */ p2 = HEAD(TAIL(parms)); inc = check_flag(maybe_evaluate(p2)); p3 = HEAD(TAIL(TAIL(parms))); file = reloc_evaluate(p3, RELOCT_F); file_ok(file); emit(i->opcode | (t << 9) | (inc << 8) | (file & 0xff)); } break; case INSN_CLASS_FUNC: r = (*(opfunc*)i->opcode)(r, name, arity, parms); break; } } } else { s = get_symbol(state.stMacros, name); if (s) { struct macro_head *h = get_symbol_annotation(s); /* Found the macro: execute it */ if (asm_enabled()) { if ((h->defined != 1) && (state.pass == 2)) { gperror(GPE_UNKNOWN, "Forward references to macros are not allowed."); } else { setup_macro(h, arity, parms); } } } else { if (asm_enabled()) { if (state.processor_chosen == 0){ gperror(GPE_UNDEF_PROC, NULL); } else { char mesg[80]; snprintf(mesg, sizeof(mesg), "Unknown opcode \"%.40s\"", name); gperror(GPE_UNKNOWN, mesg); } } } } return r; } /************************************************************************/ /* There are several groups of operations that we handle here. First is op_0: the instructions that can happen before the processor type is known. Second is op_1, the set of instructions that are common to all processors, third is processor-family specific: op_XXX */ /* Note that instructions within each group are sorted alphabetically */ struct insn op_0[] = { { "code", 0, (long int)do_code, INSN_CLASS_FUNC, 0 }, { "code_pack", 0, (long int)do_code_pack, INSN_CLASS_FUNC, 0 }, { "constant", 0, (long int)do_constant, INSN_CLASS_FUNC, 0 }, { "else", 0, (long int)do_else, INSN_CLASS_FUNC, ATTRIB_COND }, { "endif", 0, (long int)do_endif, INSN_CLASS_FUNC, ATTRIB_COND }, { "endm", 0, (long int)do_endm, INSN_CLASS_FUNC, 0 }, { "endw", 0, (long int)do_endw, INSN_CLASS_FUNC, 0 }, { "equ", 0, (long int)do_equ, INSN_CLASS_FUNC, 0 }, { "error", 0, (long int)do_error, INSN_CLASS_FUNC, 0 }, { "exitm", 0, (long int)do_exitm, INSN_CLASS_FUNC, 0 }, { "expand", 0, (long int)do_expand, INSN_CLASS_FUNC, 0 }, { "extern", 0, (long int)do_extern, INSN_CLASS_FUNC, 0 }, { "errorlevel", 0, (long int)do_errlvl, INSN_CLASS_FUNC, 0 }, { "global", 0, (long int)do_global, INSN_CLASS_FUNC, 0 }, { "idata", 0, (long int)do_idata, INSN_CLASS_FUNC, 0 }, { "if", 0, (long int)do_if, INSN_CLASS_FUNC, ATTRIB_COND }, { "ifdef", 0, (long int)do_ifdef, INSN_CLASS_FUNC, ATTRIB_COND }, { "ifndef", 0, (long int)do_ifndef, INSN_CLASS_FUNC, ATTRIB_COND }, { "include", 0, (long int)do_include, INSN_CLASS_FUNC, 0 }, { "list", 0, (long int)do_list, INSN_CLASS_FUNC, 0 }, { "local", 0, (long int)do_local, INSN_CLASS_FUNC, 0 }, { "macro", 0, (long int)do_macro, INSN_CLASS_FUNC, 0 }, { "messg", 0, (long int)do_messg, INSN_CLASS_FUNC, 0 }, { "noexpand", 0, (long int)do_noexpand, INSN_CLASS_FUNC, 0 }, { "nolist", 0, (long int)do_nolist, INSN_CLASS_FUNC, 0 }, { "page", 0, (long int)do_page, INSN_CLASS_FUNC, 0 }, { "processor", 0, (long int)do_processor, INSN_CLASS_FUNC, 0 }, { "radix", 0, (long int)do_radix, INSN_CLASS_FUNC, 0 }, { "set", 0, (long int)do_set, INSN_CLASS_FUNC, 0 }, { "space", 0, (long int)do_space, INSN_CLASS_FUNC, 0 }, { "subtitle", 0, (long int)do_subtitle, INSN_CLASS_FUNC, 0 }, { "title", 0, (long int)do_title, INSN_CLASS_FUNC, 0 }, { "udata", 0, (long int)do_udata, INSN_CLASS_FUNC, 0 }, { "udata_acs", 0, (long int)do_udata_acs, INSN_CLASS_FUNC, 0 }, { "udata_ovr", 0, (long int)do_udata_ovr, INSN_CLASS_FUNC, 0 }, { "udata_shr", 0, (long int)do_udata_shr, INSN_CLASS_FUNC, 0 }, { "variable", 0, (long int)do_variable, INSN_CLASS_FUNC, 0 }, { "while", 0, (long int)do_while, INSN_CLASS_FUNC, 0 }, { ".def", 0, (long int)do_def, INSN_CLASS_FUNC, 0 }, { ".dim", 0, (long int)do_dim, INSN_CLASS_FUNC, 0 }, { ".direct", 0, (long int)do_direct, INSN_CLASS_FUNC, 0 }, { ".eof", 0, (long int)do_eof, INSN_CLASS_FUNC, 0 }, { ".file", 0, (long int)do_file, INSN_CLASS_FUNC, 0 }, { ".ident", 0, (long int)do_ident, INSN_CLASS_FUNC, 0 }, { ".line", 0, (long int)do_line, INSN_CLASS_FUNC, 0 }, { ".set", 0, (long int)do_set, INSN_CLASS_FUNC, 0 }, { ".type", 0, (long int)do_type, INSN_CLASS_FUNC, 0 }, { "#if", 0, (long int)do_if, INSN_CLASS_FUNC, ATTRIB_COND }, { "#else", 0, (long int)do_else, INSN_CLASS_FUNC, ATTRIB_COND }, { "#endif", 0, (long int)do_endif, INSN_CLASS_FUNC, ATTRIB_COND }, { "#ifdef", 0, (long int)do_ifdef, INSN_CLASS_FUNC, ATTRIB_COND }, { "#ifndef", 0, (long int)do_ifndef, INSN_CLASS_FUNC, ATTRIB_COND }, { "#define", 0, (long int)do_define, INSN_CLASS_FUNC, 0 }, { "#undefine", 0, (long int)do_undefine, INSN_CLASS_FUNC, 0 } }; const int num_op_0 = TABLE_SIZE(op_0); struct insn op_1[] = { { "__badram", 0, (long int)do_badram, INSN_CLASS_FUNC, 0 }, { "__badrom", 0, (long int)do_badrom, INSN_CLASS_FUNC, 0 }, { "__config", 0, (long int)do_config, INSN_CLASS_FUNC, 0 }, { "__fuses", 0, (long int)do_config, INSN_CLASS_FUNC, 0 }, { "__idlocs", 0, (long int)do_idlocs, INSN_CLASS_FUNC, 0 }, { "__maxram", 0, (long int)do_maxram, INSN_CLASS_FUNC, 0 }, { "__maxrom", 0, (long int)do_maxrom, INSN_CLASS_FUNC, 0 }, { "bankisel", 0, (long int)do_bankisel, INSN_CLASS_FUNC, 0 }, { "banksel", 0, (long int)do_banksel, INSN_CLASS_FUNC, 0 }, { "CONFIG", 0, (long int)do_16_config, INSN_CLASS_FUNC, 0 }, { "data", 0, (long int)do_data, INSN_CLASS_FUNC, 0 }, { "da", 0, (long int)do_da, INSN_CLASS_FUNC, 0 }, { "db", 0, (long int)do_db, INSN_CLASS_FUNC, 0 }, { "de", 0, (long int)do_de, INSN_CLASS_FUNC, 0 }, { "dt", 0, (long int)do_dt, INSN_CLASS_FUNC, 0 }, { "dw", 0, (long int)do_dw, INSN_CLASS_FUNC, 0 }, { "fill", 0, (long int)do_fill, INSN_CLASS_FUNC, 0 }, { "org", 0, (long int)do_org, INSN_CLASS_FUNC, 0 }, { "pagesel", 0, (long int)do_pagesel, INSN_CLASS_FUNC, 0 }, { "pageselw", 0, (long int)do_pageselw, INSN_CLASS_FUNC, 0 }, { "res", 0, (long int)do_res, INSN_CLASS_FUNC, 0 } }; const int num_op_1 = TABLE_SIZE(op_1); void opcode_init(int stage) { int i; int count = 0; struct insn *base = NULL; switch (stage) { case 0: base = op_0; count = num_op_0; break; case 1: base = op_1; count = num_op_1; break; case 2: state.device.class = gp_processor_class(state.processor); switch (state.device.class) { case PROC_CLASS_EEPROM8: base = 0; count = 0; state.device.core_size = CORE_8BIT_MASK; state.device.config_address = 0; state.device.id_location = 0; break; case PROC_CLASS_EEPROM16: base = 0; count = 0; state.device.core_size = CORE_16BIT_MASK; state.device.config_address = 0; state.device.id_location = 0; break; case PROC_CLASS_GENERIC: base = 0; count = 0; state.device.core_size = CORE_12BIT_MASK; state.device.config_address = CONFIG_ADDRESS_12; state.device.id_location = IDLOC_ADDRESS_12; break; case PROC_CLASS_PIC12: base = op_12c5xx; count = num_op_12c5xx; state.device.core_size = CORE_12BIT_MASK; state.device.config_address = CONFIG_ADDRESS_12; state.device.id_location = IDLOC_ADDRESS_12; break; case PROC_CLASS_SX: base = op_sx; count = num_op_sx; state.device.core_size = CORE_12BIT_MASK; state.device.config_address = CONFIG_ADDRESS_12; state.device.id_location = IDLOC_ADDRESS_12; /* page instruction conflicts with the page directive */ remove_symbol(state.stBuiltin, "page"); break; case PROC_CLASS_PIC14: base = op_16cxx; count = num_op_16cxx; state.device.core_size = CORE_14BIT_MASK; state.device.config_address = CONFIG_ADDRESS_14; state.device.id_location = IDLOC_ADDRESS_14; break; case PROC_CLASS_PIC16: base = op_17cxx; count = num_op_17cxx; state.device.core_size = CORE_16BIT_MASK; _17cxx_core = 1; state.device.config_address = CONFIG_17CXX; break; case PROC_CLASS_PIC16E: base = op_18cxx; count = num_op_18cxx; state.device.core_size = CORE_16BIT_MASK; _16bit_core = 1; state.c_memory_base = CONFIG1L; state.device.config_address = CONFIG1L; state.device.bsr_boundary = gp_processor_bsr_boundary(state.processor); /* The 16_bit core special macros are encoded directly into the * symbol table like regular instructions. */ for (i = 0; i < num_op_18cxx_sp; i++) annotate_symbol( add_symbol(state.stBuiltin, op_18cxx_sp[i].name), &op_18cxx_sp[i]); if (state.extended_pic16e) { /* Some 18xx devices have an extended instruction set. */ for (i = 0; i < num_op_18cxx_ext; i++) annotate_symbol( add_symbol(state.stBuiltin, op_18cxx_ext[i].name), &op_18cxx_ext[i]); } break; default: assert(0); } break; case 3: /* add 12 and 14 bit special macros */ base = special; count = num_op_special; break; default: assert(0); } for (i = 0; i < count; i++) annotate_symbol(add_symbol(state.stBuiltin, base[i].name), &base[i]); if (state.processor) { const char *name = gp_processor_name(state.processor, 0); /* Special Case, Some instructions not available on 17c42 devices */ if (strcmp(name, "pic17c42") == 0) { remove_symbol(state.stBuiltin, "MULWF"); remove_symbol(state.stBuiltin, "MOVLR"); remove_symbol(state.stBuiltin, "MULLW"); } /* Special Case, Some instructions not available on 16f5x devices */ if (strcmp(name, "pic16f54") == 0 || strcmp(name, "pic16f57") == 0 || strcmp(name, "pic16f59") == 0) { remove_symbol(state.stBuiltin, "ADDLW"); remove_symbol(state.stBuiltin, "SUBLW"); remove_symbol(state.stBuiltin, "RETURN"); remove_symbol(state.stBuiltin, "RETFIE"); } if (strcmp(name, "sx48bd") == 0 || strcmp(name, "sx52bd") == 0) { struct symbol *mode_sym = get_symbol(state.stBuiltin, "MODE"); if (mode_sym != NULL) annotate_symbol(mode_sym, &op_sx_mode); } } } /************************************************************************/ void begin_cblock(struct pnode *c) { if (asm_enabled()) { state.cblock_defined = 1; state.cblock = maybe_evaluate(c); } } void continue_cblock(void) { if (state.cblock_defined == 0) gpmessage(GPM_CBLOCK, NULL); state.cblock_defined = 1; } void cblock_expr(struct pnode *s) { if ((asm_enabled()) && (can_evaluate_concatenation(s))) { set_global(evaluate_concatenation(s), state.cblock, PERMANENT, gvt_cblock); state.cblock++; } } void cblock_expr_incr(struct pnode *s, struct pnode *incr) { if ((asm_enabled()) && (can_evaluate_concatenation(s))) { set_global(evaluate_concatenation(s), state.cblock, PERMANENT, gvt_cblock); state.cblock += maybe_evaluate(incr); } } gputils-0.13.7/gpasm/gperror.c0000644000175000017500000002451211156313231013145 00000000000000/* Error handling for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "gperror.h" #include "lst.h" struct error_list { int value; struct error_list *next; }; static struct error_list *errorcodes_list = NULL; void add_code(int code) { struct error_list *new; struct error_list *list; if ((code <= -100) && (code >= -199)) { gpwarning(GPW_DISABLE_ERROR, NULL); } else { new = (struct error_list *)malloc(sizeof(*new)); new->value = code; new->next = NULL; if (errorcodes_list) { /* the list has been started, scan the list for the end */ list = errorcodes_list; while(list->next) { list = list->next; } list->next = new; /* append the new value to the end of list */ } else { errorcodes_list = new; /* new list */ } } } static int check_code(int code) { struct error_list *p; int print = 1; p = errorcodes_list; while(p) { if (p->value == code){ print = 1; } else if (p->value == -(code)) { print = 0; } p = p->next; } return print; } char *gp_geterror(unsigned int code) { switch(code) { case GPE_OPENPAR: return "Unmatched ("; case GPE_CLOSEPAR: return "Unmatched )"; case GPE_BADCHAR: return "Illegal character."; case GPE_NOSYM: return "Symbol not previously defined."; case GPE_DIVBY0: return "Divide by zero."; case GPE_DUPLAB: return "Duplicate label or redefining symbol that cannot be redefined."; case GPE_DIFFLAB: return "Address label duplicated or different in second pass."; case GPE_ADDROVF: return "Address wrapped around 0. "; case GPE_ADDROVR: return "Overwriting previous address contents."; case GPE_BAD_CALL_ADDR: return "Call or jump not allowed at this address (must be in low half of page)"; case GPE_ILLEGAL_LABEL: return "Illegal label."; case GPE_ILLEGAL_DIR: return "Illegal directive (Not Valid for this processor)."; case GPE_ILLEGAL_ARGU: return "Illegal argument."; case GPE_ILLEGAL_COND: return "Illegal condition."; case GPE_RANGE: return "Argument out of range."; case GPE_TOO_MANY_ARGU: return "Too many arguments."; case GPE_MISSING_ARGU: return "Missing argument(s)."; case GPE_EXPECTED: return "Expected"; case GPE_EXTRA_PROC: return "Processor type previously defined."; case GPE_UNDEF_PROC: return "Processor type is undefined."; case GPE_UNKNOWN_PROC: return "Unknown processor."; case GPE_IHEX: return "Hex file format INHX32 required."; case GPE_NO_MACRO_NAME: return "Macro name missing."; case GPE_DUPLICATE_MACRO: return "Duplicate macro name."; case GPE_BAD_WHILE_LOOP: return "WHILE must terminate within 256 iterations."; case GPE_ILLEGAL_NESTING: return "Illegal nesting."; case GPE_UNMATCHED_ENDM: return "Unmatched ENDM."; case GPE_OBJECT_ONLY: return "Directive only allowed when generating an object file."; case GPE_UNRESOLVABLE: return "Operand contains unresolvable labels or is too complex."; case GPE_WRONG_SECTION: return "Executable code and data must be defined in an appropriate section."; case GPE_CONTIG_SECTION: return "Each object file section must be contiguous."; case GPE_MUST_BE_LABEL: return "Operand must be an address label."; case GPE_ORG_ODD: return "ORG at odd address."; case GPE_FILL_ODD: return "Cannot use FILL Directive with odd number of bytes."; case GPE_CONTIG_CONFIG: return "__CONFIG directives must be contiguous."; case GPE_CONTIG_IDLOC: return "__IDLOC directives must be contiguous."; case GPE_MISSING_BRACKET: return "Square brackets required around offset operand."; case GPE_CONFIG_UNKNOWN: return "An error with the CONFIG directive occured."; case GPE_CONFIG_usCONFIG: return "You cannot mix CONFIG and __CONFIG directives."; case GPE_UNKNOWN: default: return "UNKNOWN"; } } void gperror(unsigned int code, char *message) { char full_message[BUFSIZ]; if (state.pass == 2) { if(message == NULL) message = gp_geterror(code); #ifndef GP_USER_ERROR /* standard output */ if (!state.quiet) { if (state.src) snprintf(full_message, sizeof(full_message), "%s:%d:Error [%03d] %s", state.src->name, state.src->line_number, code, message); else snprintf(full_message, sizeof(full_message), "Error [%03d] %s", code, message); printf("%s\n", full_message); } #else user_error(code, message); #endif /* list file output */ snprintf(full_message, sizeof(full_message), "Error [%03d] : %s", code, message); lst_line(full_message); state.num.errors++; } } char *gp_getwarning(unsigned int code) { switch(code) { case GPW_NOT_DEFINED: return "Symbol not previously defined."; case GPW_RANGE: return "Argument out of range. Least significant bits used."; case GPW_OP_COLUMN_ONE: return "Found opcode in column 1."; case GPW_DIR_COLUMN_ONE: return "Found directive in column 1."; case GPW_MACRO_COLUMN_ONE: return "Found call to macro in column 1."; case GPW_LABEL_COLUMN: return "Found label after column 1."; case GPW_MISSING_QUOTE: return "Missing quote."; case GPW_EXTRANEOUS: return "Extraneous arguments on the line."; case GPW_EXPECTED: return "Expected."; case GPW_CMDLINE_PROC: return "Processor superseded by command line."; case GPW_CMDLINE_RADIX: return "Radix superseded by command line."; case GPW_CMDLINE_HEXFMT: return "Hex file format specified on command line."; case GPW_RADIX: return "Expected dec, oct, hex. Will use hex."; case GPW_INVALID_RAM: return "Invalid RAM location specified."; case GPW_EXCEED_ROM: return "Address exceeds maximum range for this processor."; case GPW_DISABLE_ERROR: return "Error messages cannot be disabled."; case GPW_REDEFINING_PROC: return "Redefining processor."; case GPW_NOT_RECOMMENDED: return "Use of this instruction is not recommended."; case GPW_INVALID_ROM: return "Invalid ROM location specified."; case GPW_UNKNOWN: default: return "UNKNOWN"; } } void gpwarning(unsigned int code, char *message) { char full_message[BUFSIZ]; if (state.pass ==2) { if ((state.error_level <= 1) && check_code(code)) { if(message == NULL) message = gp_getwarning(code); #ifndef GP_USER_WARNING /* standard output */ if (!state.quiet) { if (state.src) snprintf(full_message, sizeof(full_message), "%s:%d:Warning [%03d] %s", state.src->name, state.src->line_number, code, message); else snprintf(full_message, sizeof(full_message), "Warning [%03d] %s", code, message); printf("%s\n", full_message); } #else user_warning(code, message); #endif /* list file output */ snprintf(full_message, sizeof(full_message), "Warning [%03d] : %s", code, message); lst_line(full_message); state.num.warnings++; } else { state.num.warnings_suppressed++; } } } char *gp_getmessage(unsigned int code) { switch(code) { case GPM_USER: return "MESSAGE:"; case GPM_BANK: return "Register in operand not in bank 0. Ensure bank bits are correct."; case GPM_RANGE: return "Program word too large. Truncated to core size."; case GPM_IDLOC: return "ID Locations value too large. Last four hex digits used."; case GPM_NOF: return "Using default destination of 1 (file)."; case GPM_PAGE: return "Crossing page boundary -- ensure page bits are set."; case GPM_PAGEBITS: return "Setting page bits."; case GPM_SUPVAL: return "Warning level superceded by command line value."; case GPM_SUPLIN: return "Macro expansion superceded by command line value."; case GPM_SUPRAM: return "Superceding current maximum RAM and RAM map."; case GPM_EXTPAGE: return "Page or Bank selection not needed for this device."; case GPM_CBLOCK: return "CBLOCK constants will start with a value of 0."; case GPM_W_MODIFIED: return "W Register modified."; case GPM_SPECIAL_MNEMONIC: return "Special Instruction Mnemonic used."; case GPM_UNKNOWN: default: return "UNKNOWN MESSAGE"; } } void gpmessage(unsigned int code, char *message) { char full_message[BUFSIZ]; if (state.pass==2) { if ((state.error_level == 0) && check_code(code)){ if(message == NULL) message = gp_getmessage(code); #ifndef GP_USER_MESSAGE /* standard output */ if (!state.quiet) { if (state.src) snprintf(full_message, sizeof(full_message), "%s:%d:Message [%03d] %s", state.src->name, state.src->line_number, code, message); else snprintf(full_message, sizeof(full_message), "Message [%03d] %s", code, message); printf("%s\n", full_message); } #else user_message(code, message); #endif /* list file output */ snprintf(full_message, sizeof(full_message), "Message [%03d] : %s", code, message); lst_line(full_message); state.num.messages++; } else { state.num.messages_suppressed++; } } } gputils-0.13.7/gpasm/gpasm.c0000644000175000017500000002731111156521302012574 00000000000000/* top level functions for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "gperror.h" #include "scan.h" #include "deps.h" #include "directive.h" #include "lst.h" #include "cod.h" #include "processor.h" #include "coff.h" struct gpasm_state state; static gp_boolean cmd_processor = false; static char *processor_name = NULL; int yyparse(void); extern int yydebug; #define GET_OPTIONS "?D:I:a:cCde:ghilLmMno:p:qr:uvw:y" static struct option longopts[] = { { "define", 1, 0, 'D' }, { "include", 1, 0, 'I' }, { "hex-format", 1, 0, 'a' }, { "object", 0, 0, 'c' }, { "new-coff", 0, 0, 'C' }, { "debug", 0, 0, 'd' }, { "expand", 1, 0, 'e' }, { "debug-info", 0, 0, 'g' }, { "help", 0, 0, 'h' }, { "ignore-case", 0, 0, 'i' }, { "list-chips", 0, 0, 'l' }, { "force-list", 0, 0, 'L' }, { "dump", 0, 0, 'm' }, { "deps", 0, 0, 'M' }, { "dos", 0, 0, 'n' }, { "output", 1, 0, 'o' }, { "processor", 1, 0, 'p' }, { "quiet", 0, 0, 'q' }, { "radix", 1, 0, 'r' }, { "absolute", 0, 0, 'u' }, { "version", 0, 0, 'v' }, { "warning", 1, 0, 'w' }, { "extended", 0, 0, 'y' }, { 0, 0, 0, 0 } }; void init(void) { gp_init(); /* restore gpasm to its initialized state */ state.mode = absolute; state.extended_pic16e = false; state.radix = 16; state.hex_format = inhx32; state.case_insensitive = false; state.quiet = false; state.use_absolute_path = false; state.error_level = 0; state.debug_info = false; state.path_num = 0; state.cmd_line.radix = false; state.cmd_line.hex_format = false; state.cmd_line.error_level = false; state.cmd_line.macro_expand = false; state.cmd_line.processor = false; state.cmd_line.lst_force = false; state.pass = 0; state.org = 0; state.dos_newlines = false; state.memory_dump = false; state.found_config = false; state.found_devid = false; state.found_idlocs = false; state.maxram = (MAX_RAM - 1); state.codfile = normal; state.depfile = suppress; state.hexfile = normal; state.lstfile = normal; state.objfile = suppress; state.num.errors = 0; state.num.warnings = 0; state.num.messages = 0; state.num.warnings_suppressed = 0; state.num.messages_suppressed = 0; state.processor = no_processor; state.processor_chosen = 0; state.cod.enabled = false; state.dep.enabled = false; state.lst.enabled = false; state.obj.enabled = false; state.obj.newcoff = 0; state.obj.object = NULL; state.obj.section = NULL; state.obj.symbol_num = 0; state.obj.section_num = 0; state.astack = NULL; state.next_state = state_nochange; return; } void add_path(char *path) { if(state.path_num < MAX_PATHS) { state.paths[state.path_num++] = strdup(path); } else { fprintf(stderr, "too many -I paths\n"); exit(1); } } static void show_usage(void) { printf("Usage: gpasm [options] file\n"); printf("Options: [defaults in brackets after descriptions]\n"); printf(" -a FMT, --hex-format FMT Select hex file format. [inhx32]\n"); printf(" -c, --object Output relocatable object.\n"); printf(" -C, --new-coff Use new Microchip format.\n"); printf(" -d, --debug Output debug messages.\n"); printf(" -D SYM=VAL, --define SYM=VAL Define SYM with value VAL.\n"); printf(" -e [ON|OFF], --expand [ON|OFF] Macro expansion.\n"); printf(" -g, --debug-info Use debug directives for COFF.\n"); printf(" -h, --help Show this usage message.\n"); printf(" -i, --ignore-case Case insensitive.\n"); printf(" -I DIR, --include DIR Specify include directory.\n"); printf(" -l, --list-chips List supported processors.\n"); printf(" -L, --force-list Ignore nolist directives.\n"); printf(" -m, --dump Memory dump.\n"); printf(" -M, --deps Output dependency file.\n"); #ifndef HAVE_DOS_BASED_FILE_SYSTEM printf(" -n, --dos Use DOS newlines in hex file.\n"); #endif printf(" -o FILE, --output FILE Alternate name of output file.\n"); printf(" -p PROC, --processor PROC Select processor.\n"); printf(" -q, --quiet Quiet.\n"); printf(" -r RADIX, --radix RADIX Select radix. [hex]\n"); printf(" -u, --absolute Use absolute pathes. \n"); printf(" -v, --version Show version.\n"); printf(" -w [0|1|2], --warning [0|1|2] Set message level. [0]\n"); printf(" -y, --extended Enable 18xx extended mode.\n"); printf("\n"); #ifdef USE_DEFAULT_PATHS if (gp_header_path) { printf("Default header file path %s\n", gp_header_path); } else { printf("Default header file path NOT SET\n"); } printf("\n"); #endif printf("Report bugs to:\n"); printf("%s\n", PACKAGE_BUGREPORT); } void process_args( int argc, char *argv[]) { extern char *optarg; extern int optind; int c; gp_boolean usage = false; int usage_code = 0; char *pc; /* Scan through the options for the -i flag. It must be set before the defines are read */ while ((c = getopt_long(argc, argv, GET_OPTIONS, longopts, 0)) != EOF) { switch (c) { case 'i': state.case_insensitive = true; break; } } /* reset the getopt_long index for the next call */ optind = 1; /* initalize the defines table for command line arguments */ state.stDefines = push_symbol_table(NULL, state.case_insensitive); while ((c = getopt_long(argc, argv, GET_OPTIONS, longopts, 0)) != EOF) { switch (c) { case '?': usage_code = 1; case 'h': usage = true; break; case 'a': select_hexformat(optarg); state.cmd_line.hex_format = true; break; case 'c': state.mode = relocatable; state.codfile = suppress; state.hexfile = suppress; state.lstfile = normal; state.objfile = normal; break; case 'C': state.obj.newcoff = 1; break; case 'd': gp_debug_disable = false; break; case 'D': if ((optarg != NULL) && (strlen(optarg) > 0)) { struct symbol *sym; char *lhs, *rhs; lhs = strdup(optarg); rhs = strchr(lhs, '='); if (rhs != NULL) { *rhs = '\0'; /* Terminate the left-hand side */ rhs++; /* right-hand side begins after the '=' */ } sym = get_symbol(state.stDefines, lhs); if (sym == NULL) sym = add_symbol(state.stDefines, lhs); if (rhs) annotate_symbol(sym, rhs); } break; case 'e': select_expand(optarg); state.cmd_line.macro_expand = true; break; case 'g': state.debug_info = true; break; case 'I': add_path(optarg); break; case 'i': state.case_insensitive = true; break; case 'L': state.cmd_line.lst_force = true; break; case 'l': gp_dump_processor_list(true, 0); exit(0); break; case 'M': state.depfile = normal; break; case 'm': state.memory_dump = true; break; case 'n': #ifndef HAVE_DOS_BASED_FILE_SYSTEM state.dos_newlines = true; #endif break; case 'o': strncpy(state.hexfilename, optarg, sizeof(state.hexfilename)); strncpy(state.basefilename, optarg, sizeof(state.basefilename)); pc = strrchr(state.basefilename, '.'); if (pc) *pc = 0; break; case 'p': cmd_processor = true; processor_name = optarg; break; case 'q': state.quiet = true; break; case 'r': select_radix(optarg); state.cmd_line.radix = true; break; case 'u': state.use_absolute_path = true; break; case 'w': select_errorlevel(atoi(optarg)); state.cmd_line.error_level = true; break; case 'y': state.extended_pic16e = true; break; case 'v': fprintf(stderr, "%s\n", GPASM_VERSION_STRING); exit(0); } if (usage) break; } if ((optind + 1) == argc) state.srcfilename = argv[optind]; else usage = true; if (usage) { show_usage(); exit(usage_code); } /* Add the header path to the include paths list last, so that the user specified directories are searched first */ if (gp_header_path) { add_path(gp_header_path); } if (state.use_absolute_path) { state.srcfilename = gp_absolute_path(state.srcfilename); } } int assemble(void) { char *pc; struct symbol_table *cmd_defines; /* store the command line defines to restore on second pass */ cmd_defines = state.stDefines; state.c_memory = state.i_memory = i_memory_create(); if(state.basefilename[0] == '\0') { strncpy(state.basefilename, state.srcfilename, sizeof(state.basefilename)); pc = strrchr(state.basefilename, '.'); if (pc) *pc = 0; } /* Builtins are always case insensitive */ state.stBuiltin = push_symbol_table(NULL, true); state.stDirective = state.stBuiltin; state.stMacros = push_symbol_table(NULL, state.case_insensitive); state.stTop = state.stGlobal = push_symbol_table(NULL, state.case_insensitive); state.stTopDefines = state.stDefines = push_symbol_table(cmd_defines, state.case_insensitive); opcode_init(0); /* the tables are built, select the processor if -p was used */ if (cmd_processor) { select_processor(processor_name); state.cmd_line.processor = true; } state.pass = 1; open_src(state.srcfilename, 0); yyparse(); state.pass++; state.org = 0; state.cblock = 0; state.cblock_defined = 0; /* clean out defines for second pass */ state.stTopDefines = state.stDefines = push_symbol_table(cmd_defines, state.case_insensitive); purge_temp_symbols(state.stTop); if (!state.cmd_line.radix) state.radix = 16; state.obj.symbol_num = 0; state.obj.section_num = 0; state.found_config = false; state.found_devid = false; state.found_idlocs = false; coff_init(); cod_init(); deps_init(); lst_init(); open_src(state.srcfilename, 0); if (!gp_debug_disable) { yydebug = 1; } else { yydebug = 0; } yyparse(); assert(state.pass == 2); pop_symbol_table(state.stBuiltin); hex_init(); if(state.memory_dump) print_i_memory(state.i_memory, state.device.class == PROC_CLASS_PIC16E ? 1 : 0); /* Maybe produce a symbol table */ if (state.lst.symboltable) { lst_throw(); /* Start symbol table on a fresh page */ lst_symbol_table(state.stGlobal); lst_defines_table(state.stDefines); } /* Maybe produce a memory map */ if ((state.mode == absolute) && (state.lst.memorymap)) { lst_memory_map(state.i_memory); } /* Finish off the object, dependency, listing, and symbol files*/ coff_close_file(); deps_close(); lst_close(); if (state.processor_info) cod_close_file(); free_files(); if ((state.num.errors > 0) || (gp_num_errors > 0)) return EXIT_FAILURE; else return EXIT_SUCCESS; } gputils-0.13.7/gpasm/lst.h0000644000175000017500000000216311156313231012272 00000000000000/* ".LST" file output for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __LST_H__ #define __LST_H__ void lst_line(char *line); void lst_throw(void); void lst_init(void); void lst_memory_map(MemBlock *m); void lst_close(void); void lst_format_line(char *line, int value); void lst_symbol_table(struct symbol_table *); void lst_defines_table(struct symbol_table *); #endif gputils-0.13.7/gpasm/special.h0000644000175000017500000000167511156521302013117 00000000000000/* Implements special instruction mnemonics Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __SPECIAL_H__ #define __SPECIAL_H__ extern struct insn special[]; extern const int num_op_special; extern struct insn op_sx_mode; #endif gputils-0.13.7/gpasm/cod.h0000644000175000017500000000210711156313231012233 00000000000000/* ".COD" file output for gpasm Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __COD_H__ #define __COD_H__ /* line types for cod_lst_line */ #define COD_FIRST_LST_LINE 1 #define COD_NORMAL_LST_LINE 2 #define COD_LAST_LST_LINE 3 void cod_init(void); void cod_close_file(void); void cod_lst_line(int line_type); void cod_write_symbols(struct symbol **,int); #endif gputils-0.13.7/gpasm/scan.h0000644000175000017500000000211611156313231012412 00000000000000/* Definitions for functions exported by the lexical analyser Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __SCAN_H__ #define __SCAN_H__ void open_src(char *name, int is_include_file); void close_file(); void execute_exitm(); void execute_macro(struct macro_head *h, int is_while); extern int force_ident; extern int force_decimal; #endif gputils-0.13.7/gpasm/directive.h0000644000175000017500000000256311156313231013452 00000000000000/* Implements directives, pseudo-ops and processor opcodes Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __OPCODE_H__ #define __OPCODE_H__ #define HEAD(L) (L)->value.list.head #define TAIL(L) (L)->value.list.tail #define CORE_8BIT_MASK 0xff #define CORE_12BIT_MASK 0xfff #define CORE_14BIT_MASK 0x3fff #define CORE_16BIT_MASK 0xffff gpasmVal do_insn(char *name, struct pnode *parms); void opcode_init(int stage); void begin_cblock(struct pnode *c); void continue_cblock(void); void cblock_expr(struct pnode *s); void cblock_expr_incr(struct pnode *s, struct pnode *incr); int asm_enabled(void); int check_page(int address); #endif gputils-0.13.7/gpasm/processor.c0000644000175000017500000000562011156521302013503 00000000000000/* PIC Processor selection Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "directive.h" #include "gperror.h" extern int _16bit_core; extern int _17cxx_core; void select_processor(char *name) { struct px *found = NULL; if (state.cmd_line.processor) { gpwarning(GPW_CMDLINE_PROC, NULL); } else { found = gp_find_processor(name); if (found) { int badrom_idx; if (state.processor == no_processor) { state.processor = found; state.maxrom = found->maxrom; /* initialize badrom from internal processor info */ state.badrom = NULL; for (badrom_idx = 0; badrom_idx < MAX_BADROM; badrom_idx+=2) { long start, end; start = found->badrom[badrom_idx]; end = found->badrom[badrom_idx+1]; if ((start == -1) || (end == -1)) break; else { struct range_pair *new_pair = malloc(sizeof(struct range_pair)); new_pair->start = start; new_pair->end = end; new_pair->next = state.badrom; state.badrom = new_pair; } } state.processor_info = found; set_global(found->defined_as, 1, PERMANENT, gvt_constant); } else if (state.processor != found ) { gpwarning(GPW_REDEFINING_PROC, NULL); gperror(GPE_EXTRA_PROC, NULL); } } else { if (state.pass) { gperror(GPE_UNKNOWN_PROC, NULL); } else { printf("Didn't find any processor named: %s\nHere are the supported processors:\n",name); gp_dump_processor_list(true, 0); exit(1); } } /* load the instruction sets if necessary */ if ((state.processor_chosen == 0) && (state.processor != no_processor)) { opcode_init(1); /* General directives */ /* seperate the directives from the opcodes */ state.stBuiltin = push_symbol_table(state.stBuiltin, true); opcode_init(2); /* Processor-specific */ if (!_16bit_core && !_17cxx_core) { opcode_init(3); /* Special pseudo ops for 12 and 14 bit devices */ } state.processor_chosen = 1; } } } gputils-0.13.7/gpasm/parse.c0000644000175000017500000023206011156521335012604 00000000000000/* A Bison parser, made by GNU Bison 2.3. */ /* Skeleton implementation for Bison's Yacc-like parsers in C Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ /* As a special exception, you may create a larger work that contains part or all of the Bison parser skeleton and distribute that work under terms of your choice, so long as that work isn't itself a parser generator using the skeleton or a modified version thereof as a parser skeleton. Alternatively, if you modify or redistribute the parser skeleton itself, you may (at your option) remove this special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ /* C LALR(1) parser skeleton written by Richard Stallman, by simplifying the original so-called "semantic" parser. */ /* All symbols defined below should begin with yy or YY, to avoid infringing on user name space. This should be done even for local variables, as they might otherwise be expanded by user macros. There are some unavoidable exceptions within include files to define necessary library symbols; they are noted "INFRINGES ON USER NAME SPACE" below. */ /* Identify Bison output. */ #define YYBISON 1 /* Bison version. */ #define YYBISON_VERSION "2.3" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" /* Pure parsers. */ #define YYPURE 0 /* Using locations. */ #define YYLSP_NEEDED 0 /* Tokens. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE /* Put the tokens into the symbol table, so that GDB and other debuggers know about them. */ enum yytokentype { LABEL = 258, IDENTIFIER = 259, CBLOCK = 260, DEBUG_LINE = 261, ENDC = 262, ERRORLEVEL = 263, FILL = 264, LIST = 265, NUMBER = 266, PROCESSOR = 267, STRING = 268, DEFINE = 269, UPPER = 270, HIGH = 271, LOW = 272, LSH = 273, RSH = 274, GREATER_EQUAL = 275, LESS_EQUAL = 276, EQUAL = 277, NOT_EQUAL = 278, LOGICAL_AND = 279, LOGICAL_OR = 280, ASSIGN_PLUS = 281, ASSIGN_MINUS = 282, ASSIGN_MULTIPLY = 283, ASSIGN_DIVIDE = 284, ASSIGN_MODULUS = 285, ASSIGN_LSH = 286, ASSIGN_RSH = 287, ASSIGN_AND = 288, ASSIGN_OR = 289, ASSIGN_XOR = 290, INCREMENT = 291, DECREMENT = 292, TBL_NO_CHANGE = 293, TBL_POST_INC = 294, TBL_POST_DEC = 295, TBL_PRE_INC = 296, CONCAT = 297, VAR = 298, VARLAB_BEGIN = 299, VAR_BEGIN = 300, VAR_END = 301 }; #endif /* Tokens. */ #define LABEL 258 #define IDENTIFIER 259 #define CBLOCK 260 #define DEBUG_LINE 261 #define ENDC 262 #define ERRORLEVEL 263 #define FILL 264 #define LIST 265 #define NUMBER 266 #define PROCESSOR 267 #define STRING 268 #define DEFINE 269 #define UPPER 270 #define HIGH 271 #define LOW 272 #define LSH 273 #define RSH 274 #define GREATER_EQUAL 275 #define LESS_EQUAL 276 #define EQUAL 277 #define NOT_EQUAL 278 #define LOGICAL_AND 279 #define LOGICAL_OR 280 #define ASSIGN_PLUS 281 #define ASSIGN_MINUS 282 #define ASSIGN_MULTIPLY 283 #define ASSIGN_DIVIDE 284 #define ASSIGN_MODULUS 285 #define ASSIGN_LSH 286 #define ASSIGN_RSH 287 #define ASSIGN_AND 288 #define ASSIGN_OR 289 #define ASSIGN_XOR 290 #define INCREMENT 291 #define DECREMENT 292 #define TBL_NO_CHANGE 293 #define TBL_POST_INC 294 #define TBL_POST_DEC 295 #define TBL_PRE_INC 296 #define CONCAT 297 #define VAR 298 #define VARLAB_BEGIN 299 #define VAR_BEGIN 300 #define VAR_END 301 /* Copy the first part of user declarations. */ #line 1 "parse.y" /* Parser for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "evaluate.h" #include "gperror.h" #include "directive.h" #include "lst.h" #include "macro.h" #include "coff.h" #include "scan.h" void yyerror(char *message) { gperror(103, message); } int yylex(void); extern int _16bit_core; extern gp_boolean _16packed_byte_acc; static gp_boolean _16packed_offset_labels; /************************************************************************/ /* Some simple functions for building parse trees */ static struct pnode *mk_pnode(enum pnode_tag tag) { struct pnode *new = malloc(sizeof(*new)); new->tag = tag; return new; } struct pnode *mk_constant(int value) { struct pnode *new = mk_pnode(constant); new->value.constant = value; return new; } struct pnode *mk_offset(struct pnode *p) { struct pnode *new = mk_pnode(offset); new->value.offset = p; return new; } static struct pnode *mk_symbol(char *value) { struct pnode *new = mk_pnode(symbol); new->value.symbol = value; return new; } static struct pnode *mk_string(char *value) { struct pnode *new = mk_pnode(string); new->value.string = value; return new; } struct pnode *mk_list(struct pnode *head, struct pnode *tail) { struct pnode *new = mk_pnode(list); new->value.list.head = head; new->value.list.tail = tail; return new; } static struct pnode *mk_2op(int op, struct pnode *p0, struct pnode *p1) { struct pnode *new = mk_pnode(binop); new->value.binop.op = op; new->value.binop.p0 = p0; new->value.binop.p1 = p1; return new; } static struct pnode *mk_1op(int op, struct pnode *p0) { struct pnode *new = mk_pnode(unop); new->value.unop.op = op; new->value.unop.p0 = p0; return new; } /************************************************************************/ /* shared functions */ gpasmVal set_label(char *label, struct pnode *parms) { gpasmVal value = 0; if (asm_enabled()) { value = do_or_append_insn("set", parms); if (!state.mac_prev) { set_global(label, value, TEMPORARY, gvt_constant); } } return value; } int return_op(int operation); void next_line(int value) { char l[BUFSIZ]; char *e = l; if ((state.src->type == src_macro) || (state.src->type == src_while)) { /* while loops can be defined inside a macro or nested */ if (state.mac_prev) { state.lst.line.linetype = none; if (state.mac_body) state.mac_body->src_line = strdup(state.src->lst.m->src_line); } if (((state.src->type == src_while) || (state.lst.expand)) && (state.pass == 2)) { assert(state.src->lst.m->src_line != NULL); lst_format_line(state.src->lst.m->src_line, value); } if (state.src->lst.m->next) { state.src->lst.m = state.src->lst.m->next; } } else if ((state.src->type == src_file) && (state.src->lst.f != NULL)) { fgets(l, BUFSIZ, state.src->lst.f); l[strlen(l) - 1] = '\0'; /* Eat the trailing newline */ if (state.mac_prev) { state.lst.line.linetype = none; if (state.mac_body) state.mac_body->src_line = strdup(l); } if (state.pass == 2) { lst_format_line(e, value); } } state.src->line_number++; switch (state.next_state) { case state_exitmacro: execute_exitm(); break; case state_include: open_src(state.next_buffer.file, 1); free(state.next_buffer.file); break; case state_macro: /* push the label for local directive */ state.stTop = push_macro_symbol_table(state.stTop); execute_macro(state.next_buffer.macro, 0); break; case state_section: /* create a new coff section */ coff_new_section(state.obj.new_sec_name, state.obj.new_sec_addr, state.obj.new_sec_flags); break; case state_while: execute_macro(state.next_buffer.macro, 1); break; default: break; } } /************************************************************************/ /* Enabling traces. */ #ifndef YYDEBUG # define YYDEBUG 1 #endif /* Enabling verbose error messages. */ #ifdef YYERROR_VERBOSE # undef YYERROR_VERBOSE # define YYERROR_VERBOSE 1 #else # define YYERROR_VERBOSE 0 #endif /* Enabling the token table. */ #ifndef YYTOKEN_TABLE # define YYTOKEN_TABLE 0 #endif #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED typedef union YYSTYPE #line 208 "parse.y" { gpasmVal i; char *s; struct pnode *p; } /* Line 187 of yacc.c. */ #line 399 "parse.c" YYSTYPE; # define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 # define YYSTYPE_IS_TRIVIAL 1 #endif /* Copy the second part of user declarations. */ /* Line 216 of yacc.c. */ #line 412 "parse.c" #ifdef short # undef short #endif #ifdef YYTYPE_UINT8 typedef YYTYPE_UINT8 yytype_uint8; #else typedef unsigned char yytype_uint8; #endif #ifdef YYTYPE_INT8 typedef YYTYPE_INT8 yytype_int8; #elif (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) typedef signed char yytype_int8; #else typedef short int yytype_int8; #endif #ifdef YYTYPE_UINT16 typedef YYTYPE_UINT16 yytype_uint16; #else typedef unsigned short int yytype_uint16; #endif #ifdef YYTYPE_INT16 typedef YYTYPE_INT16 yytype_int16; #else typedef short int yytype_int16; #endif #ifndef YYSIZE_T # ifdef __SIZE_TYPE__ # define YYSIZE_T __SIZE_TYPE__ # elif defined size_t # define YYSIZE_T size_t # elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) # include /* INFRINGES ON USER NAME SPACE */ # define YYSIZE_T size_t # else # define YYSIZE_T unsigned int # endif #endif #define YYSIZE_MAXIMUM ((YYSIZE_T) -1) #ifndef YY_ # if YYENABLE_NLS # if ENABLE_NLS # include /* INFRINGES ON USER NAME SPACE */ # define YY_(msgid) dgettext ("bison-runtime", msgid) # endif # endif # ifndef YY_ # define YY_(msgid) msgid # endif #endif /* Suppress unused-variable warnings by "using" E. */ #if ! defined lint || defined __GNUC__ # define YYUSE(e) ((void) (e)) #else # define YYUSE(e) /* empty */ #endif /* Identity function, used to suppress warnings about constant conditions. */ #ifndef lint # define YYID(n) (n) #else #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static int YYID (int i) #else static int YYID (i) int i; #endif { return i; } #endif #if ! defined yyoverflow || YYERROR_VERBOSE /* The parser invokes alloca or malloc; define the necessary symbols. */ # ifdef YYSTACK_USE_ALLOCA # if YYSTACK_USE_ALLOCA # ifdef __GNUC__ # define YYSTACK_ALLOC __builtin_alloca # elif defined __BUILTIN_VA_ARG_INCR # include /* INFRINGES ON USER NAME SPACE */ # elif defined _AIX # define YYSTACK_ALLOC __alloca # elif defined _MSC_VER # include /* INFRINGES ON USER NAME SPACE */ # define alloca _alloca # else # define YYSTACK_ALLOC alloca # if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) # include /* INFRINGES ON USER NAME SPACE */ # ifndef _STDLIB_H # define _STDLIB_H 1 # endif # endif # endif # endif # endif # ifdef YYSTACK_ALLOC /* Pacify GCC's `empty if-body' warning. */ # define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0)) # ifndef YYSTACK_ALLOC_MAXIMUM /* The OS might guarantee only one guard page at the bottom of the stack, and a page size can be as small as 4096 bytes. So we cannot safely invoke alloca (N) if N exceeds 4096. Use a slightly smaller number to allow for a few compiler-allocated temporary stack slots. */ # define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */ # endif # else # define YYSTACK_ALLOC YYMALLOC # define YYSTACK_FREE YYFREE # ifndef YYSTACK_ALLOC_MAXIMUM # define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM # endif # if (defined __cplusplus && ! defined _STDLIB_H \ && ! ((defined YYMALLOC || defined malloc) \ && (defined YYFREE || defined free))) # include /* INFRINGES ON USER NAME SPACE */ # ifndef _STDLIB_H # define _STDLIB_H 1 # endif # endif # ifndef YYMALLOC # define YYMALLOC malloc # if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ # endif # endif # ifndef YYFREE # define YYFREE free # if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif # endif # endif #endif /* ! defined yyoverflow || YYERROR_VERBOSE */ #if (! defined yyoverflow \ && (! defined __cplusplus \ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) /* A type that is properly aligned for any stack member. */ union yyalloc { yytype_int16 yyss; YYSTYPE yyvs; }; /* The size of the maximum gap between one aligned stack and the next. */ # define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1) /* The size of an array large to enough to hold all stacks, each with N elements. */ # define YYSTACK_BYTES(N) \ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \ + YYSTACK_GAP_MAXIMUM) /* Copy COUNT objects from FROM to TO. The source and destination do not overlap. */ # ifndef YYCOPY # if defined __GNUC__ && 1 < __GNUC__ # define YYCOPY(To, From, Count) \ __builtin_memcpy (To, From, (Count) * sizeof (*(From))) # else # define YYCOPY(To, From, Count) \ do \ { \ YYSIZE_T yyi; \ for (yyi = 0; yyi < (Count); yyi++) \ (To)[yyi] = (From)[yyi]; \ } \ while (YYID (0)) # endif # endif /* Relocate STACK from its old location to the new one. The local variables YYSIZE and YYSTACKSIZE give the old and new number of elements in the stack, and YYPTR gives the new location of the stack. Advance YYPTR to a properly aligned location for the next stack. */ # define YYSTACK_RELOCATE(Stack) \ do \ { \ YYSIZE_T yynewbytes; \ YYCOPY (&yyptr->Stack, Stack, yysize); \ Stack = &yyptr->Stack; \ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ yyptr += yynewbytes / sizeof (*yyptr); \ } \ while (YYID (0)) #endif /* YYFINAL -- State number of the termination state. */ #define YYFINAL 2 /* YYLAST -- Last index in YYTABLE. */ #define YYLAST 421 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 68 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 41 /* YYNRULES -- Number of rules. */ #define YYNRULES 123 /* YYNRULES -- Number of states. */ #define YYNSTATES 186 /* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ #define YYUNDEFTOK 2 #define YYMAXUTOK 301 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) /* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */ static const yytype_uint8 yytranslate[] = { 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, 62, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 60, 2, 2, 66, 59, 26, 2, 67, 63, 57, 55, 64, 56, 2, 58, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 65, 2, 24, 31, 25, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 53, 2, 54, 28, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 27, 2, 61, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 29, 30, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 }; #if YYDEBUG /* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in YYRHS. */ static const yytype_uint16 yyprhs[] = { 0, 0, 3, 4, 5, 9, 13, 18, 23, 27, 31, 34, 36, 38, 40, 42, 43, 48, 51, 52, 57, 58, 63, 68, 72, 75, 78, 82, 89, 97, 98, 106, 107, 114, 119, 120, 123, 125, 128, 131, 135, 137, 141, 143, 147, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 172, 176, 179, 181, 183, 187, 189, 191, 195, 197, 199, 203, 205, 207, 211, 213, 215, 217, 219, 223, 225, 227, 229, 231, 233, 235, 237, 241, 243, 245, 247, 251, 253, 255, 257, 261, 263, 265, 267, 269, 272, 274, 276, 278, 280, 282, 284, 286, 288, 290, 292, 294, 298, 302, 304, 306, 308, 310, 312, 316, 320, 322, 326, 330, 332, 336, 337, 342 }; /* YYRHS -- A `-1'-separated list of the rules' RHS. */ static const yytype_int8 yyrhs[] = { 69, 0, -1, -1, -1, 69, 70, 71, -1, 69, 1, 62, -1, 105, 83, 85, 62, -1, 105, 31, 85, 62, -1, 105, 43, 62, -1, 105, 42, 62, -1, 105, 73, -1, 73, -1, 8, -1, 6, -1, 62, -1, -1, 12, 74, 4, 62, -1, 10, 62, -1, -1, 10, 75, 106, 62, -1, -1, 72, 76, 84, 62, -1, 14, 4, 13, 62, -1, 14, 4, 62, -1, 14, 62, -1, 4, 62, -1, 4, 84, 62, -1, 9, 4, 63, 64, 85, 62, -1, 9, 4, 84, 63, 64, 85, 62, -1, -1, 5, 85, 62, 77, 79, 7, 62, -1, -1, 5, 62, 78, 79, 7, 62, -1, 5, 1, 7, 62, -1, -1, 79, 80, -1, 62, -1, 81, 62, -1, 105, 62, -1, 105, 85, 62, -1, 82, -1, 81, 64, 82, -1, 104, -1, 104, 65, 85, -1, 32, -1, 33, -1, 34, -1, 35, -1, 36, -1, 37, -1, 38, -1, 39, -1, 40, -1, 41, -1, 85, -1, 85, 64, -1, 85, 64, 84, -1, 64, 84, -1, 64, -1, 87, -1, 85, 86, 87, -1, 31, -1, 89, -1, 87, 88, 89, -1, 30, -1, 91, -1, 89, 90, 91, -1, 29, -1, 93, -1, 91, 92, 93, -1, 26, -1, 27, -1, 28, -1, 95, -1, 93, 94, 95, -1, 24, -1, 25, -1, 22, -1, 23, -1, 20, -1, 21, -1, 97, -1, 95, 96, 97, -1, 18, -1, 19, -1, 99, -1, 97, 98, 99, -1, 55, -1, 56, -1, 101, -1, 99, 100, 101, -1, 57, -1, 58, -1, 59, -1, 103, -1, 102, 103, -1, 15, -1, 16, -1, 17, -1, 56, -1, 60, -1, 61, -1, 55, -1, 104, -1, 11, -1, 66, -1, 13, -1, 67, 85, 63, -1, 53, 85, 54, -1, 57, -1, 45, -1, 46, -1, 47, -1, 4, -1, 51, 85, 63, -1, 51, 85, 52, -1, 3, -1, 50, 85, 63, -1, 50, 85, 52, -1, 107, -1, 107, 64, 106, -1, -1, 4, 108, 86, 87, -1, 87, -1 }; /* YYRLINE[YYN] -- source line where rule number YYN was defined. */ static const yytype_uint16 yyrline[] = { 0, 306, 306, 310, 309, 315, 322, 334, 343, 352, 361, 432, 444, 444, 447, 456, 456, 463, 468, 468, 475, 475, 482, 488, 493, 498, 503, 508, 524, 541, 540, 559, 558, 576, 582, 584, 591, 593, 600, 609, 620, 622, 626, 633, 641, 641, 641, 642, 642, 642, 642, 643, 643, 643, 646, 651, 656, 661, 666, 673, 675, 683, 686, 688, 696, 699, 701, 709, 712, 714, 722, 722, 722, 725, 727, 735, 735, 735, 735, 735, 735, 738, 740, 748, 748, 751, 753, 761, 761, 764, 766, 774, 774, 774, 777, 779, 786, 786, 786, 786, 786, 786, 786, 789, 794, 799, 804, 809, 814, 819, 824, 829, 834, 841, 846, 851, 859, 874, 883, 894, 899, 907, 906, 918 }; #endif #if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = { "$end", "error", "$undefined", "LABEL", "IDENTIFIER", "CBLOCK", "DEBUG_LINE", "ENDC", "ERRORLEVEL", "FILL", "LIST", "NUMBER", "PROCESSOR", "STRING", "DEFINE", "UPPER", "HIGH", "LOW", "LSH", "RSH", "GREATER_EQUAL", "LESS_EQUAL", "EQUAL", "NOT_EQUAL", "'<'", "'>'", "'&'", "'|'", "'^'", "LOGICAL_AND", "LOGICAL_OR", "'='", "ASSIGN_PLUS", "ASSIGN_MINUS", "ASSIGN_MULTIPLY", "ASSIGN_DIVIDE", "ASSIGN_MODULUS", "ASSIGN_LSH", "ASSIGN_RSH", "ASSIGN_AND", "ASSIGN_OR", "ASSIGN_XOR", "INCREMENT", "DECREMENT", "TBL_NO_CHANGE", "TBL_POST_INC", "TBL_POST_DEC", "TBL_PRE_INC", "CONCAT", "VAR", "VARLAB_BEGIN", "VAR_BEGIN", "VAR_END", "'['", "']'", "'+'", "'-'", "'*'", "'/'", "'%'", "'!'", "'~'", "'\\n'", "')'", "','", "':'", "'$'", "'('", "$accept", "program", "@1", "line", "decimal_ops", "statement", "@2", "@3", "@4", "@5", "@6", "const_block", "const_line", "const_def_list", "const_def", "assign_equal_ops", "parameter_list", "expr", "e9op", "e8", "e8op", "e7", "e7op", "e6", "e6op", "e5", "e5op", "e4", "e4op", "e3", "e3op", "e2", "e2op", "e1", "e1op", "e0", "cidentifier", "label_concat", "list_block", "list_expr", "@7", 0 }; #endif # ifdef YYPRINT /* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to token YYLEX-NUM. */ static const yytype_uint16 yytoknum[] = { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 60, 62, 38, 124, 94, 279, 280, 61, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 91, 93, 43, 45, 42, 47, 37, 33, 126, 10, 41, 44, 58, 36, 40 }; # endif /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { 0, 68, 69, 70, 69, 69, 71, 71, 71, 71, 71, 71, 72, 72, 73, 74, 73, 73, 75, 73, 76, 73, 73, 73, 73, 73, 73, 73, 73, 77, 73, 78, 73, 73, 79, 79, 80, 80, 80, 80, 81, 81, 82, 82, 83, 83, 83, 83, 83, 83, 83, 83, 83, 83, 84, 84, 84, 84, 84, 85, 85, 86, 87, 87, 88, 89, 89, 90, 91, 91, 92, 92, 92, 93, 93, 94, 94, 94, 94, 94, 94, 95, 95, 96, 96, 97, 97, 98, 98, 99, 99, 100, 100, 100, 101, 101, 102, 102, 102, 102, 102, 102, 102, 103, 103, 103, 103, 103, 103, 103, 103, 103, 103, 104, 104, 104, 105, 105, 105, 106, 106, 108, 107, 107 }; /* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ static const yytype_uint8 yyr2[] = { 0, 2, 0, 0, 3, 3, 4, 4, 3, 3, 2, 1, 1, 1, 1, 0, 4, 2, 0, 4, 0, 4, 4, 3, 2, 2, 3, 6, 7, 0, 7, 0, 6, 4, 0, 2, 1, 2, 2, 3, 1, 3, 1, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 2, 1, 1, 3, 1, 1, 3, 1, 1, 3, 1, 1, 3, 1, 1, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 3, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1, 1, 1, 3, 3, 1, 3, 3, 1, 3, 0, 4, 1 }; /* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state STATE-NUM when YYTABLE doesn't specify something else to do. Zero means the default is an error. */ static const yytype_uint8 yydefact[] = { 2, 0, 1, 0, 0, 5, 116, 0, 0, 13, 12, 0, 18, 15, 0, 0, 14, 4, 20, 11, 0, 113, 104, 106, 96, 97, 98, 110, 111, 112, 0, 0, 102, 99, 109, 100, 101, 25, 58, 105, 0, 0, 54, 59, 62, 65, 68, 73, 81, 85, 89, 0, 94, 103, 0, 31, 0, 0, 17, 0, 0, 0, 24, 0, 0, 0, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 0, 0, 10, 0, 0, 0, 57, 0, 26, 61, 55, 0, 64, 0, 67, 0, 70, 71, 72, 0, 79, 80, 77, 78, 75, 76, 0, 83, 84, 0, 87, 88, 0, 91, 92, 93, 0, 95, 0, 34, 29, 0, 0, 113, 123, 0, 119, 0, 0, 23, 118, 117, 0, 0, 9, 8, 0, 115, 114, 108, 107, 56, 60, 63, 66, 69, 74, 82, 86, 90, 33, 0, 34, 0, 0, 0, 19, 0, 16, 22, 21, 7, 6, 0, 36, 35, 0, 40, 42, 0, 0, 0, 0, 0, 120, 32, 37, 0, 0, 38, 0, 0, 27, 0, 122, 41, 43, 39, 30, 28 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int16 yydefgoto[] = { -1, 1, 4, 17, 18, 19, 60, 59, 64, 148, 115, 147, 161, 162, 163, 79, 41, 42, 87, 43, 89, 44, 91, 45, 95, 46, 102, 47, 105, 48, 108, 49, 112, 50, 51, 52, 53, 165, 121, 122, 151 }; /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing STATE-NUM. */ #define YYPACT_NINF -60 static const yytype_int16 yypact[] = { -60, 327, -60, -44, 272, -60, -60, -2, 23, -60, -60, 24, -32, -60, -1, 184, -60, -60, -60, -60, 359, -60, -60, -60, -60, -60, -60, -60, -60, -60, 184, 184, -60, -60, -60, -60, -60, -60, 108, -60, 184, -29, -27, 17, 34, 82, 169, 2, -30, 127, -60, 259, -60, -60, 66, -60, -12, 83, -60, 242, 63, 4, -60, -21, 108, 184, -60, -60, -60, -60, -60, -60, -60, -60, -60, -60, 30, 31, -60, 184, 50, -19, -60, -15, -60, -60, 108, 184, -60, 184, -60, 184, -60, -60, -60, 184, -60, -60, -60, -60, -60, -60, 184, -60, -60, 184, -60, -60, 184, -60, -60, -60, 184, -60, 35, -60, -60, 39, 42, 75, 17, 53, 52, 56, 58, -60, -60, -60, 64, 10, -60, -60, 15, -60, -60, -60, -60, -60, 17, 34, 82, 169, 2, -30, 127, -60, -60, 211, -60, 184, 67, 96, -60, 242, -60, -60, -60, -60, -60, 71, -60, -60, -56, -60, 72, 166, 310, 55, 184, 184, -60, -60, -60, 1, 184, -60, 60, 73, -60, 70, 17, -60, 96, -60, -60, -60 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int16 yypgoto[] = { -60, -60, -60, -60, -60, 122, -60, -60, -60, -60, -60, -3, -60, -60, -25, -60, 18, -8, 0, -58, -60, 69, -60, 61, -60, 76, -60, 54, -60, 57, -60, 59, -60, 68, -60, 125, -59, 174, 20, -60, -60 }; /* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If positive, shift that token. If negative, reduce the rule which number is the opposite. If zero, do what YYDEFACT says. If YYTABLE_NINF, syntax error. */ #define YYTABLE_NINF -122 static const yytype_int16 yytable[] = { 56, 120, 21, 61, 85, 21, 172, 63, 173, 22, 85, 23, 85, 24, 25, 26, 85, 124, 5, 85, 103, 104, 80, 81, 54, 106, 107, 21, 57, 138, 58, 126, 83, 84, 22, 135, 23, 86, 24, 25, 26, 85, 127, 27, 28, 29, 85, 88, 136, 30, 116, 31, 30, 32, 33, 34, 82, 129, 35, 36, 37, 62, 38, 90, 39, 40, 125, 123, 27, 28, 29, 132, 157, 114, 30, 118, 31, 158, 32, 33, 34, 85, 128, 35, 36, 55, 85, 21, 164, 39, 40, 85, 130, 131, 22, 120, 23, 146, 24, 25, 26, 85, 133, 149, 137, 150, -121, 164, 92, 93, 94, 180, 21, 134, 164, 152, 153, 178, 154, 22, 155, 23, 183, 24, 25, 26, 156, 85, 27, 28, 29, 168, 185, 171, 30, 184, 31, 174, 32, 33, 34, 167, 78, 35, 36, 166, 117, 38, 181, 39, 40, 169, 140, 27, 28, 29, 142, 176, 139, 30, 179, 31, 143, 32, 33, 34, 182, 144, 35, 36, 21, 141, 38, 170, 39, 40, 113, 22, 20, 23, 145, 24, 25, 26, 109, 110, 111, 0, 21, 96, 97, 98, 99, 100, 101, 22, 0, 23, 0, 24, 25, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 27, 28, 29, 6, 21, 0, 30, 159, 31, 0, 32, 33, 34, 0, 0, 35, 36, 175, 27, 28, 29, 39, 40, 0, 30, 0, 31, 0, 32, 33, 34, 0, 0, 35, 36, 119, 0, 0, 0, 39, 40, 0, 22, 0, 23, 0, 24, 25, 26, 0, 15, 30, 21, 0, 0, 0, 0, 0, 0, 22, 0, 23, 160, 0, 6, 7, 8, 9, 0, 10, 11, 12, 0, 13, 0, 14, 27, 28, 29, 0, 0, 0, 30, 0, 31, 0, 32, 33, 34, 0, 0, 35, 36, 27, 28, 29, 0, 39, 40, 30, 0, 31, 6, 21, 0, 34, 177, 0, 0, 0, 0, 15, 0, 0, 39, 40, 2, 3, 0, -3, -3, -3, -3, 16, -3, -3, -3, 0, -3, 0, -3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 30, 0, 7, 8, 9, 0, 10, 11, 12, 0, 13, 160, 14, 0, 0, 0, -3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -3, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16 }; static const yytype_int16 yycheck[] = { 8, 59, 4, 4, 31, 4, 62, 15, 64, 11, 31, 13, 31, 15, 16, 17, 31, 13, 62, 31, 18, 19, 30, 31, 1, 55, 56, 4, 4, 87, 62, 52, 40, 62, 11, 54, 13, 64, 15, 16, 17, 31, 63, 45, 46, 47, 31, 30, 63, 51, 62, 53, 51, 55, 56, 57, 38, 65, 60, 61, 62, 62, 64, 29, 66, 67, 62, 4, 45, 46, 47, 79, 62, 7, 51, 57, 53, 62, 55, 56, 57, 31, 64, 60, 61, 62, 31, 4, 147, 66, 67, 31, 62, 62, 11, 153, 13, 62, 15, 16, 17, 31, 52, 64, 86, 63, 31, 166, 26, 27, 28, 169, 4, 63, 173, 62, 64, 62, 62, 11, 62, 13, 62, 15, 16, 17, 62, 31, 45, 46, 47, 64, 62, 62, 51, 62, 53, 65, 55, 56, 57, 149, 20, 60, 61, 148, 63, 64, 173, 66, 67, 151, 91, 45, 46, 47, 102, 165, 89, 51, 168, 53, 105, 55, 56, 57, 174, 108, 60, 61, 4, 95, 64, 153, 66, 67, 51, 11, 4, 13, 112, 15, 16, 17, 57, 58, 59, -1, 4, 20, 21, 22, 23, 24, 25, 11, -1, 13, -1, 15, 16, 17, -1, -1, -1, -1, -1, -1, -1, -1, -1, 45, 46, 47, 3, 4, -1, 51, 7, 53, -1, 55, 56, 57, -1, -1, 60, 61, 62, 45, 46, 47, 66, 67, -1, 51, -1, 53, -1, 55, 56, 57, -1, -1, 60, 61, 4, -1, -1, -1, 66, 67, -1, 11, -1, 13, -1, 15, 16, 17, -1, 50, 51, 4, -1, -1, -1, -1, -1, -1, 11, -1, 13, 62, -1, 3, 4, 5, 6, -1, 8, 9, 10, -1, 12, -1, 14, 45, 46, 47, -1, -1, -1, 51, -1, 53, -1, 55, 56, 57, -1, -1, 60, 61, 45, 46, 47, -1, 66, 67, 51, -1, 53, 3, 4, -1, 57, 7, -1, -1, -1, -1, 50, -1, -1, 66, 67, 0, 1, -1, 3, 4, 5, 6, 62, 8, 9, 10, -1, 12, -1, 14, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 50, 51, -1, 4, 5, 6, -1, 8, 9, 10, -1, 12, 62, 14, -1, -1, -1, 50, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 62, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 62 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { 0, 69, 0, 1, 70, 62, 3, 4, 5, 6, 8, 9, 10, 12, 14, 50, 62, 71, 72, 73, 105, 4, 11, 13, 15, 16, 17, 45, 46, 47, 51, 53, 55, 56, 57, 60, 61, 62, 64, 66, 67, 84, 85, 87, 89, 91, 93, 95, 97, 99, 101, 102, 103, 104, 1, 62, 85, 4, 62, 75, 74, 4, 62, 85, 76, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 73, 83, 85, 85, 84, 85, 62, 31, 64, 86, 30, 88, 29, 90, 26, 27, 28, 92, 20, 21, 22, 23, 24, 25, 94, 18, 19, 96, 55, 56, 98, 57, 58, 59, 100, 103, 7, 78, 62, 63, 84, 4, 87, 106, 107, 4, 13, 62, 52, 63, 84, 85, 62, 62, 85, 52, 63, 54, 63, 84, 87, 89, 91, 93, 95, 97, 99, 101, 62, 79, 77, 64, 63, 108, 62, 64, 62, 62, 62, 62, 62, 7, 62, 80, 81, 82, 104, 105, 79, 85, 64, 86, 106, 62, 62, 64, 65, 62, 85, 7, 62, 85, 87, 82, 85, 62, 62, 62 }; #define yyerrok (yyerrstatus = 0) #define yyclearin (yychar = YYEMPTY) #define YYEMPTY (-2) #define YYEOF 0 #define YYACCEPT goto yyacceptlab #define YYABORT goto yyabortlab #define YYERROR goto yyerrorlab /* Like YYERROR except do call yyerror. This remains here temporarily to ease the transition to the new meaning of YYERROR, for GCC. Once GCC version 2 has supplanted version 1, this can go. */ #define YYFAIL goto yyerrlab #define YYRECOVERING() (!!yyerrstatus) #define YYBACKUP(Token, Value) \ do \ if (yychar == YYEMPTY && yylen == 1) \ { \ yychar = (Token); \ yylval = (Value); \ yytoken = YYTRANSLATE (yychar); \ YYPOPSTACK (1); \ goto yybackup; \ } \ else \ { \ yyerror (YY_("syntax error: cannot back up")); \ YYERROR; \ } \ while (YYID (0)) #define YYTERROR 1 #define YYERRCODE 256 /* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N]. If N is 0, then set CURRENT to the empty location which ends the previous symbol: RHS[0] (always defined). */ #define YYRHSLOC(Rhs, K) ((Rhs)[K]) #ifndef YYLLOC_DEFAULT # define YYLLOC_DEFAULT(Current, Rhs, N) \ do \ if (YYID (N)) \ { \ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ } \ else \ { \ (Current).first_line = (Current).last_line = \ YYRHSLOC (Rhs, 0).last_line; \ (Current).first_column = (Current).last_column = \ YYRHSLOC (Rhs, 0).last_column; \ } \ while (YYID (0)) #endif /* YY_LOCATION_PRINT -- Print the location on the stream. This macro was not mandated originally: define only if we know we won't break user code: when these are the locations we know. */ #ifndef YY_LOCATION_PRINT # if YYLTYPE_IS_TRIVIAL # define YY_LOCATION_PRINT(File, Loc) \ fprintf (File, "%d.%d-%d.%d", \ (Loc).first_line, (Loc).first_column, \ (Loc).last_line, (Loc).last_column) # else # define YY_LOCATION_PRINT(File, Loc) ((void) 0) # endif #endif /* YYLEX -- calling `yylex' with the right arguments. */ #ifdef YYLEX_PARAM # define YYLEX yylex (YYLEX_PARAM) #else # define YYLEX yylex () #endif /* Enable debugging if requested. */ #if YYDEBUG # ifndef YYFPRINTF # include /* INFRINGES ON USER NAME SPACE */ # define YYFPRINTF fprintf # endif # define YYDPRINTF(Args) \ do { \ if (yydebug) \ YYFPRINTF Args; \ } while (YYID (0)) # define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ do { \ if (yydebug) \ { \ YYFPRINTF (stderr, "%s ", Title); \ yy_symbol_print (stderr, \ Type, Value); \ YYFPRINTF (stderr, "\n"); \ } \ } while (YYID (0)) /*--------------------------------. | Print this symbol on YYOUTPUT. | `--------------------------------*/ /*ARGSUSED*/ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static void yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) #else static void yy_symbol_value_print (yyoutput, yytype, yyvaluep) FILE *yyoutput; int yytype; YYSTYPE const * const yyvaluep; #endif { if (!yyvaluep) return; # ifdef YYPRINT if (yytype < YYNTOKENS) YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); # else YYUSE (yyoutput); # endif switch (yytype) { default: break; } } /*--------------------------------. | Print this symbol on YYOUTPUT. | `--------------------------------*/ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static void yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) #else static void yy_symbol_print (yyoutput, yytype, yyvaluep) FILE *yyoutput; int yytype; YYSTYPE const * const yyvaluep; #endif { if (yytype < YYNTOKENS) YYFPRINTF (yyoutput, "token %s (", yytname[yytype]); else YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]); yy_symbol_value_print (yyoutput, yytype, yyvaluep); YYFPRINTF (yyoutput, ")"); } /*------------------------------------------------------------------. | yy_stack_print -- Print the state stack from its BOTTOM up to its | | TOP (included). | `------------------------------------------------------------------*/ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static void yy_stack_print (yytype_int16 *bottom, yytype_int16 *top) #else static void yy_stack_print (bottom, top) yytype_int16 *bottom; yytype_int16 *top; #endif { YYFPRINTF (stderr, "Stack now"); for (; bottom <= top; ++bottom) YYFPRINTF (stderr, " %d", *bottom); YYFPRINTF (stderr, "\n"); } # define YY_STACK_PRINT(Bottom, Top) \ do { \ if (yydebug) \ yy_stack_print ((Bottom), (Top)); \ } while (YYID (0)) /*------------------------------------------------. | Report that the YYRULE is going to be reduced. | `------------------------------------------------*/ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static void yy_reduce_print (YYSTYPE *yyvsp, int yyrule) #else static void yy_reduce_print (yyvsp, yyrule) YYSTYPE *yyvsp; int yyrule; #endif { int yynrhs = yyr2[yyrule]; int yyi; unsigned long int yylno = yyrline[yyrule]; YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", yyrule - 1, yylno); /* The symbols being reduced. */ for (yyi = 0; yyi < yynrhs; yyi++) { fprintf (stderr, " $%d = ", yyi + 1); yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi], &(yyvsp[(yyi + 1) - (yynrhs)]) ); fprintf (stderr, "\n"); } } # define YY_REDUCE_PRINT(Rule) \ do { \ if (yydebug) \ yy_reduce_print (yyvsp, Rule); \ } while (YYID (0)) /* Nonzero means print parse trace. It is left uninitialized so that multiple parsers can coexist. */ int yydebug; #else /* !YYDEBUG */ # define YYDPRINTF(Args) # define YY_SYMBOL_PRINT(Title, Type, Value, Location) # define YY_STACK_PRINT(Bottom, Top) # define YY_REDUCE_PRINT(Rule) #endif /* !YYDEBUG */ /* YYINITDEPTH -- initial size of the parser's stacks. */ #ifndef YYINITDEPTH # define YYINITDEPTH 200 #endif /* YYMAXDEPTH -- maximum size the stacks can grow to (effective only if the built-in stack extension method is used). Do not make this value too large; the results are undefined if YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH) evaluated with infinite-precision integer arithmetic. */ #ifndef YYMAXDEPTH # define YYMAXDEPTH 10000 #endif #if YYERROR_VERBOSE # ifndef yystrlen # if defined __GLIBC__ && defined _STRING_H # define yystrlen strlen # else /* Return the length of YYSTR. */ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static YYSIZE_T yystrlen (const char *yystr) #else static YYSIZE_T yystrlen (yystr) const char *yystr; #endif { YYSIZE_T yylen; for (yylen = 0; yystr[yylen]; yylen++) continue; return yylen; } # endif # endif # ifndef yystpcpy # if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE # define yystpcpy stpcpy # else /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in YYDEST. */ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static char * yystpcpy (char *yydest, const char *yysrc) #else static char * yystpcpy (yydest, yysrc) char *yydest; const char *yysrc; #endif { char *yyd = yydest; const char *yys = yysrc; while ((*yyd++ = *yys++) != '\0') continue; return yyd - 1; } # endif # endif # ifndef yytnamerr /* Copy to YYRES the contents of YYSTR after stripping away unnecessary quotes and backslashes, so that it's suitable for yyerror. The heuristic is that double-quoting is unnecessary unless the string contains an apostrophe, a comma, or backslash (other than backslash-backslash). YYSTR is taken from yytname. If YYRES is null, do not copy; instead, return the length of what the result would have been. */ static YYSIZE_T yytnamerr (char *yyres, const char *yystr) { if (*yystr == '"') { YYSIZE_T yyn = 0; char const *yyp = yystr; for (;;) switch (*++yyp) { case '\'': case ',': goto do_not_strip_quotes; case '\\': if (*++yyp != '\\') goto do_not_strip_quotes; /* Fall through. */ default: if (yyres) yyres[yyn] = *yyp; yyn++; break; case '"': if (yyres) yyres[yyn] = '\0'; return yyn; } do_not_strip_quotes: ; } if (! yyres) return yystrlen (yystr); return yystpcpy (yyres, yystr) - yyres; } # endif /* Copy into YYRESULT an error message about the unexpected token YYCHAR while in state YYSTATE. Return the number of bytes copied, including the terminating null byte. If YYRESULT is null, do not copy anything; just return the number of bytes that would be copied. As a special case, return 0 if an ordinary "syntax error" message will do. Return YYSIZE_MAXIMUM if overflow occurs during size calculation. */ static YYSIZE_T yysyntax_error (char *yyresult, int yystate, int yychar) { int yyn = yypact[yystate]; if (! (YYPACT_NINF < yyn && yyn <= YYLAST)) return 0; else { int yytype = YYTRANSLATE (yychar); YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]); YYSIZE_T yysize = yysize0; YYSIZE_T yysize1; int yysize_overflow = 0; enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; int yyx; # if 0 /* This is so xgettext sees the translatable formats that are constructed on the fly. */ YY_("syntax error, unexpected %s"); YY_("syntax error, unexpected %s, expecting %s"); YY_("syntax error, unexpected %s, expecting %s or %s"); YY_("syntax error, unexpected %s, expecting %s or %s or %s"); YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s"); # endif char *yyfmt; char const *yyf; static char const yyunexpected[] = "syntax error, unexpected %s"; static char const yyexpecting[] = ", expecting %s"; static char const yyor[] = " or %s"; char yyformat[sizeof yyunexpected + sizeof yyexpecting - 1 + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2) * (sizeof yyor - 1))]; char const *yyprefix = yyexpecting; /* Start YYX at -YYN if negative to avoid negative indexes in YYCHECK. */ int yyxbegin = yyn < 0 ? -yyn : 0; /* Stay within bounds of both yycheck and yytname. */ int yychecklim = YYLAST - yyn + 1; int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS; int yycount = 1; yyarg[0] = yytname[yytype]; yyfmt = yystpcpy (yyformat, yyunexpected); for (yyx = yyxbegin; yyx < yyxend; ++yyx) if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR) { if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM) { yycount = 1; yysize = yysize0; yyformat[sizeof yyunexpected - 1] = '\0'; break; } yyarg[yycount++] = yytname[yyx]; yysize1 = yysize + yytnamerr (0, yytname[yyx]); yysize_overflow |= (yysize1 < yysize); yysize = yysize1; yyfmt = yystpcpy (yyfmt, yyprefix); yyprefix = yyor; } yyf = YY_(yyformat); yysize1 = yysize + yystrlen (yyf); yysize_overflow |= (yysize1 < yysize); yysize = yysize1; if (yysize_overflow) return YYSIZE_MAXIMUM; if (yyresult) { /* Avoid sprintf, as that infringes on the user's name space. Don't have undefined behavior even if the translation produced a string with the wrong number of "%s"s. */ char *yyp = yyresult; int yyi = 0; while ((*yyp = *yyf) != '\0') { if (*yyp == '%' && yyf[1] == 's' && yyi < yycount) { yyp += yytnamerr (yyp, yyarg[yyi++]); yyf += 2; } else { yyp++; yyf++; } } } return yysize; } } #endif /* YYERROR_VERBOSE */ /*-----------------------------------------------. | Release the memory associated to this symbol. | `-----------------------------------------------*/ /*ARGSUSED*/ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) static void yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) #else static void yydestruct (yymsg, yytype, yyvaluep) const char *yymsg; int yytype; YYSTYPE *yyvaluep; #endif { YYUSE (yyvaluep); if (!yymsg) yymsg = "Deleting"; YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); switch (yytype) { default: break; } } /* Prevent warnings from -Wmissing-prototypes. */ #ifdef YYPARSE_PARAM #if defined __STDC__ || defined __cplusplus int yyparse (void *YYPARSE_PARAM); #else int yyparse (); #endif #else /* ! YYPARSE_PARAM */ #if defined __STDC__ || defined __cplusplus int yyparse (void); #else int yyparse (); #endif #endif /* ! YYPARSE_PARAM */ /* The look-ahead symbol. */ int yychar; /* The semantic value of the look-ahead symbol. */ YYSTYPE yylval; /* Number of syntax errors so far. */ int yynerrs; /*----------. | yyparse. | `----------*/ #ifdef YYPARSE_PARAM #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) int yyparse (void *YYPARSE_PARAM) #else int yyparse (YYPARSE_PARAM) void *YYPARSE_PARAM; #endif #else /* ! YYPARSE_PARAM */ #if (defined __STDC__ || defined __C99__FUNC__ \ || defined __cplusplus || defined _MSC_VER) int yyparse (void) #else int yyparse () #endif #endif { int yystate; int yyn; int yyresult; /* Number of tokens to shift before error messages enabled. */ int yyerrstatus; /* Look-ahead token as an internal (translated) token number. */ int yytoken = 0; #if YYERROR_VERBOSE /* Buffer for error messages, and its allocated size. */ char yymsgbuf[128]; char *yymsg = yymsgbuf; YYSIZE_T yymsg_alloc = sizeof yymsgbuf; #endif /* Three stacks and their tools: `yyss': related to states, `yyvs': related to semantic values, `yyls': related to locations. Refer to the stacks thru separate pointers, to allow yyoverflow to reallocate them elsewhere. */ /* The state stack. */ yytype_int16 yyssa[YYINITDEPTH]; yytype_int16 *yyss = yyssa; yytype_int16 *yyssp; /* The semantic value stack. */ YYSTYPE yyvsa[YYINITDEPTH]; YYSTYPE *yyvs = yyvsa; YYSTYPE *yyvsp; #define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N)) YYSIZE_T yystacksize = YYINITDEPTH; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; /* The number of symbols on the RHS of the reduced rule. Keep to zero when no symbol should be popped. */ int yylen = 0; YYDPRINTF ((stderr, "Starting parse\n")); yystate = 0; yyerrstatus = 0; yynerrs = 0; yychar = YYEMPTY; /* Cause a token to be read. */ /* Initialize stack pointers. Waste one element of value and location stack so that they stay on the same level as the state stack. The wasted elements are never initialized. */ yyssp = yyss; yyvsp = yyvs; goto yysetstate; /*------------------------------------------------------------. | yynewstate -- Push a new state, which is found in yystate. | `------------------------------------------------------------*/ yynewstate: /* In all cases, when you get here, the value and location stacks have just been pushed. So pushing a state here evens the stacks. */ yyssp++; yysetstate: *yyssp = yystate; if (yyss + yystacksize - 1 <= yyssp) { /* Get the current used size of the three stacks, in elements. */ YYSIZE_T yysize = yyssp - yyss + 1; #ifdef yyoverflow { /* Give user a chance to reallocate the stack. Use copies of these so that the &'s don't force the real ones into memory. */ YYSTYPE *yyvs1 = yyvs; yytype_int16 *yyss1 = yyss; /* Each stack pointer address is followed by the size of the data in use in that stack, in bytes. This used to be a conditional around just the two extra args, but that might be undefined if yyoverflow is a macro. */ yyoverflow (YY_("memory exhausted"), &yyss1, yysize * sizeof (*yyssp), &yyvs1, yysize * sizeof (*yyvsp), &yystacksize); yyss = yyss1; yyvs = yyvs1; } #else /* no yyoverflow */ # ifndef YYSTACK_RELOCATE goto yyexhaustedlab; # else /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) goto yyexhaustedlab; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) yystacksize = YYMAXDEPTH; { yytype_int16 *yyss1 = yyss; union yyalloc *yyptr = (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); if (! yyptr) goto yyexhaustedlab; YYSTACK_RELOCATE (yyss); YYSTACK_RELOCATE (yyvs); # undef YYSTACK_RELOCATE if (yyss1 != yyssa) YYSTACK_FREE (yyss1); } # endif #endif /* no yyoverflow */ yyssp = yyss + yysize - 1; yyvsp = yyvs + yysize - 1; YYDPRINTF ((stderr, "Stack size increased to %lu\n", (unsigned long int) yystacksize)); if (yyss + yystacksize - 1 <= yyssp) YYABORT; } YYDPRINTF ((stderr, "Entering state %d\n", yystate)); goto yybackup; /*-----------. | yybackup. | `-----------*/ yybackup: /* Do appropriate processing given the current state. Read a look-ahead token if we need one and don't already have one. */ /* First try to decide what to do without reference to look-ahead token. */ yyn = yypact[yystate]; if (yyn == YYPACT_NINF) goto yydefault; /* Not known => get a look-ahead token if don't already have one. */ /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol. */ if (yychar == YYEMPTY) { YYDPRINTF ((stderr, "Reading a token: ")); yychar = YYLEX; } if (yychar <= YYEOF) { yychar = yytoken = YYEOF; YYDPRINTF ((stderr, "Now at end of input.\n")); } else { yytoken = YYTRANSLATE (yychar); YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc); } /* If the proper action on seeing token YYTOKEN is to reduce or to detect an error, take that action. */ yyn += yytoken; if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken) goto yydefault; yyn = yytable[yyn]; if (yyn <= 0) { if (yyn == 0 || yyn == YYTABLE_NINF) goto yyerrlab; yyn = -yyn; goto yyreduce; } if (yyn == YYFINAL) YYACCEPT; /* Count tokens shifted since error; after three, turn off error status. */ if (yyerrstatus) yyerrstatus--; /* Shift the look-ahead token. */ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc); /* Discard the shifted token unless it is eof. */ if (yychar != YYEOF) yychar = YYEMPTY; yystate = yyn; *++yyvsp = yylval; goto yynewstate; /*-----------------------------------------------------------. | yydefault -- do the default action for the current state. | `-----------------------------------------------------------*/ yydefault: yyn = yydefact[yystate]; if (yyn == 0) goto yyerrlab; goto yyreduce; /*-----------------------------. | yyreduce -- Do a reduction. | `-----------------------------*/ yyreduce: /* yyn is the number of a rule to reduce with. */ yylen = yyr2[yyn]; /* If YYLEN is nonzero, implement the default value of the action: `$$ = $1'. Otherwise, the following line sets YYVAL to garbage. This behavior is undocumented and Bison users should not rely upon it. Assigning to YYVAL unconditionally makes the parser a bit smaller, and it avoids a GCC warning that YYVAL may be used uninitialized. */ yyval = yyvsp[1-yylen]; YY_REDUCE_PRINT (yyn); switch (yyn) { case 3: #line 310 "parse.y" { state.lst.line.was_org = state.org; state.lst.line.linetype = none; state.next_state = state_nochange; } break; case 5: #line 316 "parse.y" { next_line(0); } break; case 6: #line 323 "parse.y" { struct pnode *parms; int exp_result; exp_result = do_insn("set", mk_list((yyvsp[(3) - (4)].p), NULL)); parms = mk_list(mk_2op(return_op((yyvsp[(2) - (4)].i)), mk_symbol((yyvsp[(1) - (4)].s)), mk_constant(exp_result)), NULL); next_line(set_label((yyvsp[(1) - (4)].s), parms)); } break; case 7: #line 335 "parse.y" { struct pnode *parms; /* implements i = 6 + 1 */ parms = mk_list((yyvsp[(3) - (4)].p), NULL); next_line(set_label((yyvsp[(1) - (4)].s), parms)); } break; case 8: #line 344 "parse.y" { struct pnode *parms; /* implements i-- */ parms = mk_list(mk_1op(DECREMENT, mk_symbol((yyvsp[(1) - (3)].s))), NULL); next_line(set_label((yyvsp[(1) - (3)].s), parms)); } break; case 9: #line 353 "parse.y" { struct pnode *parms; /* implements i++ */ parms = mk_list(mk_1op(INCREMENT, mk_symbol((yyvsp[(1) - (3)].s))), NULL); next_line(set_label((yyvsp[(1) - (3)].s), parms)); } break; case 10: #line 362 "parse.y" { if (asm_enabled() && (state.lst.line.linetype == none)) { if ((state.mode == relocatable) && (SECTION_FLAGS & (STYP_BSS | STYP_DATA))) /* alias to next definition */ state.lst.line.linetype = res; else state.lst.line.linetype = insn; } if (asm_enabled()) { if (state.mac_head) { /* This is a macro definition. Set it up */ struct symbol *mac; struct macro_head *h = NULL; mac = get_symbol(state.stMacros, (yyvsp[(1) - (2)].s)); if (mac) h = get_symbol_annotation(mac); /* It's not an error if macro was defined on pass 1 and we're in pass 2. */ if (h && !((h->pass == 1) && (state.pass == 2))) { gperror(GPE_DUPLICATE_MACRO, NULL); } else { if (!mac) mac = add_symbol(state.stMacros, (yyvsp[(1) - (2)].s)); annotate_symbol(mac, state.mac_head); h = state.mac_head; h->line_number = state.src->line_number; h->file_symbol = state.src->file_symbol; } h->pass = state.pass; /* The macro is defined so allow calls. */ if (state.pass == 2) h->defined = 1; state.mac_head = NULL; } else if (!state.mac_prev) { /* Outside a macro, just define the label. */ switch (state.lst.line.linetype) { case sec: strncpy(state.obj.new_sec_name, (yyvsp[(1) - (2)].s), 78); break; case set: set_global((yyvsp[(1) - (2)].s), (yyvsp[(2) - (2)].i), TEMPORARY, gvt_constant); break; case org: case equ: set_global((yyvsp[(1) - (2)].s), (yyvsp[(2) - (2)].i), PERMANENT, gvt_constant); break; case insn: set_global((yyvsp[(1) - (2)].s), ((yyvsp[(2) - (2)].i) << _16bit_core) - _16packed_offset_labels, PERMANENT, gvt_address); break; case res: set_global((yyvsp[(1) - (2)].s), (yyvsp[(2) - (2)].i), PERMANENT, gvt_static); break; case dir: gperror(GPE_ILLEGAL_LABEL, NULL); break; default: break; } } } next_line((yyvsp[(2) - (2)].i)); } break; case 11: #line 433 "parse.y" { if (state.mac_head) { /* This is a macro definition, but the label was missing */ state.mac_head = NULL; gperror(GPE_NO_MACRO_NAME, NULL); } else { next_line(0); } } break; case 14: #line 448 "parse.y" { if (!state.mac_prev) { (yyval.i) = state.org; } else { macro_append(); } } break; case 15: #line 456 "parse.y" { force_ident = 1; } break; case 16: #line 458 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (4)].s), mk_list(mk_symbol((yyvsp[(3) - (4)].s)), NULL)); force_ident = 0; } break; case 17: #line 464 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (2)].s), NULL); } break; case 18: #line 468 "parse.y" { force_decimal = 1; } break; case 19: #line 470 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (4)].s), (yyvsp[(3) - (4)].p)); force_decimal = 0; } break; case 20: #line 475 "parse.y" { force_decimal = 1; } break; case 21: #line 477 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (4)].s), (yyvsp[(3) - (4)].p)); force_decimal = 0; } break; case 22: #line 483 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (4)].s), mk_list(mk_string((yyvsp[(2) - (4)].s)), mk_list(mk_string((yyvsp[(3) - (4)].s)), NULL))); } break; case 23: #line 489 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (3)].s), mk_list(mk_string((yyvsp[(2) - (3)].s)), NULL)); } break; case 24: #line 494 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (2)].s), NULL); } break; case 25: #line 499 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (2)].s), NULL); } break; case 26: #line 504 "parse.y" { (yyval.i) = do_or_append_insn((yyvsp[(1) - (3)].s), (yyvsp[(2) - (3)].p)); } break; case 27: #line 509 "parse.y" { int number; int i; if (!state.mac_prev) { number = eval_fill_number((yyvsp[(5) - (6)].p)); for (i = 0; i < number; i++) { (yyval.i) = do_insn((yyvsp[(2) - (6)].s), NULL); } } else { macro_append(); } } break; case 28: #line 525 "parse.y" { int number; int i; if (!state.mac_prev) { number = eval_fill_number((yyvsp[(6) - (7)].p)); for (i = 0; i < number; i++) { (yyval.i) = do_insn((yyvsp[(2) - (7)].s), (yyvsp[(3) - (7)].p)); } } else { macro_append(); } } break; case 29: #line 541 "parse.y" { if (!state.mac_prev) { begin_cblock((yyvsp[(2) - (3)].p)); } else { macro_append(); } next_line(0); } break; case 30: #line 551 "parse.y" { if (state.mac_prev) { macro_append(); } (yyval.i) = 0; } break; case 31: #line 559 "parse.y" { if (!state.mac_prev) { continue_cblock(); } else { macro_append(); } next_line(0); } break; case 32: #line 569 "parse.y" { if (state.mac_prev) { macro_append(); } (yyval.i) = 0; } break; case 33: #line 577 "parse.y" { (yyval.i) = 0; } break; case 35: #line 585 "parse.y" { next_line(0); } break; case 37: #line 594 "parse.y" { if (state.mac_prev) { macro_append(); } } break; case 38: #line 601 "parse.y" { if (!state.mac_prev) { cblock_expr(mk_symbol((yyvsp[(1) - (2)].s))); } else { macro_append(); } } break; case 39: #line 610 "parse.y" { if (!state.mac_prev) { cblock_expr_incr(mk_symbol((yyvsp[(1) - (3)].s)), (yyvsp[(2) - (3)].p)); } else { macro_append(); } } break; case 42: #line 627 "parse.y" { if (!state.mac_prev) { cblock_expr((yyvsp[(1) - (1)].p)); } } break; case 43: #line 634 "parse.y" { if (!state.mac_prev) { cblock_expr_incr((yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } } break; case 54: #line 647 "parse.y" { (yyval.p) = mk_list((yyvsp[(1) - (1)].p), NULL); } break; case 55: #line 652 "parse.y" { (yyval.p) = mk_list((yyvsp[(1) - (2)].p), mk_list(mk_symbol(""), NULL)); } break; case 56: #line 657 "parse.y" { (yyval.p) = mk_list((yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 57: #line 662 "parse.y" { (yyval.p) = mk_list(mk_symbol(""), (yyvsp[(2) - (2)].p)); } break; case 58: #line 667 "parse.y" { (yyval.p) = mk_list(mk_symbol(""), mk_list(mk_symbol(""), NULL)); } break; case 60: #line 676 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 63: #line 689 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 66: #line 702 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 69: #line 715 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 74: #line 728 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 82: #line 741 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 86: #line 754 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 90: #line 767 "parse.y" { coerce_str1((yyvsp[(1) - (3)].p)); coerce_str1((yyvsp[(3) - (3)].p)); (yyval.p) = mk_2op((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 95: #line 780 "parse.y" { coerce_str1((yyvsp[(2) - (2)].p)); (yyval.p) = mk_1op((yyvsp[(1) - (2)].i), (yyvsp[(2) - (2)].p)); } break; case 103: #line 790 "parse.y" { (yyval.p) = (yyvsp[(1) - (1)].p); } break; case 104: #line 795 "parse.y" { (yyval.p) = mk_constant((yyvsp[(1) - (1)].i)); } break; case 105: #line 800 "parse.y" { (yyval.p) = mk_symbol("$"); } break; case 106: #line 805 "parse.y" { (yyval.p) = mk_string((yyvsp[(1) - (1)].s)); } break; case 107: #line 810 "parse.y" { (yyval.p) = (yyvsp[(2) - (3)].p); } break; case 108: #line 815 "parse.y" { (yyval.p) = mk_offset((yyvsp[(2) - (3)].p)); } break; case 109: #line 820 "parse.y" { (yyval.p) = mk_constant(TBL_NO_CHANGE); } break; case 110: #line 825 "parse.y" { (yyval.p) = mk_constant((yyvsp[(1) - (1)].i)); } break; case 111: #line 830 "parse.y" { (yyval.p) = mk_constant((yyvsp[(1) - (1)].i)); } break; case 112: #line 835 "parse.y" { (yyval.p) = mk_constant((yyvsp[(1) - (1)].i)); } break; case 113: #line 842 "parse.y" { (yyval.p) = mk_symbol((yyvsp[(1) - (1)].s)); } break; case 114: #line 847 "parse.y" { (yyval.p) = mk_2op(CONCAT, mk_symbol((yyvsp[(1) - (3)].s)), mk_1op(VAR, (yyvsp[(2) - (3)].p))); } break; case 115: #line 852 "parse.y" { (yyval.p) = mk_2op(CONCAT, mk_symbol((yyvsp[(1) - (3)].s)), mk_2op(CONCAT, mk_1op(VAR, (yyvsp[(2) - (3)].p)), mk_symbol((yyvsp[(3) - (3)].s)))); } break; case 116: #line 860 "parse.y" { (yyval.s) = (yyvsp[(1) - (1)].s); /* * statements return their org - but, with 16bit cores, org is a word * address. for us to know whether a label points at a non word aligned * address, we must get status from the directive.c module through a * back channel. however, we must make sure to store this status before * any statement on the current line is processed, so we must save it here * before the statement rules run. */ _16packed_offset_labels = _16packed_byte_acc; } break; case 117: #line 875 "parse.y" { if (asm_enabled() && !state.mac_prev) { (yyval.s) = evaluate_concatenation(mk_2op(CONCAT, mk_symbol((yyvsp[(1) - (3)].s)), mk_1op(VAR, (yyvsp[(2) - (3)].p)))); _16packed_offset_labels = _16packed_byte_acc; } } break; case 118: #line 884 "parse.y" { if (asm_enabled() && !state.mac_prev) { (yyval.s) = evaluate_concatenation(mk_2op(CONCAT, mk_symbol((yyvsp[(1) - (3)].s)), mk_2op(CONCAT, mk_1op(VAR, (yyvsp[(2) - (3)].p)), mk_symbol((yyvsp[(3) - (3)].s))))); _16packed_offset_labels = _16packed_byte_acc; } } break; case 119: #line 895 "parse.y" { (yyval.p) = mk_list((yyvsp[(1) - (1)].p), NULL); } break; case 120: #line 900 "parse.y" { (yyval.p) = mk_list((yyvsp[(1) - (3)].p), (yyvsp[(3) - (3)].p)); } break; case 121: #line 907 "parse.y" { if ((strcasecmp((yyvsp[(1) - (1)].s), "p") == 0) || (strcasecmp((yyvsp[(1) - (1)].s), "pe") == 0)) { force_ident = 1; } } break; case 122: #line 913 "parse.y" { (yyval.p) = mk_2op((yyvsp[(3) - (4)].i), mk_symbol((yyvsp[(1) - (4)].s)), (yyvsp[(4) - (4)].p)); force_ident = 0; } break; case 123: #line 919 "parse.y" { (yyval.p) = (yyvsp[(1) - (1)].p); } break; /* Line 1267 of yacc.c. */ #line 2514 "parse.c" default: break; } YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); YYPOPSTACK (yylen); yylen = 0; YY_STACK_PRINT (yyss, yyssp); *++yyvsp = yyval; /* Now `shift' the result of the reduction. Determine what state that goes to, based on the state we popped back to and the rule number reduced by. */ yyn = yyr1[yyn]; yystate = yypgoto[yyn - YYNTOKENS] + *yyssp; if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp) yystate = yytable[yystate]; else yystate = yydefgoto[yyn - YYNTOKENS]; goto yynewstate; /*------------------------------------. | yyerrlab -- here on detecting error | `------------------------------------*/ yyerrlab: /* If not already recovering from an error, report this error. */ if (!yyerrstatus) { ++yynerrs; #if ! YYERROR_VERBOSE yyerror (YY_("syntax error")); #else { YYSIZE_T yysize = yysyntax_error (0, yystate, yychar); if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM) { YYSIZE_T yyalloc = 2 * yysize; if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM)) yyalloc = YYSTACK_ALLOC_MAXIMUM; if (yymsg != yymsgbuf) YYSTACK_FREE (yymsg); yymsg = (char *) YYSTACK_ALLOC (yyalloc); if (yymsg) yymsg_alloc = yyalloc; else { yymsg = yymsgbuf; yymsg_alloc = sizeof yymsgbuf; } } if (0 < yysize && yysize <= yymsg_alloc) { (void) yysyntax_error (yymsg, yystate, yychar); yyerror (yymsg); } else { yyerror (YY_("syntax error")); if (yysize != 0) goto yyexhaustedlab; } } #endif } if (yyerrstatus == 3) { /* If just tried and failed to reuse look-ahead token after an error, discard it. */ if (yychar <= YYEOF) { /* Return failure if at end of input. */ if (yychar == YYEOF) YYABORT; } else { yydestruct ("Error: discarding", yytoken, &yylval); yychar = YYEMPTY; } } /* Else will try to reuse look-ahead token after shifting the error token. */ goto yyerrlab1; /*---------------------------------------------------. | yyerrorlab -- error raised explicitly by YYERROR. | `---------------------------------------------------*/ yyerrorlab: /* Pacify compilers like GCC when the user code never invokes YYERROR and the label yyerrorlab therefore never appears in user code. */ if (/*CONSTCOND*/ 0) goto yyerrorlab; /* Do not reclaim the symbols of the rule which action triggered this YYERROR. */ YYPOPSTACK (yylen); yylen = 0; YY_STACK_PRINT (yyss, yyssp); yystate = *yyssp; goto yyerrlab1; /*-------------------------------------------------------------. | yyerrlab1 -- common code for both syntax error and YYERROR. | `-------------------------------------------------------------*/ yyerrlab1: yyerrstatus = 3; /* Each real token shifted decrements this. */ for (;;) { yyn = yypact[yystate]; if (yyn != YYPACT_NINF) { yyn += YYTERROR; if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) { yyn = yytable[yyn]; if (0 < yyn) break; } } /* Pop the current state because it cannot handle the error token. */ if (yyssp == yyss) YYABORT; yydestruct ("Error: popping", yystos[yystate], yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); } if (yyn == YYFINAL) YYACCEPT; *++yyvsp = yylval; /* Shift the error token. */ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp); yystate = yyn; goto yynewstate; /*-------------------------------------. | yyacceptlab -- YYACCEPT comes here. | `-------------------------------------*/ yyacceptlab: yyresult = 0; goto yyreturn; /*-----------------------------------. | yyabortlab -- YYABORT comes here. | `-----------------------------------*/ yyabortlab: yyresult = 1; goto yyreturn; #ifndef yyoverflow /*-------------------------------------------------. | yyexhaustedlab -- memory exhaustion comes here. | `-------------------------------------------------*/ yyexhaustedlab: yyerror (YY_("memory exhausted")); yyresult = 2; /* Fall through. */ #endif yyreturn: if (yychar != YYEOF && yychar != YYEMPTY) yydestruct ("Cleanup: discarding lookahead", yytoken, &yylval); /* Do not reclaim the symbols of the rule which action triggered this YYABORT or YYACCEPT. */ YYPOPSTACK (yylen); YY_STACK_PRINT (yyss, yyssp); while (yyssp != yyss) { yydestruct ("Cleanup: popping", yystos[*yyssp], yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow if (yyss != yyssa) YYSTACK_FREE (yyss); #endif #if YYERROR_VERBOSE if (yymsg != yymsgbuf) YYSTACK_FREE (yymsg); #endif /* Make sure YYID is used. */ return YYID (yyresult); } #line 924 "parse.y" int return_op(int operation) { /* returns an operator for the replacement of i+=1 with i=i+1*/ switch(operation) { case ASSIGN_PLUS: return '+'; case ASSIGN_MINUS: return '-'; case ASSIGN_MULTIPLY: return '*'; case ASSIGN_DIVIDE: return '/'; case ASSIGN_MODULUS: return '%'; case ASSIGN_LSH: return LSH; case ASSIGN_RSH: return RSH; case ASSIGN_AND: return '&'; case ASSIGN_OR: return '|'; case ASSIGN_XOR: return '^'; default: assert(0); /* Unhandled operator */ } return 0; } gputils-0.13.7/gpasm/macro.h0000644000175000017500000000200011156313231012557 00000000000000/* Implements macros Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __MACRO_H__ #define __MACRO_H__ void setup_macro(struct macro_head *h, int arity, struct pnode *parms); char *make_macro_buffer(struct macro_head *h); struct symbol_table * push_macro_symbol_table(struct symbol_table *table); #endif gputils-0.13.7/gpasm/main.c0000644000175000017500000000164011156313231012406 00000000000000/* Main function for gpasm Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgpasm.h" int main(int argc, char *argv[]) { init(); process_args(argc, argv); return assemble(); } gputils-0.13.7/gpasm/evaluate.h0000644000175000017500000000250111156313231013272 00000000000000/* evaluates variables Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __EVALUATE_H__ #define __EVALUATE_H__ int enforce_arity(int arity, int must_be); int enforce_simple(struct pnode *p); int list_length(struct pnode *L); int can_evaluate_concatenation(struct pnode *p); char *evaluate_concatenation(struct pnode *p); char *maybe_evaluate_concat(struct pnode *p); int can_evaluate(struct pnode *p); gpasmVal evaluate(struct pnode *p); gpasmVal maybe_evaluate(struct pnode *p); int count_reloc(struct pnode *p); gpasmVal reloc_evaluate(struct pnode *p, unsigned short type); int eval_fill_number(struct pnode *p); #endif gputils-0.13.7/gpasm/gpasm.h0000644000175000017500000002645711156521302012613 00000000000000/* Common definitions for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPASM_H__ #define __GPASM_H__ #define GPASM_VERSION_STRING ("gpasm-" VERSION " beta") /* This symbol will get placed into the symbol table for the 16bit cores * and thus allow compile-time selection of the proper macro set */ #define __16bit_core_ "__16bit_core_" #define STRCMP(s1, s2) (state.case_insensitive ? \ strcasecmp((s1), (s2)) : \ strcmp((s1), (s2))) #define MAX_PATHS 100 typedef int gpasmVal; /* The type that internal arithmetic uses */ enum gpasmValTypes { gvt_constant, gvt_cblock, gvt_org, gvt_address, gvt_extern, gvt_global, gvt_static, gvt_debug, gvt_absolute }; enum state_types { state_nochange, state_exitmacro, state_include, state_macro, state_section, state_substitution, state_while }; enum outfile { normal, suppress, named }; enum file_types { ft_src, ft_other }; enum gpasm_modes { absolute, relocatable }; struct range_pair { long start, end; struct range_pair *next; }; extern struct gpasm_state { enum gpasm_modes mode; gp_boolean extended_pic16e; int radix; enum formats hex_format; gp_boolean case_insensitive; gp_boolean quiet; gp_boolean use_absolute_path; int error_level; /* 0, 1, 2 */ gp_boolean debug_info; /* use debug directives for coff outputs */ int path_num; /* number of paths in the list */ char *paths[MAX_PATHS]; /* the list of include paths */ struct { /* Command line override flags */ gp_boolean radix; /* value is specified by the command line */ gp_boolean hex_format; gp_boolean error_level; gp_boolean macro_expand; gp_boolean processor; gp_boolean lst_force; } cmd_line; int pass; /* 1 or 2 */ unsigned int org; /* Current code-generation point */ gp_boolean dos_newlines; /* Use DOS newlines in hex file */ gp_boolean memory_dump; /* Dump instruction memory to standard output */ gp_boolean found_config; /* config directive in source code */ gp_boolean found_devid; /* config directive in source code */ gp_boolean found_idlocs; /* idlocs directive in source code */ unsigned int maxram; /* Highest legal memory location */ long maxrom; /* Highest legal program memory location */ struct range_pair *badrom; enum outfile codfile, /* Symbol output file control */ depfile, /* Dependency output file control */ hexfile, /* Hex output file control */ lstfile, /* List output file control */ objfile; /* Relocatable object file control */ struct { /* Totals for errors, warnings, messages */ int errors; int warnings; int messages; int warnings_suppressed; int messages_suppressed; } num; pic_processor_t processor; struct px *processor_info; /* Processor identifiers (e.g. name) */ int processor_chosen; /* Nonzero after processor-specific init */ struct { /* Processor data */ enum proc_class class; /* Processor class */ int core_size; /* Processor core size */ int config_address; /* configuration address */ int id_location; /* location for idlocs for 12 and 14 bit proc */ int bsr_boundary; /* 18xx bsr boundary location */ } device; unsigned int c_memory_base; /* Base address of configuration memory */ char badram[MAX_RAM]; /* nonzero indicates illegal memory */ struct symbol_table *stBuiltin, /* Built-ins: instructions, pseudo-ops */ *stDirective, /* bottom half of Builtin with directives */ *stGlobal, /* Global symbols */ *stTop, /* Top of locals stack (stGlobal is base) */ *stDefines, /* Preprocessor #defines */ *stTopDefines, /* Macro #defines (stDefines is base) */ *stMacros; /* Macros */ MemBlock *i_memory; /* Instruction memory linked list */ MemBlock *c_memory; /* Configuration memory linked list (shadow) */ char *srcfilename, /* Source (.asm) file name */ basefilename[BUFSIZ], /* basename for generating hex,list,symbol filenames */ codfilename[BUFSIZ], /* Symbol (.cod) file name */ depfilename[BUFSIZ], /* Dependency (.d) file name */ hexfilename[BUFSIZ], /* Hex (.hex) file name */ lstfilename[BUFSIZ], /* List (.lst) file name */ objfilename[BUFSIZ]; /* Object (.o) file name */ struct { /* Symbol file state: */ FILE *f; /* Symbol file output */ gp_boolean enabled; /* true if symbol file is enabled */ int emitting; /* flag indicating when an opcode is emitted */ } cod; struct { /* Dep file state: */ FILE *f; /* Dep file output */ gp_boolean enabled; /* true if dep file is enabled */ } dep; struct { /* List file state: */ FILE *f; /* List file output */ unsigned int lineofpage, /* What line are we at within the page */ page, /* What page are we at */ linesperpage, /* Lines per page */ line_number, /* What line are we at within the file */ memorymap, /* Memory Map dump enabled */ symboltable; /* Symbol table dump enabled */ struct { unsigned int was_org; /* value of state.org at start of line */ /* What kind of line was it? */ enum { none, /* Nothing - blank line */ org, /* ORG pseudo-op */ dir, /* Directive, non-code generating */ idlocs, /* ID locations for 12 and 14 bit cores */ insn, /* Some other instruction or pseudo */ equ, /* An equate */ res, /* reserve memory */ sec, /* new coff section */ set, /* A SET or '=' */ config } /* A __config line */ linetype; } line; char startdate[80]; /* When assembly started */ gp_boolean enabled; /* listing is enabled */ gp_boolean expand; /* macro listings are expanded */ gp_boolean force; /* ignoring nolist directives */ int config_address; /* list config address for 16 bit devices */ char title_name[80]; /* given in TITLE directive */ char subtitle_name[80]; /* given in SUBTITLE directive */ int tabstop; /* tab-stop distance */ } lst; struct { /* Object file state: */ gp_object_type *object; /* Object file */ gp_section_type *section; /* Current section */ int section_num; /* Current section number */ gp_boolean enabled; /* true if object file is enabled */ char new_sec_name[80]; /* new section name */ int new_sec_addr; /* new section name */ int new_sec_flags; /* new section name */ int symbol_num; /* Current symbol number */ int flags; /* Current section flags */ gp_symbol_type *debug_file; /* Debug information for high level langs */ unsigned int debug_line; int newcoff; } obj; struct source_context *src; /* Top of the stack of source files */ struct file_context *files; /* Top of the stack of all files */ struct amode *astack; /* Stack of amodes (macros, etc) */ gpasmVal cblock; /* cblock constant */ int cblock_defined; struct macro_head *mac_head; /* Starting a macro... */ struct macro_body **mac_prev; /* Stitching ptr */ struct macro_body *mac_body; /* While we're building a macro */ struct macro_head *while_head;/* WHILEs work a lot like macros... */ enum state_types next_state; union { char *file; struct macro_head *macro; } next_buffer; } state; enum globalLife { TEMPORARY, PERMANENT }; struct variable { int value; int coff_num; int coff_section_num; enum gpasmValTypes type; enum gpasmValTypes previous_type; /* can change from static to global */ enum globalLife lifetime; }; /************************************************************************/ /* Parse node: created by the parser, interpreted by the 'backend' */ struct pnode { enum pnode_tag { constant, offset, symbol, string, list, binop, unop } tag; union { int constant; struct pnode *offset; char *symbol; struct { struct pnode *head, *tail; } list; struct { int op; struct pnode *p0, *p1; } binop; struct { int op; struct pnode *p0; } unop; char *string; } value; }; /************************************************************************/ /* file_context: a structure to keep track of all files that have been opened. Used to create the list of project files that can be found in the .cod file. */ struct file_context { char *name; /* file name */ unsigned int id; /* Unique identifier */ enum file_types ft; /* allowed file types */ struct file_context *prev; /* Previous in list pointer */ struct file_context *next; /* Next in list pointer */ }; enum src_types { src_unknown, src_file, src_macro, src_substitution, src_while }; struct source_context { char *name; enum src_types type; FILE *f; struct macro_head *h; union { FILE *f; struct macro_body *m; } lst; struct yy_buffer_state *yybuf; unsigned int line_number; unsigned int loop_number; /* Loop number for while loops */ gp_symbol_type *file_symbol; struct file_context *fc; /* Position in the file context stack */ struct amode *astack; /* Stack of amodes when a macro was called */ struct source_context *prev; }; void yyerror(char *s); int stringtolong(char *string, int radix); int gpasm_magic(char *); char *convert_escape_chars(char *ps, int *value); char *convert_escaped_char(char *str, char c); void coerce_str1(struct pnode *exp); gpasmVal do_or_append_insn(char *op, struct pnode *parms); void set_global(char *name, gpasmVal value, enum globalLife lifetime, enum gpasmValTypes type); void purge_temp_symbols(struct symbol_table *table); void select_errorlevel(int level); void select_expand(char *expand); void select_hexformat(char *format_name); void select_radix(char *name); struct file_context *add_file(unsigned int type, char *name); void free_files(void); void macro_append(void); void hex_init(void); void add_path(char *path); /************************************************************************/ struct macro_head { int pass; /* Pass in which macro was defined: 1 or 2 */ struct pnode *parms; struct macro_body *body; int defined; /* 1 macro has been defined so calls are valid */ char *src_name; unsigned int line_number; gp_symbol_type *file_symbol; }; struct macro_body { char *src_line; /* Original source line - for listing */ struct macro_body *next; /* Next line in listing */ }; struct amode { enum { in_then, in_else } mode; int enabled; /* Are we currently enabled? */ int prev_enabled; struct amode *prev; }; #endif gputils-0.13.7/gpasm/lst.c0000644000175000017500000003477411156521302012302 00000000000000/* ".LST" file output for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "cod.h" #include "coff.h" extern int _16bit_core; void lst_throw() { if(state.lst.f) { state.lst.page++; fprintf(state.lst.f, "%s%-32s%-12s%-29sPAGE %2d\n%s\n%s\n", (state.lst.page == 1) ? "" : "\f", GPASM_VERSION_STRING, state.srcfilename, state.lst.startdate, state.lst.page, state.lst.title_name, state.lst.subtitle_name); state.lst.lineofpage = 4; cod_lst_line(COD_NORMAL_LST_LINE); cod_lst_line(COD_NORMAL_LST_LINE); cod_lst_line(COD_NORMAL_LST_LINE); state.lst.line_number += 3; } } void lst_line(char *line) { if (state.lst.f) { if (state.lst.linesperpage != 0) { if ((state.lst.lineofpage++ % state.lst.linesperpage) == 0) { lst_throw(); lst_line("LOC OBJECT CODE LINE SOURCE TEXT"); lst_line(" VALUE"); lst_line(" "); } } fprintf(state.lst.f, "%s\n", line); state.lst.line_number++; cod_lst_line(COD_NORMAL_LST_LINE); } } void lst_init() { state.lst.lineofpage = 0; state.lst.page = 0; state.lst.linesperpage = 60; state.lst.line_number = 1; state.lst.memorymap = 1; state.lst.symboltable = 1; /* Determine state.startdate */ gp_date_string(state.lst.startdate, sizeof(state.lst.startdate)); if (!state.cmd_line.macro_expand){ state.lst.expand = true; } if (state.cmd_line.lst_force) state.lst.force = true; else state.lst.force = false; state.lst.config_address = 0; state.lst.title_name[0] = '\0'; state.lst.subtitle_name[0] = '\0'; state.lst.tabstop = 8; /* Default tabstop every 8 */ if (state.lstfile != named) { strncpy(state.lstfilename, state.basefilename, sizeof(state.lstfilename)); strncat(state.lstfilename, ".lst", sizeof(state.lstfilename)); } if (state.lstfile == suppress) { state.lst.f = NULL; state.lst.enabled = false; unlink(state.lstfilename); } else { state.lst.f = fopen(state.lstfilename, "wt"); if (state.lst.f == NULL) { perror(state.lstfilename); exit(1); } state.lst.enabled = true; } cod_lst_line(COD_FIRST_LST_LINE); } void lst_memory_map(MemBlock *m) { char buf[BUFSIZ]; int i, j, base, row_used, num_per_line, num_per_block; lst_line(""); lst_line(""); lst_line("MEMORY USAGE MAP ('X' = Used, '-' = Unused)"); lst_line(""); if (_16bit_core) { /* uses byte addressing so read half as many words */ num_per_line = 32; num_per_block = 8; } else { num_per_line = 64; num_per_block = 16; } while(m) { assert(m->memory != NULL); base = (m->base << I_MEM_BITS); for (i = 0; i < MAX_I_MEM; i += num_per_line) { row_used = 0; for (j = 0; j < num_per_line; j++) { if (m->memory[i+j] & MEM_USED_MASK) { row_used = 1; break; } } if(row_used) { snprintf(buf, sizeof(buf), "%08x :", (i + base) << _16bit_core); for (j = 0; j < num_per_line; j++) { if ((j % num_per_block) == 0) { strncat(buf, " ", sizeof(buf)); } if (m->memory[i + j] & MEM_USED_MASK) { strncat(buf, "X", sizeof(buf)); if (_16bit_core) { /* each word has two bytes */ strncat(buf, "X", sizeof(buf)); } } else { strncat(buf, "-", sizeof(buf)); if (_16bit_core) { /* each word has two bytes */ strncat(buf, "-", sizeof(buf)); } } } lst_line(buf); } } m = m->next; } lst_line(""); lst_line("All other memory blocks unused."); lst_line(""); snprintf(buf, sizeof(buf), "Program Memory Words Used: %i", i_memory_used(state.i_memory)); lst_line(buf); } void lst_close() { cod_lst_line(COD_LAST_LST_LINE); if (state.lst.f) { fprintf(state.lst.f, "\n\n"); fprintf(state.lst.f, "Errors : %7d\n", state.num.errors); fprintf(state.lst.f, "Warnings : %7d reported, %7d suppressed\n", state.num.warnings, state.num.warnings_suppressed); fprintf(state.lst.f, "Messages : %7d reported, %7d suppressed\n", state.num.messages, state.num.messages_suppressed); fprintf(state.lst.f, "\f\n"); fclose(state.lst.f); } } unsigned int lst_data(char *m, unsigned int byte_org, unsigned int bytes_emitted, size_t sizeof_m) { char buf[BUFSIZ]; unsigned int i; unsigned int lst_bytes = 0; size_t m_spacing, m_prev_len = strlen(m), m_after_len; if (bytes_emitted == 0) return 0; /* when in a byte packed section, print byte by byte */ if (state.obj.new_sec_flags & STYP_BPACK) { gp_boolean started_odd = (byte_org & 1) != 0; if (started_odd) { /* not word-aligned */ /* list first byte */ unsigned char emit_byte = (unsigned char)(i_memory_get(state.i_memory, (byte_org >> 1)) >> 8); snprintf(buf, sizeof(buf), "%02X ", emit_byte); strncat(m, buf, sizeof_m); ++lst_bytes; } else if (bytes_emitted == 1) { /* word-aligned */ /* but only one byte */ unsigned char emit_byte = (unsigned char)(i_memory_get(state.i_memory, (byte_org >> 1)) & 0xff); snprintf(buf, sizeof(buf), "%02X ", emit_byte); strncat(m, buf, sizeof_m); ++lst_bytes; } /* list whole words */ for (i = 0; (i < ((bytes_emitted-started_odd) >> 1)) && (i < 1); ++i) { unsigned int emit_word = i_memory_get(state.i_memory, ((byte_org+started_odd) >> 1) + i) & 0xffff; snprintf(buf, sizeof(buf), "%02X %02X ", emit_word & 0x00ff, emit_word >> 8); strncat(m, buf, sizeof_m); lst_bytes += 2; } if (i != 1 && started_odd && bytes_emitted > 1) { /* we have space for an extra byte if we had no whole word and we started odd */ snprintf(buf, sizeof(buf), "%02X", i_memory_get(state.i_memory, ((byte_org + 1) >> 1)) & 0xff00 >> 8); strncat(m, buf, sizeof_m); ++lst_bytes; } else if (!started_odd && i == 1 && bytes_emitted > 2) { /* we have space for another byte, word aligned */ snprintf(buf, sizeof(buf), "%02X", i_memory_get(state.i_memory, (byte_org + 2) >> 1) & 0xff); strncat(m, buf, sizeof_m); ++lst_bytes; } } else { /* non-code pack section */ /* list full words as bytes */ for (i = 0; (i < (bytes_emitted >> 1)) && (i < 2); ++i) { unsigned int emit_word = i_memory_get(state.i_memory, (byte_org>>1) + i) & 0xffff; snprintf(buf, sizeof(buf), "%04X ", emit_word); strncat(m, buf, sizeof_m); lst_bytes += 2; } if (bytes_emitted < 4) { /* list extra byte if odd */ if (((byte_org+bytes_emitted) & 1) != 0) { snprintf(buf, sizeof(buf), "%02X ", i_memory_get(state.i_memory, (byte_org+bytes_emitted)>>1) & 0x00ff); strncat(m, buf, sizeof_m); ++lst_bytes; } else { strncat(m, " ", sizeof_m); } } } /* append appropriate spacing */ m_after_len = strlen(m); m_spacing = m_after_len - m_prev_len; for(; m_spacing < 10; m_spacing++) { m[m_after_len++] = ' '; } m[m_after_len] = '\0'; return lst_bytes; } void lst_format_line(char *src_line, int value) { char m[BUFSIZ]; char buf[BUFSIZ]; unsigned int emitted = 0; unsigned int byte_org = 0; unsigned int bytes_emitted = 0; unsigned int lst_bytes; assert(src_line != NULL); switch (state.lst.line.linetype) { case equ: case set: snprintf(m, sizeof(m), " %08X", value); strncat(m, " ", sizeof(m)); break; case org: snprintf(m, sizeof(m), "%04X ", state.org << _16bit_core); strncat(m, " ", sizeof(m)); break; case idlocs: /* not used for 16 bit devices, config is used */ snprintf(m, sizeof(m), "%04X %04X %04X ", state.device.id_location, i_memory_get(state.i_memory, state.device.id_location) & 0xffff, i_memory_get(state.i_memory, state.device.id_location + 1) & 0xffff); break; case insn: byte_org = (state.lst.line.was_org << 1); if (state.obj.section) byte_org -= (state.obj.section->emitted_pack_byte ? 1 : 0); bytes_emitted = (state.org << 1) - byte_org; /* deal with offset changes for non-word aligned data */ if (state.obj.section) { /* do we have a pending byte for a full word? */ if (state.obj.section->have_pack_byte) { /* did we emit some bytes? if so we have to subtract a half word */ if (bytes_emitted > 0 && state.obj.section->have_pack_byte) bytes_emitted--; /* is this a label or something with no instructions? then our * org must be modified. */ else if (bytes_emitted == 0) byte_org--; } } emitted = (bytes_emitted >> 1); if (bytes_emitted > 0 && ((byte_org & 1) == 0) && ((bytes_emitted & 1) != 0)) emitted += 1; snprintf(m, sizeof(m), "%04X ", byte_org >> (1 - _16bit_core)); lst_bytes = lst_data(m, byte_org, bytes_emitted, sizeof(m)); byte_org += lst_bytes; bytes_emitted -= lst_bytes; break; case config: if(_16bit_core) { /* config data is byte addressable, but we only want to print words in the list file. */ if (state.lst.config_address == CONFIG4L) { /* Special case */ snprintf(m, sizeof(m), "%06X %04X ", state.lst.config_address, i_memory_get(state.i_memory, state.lst.config_address >> 1) & 0xffff); } else if((state.lst.config_address & 0x1) == 0) { /* if it is an even address don't print anything */ strncpy(m, " ", sizeof(m)); } else { snprintf(m, sizeof(m), "%06X %04X ", state.lst.config_address - 1, i_memory_get(state.i_memory, (state.lst.config_address - 1) >> 1) & 0xffff); } } else { snprintf(m, sizeof(m), "%06X %04X ", state.lst.config_address, i_memory_get(state.i_memory, state.lst.config_address) & 0xffff); } break; case res: strncpy(m, " ", sizeof(m)); if (SECTION_FLAGS & STYP_TEXT) { /* generate line numbers for res directives in program memory */ emitted = state.org - state.lst.line.was_org; } break; case sec: case dir: case none: default: strncpy(m, " ", sizeof(m)); break; } if (state.stGlobal == state.stTop) { snprintf(buf, sizeof(buf), "%05d ", state.src->line_number); } else { snprintf(buf, sizeof(buf), " M "); } strncat(m, buf, sizeof(m)); /* Now copy 'l' to 'e', expanding tabs as required */ { int offset = strlen(m); int column = 0; char *old; char *e = m + offset; old = src_line; while (*old) { if (*old == '\t') { int len = state.lst.tabstop - column % state.lst.tabstop; if ((offset + (column += len)) >= sizeof(m)) break; while (len--) *e++ = ' '; } else { if ((offset + (++column)) >= sizeof(m)) break; *e++ = *old; } old++; } *e = '\0'; /* terminate the new string */ } coff_linenum(emitted); /* Don't write to file is list is disabled */ if (!state.lst.enabled) return; /* Tell the .cod file that the next line(s) has an opcode(s) */ state.cod.emitting = emitted; lst_line(m); #ifdef GPUTILS_DEBUG fprintf(stderr, "%s\n\n", m); #endif if (state.lst.line.linetype == idlocs) { snprintf(m, sizeof(m), " %04X %04X ", i_memory_get(state.i_memory, state.device.id_location + 2) & 0xffff, i_memory_get(state.i_memory, state.device.id_location + 3) & 0xffff); lst_line(m); } if (bytes_emitted > 0) { while (bytes_emitted > 0) { /* data left to print on separate lines */ strncpy(m, " ", sizeof(m)); lst_bytes = lst_data(m, byte_org, bytes_emitted, sizeof(m)); byte_org += lst_bytes; bytes_emitted -= lst_bytes; lst_line(m); } state.cod.emitting = 0; } /* we reset this here, otherwise labels will display bytes again */ if(state.obj.section) state.obj.section->emitted_pack_byte = false; } /* append the symbol table to the .lst file */ void lst_symbol_table(struct symbol_table *table) { int i; const char *symbol_format = "%-32s %08X"; struct symbol **lst, **ps, *s; char buf[BUFSIZ]; lst_line("SYMBOL TABLE"); snprintf(buf, sizeof(buf), "%-32s %-8s", " LABEL", " VALUE"); lst_line(buf); lst_line(""); ps = lst = malloc(table->count * sizeof(lst[0])); for (i = 0; i < HASH_SIZE; i++) for (s = table->hash_table[i]; s; s = s->next) *ps++ = s; assert(ps == &lst[table->count]); qsort(lst, table->count, sizeof(lst[0]), symbol_compare); for (i = 0; i < table->count; i++) { struct variable *var; var = get_symbol_annotation(lst[i]); snprintf(buf, sizeof(buf), symbol_format, get_symbol_name(lst[i]), var ? var->value : 0); lst_line(buf); } cod_write_symbols(lst,table->count); } void lst_defines_table(struct symbol_table *table) { int i; const char *symbol_format = "%-32s %s"; struct symbol **lst, **ps, *s; char buf[BUFSIZ]; ps = lst = malloc(table->count * sizeof(lst[0])); for (i = 0; i < HASH_SIZE; i++) for (s = table->hash_table[i]; s; s = s->next) *ps++ = s; assert(ps == &lst[table->count]); qsort(lst, table->count, sizeof(lst[0]), symbol_compare); for (i = 0; i < table->count; i++) { char *defined_as; defined_as = get_symbol_annotation(lst[i]); snprintf(buf, sizeof(buf), symbol_format, get_symbol_name(lst[i]), defined_as); lst_line(buf); } } gputils-0.13.7/gpasm/util.c0000644000175000017500000003227311156521302012445 00000000000000/* Some helpful utility functions for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "gperror.h" #include "directive.h" #include "coff.h" static struct file_context *last = NULL; int stringtolong(char *string, int radix) { char *endptr; int value; value = strtoul(string, &endptr, radix); if ((endptr == NULL) || (*endptr != '\0')) { char complaint[80]; snprintf(complaint, sizeof(complaint), isprint(*endptr) ? "Illegal character '%c' in numeric constant " : "Illegal character %#x in numeric constant" , *endptr); gperror(GPE_UNKNOWN, complaint); } return value; } int gpasm_magic(char *c) { if (c[0] == '\\') { switch (c[1]) { case 'a': return '\a'; case 'b': return '\b'; case 'f': return '\f'; case 'n': return '\n'; case 'r': return '\r'; case 't': return '\t'; case 'v': return '\v'; default: return c[1]; } } return c[0]; } /* convert_escaped_char(char *src,char c) Input: pointer to a string Output returns the input string with escaped char converted to a regular char For example if escaped character is a double quote then: This is a escaped quote: \" is translated to: This is a escaped quote: " */ char * convert_escaped_char(char *str, char c) { char *src = str; char *dest = str; if (!str) return str; while (*src) { if (*src =='\\' && src[1] == c) src++; *dest++ = *src++; } *dest=0; return str; } /* Determine the value of the escape char pointed to by ps. Return a pointer to the next character. */ char * convert_escape_chars(char *ps, int *value) { int count; if (*ps != '\\') { *value = *ps++; } else { /* escape char, convert its value and write to the new string */ switch (ps[1]) { case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': /* octal number */ count = 0; *value = 0; ps++; while (count < 3) { if (*ps < '0' || *ps > '7') break; *value = (*value << 3) + *ps - '0'; ps++; count++; } break; case 'x': /* hex number */ if ((ps[2] == '\0') || (ps[3] == '\0')) { gperror(GPE_UNKNOWN, "missing hex value in \\x escape character"); *value = 0; /* return a NULL character */ ps[2] = '\0'; ps += 2; } else { char buffer[3]; buffer[0] = ps[2]; buffer[1] = ps[3]; buffer[2] = 0; *value = stringtolong(buffer, 16); ps += 4; } break; default: if (ps[1] == '\0') { gperror(GPE_UNKNOWN, "missing value in \\ escape character"); *value = 0; /* return a NULL character */ ps++; } else { *value = gpasm_magic(ps); ps += 2; } } } return ps; } /* In some contexts, such as in the operand to a literal instruction, a * single-character string literal in an expression can be coerced to a * character literal. coerce_str1 converts a string-type pnode to a * constant-type pnode in-place. */ void coerce_str1(struct pnode *exp) { if ((exp != NULL) && (exp->tag == string)) { int value; char *pc = convert_escape_chars(exp->value.string, &value); if (*pc == '\0') { /* castable string, make the conversion */ exp->tag = constant; exp->value.constant = value; } } } void set_global(char *name, gpasmVal value, enum globalLife lifetime, enum gpasmValTypes type) { struct symbol *sym; struct variable *var; /* Search the entire stack (i.e. include macro's local symbol tables) for the symbol. If not found, then add it to the global symbol table. */ sym = get_symbol(state.stTop, name); if (sym == NULL) sym = add_symbol(state.stGlobal, name); var = get_symbol_annotation(sym); if (var == NULL) { /* new symbol */ var = malloc(sizeof(*var)); annotate_symbol(sym, var); var->value = value; var->coff_num = state.obj.symbol_num; var->coff_section_num = state.obj.section_num; var->type = type; var->previous_type = type; /* coff symbols can be changed to global */ var->lifetime = lifetime; /* increment the index into the coff symbol table for the relocations */ switch(type) { case gvt_extern: case gvt_global: case gvt_static: case gvt_address: case gvt_debug: case gvt_absolute: state.obj.symbol_num++; break; default: break; } } else if (lifetime == TEMPORARY) { /* * TSD - the following embarrassing piece of code is a hack * to fix a problem when global variables are changed * during the expansion of a macro. Macros are expanded * by running through them twice. if you have a stetement * like: * some_var set some_var + 1 * then this is incremented twice! So the if statement * makes sure that the value is assigned on the second * pass only in the macro. Jeez this really sucks.... */ var->value = value; } else if (state.pass == 2) { char *coff_name; if (var->value != value) { char message[BUFSIZ]; snprintf(message, sizeof(message), "Value of symbol \"%s\" differs on second pass\n pass 1=%d, pass 2=%d", name,var->value,value); gperror(GPE_DIFFLAB, message); } coff_name = coff_local_name(name); coff_add_sym(coff_name, value, var->type); if (coff_name != NULL) free(coff_name); } } void purge_temp_symbols(struct symbol_table *table) { int i; if (table != NULL) { for (i = 0; i < HASH_SIZE; ++i) { struct symbol *cur_symbol; struct symbol *last_symbol = NULL; cur_symbol = table->hash_table[i]; while (cur_symbol != NULL) { if (cur_symbol != NULL) { struct variable *var = (struct variable *)get_symbol_annotation(cur_symbol); if (var != NULL) { if (var->lifetime == TEMPORARY) { struct symbol *next_symbol = cur_symbol->next; free(cur_symbol); table->count--; if (last_symbol == NULL) table->hash_table[i] = next_symbol; else last_symbol->next = next_symbol; cur_symbol = next_symbol; continue; } } } last_symbol = cur_symbol; cur_symbol = cur_symbol->next; } } purge_temp_symbols(table->prev); } } void select_errorlevel(int level) { if (state.cmd_line.error_level) { gpmessage(GPM_SUPVAL, NULL); } else { if (level == 0) { state.error_level = 0; } else if (level == 1) { state.error_level = 1; } else if (level == 2) { state.error_level = 2; } else { if (state.pass == 0) { fprintf(stderr, "Error: invalid warning level \"%i\"\n", level); } else { gperror(GPE_ILLEGAL_ARGU, "Expected w= 0, 1, 2"); } } } } void select_expand(char *expand) { if (state.cmd_line.macro_expand) { gpmessage(GPM_SUPLIN, NULL); } else { if (strcasecmp(expand, "ON") == 0) { state.lst.expand = true; } else if (strcasecmp(expand, "OFF") == 0) { state.lst.expand = false; } else { state.lst.expand = true; if (state.pass == 0) { fprintf(stderr, "Error: invalid option \"%s\"\n", expand); } else { gpwarning(GPE_ILLEGAL_ARGU, "Expected ON or OFF"); } } } } void select_hexformat(char *format_name) { if (state.cmd_line.hex_format) { gpwarning(GPW_CMDLINE_HEXFMT, NULL); } else { if (strcasecmp(format_name, "inhx8m") == 0) { state.hex_format = inhx8m; } else if (strcasecmp(format_name, "inhx8s") == 0) { state.hex_format = inhx8s; } else if (strcasecmp(format_name, "inhx16") == 0) { state.hex_format = inhx16; } else if (strcasecmp(format_name, "inhx32") == 0) { state.hex_format = inhx32; } else { state.hex_format = inhx8m; if (state.pass == 0) { fprintf(stderr, "Error: invalid format \"%s\"\n", format_name); } else { gperror(GPE_ILLEGAL_ARGU, "Expected inhx8m, inhx8s, inhx16, or inhx32"); } } } } void select_radix(char *radix_name) { if (state.cmd_line.radix) { gpwarning(GPW_CMDLINE_RADIX, NULL); } else { if (strcasecmp(radix_name, "hex") == 0) { state.radix = 16; } else if (strcasecmp(radix_name, "dec") == 0) { state.radix = 10; } else if (strcasecmp(radix_name, "decimal") == 0) { state.radix = 10; } else if (strcasecmp(radix_name, "oct") == 0) { state.radix = 8; } else if (strcasecmp(radix_name, "octal") == 0) { state.radix = 8; } else { state.radix = 16; if (state.pass == 0) { fprintf(stderr, "invalid radix \"%s\", will use hex.\n", radix_name); } else { gpwarning(GPW_RADIX, NULL); } } } } /************************************************************************/ /* Function to append a line to an ongoing macro definition */ void macro_append(void) { struct macro_body *body = malloc(sizeof(*body)); body->src_line = NULL; *state.mac_prev = body; /* append this to the chain */ state.mac_prev = &body->next; /* this is the new end of the chain */ state.mac_body = body; body->next = NULL; /* make sure it's terminated */ } gpasmVal do_or_append_insn(char *op, struct pnode *parms) { gpasmVal r; if (!state.mac_prev || (strcasecmp(op, "endm") == 0) || (state.while_head && (strcasecmp(op, "endw") == 0))) { r = do_insn(op, parms); } else { macro_append(); r = 0; } return r; } void print_pnode(struct pnode *p) { if(!p) { printf("Null\n"); return; } switch(p->tag) { case constant: printf(" constant: %d\n",p->value.constant); break; case symbol: printf(" symbol: %s\n",p->value.symbol); break; case unop: printf(" unop: %d\n",p->value.unop.op); break; case binop: printf(" binop: %d\n",p->value.binop.op); break; case string: printf(" string: %s\n",p->value.string); break; case list: printf(" list:\n"); break; default: printf("unknown type\n"); } } void print_macro_node(struct macro_body *mac) { if(mac->src_line) printf(" src_line = %s\n",mac->src_line); } void print_macro_body(struct macro_body *mac) { struct macro_body *mb = mac; printf("{\n"); while(mb) { print_macro_node(mb); mb = mb->next; } printf("}\n"); } /************************************************************************/ /* add_file: add a file of type 'type' to the file_context stack. */ struct file_context * add_file(unsigned int type, char *name) { static unsigned int file_id = 0; struct file_context *new; /* First check to make sure this file is not already in the list */ if(last) { new = last; do { if(strcmp(new->name, name) == 0) return(new); new = new->prev; } while(new != NULL); } new = malloc(sizeof(*new)); new->name = strdup(name); new->ft = type; new->prev = last; new->id = file_id++; new->next = NULL; if(last) last->next = new; last = new; state.files = new; return(new); } /* free_files: free memory allocated to the file_context stack */ void free_files(void) { struct file_context *old; while(last != NULL) { old = last; last = old->prev; free(old->name); free(old); } } void hex_init(void) { if (state.hexfile == suppress) { /* Must delete hex file when suppressed. */ writehex(state.basefilename, state.i_memory, state.hex_format, 1, 0, state.dos_newlines); return; } if (check_writehex(state.i_memory, state.hex_format)) { gperror(GPE_IHEX,NULL); } else { int byte_words; if (state.device.core_size > 0xff) { byte_words = 0; } else { byte_words = 1; if (state.hex_format != inhx8m) { gpwarning(GPW_UNKNOWN,"Must use inhx8m format for EEPROM8"); state.hex_format = inhx8m; } } if (writehex(state.basefilename, state.i_memory, state.hex_format, state.num.errors, byte_words, state.dos_newlines)) { gperror(GPE_UNKNOWN,"Error generating hex file"); } } return; } gputils-0.13.7/gpasm/Makefile.am0000644000175000017500000000125111156521302013350 00000000000000## Process this file with automake to produce Makefile.in bin_PROGRAMS = gpasm noinst_LIBRARIES = libgpasm.a AM_CPPFLAGS = -I${top_srcdir}/libgputils -I${top_srcdir}/include libgpasm_a_SOURCES=\ parse.y \ cod.c \ coff.c \ deps.c \ directive.c \ evaluate.c \ gpasm.c \ scan.l \ gperror.c \ lst.c \ macro.c \ processor.c \ special.c \ util.c \ cod.h \ coff.h \ deps.h \ directive.h \ evaluate.h \ gpasm.h \ gperror.h \ libgpasm.h \ lst.h \ macro.h \ processor.h \ scan.h \ special.h gpasm_SOURCES = main.c gpasm_LDADD = libgpasm.a ${top_builddir}/@LIBGPUTILS@ ${top_builddir}/@LIBIBERTY@ AM_YFLAGS = -d -vt AM_LFLAGS = -i CLEANFILES = parse.output gputils-0.13.7/gpasm/scan.c0000644000175000017500000032150211156521335012416 00000000000000 #line 3 "scan.c" #define YY_INT_ALIGNED short int /* A lexical scanner generated by flex */ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 #define YY_FLEX_MINOR_VERSION 5 #define YY_FLEX_SUBMINOR_VERSION 35 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif /* First, we deal with platform-specific or compiler-specific issues. */ /* begin standard C headers. */ #include #include #include #include /* end standard C headers. */ /* flex integer type definitions */ #ifndef FLEXINT_H #define FLEXINT_H /* C99 systems have . Non-C99 systems may or may not. */ #if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 199901L /* C99 says to define __STDC_LIMIT_MACROS before including stdint.h, * if you want the limit (max/min) macros for int types. */ #ifndef __STDC_LIMIT_MACROS #define __STDC_LIMIT_MACROS 1 #endif #include typedef int8_t flex_int8_t; typedef uint8_t flex_uint8_t; typedef int16_t flex_int16_t; typedef uint16_t flex_uint16_t; typedef int32_t flex_int32_t; typedef uint32_t flex_uint32_t; #else typedef signed char flex_int8_t; typedef short int flex_int16_t; typedef int flex_int32_t; typedef unsigned char flex_uint8_t; typedef unsigned short int flex_uint16_t; typedef unsigned int flex_uint32_t; /* Limits of integral types. */ #ifndef INT8_MIN #define INT8_MIN (-128) #endif #ifndef INT16_MIN #define INT16_MIN (-32767-1) #endif #ifndef INT32_MIN #define INT32_MIN (-2147483647-1) #endif #ifndef INT8_MAX #define INT8_MAX (127) #endif #ifndef INT16_MAX #define INT16_MAX (32767) #endif #ifndef INT32_MAX #define INT32_MAX (2147483647) #endif #ifndef UINT8_MAX #define UINT8_MAX (255U) #endif #ifndef UINT16_MAX #define UINT16_MAX (65535U) #endif #ifndef UINT32_MAX #define UINT32_MAX (4294967295U) #endif #endif /* ! C99 */ #endif /* ! FLEXINT_H */ #ifdef __cplusplus /* The "const" storage-class-modifier is valid. */ #define YY_USE_CONST #else /* ! __cplusplus */ /* C99 requires __STDC__ to be defined as 1. */ #if defined (__STDC__) #define YY_USE_CONST #endif /* defined (__STDC__) */ #endif /* ! __cplusplus */ #ifdef YY_USE_CONST #define yyconst const #else #define yyconst #endif /* Returned upon end-of-file. */ #define YY_NULL 0 /* Promotes a possibly negative, possibly signed char to an unsigned * integer for use as an array index. If the signed char is negative, * we want to instead treat it as an 8-bit unsigned char, hence the * double cast. */ #define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c) /* Enter a start condition. This macro really ought to take a parameter, * but we do it the disgusting crufty way forced on us by the ()-less * definition of BEGIN. */ #define BEGIN (yy_start) = 1 + 2 * /* Translate the current start state into a value that can be later handed * to BEGIN to return to the state. The YYSTATE alias is for lex * compatibility. */ #define YY_START (((yy_start) - 1) / 2) #define YYSTATE YY_START /* Action number for EOF rule of a given start state. */ #define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) /* Special action meaning "start processing a new file". */ #define YY_NEW_FILE yyrestart(yyin ) #define YY_END_OF_BUFFER_CHAR 0 /* Size of default input buffer. */ #ifndef YY_BUF_SIZE #define YY_BUF_SIZE 16384 #endif /* The state buf must be large enough to hold one state per character in the main buffer. */ #define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type)) #ifndef YY_TYPEDEF_YY_BUFFER_STATE #define YY_TYPEDEF_YY_BUFFER_STATE typedef struct yy_buffer_state *YY_BUFFER_STATE; #endif extern int yyleng; extern FILE *yyin, *yyout; #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 #define YY_LESS_LINENO(n) /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \ YY_DO_BEFORE_ACTION; /* set up yytext again */ \ } \ while ( 0 ) #define unput(c) yyunput( c, (yytext_ptr) ) #ifndef YY_TYPEDEF_YY_SIZE_T #define YY_TYPEDEF_YY_SIZE_T typedef size_t yy_size_t; #endif #ifndef YY_STRUCT_YY_BUFFER_STATE #define YY_STRUCT_YY_BUFFER_STATE struct yy_buffer_state { FILE *yy_input_file; char *yy_ch_buf; /* input buffer */ char *yy_buf_pos; /* current position in input buffer */ /* Size of input buffer in bytes, not including room for EOB * characters. */ yy_size_t yy_buf_size; /* Number of characters read into yy_ch_buf, not including EOB * characters. */ int yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to * delete it. */ int yy_is_our_buffer; /* Whether this is an "interactive" input source; if so, and * if we're using stdio for input, then we want to use getc() * instead of fread(), to make sure we stop fetching input after * each newline. */ int yy_is_interactive; /* Whether we're considered to be at the beginning of a line. * If so, '^' rules will be active on the next match, otherwise * not. */ int yy_at_bol; int yy_bs_lineno; /**< The line count. */ int yy_bs_column; /**< The column count. */ /* Whether to try to fill the input buffer when we reach the * end of it. */ int yy_fill_buffer; int yy_buffer_status; #define YY_BUFFER_NEW 0 #define YY_BUFFER_NORMAL 1 /* When an EOF's been seen but there's still some text to process * then we mark the buffer as YY_EOF_PENDING, to indicate that we * shouldn't try reading from the input source any more. We might * still have a bunch of tokens to match, though, because of * possible backing-up. * * When we actually see the EOF, we change the status to "new" * (via yyrestart()), so that the user can continue scanning by * just pointing yyin at a new input file. */ #define YY_BUFFER_EOF_PENDING 2 }; #endif /* !YY_STRUCT_YY_BUFFER_STATE */ /* Stack of input buffers. */ static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */ static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */ static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */ /* We provide macros for accessing buffer states in case in the * future we want to put the buffer states in a more general * "scanner state". * * Returns the top of the stack, or NULL. */ #define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ : NULL) /* Same as previous macro, but useful when we know that the buffer stack is not * NULL or when we need an lvalue. For internal use only. */ #define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)] /* yy_hold_char holds the character lost when yytext is formed. */ static char yy_hold_char; static int yy_n_chars; /* number of characters read into yy_ch_buf */ int yyleng; /* Points to current character in buffer. */ static char *yy_c_buf_p = (char *) 0; static int yy_init = 0; /* whether we need to initialize */ static int yy_start = 0; /* start state number */ /* Flag which is used to allow yywrap()'s to do buffer switches * instead of setting up a fresh yyin. A bit of a hack ... */ static int yy_did_buffer_switch_on_eof; void yyrestart (FILE *input_file ); void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ); YY_BUFFER_STATE yy_create_buffer (FILE *file,int size ); void yy_delete_buffer (YY_BUFFER_STATE b ); void yy_flush_buffer (YY_BUFFER_STATE b ); void yypush_buffer_state (YY_BUFFER_STATE new_buffer ); void yypop_buffer_state (void ); static void yyensure_buffer_stack (void ); static void yy_load_buffer_state (void ); static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file ); #define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER ) YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size ); YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str ); YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len ); void *yyalloc (yy_size_t ); void *yyrealloc (void *,yy_size_t ); void yyfree (void * ); #define yy_new_buffer yy_create_buffer #define yy_set_interactive(is_interactive) \ { \ if ( ! YY_CURRENT_BUFFER ){ \ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ yy_create_buffer(yyin,YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ } #define yy_set_bol(at_bol) \ { \ if ( ! YY_CURRENT_BUFFER ){\ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ yy_create_buffer(yyin,YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ } #define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) /* Begin user sect3 */ #define yywrap(n) 1 #define YY_SKIP_YYWRAP typedef unsigned char YY_CHAR; FILE *yyin = (FILE *) 0, *yyout = (FILE *) 0; typedef int yy_state_type; extern int yylineno; int yylineno = 1; extern char *yytext; #define yytext_ptr yytext static yy_state_type yy_get_previous_state (void ); static yy_state_type yy_try_NUL_trans (yy_state_type current_state ); static int yy_get_next_buffer (void ); static void yy_fatal_error (yyconst char msg[] ); /* Done after the current pattern has been matched and before the * corresponding action - sets up yytext. */ #define YY_DO_BEFORE_ACTION \ (yytext_ptr) = yy_bp; \ yyleng = (size_t) (yy_cp - yy_bp); \ (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; #define YY_NUM_RULES 73 #define YY_END_OF_BUFFER 74 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info { flex_int32_t yy_verify; flex_int32_t yy_nxt; }; static yyconst flex_int16_t yy_accept[459] = { 0, 69, 69, 69, 69, 69, 69, 0, 0, 69, 69, 74, 72, 69, 70, 72, 39, 27, 72, 72, 72, 72, 72, 72, 72, 72, 72, 38, 38, 71, 72, 72, 72, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 27, 72, 72, 69, 24, 72, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 43, 72, 45, 45, 10, 72, 69, 51, 39, 39, 39, 27, 27, 27, 27, 27, 58, 52, 61, 0, 0, 26, 66, 67, 56, 68, 64, 54, 65, 55, 27, 35, 27, 57, 38, 29, 33, 36, 31, 38, 71, 46, 49, 50, 48, 47, 0, 27, 27, 27, 27, 27, 0, 27, 0, 27, 27, 27, 27, 0, 27, 16, 27, 27, 0, 27, 27, 63, 62, 53, 69, 0, 0, 0, 0, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 16, 24, 24, 24, 24, 24, 24, 24, 24, 43, 0, 42, 0, 45, 0, 45, 0, 44, 0, 45, 10, 10, 39, 39, 39, 39, 27, 27, 27, 16, 27, 40, 40, 0, 0, 27, 28, 28, 28, 28, 28, 59, 60, 0, 0, 0, 0, 27, 0, 0, 27, 2, 27, 27, 0, 0, 27, 27, 27, 27, 13, 0, 0, 27, 27, 0, 0, 0, 0, 0, 24, 24, 24, 24, 16, 24, 24, 24, 24, 24, 2, 24, 24, 24, 24, 24, 24, 24, 13, 24, 24, 24, 24, 24, 0, 0, 0, 0, 45, 45, 44, 45, 44, 0, 44, 45, 45, 45, 45, 39, 39, 25, 27, 27, 27, 27, 27, 0, 0, 27, 41, 41, 0, 0, 30, 27, 34, 17, 7, 27, 27, 27, 37, 12, 27, 27, 14, 32, 27, 27, 0, 0, 0, 0, 0, 23, 24, 24, 24, 24, 24, 24, 24, 24, 24, 17, 7, 24, 24, 24, 12, 24, 24, 24, 14, 24, 24, 24, 24, 24, 0, 0, 44, 45, 45, 45, 45, 44, 0, 0, 0, 0, 45, 45, 17, 27, 27, 27, 27, 22, 0, 0, 27, 18, 27, 0, 8, 19, 27, 27, 11, 0, 0, 0, 0, 0, 24, 17, 24, 24, 24, 24, 24, 22, 24, 18, 24, 19, 24, 24, 24, 24, 24, 24, 11, 45, 45, 0, 0, 18, 19, 27, 27, 5, 27, 20, 27, 0, 0, 0, 0, 0, 24, 18, 19, 24, 24, 24, 5, 24, 20, 24, 24, 24, 24, 3, 20, 27, 27, 27, 0, 0, 0, 0, 24, 20, 24, 24, 24, 24, 24, 4, 24, 27, 27, 27, 0, 0, 0, 9, 24, 24, 24, 1, 24, 24, 21, 27, 15, 0, 21, 24, 15, 6, 6, 0 } ; static yyconst flex_int32_t yy_ec[256] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 5, 6, 7, 1, 8, 9, 10, 11, 12, 13, 14, 1, 15, 16, 17, 18, 19, 19, 19, 19, 19, 19, 19, 20, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 37, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 37, 37, 1, 51, 1, 52, 53, 1, 54, 55, 56, 57, 58, 59, 60, 61, 62, 37, 63, 64, 37, 65, 66, 67, 43, 68, 69, 70, 71, 72, 73, 74, 37, 37, 1, 75, 1, 1, 1, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53, 53 } ; static yyconst flex_int32_t yy_meta[76] = { 0, 1, 2, 3, 4, 1, 5, 6, 1, 1, 7, 1, 1, 1, 1, 8, 9, 1, 10, 11, 11, 12, 13, 2, 1, 2, 14, 6, 15, 15, 16, 16, 16, 15, 17, 17, 17, 17, 17, 17, 18, 17, 17, 17, 18, 17, 18, 17, 18, 17, 18, 19, 1, 20, 15, 15, 16, 16, 16, 15, 17, 17, 17, 17, 17, 18, 17, 17, 18, 17, 18, 17, 18, 17, 18, 1 } ; static yyconst flex_int16_t yy_base[493] = { 0, 0, 75, 149, 154, 159, 164, 186, 261, 210, 213, 1667, 2192, 171, 2192, 1642, 172, 186, 1641, 145, 1613, 0, 205, 212, 206, 269, 1639, 261, 262, 0, 159, 1638, 160, 1654, 330, 390, 239, 1650, 285, 290, 1649, 296, 288, 328, 1648, 299, 321, 1632, 156, 368, 403, 359, 220, 468, 528, 305, 1645, 402, 345, 1644, 356, 389, 391, 1634, 300, 416, 366, 338, 0, 199, 1640, 466, 0, 0, 238, 2192, 248, 2192, 585, 401, 1632, 437, 448, 344, 2192, 2192, 2192, 1628, 472, 0, 2192, 2192, 2192, 2192, 2192, 2192, 2192, 2192, 1630, 227, 457, 2192, 475, 521, 555, 617, 632, 651, 0, 1612, 2192, 2192, 2192, 1611, 1583, 1623, 1621, 1620, 1617, 1608, 1602, 372, 240, 470, 448, 498, 376, 1556, 514, 562, 482, 410, 1543, 502, 486, 2192, 2192, 2192, 664, 544, 188, 553, 464, 584, 382, 2192, 630, 663, 678, 674, 464, 669, 1509, 1492, 1490, 1469, 1403, 481, 632, 597, 681, 697, 686, 711, 578, 687, 488, 694, 607, 709, 712, 537, 0, 489, 2192, 777, 1409, 1369, 748, 753, 1364, 250, 850, 0, 0, 507, 734, 919, 0, 232, 717, 716, 750, 734, 2192, 1346, 233, 0, 723, 899, 900, 950, 951, 984, 2192, 2192, 1323, 759, 1312, 149, 756, 760, 774, 779, 788, 798, 762, 1311, 550, 806, 803, 809, 819, 1313, 1248, 582, 790, 845, 583, 608, 709, 719, 284, 827, 836, 852, 905, 983, 863, 938, 867, 844, 848, 973, 861, 852, 923, 978, 987, 853, 898, 1243, 990, 986, 988, 962, 989, 862, 1012, 1046, 0, 1166, 1047, 1163, 1104, 2192, 1173, 1066, 1085, 1090, 1246, 0, 1064, 1288, 2192, 1035, 1054, 1053, 1082, 1087, 323, 0, 1088, 2192, 1152, 697, 0, 2192, 1108, 2192, 1130, 1121, 1114, 1018, 1041, 2192, 1111, 1118, 1023, 1047, 2192, 1117, 1113, 930, 275, 829, 1083, 281, 2192, 1135, 1173, 1175, 1177, 1179, 1186, 1182, 1197, 1160, 1012, 992, 1133, 1178, 1247, 977, 1175, 1229, 1220, 954, 1241, 1205, 1063, 1252, 1244, 1264, 1330, 1329, 1330, 1351, 1401, 0, 571, 614, 1274, 1455, 0, 1373, 1497, 846, 1128, 1226, 1264, 1265, 823, 863, 0, 1157, 804, 1301, 912, 2192, 802, 1280, 1285, 786, 1018, 1223, 847, 1098, 1228, 1334, 946, 1357, 1376, 1393, 1375, 1394, 1017, 1271, 757, 1398, 734, 1384, 1408, 1367, 1396, 1394, 1327, 719, 1516, 1550, 1472, 1592, 706, 672, 1434, 1331, 639, 1434, 637, 1400, 906, 1341, 1410, 1380, 643, 1473, 1205, 1235, 1474, 1529, 1525, 620, 1438, 616, 1439, 1479, 1366, 1437, 607, 566, 1398, 1472, 1498, 1440, 1445, 568, 1020, 1538, 1307, 1542, 1536, 1494, 1563, 1531, 565, 1582, 1530, 1489, 1575, 531, 529, 1594, 467, 1592, 1570, 1583, 450, 1585, 1588, 388, 1593, 383, 372, 1568, 1606, 352, 297, 224, 2192, 1670, 1690, 1710, 1730, 1745, 1765, 1777, 1792, 1803, 1821, 1836, 1851, 1866, 1881, 1901, 1921, 1941, 1961, 1976, 1991, 2007, 2017, 2035, 2048, 2059, 2070, 2088, 2108, 2128, 2139, 2151, 2161, 2168, 2175 } ; static yyconst flex_int16_t yy_def[493] = { 0, 458, 458, 459, 459, 460, 460, 461, 461, 460, 460, 458, 458, 458, 458, 458, 462, 463, 458, 458, 464, 465, 458, 458, 458, 466, 458, 467, 467, 468, 458, 458, 458, 463, 469, 469, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 35, 458, 458, 458, 470, 471, 470, 472, 472, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 473, 474, 475, 476, 477, 478, 458, 458, 462, 458, 462, 463, 463, 463, 463, 463, 458, 458, 458, 458, 479, 465, 458, 458, 458, 458, 458, 458, 458, 458, 463, 458, 463, 458, 467, 467, 467, 467, 467, 480, 468, 458, 458, 458, 458, 458, 481, 35, 35, 35, 35, 35, 482, 35, 458, 35, 35, 35, 35, 483, 35, 35, 35, 35, 484, 35, 35, 458, 458, 458, 458, 458, 458, 458, 458, 470, 470, 458, 470, 470, 470, 470, 470, 470, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 473, 474, 458, 474, 475, 485, 476, 486, 475, 487, 476, 477, 477, 462, 462, 462, 78, 463, 463, 463, 463, 463, 458, 458, 458, 488, 463, 480, 480, 480, 480, 480, 458, 458, 458, 489, 482, 482, 35, 458, 458, 35, 35, 35, 35, 483, 483, 35, 35, 35, 35, 35, 484, 484, 35, 35, 458, 458, 458, 458, 458, 470, 470, 470, 470, 470, 470, 470, 470, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 474, 474, 474, 175, 485, 486, 485, 486, 458, 487, 476, 476, 476, 476, 182, 462, 187, 458, 463, 463, 463, 463, 463, 458, 490, 463, 458, 458, 458, 491, 458, 35, 458, 35, 35, 35, 35, 35, 458, 35, 35, 35, 35, 458, 35, 35, 458, 458, 458, 458, 458, 458, 470, 470, 470, 470, 470, 470, 470, 470, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 474, 259, 486, 486, 486, 486, 264, 487, 487, 487, 487, 266, 476, 270, 463, 463, 463, 463, 463, 463, 458, 492, 35, 35, 35, 458, 458, 35, 35, 35, 35, 458, 458, 458, 458, 458, 470, 470, 470, 470, 470, 470, 470, 470, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 54, 486, 338, 487, 343, 463, 463, 463, 463, 35, 35, 35, 35, 458, 458, 458, 458, 458, 470, 470, 470, 470, 470, 470, 54, 54, 54, 54, 54, 54, 54, 458, 463, 463, 35, 35, 458, 458, 458, 458, 470, 470, 470, 470, 54, 54, 54, 458, 54, 463, 35, 35, 458, 458, 458, 458, 470, 470, 54, 458, 54, 54, 463, 35, 35, 458, 470, 54, 54, 35, 54, 0, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458 } ; static yyconst flex_int16_t yy_nxt[2268] = { 0, 12, 13, 14, 13, 15, 16, 17, 18, 19, 20, 12, 21, 22, 23, 24, 25, 26, 27, 28, 28, 12, 29, 30, 31, 32, 33, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 40, 40, 43, 40, 44, 45, 44, 40, 40, 40, 46, 40, 40, 40, 12, 47, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 40, 43, 40, 44, 45, 40, 40, 40, 46, 40, 40, 40, 48, 12, 49, 14, 13, 15, 16, 50, 18, 19, 20, 12, 21, 22, 23, 24, 51, 26, 27, 28, 28, 12, 29, 30, 31, 32, 52, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 59, 59, 62, 59, 63, 64, 63, 59, 65, 66, 67, 59, 59, 59, 12, 47, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 59, 62, 59, 63, 64, 59, 65, 66, 67, 59, 59, 59, 48, 13, 14, 13, 85, 16, 13, 14, 13, 287, 16, 13, 14, 13, 458, 71, 13, 14, 13, 86, 71, 29, 69, 74, 12, 74, 29, 69, 77, 12, 136, 29, 109, 110, 112, 113, 29, 12, 12, 14, 12, 12, 12, 79, 12, 12, 12, 12, 12, 12, 12, 12, 73, 12, 12, 12, 12, 12, 29, 12, 12, 12, 13, 14, 13, 13, 14, 13, 81, 90, 91, 96, 82, 78, 174, 93, 94, 143, 229, 92, 97, 137, 29, 83, 458, 29, 95, 12, 12, 79, 74, 145, 74, 274, 81, 99, 99, 99, 82, 458, 175, 280, 280, 229, 77, 211, 265, 83, 212, 212, 212, 12, 12, 12, 14, 12, 12, 12, 121, 12, 12, 12, 12, 12, 12, 12, 12, 73, 12, 12, 12, 12, 12, 29, 12, 12, 12, 99, 99, 99, 103, 103, 104, 104, 121, 458, 105, 105, 458, 78, 458, 266, 106, 106, 106, 106, 127, 458, 100, 458, 458, 107, 12, 12, 365, 458, 103, 103, 104, 104, 368, 129, 105, 105, 123, 124, 126, 106, 106, 125, 307, 458, 128, 100, 157, 107, 12, 79, 458, 365, 114, 87, 87, 133, 167, 368, 80, 129, 458, 123, 124, 79, 126, 125, 307, 458, 80, 80, 128, 116, 157, 117, 458, 134, 130, 118, 127, 133, 167, 131, 138, 119, 74, 119, 434, 139, 458, 99, 99, 99, 171, 161, 458, 80, 193, 116, 458, 117, 134, 143, 130, 118, 162, 458, 131, 79, 119, 79, 151, 458, 120, 458, 170, 145, 140, 171, 80, 161, 79, 193, 143, 210, 458, 141, 142, 216, 80, 80, 162, 116, 458, 117, 163, 151, 145, 118, 458, 165, 170, 164, 140, 119, 166, 119, 146, 147, 210, 141, 142, 148, 216, 158, 159, 80, 79, 116, 160, 117, 163, 189, 149, 118, 446, 165, 164, 79, 119, 166, 458, 223, 146, 147, 168, 169, 79, 148, 158, 159, 179, 442, 160, 143, 180, 189, 149, 143, 190, 191, 114, 214, 458, 192, 195, 223, 144, 145, 168, 169, 181, 145, 196, 458, 458, 198, 144, 144, 458, 153, 458, 154, 232, 190, 191, 155, 103, 214, 104, 192, 458, 156, 105, 156, 458, 77, 174, 213, 106, 182, 106, 198, 241, 144, 197, 153, 458, 154, 232, 222, 227, 155, 103, 446, 104, 442, 156, 143, 105, 251, 120, 213, 175, 106, 215, 226, 144, 241, 197, 458, 219, 145, 103, 222, 104, 227, 144, 144, 105, 153, 78, 154, 295, 251, 106, 155, 106, 458, 215, 434, 226, 156, 434, 156, 458, 79, 219, 228, 103, 265, 104, 256, 140, 144, 105, 153, 103, 154, 104, 106, 458, 155, 105, 143, 300, 220, 156, 185, 106, 458, 106, 230, 231, 228, 221, 186, 256, 145, 140, 458, 249, 418, 103, 185, 104, 185, 185, 303, 105, 458, 185, 220, 265, 106, 266, 230, 231, 185, 458, 221, 243, 185, 458, 185, 233, 185, 249, 187, 188, 143, 304, 185, 185, 303, 458, 253, 185, 418, 103, 458, 104, 458, 185, 145, 105, 185, 243, 185, 233, 185, 106, 187, 106, 103, 234, 104, 304, 266, 138, 105, 74, 253, 143, 139, 103, 106, 104, 106, 143, 242, 105, 79, 200, 143, 201, 106, 145, 143, 202, 103, 234, 104, 145, 458, 203, 105, 203, 145, 458, 458, 106, 145, 140, 242, 235, 236, 458, 240, 200, 458, 201, 141, 142, 237, 202, 79, 239, 353, 353, 203, 238, 458, 246, 458, 458, 79, 79, 244, 140, 235, 236, 458, 79, 240, 250, 141, 142, 252, 245, 237, 254, 239, 77, 79, 247, 238, 458, 305, 246, 276, 306, 244, 179, 248, 272, 272, 180, 179, 250, 79, 255, 263, 252, 245, 275, 282, 254, 279, 458, 458, 247, 284, 181, 305, 458, 276, 306, 181, 248, 285, 212, 212, 212, 277, 255, 257, 289, 78, 275, 257, 282, 458, 278, 279, 212, 212, 212, 258, 458, 288, 458, 182, 458, 294, 174, 257, 264, 257, 257, 277, 458, 286, 257, 290, 458, 458, 458, 278, 458, 257, 291, 458, 301, 257, 288, 257, 292, 257, 294, 259, 260, 458, 79, 257, 257, 286, 143, 297, 257, 290, 308, 293, 298, 296, 257, 143, 291, 257, 301, 257, 145, 257, 292, 259, 179, 79, 458, 458, 267, 145, 458, 143, 268, 297, 458, 458, 293, 299, 298, 296, 269, 309, 143, 458, 181, 145, 143, 366, 268, 302, 268, 268, 318, 206, 206, 268, 145, 317, 402, 174, 145, 299, 268, 322, 326, 314, 268, 309, 268, 310, 268, 366, 270, 271, 321, 302, 268, 268, 318, 316, 458, 268, 317, 402, 143, 175, 358, 268, 322, 326, 268, 314, 268, 310, 268, 359, 270, 77, 145, 321, 200, 200, 201, 201, 316, 458, 202, 202, 311, 273, 273, 273, 203, 203, 203, 203, 327, 143, 423, 273, 273, 273, 273, 273, 273, 143, 200, 200, 201, 201, 323, 145, 202, 202, 311, 364, 458, 203, 203, 145, 327, 315, 78, 423, 458, 273, 273, 273, 273, 273, 273, 200, 200, 201, 201, 458, 323, 202, 202, 458, 458, 364, 143, 203, 203, 203, 203, 315, 458, 458, 458, 458, 458, 331, 458, 319, 145, 200, 200, 201, 201, 320, 324, 202, 202, 200, 312, 201, 203, 203, 325, 202, 328, 332, 458, 313, 143, 203, 331, 203, 458, 319, 333, 333, 329, 458, 330, 320, 324, 174, 145, 200, 312, 201, 79, 358, 325, 202, 328, 332, 313, 179, 203, 458, 359, 263, 400, 361, 329, 458, 330, 441, 79, 79, 357, 175, 334, 334, 334, 347, 179, 181, 77, 174, 180, 458, 334, 334, 334, 334, 334, 334, 400, 361, 185, 185, 441, 349, 357, 179, 181, 79, 348, 180, 179, 347, 79, 79, 180, 175, 264, 385, 334, 334, 334, 334, 334, 334, 179, 181, 345, 345, 335, 349, 181, 350, 336, 78, 348, 182, 458, 351, 352, 458, 337, 458, 458, 385, 181, 458, 458, 367, 336, 458, 336, 336, 403, 79, 182, 336, 355, 350, 458, 182, 143, 458, 336, 351, 352, 356, 336, 362, 336, 360, 336, 367, 338, 339, 145, 363, 336, 336, 403, 392, 283, 336, 355, 177, 378, 458, 177, 336, 458, 369, 336, 356, 336, 362, 336, 360, 338, 340, 143, 363, 143, 341, 143, 458, 143, 392, 458, 143, 377, 342, 378, 143, 145, 396, 145, 369, 145, 341, 145, 341, 341, 145, 143, 370, 341, 145, 380, 372, 373, 371, 143, 341, 375, 458, 377, 341, 145, 341, 396, 341, 379, 343, 344, 374, 145, 341, 341, 376, 458, 370, 341, 79, 380, 372, 373, 371, 341, 458, 375, 341, 143, 341, 384, 341, 379, 343, 179, 358, 374, 458, 180, 458, 458, 376, 145, 458, 359, 393, 404, 381, 458, 458, 346, 346, 346, 382, 181, 384, 401, 79, 79, 383, 346, 346, 346, 346, 346, 346, 265, 458, 257, 257, 386, 393, 404, 381, 387, 174, 458, 382, 390, 390, 401, 458, 394, 182, 395, 383, 346, 346, 346, 346, 346, 346, 185, 185, 185, 411, 386, 458, 387, 398, 143, 175, 185, 185, 185, 185, 185, 185, 394, 458, 395, 266, 458, 458, 145, 418, 399, 179, 179, 283, 411, 263, 263, 458, 79, 398, 397, 143, 185, 185, 185, 185, 185, 185, 257, 257, 257, 181, 181, 179, 399, 145, 194, 263, 257, 257, 257, 257, 257, 257, 143, 397, 177, 420, 434, 388, 388, 177, 424, 181, 405, 179, 458, 458, 145, 180, 264, 264, 143, 143, 257, 257, 257, 257, 257, 257, 406, 268, 268, 420, 458, 181, 145, 145, 424, 405, 143, 143, 264, 179, 458, 79, 458, 263, 458, 407, 458, 177, 415, 458, 145, 145, 406, 413, 458, 389, 389, 389, 409, 181, 182, 408, 426, 410, 416, 389, 389, 389, 389, 389, 389, 407, 415, 412, 436, 414, 417, 79, 425, 413, 458, 422, 409, 458, 458, 458, 426, 408, 264, 410, 416, 389, 389, 389, 389, 389, 389, 265, 412, 436, 417, 414, 421, 419, 425, 422, 431, 432, 439, 391, 391, 391, 435, 440, 265, 458, 143, 143, 458, 391, 391, 391, 391, 391, 391, 458, 341, 341, 421, 419, 145, 145, 431, 432, 439, 458, 458, 435, 458, 440, 458, 427, 266, 428, 458, 391, 391, 391, 391, 391, 391, 268, 268, 268, 179, 458, 437, 450, 263, 266, 433, 268, 268, 268, 268, 268, 268, 427, 143, 428, 336, 336, 143, 79, 181, 438, 442, 458, 445, 143, 437, 143, 145, 450, 433, 143, 145, 268, 268, 268, 268, 268, 268, 145, 224, 145, 429, 430, 449, 145, 438, 446, 445, 264, 336, 336, 336, 217, 447, 458, 443, 143, 444, 143, 336, 336, 336, 336, 336, 336, 434, 458, 429, 430, 449, 145, 434, 145, 458, 458, 446, 458, 434, 447, 458, 143, 443, 444, 453, 458, 336, 336, 336, 336, 336, 336, 341, 341, 341, 145, 448, 454, 458, 208, 458, 451, 341, 341, 341, 341, 341, 341, 452, 458, 453, 455, 458, 458, 456, 458, 207, 205, 204, 79, 194, 79, 448, 454, 177, 451, 132, 457, 341, 341, 341, 341, 341, 341, 452, 455, 458, 122, 135, 456, 132, 458, 122, 79, 111, 101, 88, 84, 75, 458, 458, 458, 457, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 68, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 70, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 72, 76, 76, 458, 458, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 76, 80, 458, 458, 80, 80, 80, 458, 458, 80, 80, 80, 80, 80, 458, 80, 87, 87, 458, 458, 458, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 87, 89, 89, 89, 458, 458, 89, 89, 89, 89, 89, 458, 89, 98, 458, 458, 458, 98, 98, 458, 458, 98, 98, 98, 98, 98, 458, 98, 102, 102, 458, 458, 458, 102, 102, 102, 102, 108, 108, 458, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 108, 115, 115, 458, 115, 115, 115, 458, 458, 115, 115, 115, 115, 115, 458, 115, 144, 458, 458, 144, 144, 144, 144, 458, 144, 144, 144, 144, 144, 458, 144, 150, 458, 458, 458, 150, 150, 458, 458, 150, 150, 150, 150, 150, 458, 150, 152, 152, 458, 152, 152, 152, 152, 458, 152, 152, 152, 152, 152, 458, 152, 172, 458, 458, 458, 458, 172, 172, 172, 172, 172, 172, 172, 458, 172, 172, 172, 172, 172, 172, 172, 173, 173, 458, 458, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, 176, 176, 458, 458, 176, 176, 176, 176, 176, 176, 176, 176, 458, 176, 176, 176, 176, 176, 176, 176, 178, 178, 458, 458, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 178, 183, 458, 458, 183, 183, 183, 458, 458, 183, 183, 183, 183, 183, 458, 183, 184, 458, 458, 458, 458, 458, 458, 458, 184, 184, 184, 184, 184, 458, 184, 87, 458, 87, 458, 458, 87, 458, 458, 458, 87, 87, 458, 458, 87, 87, 199, 199, 458, 458, 458, 199, 199, 199, 199, 206, 206, 458, 458, 458, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 206, 209, 458, 209, 209, 458, 458, 458, 209, 209, 209, 209, 218, 458, 218, 218, 458, 458, 458, 218, 218, 218, 218, 225, 458, 225, 225, 458, 458, 458, 225, 225, 225, 225, 261, 261, 458, 458, 261, 261, 261, 261, 261, 261, 261, 261, 458, 261, 261, 261, 261, 261, 261, 261, 262, 262, 458, 458, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 262, 181, 181, 458, 458, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 181, 281, 281, 458, 458, 458, 281, 281, 206, 458, 206, 458, 458, 206, 458, 458, 458, 206, 206, 458, 458, 206, 206, 87, 87, 458, 458, 458, 87, 87, 354, 354, 458, 458, 458, 354, 354, 206, 206, 458, 458, 458, 206, 206, 11, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458 } ; static yyconst flex_int16_t yy_chk[2268] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 19, 3, 4, 4, 4, 209, 4, 5, 5, 5, 209, 5, 6, 6, 6, 19, 6, 3, 3, 13, 3, 13, 4, 4, 16, 4, 48, 5, 30, 30, 32, 32, 6, 7, 7, 7, 7, 7, 7, 17, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 9, 9, 9, 10, 10, 10, 17, 22, 22, 24, 17, 16, 69, 23, 23, 52, 140, 22, 24, 48, 9, 17, 457, 10, 23, 7, 7, 189, 74, 52, 74, 189, 17, 99, 99, 99, 17, 36, 69, 196, 196, 140, 76, 122, 181, 17, 122, 122, 122, 7, 8, 8, 8, 8, 8, 8, 36, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 25, 25, 25, 27, 28, 27, 28, 36, 38, 27, 28, 42, 76, 39, 181, 27, 28, 27, 28, 41, 456, 25, 45, 64, 27, 8, 8, 304, 55, 27, 28, 27, 28, 307, 42, 27, 28, 38, 38, 39, 27, 28, 38, 232, 46, 41, 25, 55, 27, 8, 34, 43, 304, 34, 280, 280, 45, 64, 307, 34, 42, 67, 38, 38, 83, 39, 38, 232, 58, 34, 34, 41, 34, 55, 34, 455, 46, 43, 34, 60, 45, 64, 43, 49, 34, 49, 34, 452, 49, 66, 51, 51, 51, 67, 58, 121, 34, 83, 34, 126, 34, 46, 144, 43, 34, 60, 451, 43, 449, 34, 35, 51, 61, 35, 62, 66, 144, 49, 67, 35, 58, 79, 83, 50, 121, 57, 49, 49, 126, 35, 35, 60, 35, 131, 35, 61, 51, 50, 35, 65, 62, 66, 61, 49, 35, 62, 35, 50, 50, 121, 49, 49, 50, 126, 57, 57, 35, 81, 35, 57, 35, 61, 79, 50, 35, 446, 62, 61, 82, 35, 62, 124, 131, 50, 50, 65, 65, 100, 50, 57, 57, 71, 442, 57, 150, 71, 79, 50, 53, 81, 81, 53, 124, 123, 82, 88, 131, 53, 150, 65, 65, 71, 53, 88, 157, 130, 100, 53, 53, 134, 53, 166, 53, 142, 81, 81, 53, 102, 124, 102, 82, 125, 53, 102, 53, 133, 185, 173, 123, 102, 71, 102, 100, 157, 53, 88, 53, 128, 53, 142, 130, 134, 53, 102, 440, 102, 439, 53, 54, 102, 166, 54, 123, 173, 102, 125, 133, 54, 157, 88, 171, 128, 54, 103, 130, 103, 134, 54, 54, 103, 54, 185, 54, 218, 166, 103, 54, 103, 218, 125, 434, 133, 54, 425, 54, 129, 419, 128, 139, 103, 340, 103, 171, 139, 54, 103, 54, 104, 54, 104, 103, 164, 54, 104, 143, 225, 129, 54, 78, 104, 225, 104, 141, 141, 139, 129, 78, 171, 143, 139, 159, 164, 418, 104, 78, 104, 78, 78, 228, 104, 168, 78, 129, 341, 104, 340, 141, 141, 78, 413, 129, 159, 78, 411, 78, 143, 78, 164, 78, 78, 146, 229, 78, 78, 228, 158, 168, 78, 404, 105, 398, 105, 396, 78, 146, 105, 78, 159, 78, 143, 78, 105, 78, 105, 106, 146, 106, 229, 341, 138, 106, 138, 168, 147, 138, 105, 106, 105, 106, 151, 158, 105, 393, 107, 149, 107, 105, 147, 148, 107, 106, 146, 106, 151, 160, 107, 106, 107, 149, 162, 165, 106, 148, 138, 158, 147, 147, 167, 151, 107, 161, 107, 138, 138, 148, 107, 392, 149, 285, 285, 107, 148, 169, 162, 163, 170, 191, 190, 160, 138, 147, 147, 387, 198, 151, 165, 138, 138, 167, 161, 148, 169, 149, 186, 193, 163, 148, 380, 230, 162, 191, 231, 160, 178, 163, 186, 186, 178, 179, 165, 192, 170, 179, 167, 161, 190, 198, 169, 193, 210, 378, 163, 207, 178, 230, 216, 191, 231, 179, 163, 207, 211, 211, 211, 192, 170, 175, 212, 186, 190, 175, 198, 213, 192, 193, 212, 212, 212, 175, 363, 210, 214, 178, 226, 216, 175, 175, 179, 175, 175, 192, 215, 207, 175, 213, 360, 220, 356, 192, 219, 175, 214, 221, 226, 175, 210, 175, 214, 175, 216, 175, 175, 222, 352, 175, 175, 207, 233, 220, 175, 213, 233, 215, 221, 219, 175, 234, 214, 175, 226, 175, 233, 175, 214, 175, 182, 347, 241, 227, 182, 234, 242, 235, 182, 220, 245, 249, 215, 222, 221, 219, 182, 234, 238, 244, 182, 235, 240, 305, 182, 227, 182, 182, 242, 353, 353, 182, 238, 241, 366, 257, 240, 222, 182, 245, 249, 238, 182, 234, 182, 235, 182, 305, 182, 182, 244, 227, 182, 182, 242, 240, 250, 182, 241, 366, 236, 257, 358, 182, 245, 249, 182, 238, 182, 235, 182, 358, 182, 187, 236, 244, 199, 200, 199, 200, 240, 246, 199, 200, 236, 187, 187, 187, 199, 200, 199, 200, 250, 239, 400, 187, 187, 187, 187, 187, 187, 370, 199, 200, 199, 200, 246, 239, 199, 200, 236, 303, 327, 199, 200, 370, 250, 239, 187, 400, 255, 187, 187, 187, 187, 187, 187, 201, 202, 201, 202, 243, 246, 201, 202, 323, 247, 303, 237, 201, 202, 201, 202, 239, 253, 248, 254, 256, 252, 255, 319, 243, 237, 201, 202, 201, 202, 243, 247, 201, 202, 203, 237, 203, 201, 202, 248, 203, 252, 256, 318, 237, 376, 203, 255, 203, 293, 243, 258, 258, 253, 298, 254, 243, 247, 258, 376, 203, 237, 203, 275, 294, 248, 203, 252, 256, 237, 262, 203, 294, 294, 262, 364, 298, 253, 299, 254, 426, 277, 276, 293, 258, 259, 259, 259, 275, 267, 262, 272, 259, 267, 330, 259, 259, 259, 259, 259, 259, 364, 298, 272, 272, 426, 277, 293, 268, 267, 278, 276, 268, 269, 275, 279, 282, 269, 259, 262, 330, 259, 259, 259, 259, 259, 259, 264, 268, 269, 269, 264, 277, 269, 278, 264, 272, 276, 267, 288, 279, 282, 296, 264, 302, 292, 330, 264, 301, 297, 306, 264, 291, 264, 264, 367, 348, 268, 264, 288, 278, 290, 269, 309, 320, 264, 279, 282, 292, 264, 301, 264, 297, 264, 306, 264, 264, 309, 302, 264, 264, 367, 348, 284, 264, 288, 263, 320, 355, 261, 264, 317, 309, 264, 292, 264, 301, 264, 297, 264, 266, 310, 302, 311, 266, 312, 324, 313, 348, 321, 315, 317, 266, 320, 314, 310, 355, 311, 309, 312, 266, 313, 266, 266, 315, 316, 310, 266, 314, 324, 312, 313, 311, 406, 266, 315, 329, 317, 266, 316, 266, 355, 266, 321, 266, 266, 314, 406, 266, 266, 316, 326, 310, 266, 349, 324, 312, 313, 311, 266, 325, 315, 266, 407, 266, 329, 266, 321, 266, 270, 322, 314, 328, 270, 251, 332, 316, 407, 322, 322, 349, 368, 325, 331, 224, 270, 270, 270, 326, 270, 329, 365, 350, 351, 328, 270, 270, 270, 270, 270, 270, 342, 377, 333, 333, 331, 349, 368, 325, 332, 333, 361, 326, 342, 342, 365, 362, 350, 270, 351, 328, 270, 270, 270, 270, 270, 270, 273, 273, 273, 377, 331, 357, 332, 361, 428, 333, 273, 273, 273, 273, 273, 273, 350, 223, 351, 342, 217, 208, 428, 386, 362, 335, 336, 206, 377, 335, 336, 386, 395, 361, 357, 369, 273, 273, 273, 273, 273, 273, 334, 334, 334, 335, 336, 337, 362, 369, 195, 337, 334, 334, 334, 334, 334, 334, 371, 357, 180, 395, 416, 337, 337, 177, 401, 337, 369, 345, 416, 383, 371, 345, 335, 336, 374, 372, 334, 334, 334, 334, 334, 334, 371, 345, 345, 395, 381, 345, 374, 372, 401, 369, 373, 375, 337, 338, 385, 420, 384, 338, 379, 372, 399, 176, 383, 156, 373, 375, 371, 381, 382, 338, 338, 338, 374, 338, 345, 373, 403, 375, 384, 338, 338, 338, 338, 338, 338, 372, 383, 379, 420, 382, 385, 394, 402, 381, 397, 399, 374, 417, 412, 414, 403, 373, 338, 375, 384, 338, 338, 338, 338, 338, 338, 343, 379, 420, 385, 382, 397, 394, 402, 399, 412, 414, 423, 343, 343, 343, 417, 424, 390, 155, 405, 408, 421, 343, 343, 343, 343, 343, 343, 415, 390, 390, 397, 394, 405, 408, 412, 414, 423, 437, 154, 417, 153, 424, 431, 405, 343, 408, 422, 343, 343, 343, 343, 343, 343, 346, 346, 346, 388, 152, 421, 437, 388, 390, 415, 346, 346, 346, 346, 346, 346, 405, 410, 408, 388, 388, 409, 436, 388, 422, 427, 433, 431, 430, 421, 427, 410, 437, 415, 429, 409, 346, 346, 346, 346, 346, 346, 430, 132, 427, 409, 410, 436, 429, 422, 432, 431, 388, 389, 389, 389, 127, 433, 432, 429, 453, 430, 444, 389, 389, 389, 389, 389, 389, 435, 438, 409, 410, 436, 453, 448, 444, 435, 445, 443, 447, 441, 433, 448, 443, 429, 430, 444, 450, 389, 389, 389, 389, 389, 389, 391, 391, 391, 443, 435, 445, 454, 120, 119, 438, 391, 391, 391, 391, 391, 391, 441, 118, 444, 447, 117, 116, 450, 115, 114, 113, 109, 98, 87, 80, 435, 445, 70, 438, 63, 454, 391, 391, 391, 391, 391, 391, 441, 447, 59, 56, 47, 450, 44, 40, 37, 33, 31, 26, 20, 18, 15, 11, 0, 0, 454, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 459, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 460, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 461, 462, 462, 0, 0, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 462, 463, 0, 0, 463, 463, 463, 0, 0, 463, 463, 463, 463, 463, 0, 463, 464, 464, 0, 0, 0, 464, 464, 464, 464, 464, 464, 464, 464, 464, 464, 464, 464, 464, 464, 464, 465, 465, 465, 0, 0, 465, 465, 465, 465, 465, 0, 465, 466, 0, 0, 0, 466, 466, 0, 0, 466, 466, 466, 466, 466, 0, 466, 467, 467, 0, 0, 0, 467, 467, 467, 467, 468, 468, 0, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 468, 469, 469, 0, 469, 469, 469, 0, 0, 469, 469, 469, 469, 469, 0, 469, 470, 0, 0, 470, 470, 470, 470, 0, 470, 470, 470, 470, 470, 0, 470, 471, 0, 0, 0, 471, 471, 0, 0, 471, 471, 471, 471, 471, 0, 471, 472, 472, 0, 472, 472, 472, 472, 0, 472, 472, 472, 472, 472, 0, 472, 473, 0, 0, 0, 0, 473, 473, 473, 473, 473, 473, 473, 0, 473, 473, 473, 473, 473, 473, 473, 474, 474, 0, 0, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 474, 475, 475, 0, 0, 475, 475, 475, 475, 475, 475, 475, 475, 0, 475, 475, 475, 475, 475, 475, 475, 476, 476, 0, 0, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 476, 477, 0, 0, 477, 477, 477, 0, 0, 477, 477, 477, 477, 477, 0, 477, 478, 0, 0, 0, 0, 0, 0, 0, 478, 478, 478, 478, 478, 0, 478, 479, 0, 479, 0, 0, 479, 0, 0, 0, 479, 479, 0, 0, 479, 479, 480, 480, 0, 0, 0, 480, 480, 480, 480, 481, 481, 0, 0, 0, 481, 481, 481, 481, 481, 481, 481, 481, 481, 481, 481, 481, 481, 481, 481, 482, 0, 482, 482, 0, 0, 0, 482, 482, 482, 482, 483, 0, 483, 483, 0, 0, 0, 483, 483, 483, 483, 484, 0, 484, 484, 0, 0, 0, 484, 484, 484, 484, 485, 485, 0, 0, 485, 485, 485, 485, 485, 485, 485, 485, 0, 485, 485, 485, 485, 485, 485, 485, 486, 486, 0, 0, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 486, 487, 487, 0, 0, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 487, 488, 488, 0, 0, 0, 488, 488, 489, 0, 489, 0, 0, 489, 0, 0, 0, 489, 489, 0, 0, 489, 489, 490, 490, 0, 0, 0, 490, 490, 491, 491, 0, 0, 0, 491, 491, 492, 492, 0, 0, 0, 492, 492, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458, 458 } ; static yy_state_type yy_last_accepting_state; static char *yy_last_accepting_cpos; extern int yy_flex_debug; int yy_flex_debug = 0; /* The intent behind this definition is that it'll catch * any uses of REJECT which flex missed. */ #define REJECT reject_used_but_not_detected #define yymore() yymore_used_but_not_detected #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; #line 1 "scan.l" #line 8 "scan.l" /* lexical analyser for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "parse.h" #include "scan.h" #include "deps.h" #include "gperror.h" #include "directive.h" #include "evaluate.h" #include "macro.h" #include "coff.h" #define OPERATOR(x) return (yylval.i = (x)) /* YY_UNPUT not used, suppress the warning */ #define YY_NO_UNPUT enum identtype { defines, directives, globals, macros, opcodes, unknown_type }; enum identtype identify(char *); static void push_string(char *str); static int found_end(); static int found_eof(); static char *check_defines(char *symbol); static int quoted; /* Used to prevent #define expansion in ifdef and ifndef... */ int force_decimal; /* Used to force radix to decimal for some directives */ int force_ident; /* Used to force numbers to identifiers for processor names */ #line 1170 "scan.c" #define INITIAL 0 #define bquote 1 #define lnquote 2 #define define 3 #define definition 4 #ifndef YY_NO_UNISTD_H /* Special case for "unistd.h", since it is non-ANSI. We include it way * down here because we want the user's section 1 to have been scanned first. * The user has a chance to override it with an option. */ #include #endif #ifndef YY_EXTRA_TYPE #define YY_EXTRA_TYPE void * #endif static int yy_init_globals (void ); /* Accessor methods to globals. These are made visible to non-reentrant scanners for convenience. */ int yylex_destroy (void ); int yyget_debug (void ); void yyset_debug (int debug_flag ); YY_EXTRA_TYPE yyget_extra (void ); void yyset_extra (YY_EXTRA_TYPE user_defined ); FILE *yyget_in (void ); void yyset_in (FILE * in_str ); FILE *yyget_out (void ); void yyset_out (FILE * out_str ); int yyget_leng (void ); char *yyget_text (void ); int yyget_lineno (void ); void yyset_lineno (int line_number ); /* Macros after this point can all be overridden by user definitions in * section 1. */ #ifndef YY_SKIP_YYWRAP #ifdef __cplusplus extern "C" int yywrap (void ); #else extern int yywrap (void ); #endif #endif static void yyunput (int c,char *buf_ptr ); #ifndef yytext_ptr static void yy_flex_strncpy (char *,yyconst char *,int ); #endif #ifdef YY_NEED_STRLEN static int yy_flex_strlen (yyconst char * ); #endif #ifndef YY_NO_INPUT #ifdef __cplusplus static int yyinput (void ); #else static int input (void ); #endif #endif /* Amount of stuff to slurp up with each read. */ #ifndef YY_READ_BUF_SIZE #define YY_READ_BUF_SIZE 8192 #endif /* Copy whatever the last rule matched to the standard output. */ #ifndef ECHO /* This used to be an fputs(), but since the string might contain NUL's, * we now use fwrite(). */ #define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0) #endif /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, * is returned in "result". */ #ifndef YY_INPUT #define YY_INPUT(buf,result,max_size) \ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ size_t n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ if ( c == '\n' ) \ buf[n++] = (char) c; \ if ( c == EOF && ferror( yyin ) ) \ YY_FATAL_ERROR( "input in flex scanner failed" ); \ result = n; \ } \ else \ { \ errno=0; \ while ( (result = fread(buf, 1, max_size, yyin))==0 && ferror(yyin)) \ { \ if( errno != EINTR) \ { \ YY_FATAL_ERROR( "input in flex scanner failed" ); \ break; \ } \ errno=0; \ clearerr(yyin); \ } \ }\ \ #endif /* No semi-colon after return; correct usage is to write "yyterminate();" - * we don't want an extra ';' after the "return" because that will cause * some compilers to complain about unreachable statements. */ #ifndef yyterminate #define yyterminate() return YY_NULL #endif /* Number of entries by which start-condition stack grows. */ #ifndef YY_START_STACK_INCR #define YY_START_STACK_INCR 25 #endif /* Report a fatal error. */ #ifndef YY_FATAL_ERROR #define YY_FATAL_ERROR(msg) yy_fatal_error( msg ) #endif /* end tables serialization structures and prototypes */ /* Default declaration of generated scanner - a define so the user can * easily add parameters. */ #ifndef YY_DECL #define YY_DECL_IS_OURS 1 extern int yylex (void); #define YY_DECL int yylex (void) #endif /* !YY_DECL */ /* Code executed at the beginning of each rule, after yytext and yyleng * have been set up. */ #ifndef YY_USER_ACTION #define YY_USER_ACTION #endif /* Code executed at the end of each rule. */ #ifndef YY_BREAK #define YY_BREAK break; #endif #define YY_RULE_SETUP \ if ( yyleng > 0 ) \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = \ (yytext[yyleng - 1] == '\n'); \ YY_USER_ACTION /** The main scanner function which does all the work. */ YY_DECL { register yy_state_type yy_current_state; register char *yy_cp, *yy_bp; register int yy_act; #line 68 "scan.l" #line 1361 "scan.c" if ( !(yy_init) ) { (yy_init) = 1; #ifdef YY_USER_INIT YY_USER_INIT; #endif if ( ! (yy_start) ) (yy_start) = 1; /* first start state */ if ( ! yyin ) yyin = stdin; if ( ! yyout ) yyout = stdout; if ( ! YY_CURRENT_BUFFER ) { yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = yy_create_buffer(yyin,YY_BUF_SIZE ); } yy_load_buffer_state( ); } while ( 1 ) /* loops until end-of-file is reached */ { yy_cp = (yy_c_buf_p); /* Support of yytext. */ *yy_cp = (yy_hold_char); /* yy_bp points to the position in yy_ch_buf of the start of * the current run. */ yy_bp = yy_cp; yy_current_state = (yy_start); yy_current_state += YY_AT_BOL(); yy_match: do { register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)]; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 459 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; ++yy_cp; } while ( yy_base[yy_current_state] != 2192 ); yy_find_action: yy_act = yy_accept[yy_current_state]; if ( yy_act == 0 ) { /* have to back up */ yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); yy_act = yy_accept[yy_current_state]; } YY_DO_BEFORE_ACTION; do_action: /* This label is used only to access EOF actions. */ switch ( yy_act ) { /* beginning of action switch */ case 0: /* must back up */ /* undo the effects of YY_DO_BEFORE_ACTION */ *yy_cp = (yy_hold_char); yy_cp = (yy_last_accepting_cpos); yy_current_state = (yy_last_accepting_state); goto yy_find_action; case 1: YY_RULE_SETUP #line 69 "scan.l" { yylval.s = "include"; BEGIN(bquote); return IDENTIFIER; } YY_BREAK case YY_STATE_EOF(INITIAL): case YY_STATE_EOF(bquote): case YY_STATE_EOF(lnquote): case YY_STATE_EOF(define): case YY_STATE_EOF(definition): #line 74 "scan.l" { if (found_eof()) yyterminate(); } YY_BREAK case 2: YY_RULE_SETUP #line 78 "scan.l" { found_end(); yyterminate(); } YY_BREAK case 3: YY_RULE_SETUP #line 82 "scan.l" { BEGIN(lnquote); yylval.s = "title"; return IDENTIFIER; } YY_BREAK case 4: YY_RULE_SETUP #line 87 "scan.l" { BEGIN(lnquote); yylval.s = "subtitle"; return IDENTIFIER; } YY_BREAK case 5: YY_RULE_SETUP #line 92 "scan.l" { return CBLOCK; } YY_BREAK case 6: YY_RULE_SETUP #line 95 "scan.l" { yylval.s = strdup(yytext); return ERRORLEVEL; } YY_BREAK case 7: YY_RULE_SETUP #line 99 "scan.l" { return ENDC; } YY_BREAK case 8: YY_RULE_SETUP #line 102 "scan.l" { /* fill with ( ) as first argument */ yylval.i = FILL; return FILL; } YY_BREAK case 9: YY_RULE_SETUP #line 107 "scan.l" { BEGIN(define); yylval.s = "#define"; return DEFINE; } YY_BREAK case 10: YY_RULE_SETUP #line 112 "scan.l" { BEGIN(definition); yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 11: YY_RULE_SETUP #line 117 "scan.l" { yylval.i = UPPER; return UPPER; } YY_BREAK case 12: YY_RULE_SETUP #line 121 "scan.l" { yylval.i = HIGH; return HIGH; } YY_BREAK case 13: YY_RULE_SETUP #line 125 "scan.l" { yylval.i = LOW; return LOW; } YY_BREAK case 14: YY_RULE_SETUP #line 129 "scan.l" { yylval.s = strdup(yytext); return LIST; } YY_BREAK case 15: YY_RULE_SETUP #line 133 "scan.l" { yylval.s = strdup(yytext); return PROCESSOR; } YY_BREAK case 16: YY_RULE_SETUP #line 137 "scan.l" { /* #if and if can appear in column 1 */ yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 17: YY_RULE_SETUP #line 142 "scan.l" { /* #else and else can appear in column 1 */ yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 18: YY_RULE_SETUP #line 147 "scan.l" { /* #endif and endif can appear in column 1 */ yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 19: YY_RULE_SETUP #line 152 "scan.l" { /* #ifdef and ifdef can appear in column 1 */ quoted = 1; yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 20: YY_RULE_SETUP #line 158 "scan.l" { /* #ifndef and ifndef can appear in column 1 */ quoted = 1; yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 21: YY_RULE_SETUP #line 164 "scan.l" { /* #undefine can appear in column 1 */ quoted = 1; yylval.s = strdup(yytext); return IDENTIFIER; } YY_BREAK case 22: YY_RULE_SETUP #line 170 "scan.l" { yylval.s = strdup(yytext); return DEBUG_LINE; } YY_BREAK case 23: YY_RULE_SETUP #line 174 "scan.l" { char *symbol; yytext[strlen(yytext) - 3] = '\0'; symbol = check_defines(yytext); if (symbol) { yylval.s = strdup(symbol); } else { yylval.s = strdup(yytext); } return VARLAB_BEGIN; } YY_BREAK case 24: YY_RULE_SETUP #line 187 "scan.l" { int has_collon = 0; struct symbol *sym; struct macro_head *h; char *subst; if (yytext[strlen(yytext) - 1] == ':') { yytext[strlen(yytext) - 1] = '\0'; has_collon = 1; } yylval.s = strdup(yytext); switch(identify(yytext)) { case defines: sym = get_symbol(state.stTopDefines, yytext); subst = get_symbol_annotation(sym); push_string(subst); break; case directives: gpwarning(GPW_DIR_COLUMN_ONE, NULL); if (has_collon) gperror(GPE_BADCHAR, "Illegal character (:)"); return IDENTIFIER; break; case macros: if(asm_enabled()) { /* make sure macro definition on second pass is ignored */ sym = get_symbol(state.stMacros, yytext); h = get_symbol_annotation(sym); if (h->line_number == state.src->line_number) { return LABEL; } else { gpwarning(GPW_MACRO_COLUMN_ONE, NULL); if (has_collon) gperror(GPE_BADCHAR, "Illegal character (:)"); return IDENTIFIER; } } else { /* if assembly is not enabled don't issue warnings about macro calls in column 1, they could be an alternate definition */ return LABEL; } break; case opcodes: gpwarning(GPW_OP_COLUMN_ONE, NULL); if (has_collon) gperror(GPE_BADCHAR, "Illegal character (:)"); return IDENTIFIER; break; case unknown_type: return LABEL; default: return LABEL; } } YY_BREAK case 25: YY_RULE_SETUP #line 244 "scan.l" { char *symbol; yytext[strlen(yytext) - 3] = '\0'; symbol = check_defines(yytext); if (symbol) { yylval.s = strdup(symbol); } else { yylval.s = strdup(yytext); } return VAR_BEGIN; } YY_BREAK case 26: YY_RULE_SETUP #line 257 "scan.l" { char *symbol; symbol = check_defines(yytext+1); if (symbol) { yylval.s = strdup(symbol); } else { yylval.s = strdup(yytext+1); } return VAR_END; } YY_BREAK case 27: YY_RULE_SETUP #line 268 "scan.l" { char *symbol; symbol = check_defines(yytext); if (symbol) { char buffer[BUFSIZ]; /* Make the substitution with a leading space, so it won't be a label */ sprintf(buffer, " %s", symbol); push_string(buffer); } else { yylval.s = strdup(yytext); return IDENTIFIER; } } YY_BREAK case 28: YY_RULE_SETUP #line 284 "scan.l" { yylval.i = stringtolong(yytext + 2, 16); return NUMBER; } YY_BREAK case 29: YY_RULE_SETUP #line 288 "scan.l" { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else if (state.radix == 16) { yylval.i = stringtolong(yytext, 16); return NUMBER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 2); return NUMBER; } } YY_BREAK case 30: YY_RULE_SETUP #line 301 "scan.l" { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 2); return NUMBER; } YY_BREAK case 31: YY_RULE_SETUP #line 306 "scan.l" { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 8); return NUMBER; } } YY_BREAK case 32: YY_RULE_SETUP #line 316 "scan.l" { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 8); return NUMBER; } YY_BREAK case 33: YY_RULE_SETUP #line 321 "scan.l" { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else if (state.radix == 16) { yylval.i = stringtolong(yytext, 16); return NUMBER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 10); return NUMBER; } } YY_BREAK case 34: YY_RULE_SETUP #line 334 "scan.l" { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 10); return NUMBER; } YY_BREAK case 35: YY_RULE_SETUP #line 339 "scan.l" { yylval.i = stringtolong(yytext + 1, 10); return NUMBER; } YY_BREAK case 36: YY_RULE_SETUP #line 343 "scan.l" { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 16); return NUMBER; } } YY_BREAK case 37: YY_RULE_SETUP #line 353 "scan.l" { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 16); return NUMBER; } YY_BREAK case 38: YY_RULE_SETUP #line 358 "scan.l" { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else if (force_decimal) { yylval.i = stringtolong(yytext, 10); return NUMBER; } else { yylval.i = stringtolong(yytext, state.radix); return NUMBER; } } YY_BREAK case 39: YY_RULE_SETUP #line 370 "scan.l" { char *pc = &yytext[yyleng - 1]; if ((yyleng > 1) && (*pc == '"')) *pc = '\0'; else gpwarning(GPW_MISSING_QUOTE, NULL); yylval.s = strdup(yytext + 1); BEGIN(INITIAL); return STRING; } YY_BREAK case 40: YY_RULE_SETUP #line 380 "scan.l" { char *pc = convert_escape_chars(yytext + 1, &yylval.i); assert(pc == &yytext[yyleng - 1]); return NUMBER; } YY_BREAK case 41: YY_RULE_SETUP #line 385 "scan.l" { yylval.i = yytext[2]; return NUMBER; } YY_BREAK case 42: YY_RULE_SETUP #line 389 "scan.l" { yytext[yyleng - 1] = '\0'; yylval.s = strdup(&yytext[1]); BEGIN(INITIAL); return STRING; } YY_BREAK case 43: YY_RULE_SETUP #line 395 "scan.l" { /* unquoted (special-case) string */ yylval.s = strdup(yytext); BEGIN(INITIAL); return STRING; } YY_BREAK case 44: YY_RULE_SETUP #line 401 "scan.l" { /* if valid, must match with length >= unquoted token below */ yytext[yyleng - 1] = '\0'; yylval.s = strdup(&yytext[1]); BEGIN(INITIAL); return STRING; } YY_BREAK case 45: YY_RULE_SETUP #line 408 "scan.l" { /* full-line (special-case) string */ /* must begin and end with non-whitespace */ yylval.s = strdup(yytext); BEGIN(INITIAL); return STRING; } YY_BREAK case 46: YY_RULE_SETUP #line 415 "scan.l" OPERATOR(LSH); YY_BREAK case 47: YY_RULE_SETUP #line 416 "scan.l" OPERATOR(RSH); YY_BREAK case 48: YY_RULE_SETUP #line 417 "scan.l" OPERATOR(GREATER_EQUAL); YY_BREAK case 49: YY_RULE_SETUP #line 418 "scan.l" OPERATOR(LESS_EQUAL); YY_BREAK case 50: YY_RULE_SETUP #line 419 "scan.l" OPERATOR(EQUAL); YY_BREAK case 51: YY_RULE_SETUP #line 420 "scan.l" OPERATOR(NOT_EQUAL); YY_BREAK case 52: YY_RULE_SETUP #line 421 "scan.l" OPERATOR(LOGICAL_AND); YY_BREAK case 53: YY_RULE_SETUP #line 422 "scan.l" OPERATOR(LOGICAL_OR); YY_BREAK case 54: YY_RULE_SETUP #line 424 "scan.l" OPERATOR(ASSIGN_PLUS); YY_BREAK case 55: YY_RULE_SETUP #line 425 "scan.l" OPERATOR(ASSIGN_MINUS); YY_BREAK case 56: YY_RULE_SETUP #line 426 "scan.l" OPERATOR(ASSIGN_MULTIPLY); YY_BREAK case 57: YY_RULE_SETUP #line 427 "scan.l" OPERATOR(ASSIGN_DIVIDE); YY_BREAK case 58: YY_RULE_SETUP #line 428 "scan.l" OPERATOR(ASSIGN_MODULUS); YY_BREAK case 59: YY_RULE_SETUP #line 429 "scan.l" OPERATOR(ASSIGN_LSH); YY_BREAK case 60: YY_RULE_SETUP #line 430 "scan.l" OPERATOR(ASSIGN_RSH); YY_BREAK case 61: YY_RULE_SETUP #line 431 "scan.l" OPERATOR(ASSIGN_AND); YY_BREAK case 62: YY_RULE_SETUP #line 432 "scan.l" OPERATOR(ASSIGN_OR); YY_BREAK case 63: YY_RULE_SETUP #line 433 "scan.l" OPERATOR(ASSIGN_XOR); YY_BREAK case 64: YY_RULE_SETUP #line 435 "scan.l" OPERATOR(INCREMENT); YY_BREAK case 65: YY_RULE_SETUP #line 436 "scan.l" OPERATOR(DECREMENT); YY_BREAK case 66: YY_RULE_SETUP #line 438 "scan.l" OPERATOR(TBL_POST_INC); YY_BREAK case 67: YY_RULE_SETUP #line 439 "scan.l" OPERATOR(TBL_POST_DEC); YY_BREAK case 68: YY_RULE_SETUP #line 440 "scan.l" OPERATOR(TBL_PRE_INC); YY_BREAK case 69: YY_RULE_SETUP #line 442 "scan.l" YY_BREAK case 70: /* rule 70 can match eol */ YY_RULE_SETUP #line 443 "scan.l" { quoted = 0; force_decimal = 0; force_ident = 0; BEGIN(INITIAL); /* no multiline states yet */ return yytext[0]; } YY_BREAK case 71: YY_RULE_SETUP #line 450 "scan.l" { } YY_BREAK case 72: YY_RULE_SETUP #line 451 "scan.l" { yylval.i = yytext[0]; return yytext[0]; } YY_BREAK case 73: YY_RULE_SETUP #line 455 "scan.l" ECHO; YY_BREAK #line 2128 "scan.c" case YY_END_OF_BUFFER: { /* Amount of text matched not including the EOB char. */ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1; /* Undo the effects of YY_DO_BEFORE_ACTION. */ *yy_cp = (yy_hold_char); YY_RESTORE_YY_MORE_OFFSET if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW ) { /* We're scanning a new file or input source. It's * possible that this happened because the user * just pointed yyin at a new source and called * yylex(). If so, then we have to assure * consistency between YY_CURRENT_BUFFER and our * globals. Here is the right place to do so, because * this is the first action (other than possibly a * back-up) that will match for the new input source. */ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; YY_CURRENT_BUFFER_LVALUE->yy_input_file = yyin; YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL; } /* Note that here we test for yy_c_buf_p "<=" to the position * of the first EOB in the buffer, since yy_c_buf_p will * already have been incremented past the NUL character * (since all states make transitions on EOB to the * end-of-buffer state). Contrast this with the test * in input(). */ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) { /* This was really a NUL. */ yy_state_type yy_next_state; (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; yy_current_state = yy_get_previous_state( ); /* Okay, we're now positioned to make the NUL * transition. We couldn't have * yy_get_previous_state() go ahead and do it * for us because it doesn't know how to deal * with the possibility of jamming (and we don't * want to build jamming into it because then it * will run more slowly). */ yy_next_state = yy_try_NUL_trans( yy_current_state ); yy_bp = (yytext_ptr) + YY_MORE_ADJ; if ( yy_next_state ) { /* Consume the NUL. */ yy_cp = ++(yy_c_buf_p); yy_current_state = yy_next_state; goto yy_match; } else { yy_cp = (yy_c_buf_p); goto yy_find_action; } } else switch ( yy_get_next_buffer( ) ) { case EOB_ACT_END_OF_FILE: { (yy_did_buffer_switch_on_eof) = 0; if ( yywrap( ) ) { /* Note: because we've taken care in * yy_get_next_buffer() to have set up * yytext, we can now set up * yy_c_buf_p so that if some total * hoser (like flex itself) wants to * call the scanner after we return the * YY_NULL, it'll still work - another * YY_NULL will get returned. */ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ; yy_act = YY_STATE_EOF(YY_START); goto do_action; } else { if ( ! (yy_did_buffer_switch_on_eof) ) YY_NEW_FILE; } break; } case EOB_ACT_CONTINUE_SCAN: (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text; yy_current_state = yy_get_previous_state( ); yy_cp = (yy_c_buf_p); yy_bp = (yytext_ptr) + YY_MORE_ADJ; goto yy_match; case EOB_ACT_LAST_MATCH: (yy_c_buf_p) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)]; yy_current_state = yy_get_previous_state( ); yy_cp = (yy_c_buf_p); yy_bp = (yytext_ptr) + YY_MORE_ADJ; goto yy_find_action; } break; } default: YY_FATAL_ERROR( "fatal flex scanner internal error--no action found" ); } /* end of action switch */ } /* end of scanning one token */ } /* end of yylex */ /* yy_get_next_buffer - try to read in a new buffer * * Returns a code representing an action: * EOB_ACT_LAST_MATCH - * EOB_ACT_CONTINUE_SCAN - continue scanning from current position * EOB_ACT_END_OF_FILE - end of file */ static int yy_get_next_buffer (void) { register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; register char *source = (yytext_ptr); register int number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) YY_FATAL_ERROR( "fatal flex scanner internal error--end of buffer missed" ); if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 ) { /* Don't try to fill the buffer, so this is an EOF. */ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 ) { /* We matched a single character, the EOB, so * treat this as a final EOF. */ return EOB_ACT_END_OF_FILE; } else { /* We matched some text prior to the EOB, first * process it. */ return EOB_ACT_LAST_MATCH; } } /* Try to read more data. */ /* First move last chars to start of buffer. */ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1; for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING ) /* don't do the read, it's not guaranteed to return an EOF, * just force an EOF */ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0; else { int num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; while ( num_to_read <= 0 ) { /* Not enough room in the buffer - grow it. */ /* just a shorter name for the current buffer */ YY_BUFFER_STATE b = YY_CURRENT_BUFFER; int yy_c_buf_p_offset = (int) ((yy_c_buf_p) - b->yy_ch_buf); if ( b->yy_is_our_buffer ) { int new_size = b->yy_buf_size * 2; if ( new_size <= 0 ) b->yy_buf_size += b->yy_buf_size / 8; else b->yy_buf_size *= 2; b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ yyrealloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 ); } else /* Can't grow it, we don't own it. */ b->yy_ch_buf = 0; if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "fatal error - scanner input buffer overflow" ); (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset]; num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; } if ( num_to_read > YY_READ_BUF_SIZE ) num_to_read = YY_READ_BUF_SIZE; /* Read in more data. */ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]), (yy_n_chars), (size_t) num_to_read ); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } if ( (yy_n_chars) == 0 ) { if ( number_to_move == YY_MORE_ADJ ) { ret_val = EOB_ACT_END_OF_FILE; yyrestart(yyin ); } else { ret_val = EOB_ACT_LAST_MATCH; YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_EOF_PENDING; } } else ret_val = EOB_ACT_CONTINUE_SCAN; if ((yy_size_t) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ yy_size_t new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); } (yy_n_chars) += number_to_move; YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR; YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR; (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0]; return ret_val; } /* yy_get_previous_state - get the state just before the EOB char was reached */ static yy_state_type yy_get_previous_state (void) { register yy_state_type yy_current_state; register char *yy_cp; yy_current_state = (yy_start); yy_current_state += YY_AT_BOL(); for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp ) { register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1); if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 459 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; } return yy_current_state; } /* yy_try_NUL_trans - try to make a transition on the NUL character * * synopsis * next_state = yy_try_NUL_trans( current_state ); */ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state ) { register int yy_is_jam; register char *yy_cp = (yy_c_buf_p); register YY_CHAR yy_c = 1; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; (yy_last_accepting_cpos) = yy_cp; } while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; if ( yy_current_state >= 459 ) yy_c = yy_meta[(unsigned int) yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; yy_is_jam = (yy_current_state == 458); return yy_is_jam ? 0 : yy_current_state; } static void yyunput (int c, register char * yy_bp ) { register char *yy_cp; yy_cp = (yy_c_buf_p); /* undo effects of setting up yytext */ *yy_cp = (yy_hold_char); if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) { /* need to shift things up to make room */ /* +2 for EOB chars. */ register int number_to_move = (yy_n_chars) + 2; register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2]; register char *source = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]; while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) *--dest = *--source; yy_cp += (int) (dest - source); yy_bp += (int) (dest - source); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size; if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) YY_FATAL_ERROR( "flex scanner push-back overflow" ); } *--yy_cp = (char) c; (yytext_ptr) = yy_bp; (yy_hold_char) = *yy_cp; (yy_c_buf_p) = yy_cp; } #ifndef YY_NO_INPUT #ifdef __cplusplus static int yyinput (void) #else static int input (void) #endif { int c; *(yy_c_buf_p) = (yy_hold_char); if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR ) { /* yy_c_buf_p now points to the character we want to return. * If this occurs *before* the EOB characters, then it's a * valid NUL; if not, then we've hit the end of the buffer. */ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] ) /* This was really a NUL. */ *(yy_c_buf_p) = '\0'; else { /* need more input */ int offset = (yy_c_buf_p) - (yytext_ptr); ++(yy_c_buf_p); switch ( yy_get_next_buffer( ) ) { case EOB_ACT_LAST_MATCH: /* This happens because yy_g_n_b() * sees that we've accumulated a * token and flags that we need to * try matching the token before * proceeding. But for input(), * there's no matching to consider. * So convert the EOB_ACT_LAST_MATCH * to EOB_ACT_END_OF_FILE. */ /* Reset buffer status. */ yyrestart(yyin ); /*FALLTHROUGH*/ case EOB_ACT_END_OF_FILE: { if ( yywrap( ) ) return EOF; if ( ! (yy_did_buffer_switch_on_eof) ) YY_NEW_FILE; #ifdef __cplusplus return yyinput(); #else return input(); #endif } case EOB_ACT_CONTINUE_SCAN: (yy_c_buf_p) = (yytext_ptr) + offset; break; } } } c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */ *(yy_c_buf_p) = '\0'; /* preserve yytext */ (yy_hold_char) = *++(yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_at_bol = (c == '\n'); return c; } #endif /* ifndef YY_NO_INPUT */ /** Immediately switch to a different input stream. * @param input_file A readable stream. * * @note This function does not reset the start condition to @c INITIAL . */ void yyrestart (FILE * input_file ) { if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = yy_create_buffer(yyin,YY_BUF_SIZE ); } yy_init_buffer(YY_CURRENT_BUFFER,input_file ); yy_load_buffer_state( ); } /** Switch to a different input buffer. * @param new_buffer The new input buffer. * */ void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ) { /* TODO. We should be able to replace this entire function body * with * yypop_buffer_state(); * yypush_buffer_state(new_buffer); */ yyensure_buffer_stack (); if ( YY_CURRENT_BUFFER == new_buffer ) return; if ( YY_CURRENT_BUFFER ) { /* Flush out information for old buffer. */ *(yy_c_buf_p) = (yy_hold_char); YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } YY_CURRENT_BUFFER_LVALUE = new_buffer; yy_load_buffer_state( ); /* We don't actually know whether we did this switch during * EOF (yywrap()) processing, but the only time this flag * is looked at is after yywrap() is called, so it's safe * to go ahead and always set it. */ (yy_did_buffer_switch_on_eof) = 1; } static void yy_load_buffer_state (void) { (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars; (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos; yyin = YY_CURRENT_BUFFER_LVALUE->yy_input_file; (yy_hold_char) = *(yy_c_buf_p); } /** Allocate and initialize an input buffer state. * @param file A readable stream. * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE. * * @return the allocated buffer state. */ YY_BUFFER_STATE yy_create_buffer (FILE * file, int size ) { YY_BUFFER_STATE b; b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_buf_size = size; /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ b->yy_ch_buf = (char *) yyalloc(b->yy_buf_size + 2 ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_is_our_buffer = 1; yy_init_buffer(b,file ); return b; } /** Destroy the buffer. * @param b a buffer created with yy_create_buffer() * */ void yy_delete_buffer (YY_BUFFER_STATE b ) { if ( ! b ) return; if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; if ( b->yy_is_our_buffer ) yyfree((void *) b->yy_ch_buf ); yyfree((void *) b ); } #ifndef __cplusplus extern int isatty (int ); #endif /* __cplusplus */ /* Initializes or reinitializes a buffer. * This function is sometimes called more than once on the same buffer, * such as during a yyrestart() or at EOF. */ static void yy_init_buffer (YY_BUFFER_STATE b, FILE * file ) { int oerrno = errno; yy_flush_buffer(b ); b->yy_input_file = file; b->yy_fill_buffer = 1; /* If b is the current buffer, then yy_init_buffer was _probably_ * called from yyrestart() or through yy_get_next_buffer. * In that case, we don't want to reset the lineno or column. */ if (b != YY_CURRENT_BUFFER){ b->yy_bs_lineno = 1; b->yy_bs_column = 0; } b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0; errno = oerrno; } /** Discard all buffered characters. On the next scan, YY_INPUT will be called. * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER. * */ void yy_flush_buffer (YY_BUFFER_STATE b ) { if ( ! b ) return; b->yy_n_chars = 0; /* We always need two end-of-buffer characters. The first causes * a transition to the end-of-buffer state. The second causes * a jam in that state. */ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR; b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR; b->yy_buf_pos = &b->yy_ch_buf[0]; b->yy_at_bol = 1; b->yy_buffer_status = YY_BUFFER_NEW; if ( b == YY_CURRENT_BUFFER ) yy_load_buffer_state( ); } /** Pushes the new state onto the stack. The new state becomes * the current state. This function will allocate the stack * if necessary. * @param new_buffer The new state. * */ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) { if (new_buffer == NULL) return; yyensure_buffer_stack(); /* This block is copied from yy_switch_to_buffer. */ if ( YY_CURRENT_BUFFER ) { /* Flush out information for old buffer. */ *(yy_c_buf_p) = (yy_hold_char); YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } /* Only push if top exists. Otherwise, replace top. */ if (YY_CURRENT_BUFFER) (yy_buffer_stack_top)++; YY_CURRENT_BUFFER_LVALUE = new_buffer; /* copied from yy_switch_to_buffer. */ yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } /** Removes and deletes the top of the stack, if present. * The next element becomes the new top. * */ void yypop_buffer_state (void) { if (!YY_CURRENT_BUFFER) return; yy_delete_buffer(YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; if ((yy_buffer_stack_top) > 0) --(yy_buffer_stack_top); if (YY_CURRENT_BUFFER) { yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } } /* Allocates the stack if it does not exist. * Guarantees space for at least one push. */ static void yyensure_buffer_stack (void) { int num_to_alloc; if (!(yy_buffer_stack)) { /* First allocation is just for 2 elements, since we don't know if this * scanner will even need a stack. We use 2 instead of 1 to avoid an * immediate realloc on the next call. */ num_to_alloc = 1; (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc (num_to_alloc * sizeof(struct yy_buffer_state*) ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*)); (yy_buffer_stack_max) = num_to_alloc; (yy_buffer_stack_top) = 0; return; } if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){ /* Increase the buffer to prepare for a possible push. */ int grow_size = 8 /* arbitrary grow size */; num_to_alloc = (yy_buffer_stack_max) + grow_size; (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc ((yy_buffer_stack), num_to_alloc * sizeof(struct yy_buffer_state*) ); if ( ! (yy_buffer_stack) ) YY_FATAL_ERROR( "out of dynamic memory in yyensure_buffer_stack()" ); /* zero only the new slots.*/ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*)); (yy_buffer_stack_max) = num_to_alloc; } } /** Setup the input buffer state to scan directly from a user-specified character buffer. * @param base the character buffer * @param size the size in bytes of the character buffer * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) { YY_BUFFER_STATE b; if ( size < 2 || base[size-2] != YY_END_OF_BUFFER_CHAR || base[size-1] != YY_END_OF_BUFFER_CHAR ) /* They forgot to leave room for the EOB's. */ return 0; b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */ b->yy_buf_pos = b->yy_ch_buf = base; b->yy_is_our_buffer = 0; b->yy_input_file = 0; b->yy_n_chars = b->yy_buf_size; b->yy_is_interactive = 0; b->yy_at_bol = 1; b->yy_fill_buffer = 0; b->yy_buffer_status = YY_BUFFER_NEW; yy_switch_to_buffer(b ); return b; } /** Setup the input buffer state to scan a string. The next call to yylex() will * scan from a @e copy of @a str. * @param yystr a NUL-terminated string to scan * * @return the newly allocated buffer state object. * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ YY_BUFFER_STATE yy_scan_string (yyconst char * yystr ) { return yy_scan_bytes(yystr,strlen(yystr) ); } /** Setup the input buffer state to scan the given bytes. The next call to yylex() will * scan from a @e copy of @a bytes. * @param bytes the byte buffer to scan * @param len the number of bytes in the buffer pointed to by @a bytes. * * @return the newly allocated buffer state object. */ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) { YY_BUFFER_STATE b; char *buf; yy_size_t n; int i; /* Get memory for full buffer, including space for trailing EOB's. */ n = _yybytes_len + 2; buf = (char *) yyalloc(n ); if ( ! buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); for ( i = 0; i < _yybytes_len; ++i ) buf[i] = yybytes[i]; buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; b = yy_scan_buffer(buf,n ); if ( ! b ) YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" ); /* It's okay to grow etc. this buffer, and we should throw it * away when we're done. */ b->yy_is_our_buffer = 1; return b; } #ifndef YY_EXIT_FAILURE #define YY_EXIT_FAILURE 2 #endif static void yy_fatal_error (yyconst char* msg ) { (void) fprintf( stderr, "%s\n", msg ); exit( YY_EXIT_FAILURE ); } /* Redefine yyless() so it works in section 3 code. */ #undef yyless #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ (yy_hold_char) = *(yy_c_buf_p); \ *(yy_c_buf_p) = '\0'; \ yyleng = yyless_macro_arg; \ } \ while ( 0 ) /* Accessor methods (get/set functions) to struct members. */ /** Get the current line number. * */ int yyget_lineno (void) { return yylineno; } /** Get the input stream. * */ FILE *yyget_in (void) { return yyin; } /** Get the output stream. * */ FILE *yyget_out (void) { return yyout; } /** Get the length of the current token. * */ int yyget_leng (void) { return yyleng; } /** Get the current token. * */ char *yyget_text (void) { return yytext; } /** Set the current line number. * @param line_number * */ void yyset_lineno (int line_number ) { yylineno = line_number; } /** Set the input stream. This does not discard the current * input buffer. * @param in_str A readable stream. * * @see yy_switch_to_buffer */ void yyset_in (FILE * in_str ) { yyin = in_str ; } void yyset_out (FILE * out_str ) { yyout = out_str ; } int yyget_debug (void) { return yy_flex_debug; } void yyset_debug (int bdebug ) { yy_flex_debug = bdebug ; } static int yy_init_globals (void) { /* Initialization is the same as for the non-reentrant scanner. * This function is called from yylex_destroy(), so don't allocate here. */ (yy_buffer_stack) = 0; (yy_buffer_stack_top) = 0; (yy_buffer_stack_max) = 0; (yy_c_buf_p) = (char *) 0; (yy_init) = 0; (yy_start) = 0; /* Defined in main.c */ #ifdef YY_STDINIT yyin = stdin; yyout = stdout; #else yyin = (FILE *) 0; yyout = (FILE *) 0; #endif /* For future reference: Set errno on error, since we are called by * yylex_init() */ return 0; } /* yylex_destroy is for both reentrant and non-reentrant scanners. */ int yylex_destroy (void) { /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ yy_delete_buffer(YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; yypop_buffer_state(); } /* Destroy the stack itself. */ yyfree((yy_buffer_stack) ); (yy_buffer_stack) = NULL; /* Reset the globals. This is important in a non-reentrant scanner so the next time * yylex() is called, initialization will occur. */ yy_init_globals( ); return 0; } /* * Internal utility routines. */ #ifndef yytext_ptr static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) { register int i; for ( i = 0; i < n; ++i ) s1[i] = s2[i]; } #endif #ifdef YY_NEED_STRLEN static int yy_flex_strlen (yyconst char * s ) { register int n; for ( n = 0; s[n]; ++n ) ; return n; } #endif void *yyalloc (yy_size_t size ) { return (void *) malloc( size ); } void *yyrealloc (void * ptr, yy_size_t size ) { /* The cast to (char *) in the following accommodates both * implementations that use char* generic pointers, and those * that use void* generic pointers. It works with the latter * because both ANSI C and C++ allow castless assignment from * any pointer type to void*, and deal with argument conversions * as though doing an assignment. */ return (void *) realloc( (char *) ptr, size ); } void yyfree (void * ptr ) { free( (char *) ptr ); /* see yyrealloc() for (char *) cast */ } #define YYTABLES_NAME "yytables" #line 455 "scan.l" static void search_pathes(struct source_context *new, char *name) { char tryname[BUFSIZ]; int i; for(i = 0; i < state.path_num; i++) { strncpy(tryname, state.paths[i], sizeof(tryname)); strncat(tryname, COPY_CHAR, sizeof(tryname)); strncat(tryname, name, sizeof(tryname)); new->f = fopen(tryname, "rt"); if(new->f) { new->name = strdup(tryname); break; } } return; } void open_src(char *name, int isinclude) { extern FILE *yyin; struct source_context *new = malloc(sizeof(*new)); if (state.src) state.src->yybuf = YY_CURRENT_BUFFER; new->f = fopen(name, "rt"); if(new->f) new->name = strdup(name); else if(isinclude && (strchr(name, PATH_CHAR) == 0)) { /* If include file and no PATH_CHAR in name, try searching include path */ search_pathes(new, name); if (new->f == NULL) { /* We didn't find a match so check for lower case. This is mainly for Microchip examples and some includes in which filenames were written without regard to case */ char *lower_case_name = gp_lower_case(name); search_pathes(new, lower_case_name); free(lower_case_name); if (new->f != NULL) gpwarning(GPW_UNKNOWN, "found lower case match for include filename"); } } if(new->f) new->lst.f = fopen(new->name, "rt"); yyin = new->f; if (new->f == NULL) { if (state.src) { char complaint[BUFSIZ]; snprintf(complaint, sizeof(complaint), "Unable to open file \"%s\" - %s", name, strerror(errno)); state.pass = 2; /* Ensure error actually gets displayed */ gperror(GPE_UNKNOWN, complaint); } else { perror(name); } exit(1); } if (state.src) { yy_switch_to_buffer(yy_create_buffer(yyin,YY_BUF_SIZE)); } if (state.use_absolute_path) { new->name = gp_absolute_path(new->name); } new->type = src_file; new->h = NULL; new->line_number = 1; new->loop_number = 1; if (state.debug_info) { new->file_symbol = NULL; } else { new->file_symbol = coff_add_filesym(new->name, isinclude); } new->prev = state.src; state.src = new; state.src->fc = add_file(ft_src, new->name); deps_add(new->name); if (!isinclude) { /* it is the top level file so initialize the lexer */ quoted = 0; force_decimal = 0; force_ident = 0; } } void execute_macro(struct macro_head *h, int is_while) { struct source_context *new = malloc(sizeof(*new)); yy_size_t macro_src_size = 0; char *macro_src; assert(state.src != NULL); state.src->yybuf = YY_CURRENT_BUFFER; /* store the stack so it can be returned when the macro is complete */ state.src->astack = state.astack; macro_src = make_macro_buffer(h); macro_src_size = strlen(macro_src) + 2; /* create new source_context */ new->name = strdup(h->src_name); if (is_while) { new->type = src_while; } else { new->type = src_macro; } new->line_number = h->line_number + 1; new->loop_number = 1; new->file_symbol = h->file_symbol; new->f = NULL; new->h = h; new->lst.m = h->body; new->prev = state.src; state.src = new; state.src->fc = add_file(ft_src, new->name); /* scan list for fc */ yy_scan_buffer(macro_src,macro_src_size); } void repeat_while(void) { struct macro_head *h; yy_size_t macro_src_size = 0; char *macro_src; h = state.src->h; /* rebuild the macro buffer, because it may have been modified */ macro_src = make_macro_buffer(h); macro_src_size = strlen(macro_src) + 2; state.src->line_number = h->line_number + 1; state.src->loop_number++; state.src->lst.m = h->body; yy_delete_buffer(YY_CURRENT_BUFFER); yy_scan_buffer(macro_src,macro_src_size); } static void push_string(char *str) { struct source_context *new = malloc(sizeof(*new)); assert(state.src != NULL); state.src->yybuf = YY_CURRENT_BUFFER; new->name = strdup(state.src->name); new->type = src_substitution; new->line_number = state.src->line_number; new->loop_number = 1; new->file_symbol = state.src->file_symbol; new->f = NULL; new->h = NULL; new->lst.f = NULL; new->fc = add_file(ft_src, new->name); /* scan list for fc */ yy_scan_string(str); new->prev = state.src; state.src = new; } void close_file() { struct source_context *old; old = state.src; state.src = state.src->prev; if (old->type == src_file) { if (old->f != NULL) { fclose(old->f); } if (old->lst.f != NULL) fclose(old->lst.f); free(old->name); if (!state.debug_info) { coff_add_eofsym(); } } else if (old->type == src_macro) { state.stTop = pop_symbol_table(state.stTop); state.stTopDefines = pop_symbol_table(state.stTopDefines); if (state.src->astack != state.astack) { gperror(GPE_ILLEGAL_NESTING, NULL); } assert(state.stTop != NULL); assert(state.stTopDefines != NULL); free(old->name); } else if (old->type == src_while) { free(old->name); } free(old); } void execute_exitm() { struct amode *previous; struct amode *old; /* The macro is ended early, so return the stack to its previous state */ previous = state.src->prev->astack; while ((state.astack != NULL) && (state.astack != previous)) { old = state.astack; state.astack = state.astack->prev; free(old); } close_file(); if (state.src) { yy_delete_buffer(YY_CURRENT_BUFFER); yy_switch_to_buffer(state.src->yybuf); } } /* found end directive, close all files and stop the parser */ static int found_end() { if (state.while_head) { state.mac_body = NULL; state.mac_prev = NULL; state.while_head = NULL; gperror(GPE_EXPECTED, "Expected (ENDW)"); } if (state.astack != NULL) { struct amode *old; while (state.astack) { old = state.astack; state.astack = state.astack->prev; free(old); } gpwarning(GPW_EXPECTED, "Expected (ENDIF)"); } if (state.mac_prev != NULL) { gperror(GPW_EXPECTED,"Expected (ENDM)"); } /* close all open files */ while(state.src) { close_file(); } /* make sure the buffer is empty when pass 2 starts */ if (YY_CURRENT_BUFFER) yy_flush_buffer(YY_CURRENT_BUFFER); return 1; } static int found_eof() { int terminate = 0; if (state.src->type == src_while) { if (maybe_evaluate(state.src->h->parms)) { if (state.src->loop_number > 255) { gperror(GPE_BAD_WHILE_LOOP, NULL); } else { /* repeat the while loop */ repeat_while(); return 0; } } } close_file(); if (state.src) { /* Just an include file */ yy_delete_buffer(YY_CURRENT_BUFFER); yy_switch_to_buffer(state.src->yybuf); } else { gperror(GPE_ILLEGAL_COND, "Illegal condition (EOF encountered before END)"); terminate = found_end(); } return terminate; } enum identtype identify(char *text) { enum identtype type; struct symbol *sym; if ((sym = get_symbol(state.stTopDefines, text)) != NULL) { type = defines; } else if ((sym = get_symbol(state.stDirective, text)) != NULL) { type = directives; } else if ((sym = get_symbol(state.stBuiltin, text)) != NULL) { type = opcodes; } else if ((sym = get_symbol(state.stGlobal, text)) != NULL) { type = globals; } else if ((sym = get_symbol(state.stMacros, text)) != NULL) { type = macros; } else { type = unknown_type; } return type; } static char * check_defines(char *symbol) { struct symbol *sym; char *subst = NULL; /* If not quoted, check for #define substitution */ if (!quoted && (sym = get_symbol(state.stTopDefines, symbol)) != NULL) { subst = get_symbol_annotation(sym); if (subst == NULL) subst = ""; if (strcmp(symbol, subst) == 0) { /* check for a bad subsitution */ subst = NULL; } } return subst; } gputils-0.13.7/gpasm/cod.c0000644000175000017500000003437111156521302012236 00000000000000/* ".COD" file output for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "lst.h" #include "cod.h" static DirBlockInfo main_dir; static int cod_lst_line_number = 0; static int blocks = 0; extern int _16bit_core; static void init_DirBlock(DirBlockInfo *a_dir) { int i; /* create space for the directory block: */ gp_cod_create(&a_dir->dir, &blocks); a_dir->next_dir_block_info = NULL; /* The code blocks associated with this directory do not yet exist. */ for(i=0; icod_image_blocks[i].block = NULL; a_dir->cod_image_blocks[i].block_number = 0; } /* Initialize the directory block with known data. It'll be written * to the .cod file after everything else */ gp_cod_strncpy(&a_dir->dir.block[COD_DIR_SOURCE], state.srcfilename, COD_DIR_DATE - COD_DIR_SOURCE); gp_cod_date(&a_dir->dir.block[COD_DIR_DATE], COD_DIR_TIME - COD_DIR_DATE); gp_cod_time(&a_dir->dir.block[COD_DIR_TIME], COD_DIR_VERSION - COD_DIR_TIME); gp_cod_strncpy(&a_dir->dir.block[COD_DIR_VERSION], VERSION, COD_DIR_COMPILER - COD_DIR_VERSION); gp_cod_strncpy(&a_dir->dir.block[COD_DIR_COMPILER], "gpasm", COD_DIR_NOTICE - COD_DIR_COMPILER); gp_cod_strncpy(&a_dir->dir.block[COD_DIR_NOTICE], GPUTILS_COPYRIGHT_STRING, COD_DIR_SYMTAB - COD_DIR_NOTICE); /* The address is always two shorts or 4 bytes long */ gp_putl16(&a_dir->dir.block[COD_DIR_ADDRSIZE], 4); } /* * init_cod - initialize the cod file */ void cod_init(void) { if (state.codfile != named) { strncpy(state.codfilename, state.basefilename, sizeof(state.codfilename)); strncat(state.codfilename, ".cod", sizeof(state.codfilename)); } if (state.codfile == suppress) { state.cod.f = NULL; state.cod.enabled = false; unlink(state.codfilename); } else { state.cod.f = fopen(state.codfilename, "wb"); if (state.cod.f == NULL) { perror(state.codfilename); exit(1); } state.cod.enabled = true; } if(!state.cod.enabled) return; init_DirBlock(&main_dir); assert(main_dir.dir.block_number == 0); fseek(state.cod.f, COD_BLOCK_SIZE, SEEK_SET); } /* * write_cod_block - write a cod block to the .cod file and adjust * the cod block ptrs in the directory block. */ static void write_cod_block(DirBlockInfo *dbp, int block_ptr_start, int block_ptr_end, Block *bptr) { /* most of the cod blocks have a 'start' and 'end' pointer in the * directory block. These pointers are 16 bits wide. If the start * pointer is zero, then this is the first time a block of this * type has been written. In this case, the block pointer is written * to both the start and end pointer locations. */ if(!gp_getl16(&dbp->dir.block[block_ptr_start])) gp_putl16(&dbp->dir.block[block_ptr_start], bptr->block_number); gp_putl16(&dbp->dir.block[block_ptr_end], bptr->block_number); fseek(state.cod.f, COD_BLOCK_SIZE*bptr->block_number, SEEK_SET); fwrite(bptr->block, 1, COD_BLOCK_SIZE, state.cod.f); } /* * write_file_block - write a code block that contains a list of the * source files. */ static void write_file_block(void) { Block fb; #define FILES_PER_BLOCK COD_BLOCK_SIZE/COD_FILE_SIZE int id_number=0; struct file_context *fc; gp_cod_create(&fb, &blocks); if(!state.files) return; /* Find the head of the file list: */ fc = state.files; while(fc->prev && id_number++ < 1000) { fc = fc->prev; } if(id_number>=1000) { /* Too many files to handle in the .cod file */ assert(0); } id_number = 0; while(fc != NULL) { /* The file id is used to define the index at which the file * name is written within the file code block. (The id's are * sequentially assigned when the files are opened.) If there * are too many files, then gpasm will abort. note: .cod files * can handle larger file lists... */ gp_cod_strncpy(&fb.block[1 + COD_FILE_SIZE * id_number], fc->name, COD_FILE_SIZE-1); id_number++; if(id_number >= FILES_PER_BLOCK) { write_cod_block(&main_dir, COD_DIR_NAMTAB, COD_DIR_NAMTAB+2, &fb); id_number = 0; gp_cod_next(&fb, &blocks); } fc = fc->next; } if(id_number) write_cod_block(&main_dir, COD_DIR_NAMTAB, COD_DIR_NAMTAB+2, &fb); gp_cod_delete(&fb); } /* cod_lst_line - add a line of information that cross references the * the opcode's address, the source file, and the list file. */ void cod_lst_line(int line_type) { #define COD_LST_FIRST_LINE 7 unsigned char smod_flag = 0xff; static int first_time = 1; static Block lb={NULL,0}; int offset; if(!state.cod.enabled) return; switch(line_type) { case COD_FIRST_LST_LINE: case COD_NORMAL_LST_LINE: /* Don't start until after the source is open */ if(state.src == NULL) return; /* If we don't have a block yet then create one: */ if(lb.block == NULL) gp_cod_create(&lb, &blocks); /* Ignore the first few line numbers */ if(state.lst.line_number < COD_LST_FIRST_LINE) return; if(cod_lst_line_number >= COD_MAX_LINE_SYM) { write_cod_block(&main_dir, COD_DIR_LSTTAB, COD_DIR_LSTTAB+2, &lb); cod_lst_line_number = 0; gp_cod_next(&lb, &blocks); } assert(state.src->fc != NULL); offset = cod_lst_line_number++ * COD_LINE_SYM_SIZE; lb.block[offset + COD_LS_SFILE] = state.src->fc->id; if(state.cod.emitting != 0) smod_flag = 0x080; else smod_flag = 0x90; if(first_time != 0) { first_time = 0; smod_flag = 0xff; } lb.block[offset + COD_LS_SMOD] = smod_flag; /* Write the source file line number corresponding to the list file line number */ gp_putl16(&lb.block[offset + COD_LS_SLINE], state.src->line_number); /* Write the address of the opcode. */ gp_putl16(&lb.block[offset + COD_LS_SLOC], state.lst.line.was_org << _16bit_core); break; case COD_LAST_LST_LINE: if(lb.block) { write_cod_block(&main_dir, COD_DIR_LSTTAB, COD_DIR_LSTTAB+2, &lb); gp_cod_delete(&lb); } break; default: assert(0); } } /* cod_write_symbols - write the symbol table to the .cod file * * This routine will read the symbol table that gpasm has created * and convert it into a format suitable for .cod files. So far, only * three variable types are supported: address, register, and constants. * */ void cod_write_symbols(struct symbol **symbol_list, int num_symbols) { /* Each symbol is written as a dynamically sized structure to the * .cod file. Its format is like this: * position 0 length of the symbol name * positions 1 to len the symbol name * positions len+1 & len+2 Type of symbol (16 bits) * positions len+3 to len+7 Value of symbol */ #define COD_SYM_TYPE 1 /* type info is 1 byte after the length */ #define COD_SYM_VALUE 3 /* value info is 3 bytes after the length */ #define COD_SYM_EXTRA 7 /* symbol name length + 7 is total structure size */ #define MAX_SYM_LEN 255 /* Maximum length of a symbol name */ int i,offset,len,type; struct variable *var; char * s; Block sb; if(!state.cod.enabled) return; gp_cod_create(&sb, &blocks); offset = 0; for(i=0; i= COD_BLOCK_SIZE) { write_cod_block(&main_dir, COD_DIR_LSYMTAB, COD_DIR_LSYMTAB+2, &sb); gp_cod_next(&sb, &blocks); offset = 0; } gp_cod_strncpy(&sb.block[offset +1], s, MAX_SYM_LEN); switch(var->type) { case gvt_cblock: type = COD_ST_C_SHORT; /* byte craft's nomenclature for a memory byte. */ break; case gvt_address: type = COD_ST_ADDRESS; break; case gvt_org: type = COD_ST_ADDRESS; break; case gvt_constant: default: type = COD_ST_CONSTANT; } gp_putl16(&sb.block[offset+len+COD_SYM_TYPE], type); /* write 32 bits, big endian */ gp_putb32(&sb.block[offset+len+COD_SYM_VALUE], var->value); offset += (len+COD_SYM_EXTRA); } if(offset) write_cod_block(&main_dir, COD_DIR_LSYMTAB, COD_DIR_LSYMTAB+2, &sb); gp_cod_delete(&sb); } /* cod_emit_opcode - write one opcode to a cod_image_block */ static void cod_emit_opcode(int address,int opcode) { DirBlockInfo *dbi; int block_index; int found; int _64k_base; char * block; if(!state.cod.enabled) return; /* The code image blocks are handled in a different manner than the * other cod blocks. In theory, it's possible to emit opcodes in a * non-sequential manner. Furthermore, it's possible that there may * be gaps in the program memory. These cases are handled by an array * of code blocks. The lower 8 bits of the opcode's address form an * index into the code block, while bits 9-15 are an index into the * array of code blocks. The code image blocks are not written until * all of the opcodes have been emitted. */ block_index = (address >> (COD_BLOCK_BITS-1)) & (COD_CODE_IMAGE_BLOCKS -1); _64k_base = (address >> 15) & 0xffff; dbi = &main_dir; /* find the directory containing this 64k segment */ found = 0; do { if(gp_getl16(&dbi->dir.block[COD_DIR_HIGHADDR]) == _64k_base) found = 1; else { /* If the next directory block (in the linked list of directory blocks) is NULL, then this is the first time to encounter this _64k segment. So we need to create a new segment. */ if(dbi->next_dir_block_info == NULL) { dbi->next_dir_block_info = malloc(sizeof(DirBlockInfo)); init_DirBlock(dbi->next_dir_block_info); gp_putl16(&dbi->dir.block[COD_DIR_NEXTDIR], dbi->next_dir_block_info->dir.block_number); gp_putl16(&dbi->next_dir_block_info->dir.block[COD_DIR_HIGHADDR], _64k_base); found = 1; } dbi = dbi->next_dir_block_info; } } while(!found); if(dbi->cod_image_blocks[block_index].block == NULL) { gp_cod_create(&dbi->cod_image_blocks[block_index], &blocks); } block = dbi->cod_image_blocks[block_index].block; gp_putl16(&block[(address*2) & (COD_BLOCK_SIZE - 1)], opcode); } static void write_cod_range_block(unsigned int address, Block *rb) { DirBlockInfo *dbi = &main_dir; unsigned int _64k_base; _64k_base = (address >> 15) & 0xffff; do { if(gp_getl16(&dbi->dir.block[COD_DIR_HIGHADDR]) == (short)_64k_base) { write_cod_block(dbi, COD_DIR_MEMMAP, COD_DIR_MEMMAP+2, rb); return; } dbi = dbi->next_dir_block_info; } while(dbi); assert(0); } /* cod_write_code - write all of the assembled pic code to the .cod file */ static void cod_write_code(void) { MemBlock *m = state.i_memory; int mem_base; int i,offset; int start_address = 0, used_flag = 0; DirBlockInfo *dbi; Block rb = {NULL, 0}; offset = 0; while(m) { mem_base = m->base << I_MEM_BITS; for(i=mem_base; (i-mem_base) <= MAX_I_MEM; i++) { if ((i_memory_get(state.i_memory, i) & MEM_USED_MASK) && ((i-mem_base) < MAX_I_MEM)) { cod_emit_opcode(i, i_memory_get(state.i_memory, i) & 0xffff); if(used_flag == 0) { /* Save the start address in a range of opcodes */ start_address = i; used_flag = 1; if(rb.block == NULL) { gp_cod_create(&rb, &blocks); } } } else { /* No code at address i, but we need to check if this is the first empty address after a range of address. */ if(used_flag == 1) { /* We need to update dir map indicating a range of memory that is needed. This is done by writing the start and end address to the directory map. */ gp_putl16(&rb.block[offset], 2*start_address); gp_putl16(&rb.block[offset+2], 2*(i-1) + 1); offset += 4; if(offset>=COD_BLOCK_SIZE) { /* If there are a whole bunch of non-contiguous pieces of code then we'll get here. But most pic apps will only need one directory block (that will give you 64 ranges or non- contiguous chunks of pic code). */ write_cod_range_block(start_address, &rb); gp_cod_delete(&rb); offset = 0; } used_flag = 0; } } } if(offset) { write_cod_range_block(start_address, &rb); gp_cod_delete(&rb); offset = 0; used_flag = 0; } m = m->next; } /* write the code image blocks */ dbi = &main_dir; do { for(i=0; icod_image_blocks[i].block) { write_cod_block(dbi, COD_DIR_CODE+i*2, COD_DIR_CODE+i*2, &dbi->cod_image_blocks[i]); free(dbi->cod_image_blocks[i].block); } dbi = dbi->next_dir_block_info; } while(dbi); } static void write_directory(void) { DirBlockInfo *dbi; dbi = &main_dir; do { fseek(state.cod.f,COD_BLOCK_SIZE * dbi->dir.block_number, SEEK_SET); fwrite(dbi->dir.block, 1, COD_BLOCK_SIZE, state.cod.f); dbi = dbi->next_dir_block_info; } while(dbi); } void cod_close_file(void) { if(!state.cod.enabled) return; cod_lst_line(COD_LAST_LST_LINE); write_file_block(); cod_write_code(); gp_cod_strncpy(&main_dir.dir.block[COD_DIR_PROCESSOR], state.processor_info->names[2], COD_DIR_LSYMTAB - COD_DIR_PROCESSOR); write_directory(); fclose(state.cod.f); free(main_dir.dir.block); } gputils-0.13.7/gpasm/coff.c0000644000175000017500000004204511156521302012403 00000000000000/* Generate coff file Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "gperror.h" #include "coff.h" extern int _16bit_core; extern int packed_hi_lo; void coff_init(void) { if (state.objfile != named) { strncpy(state.objfilename, state.basefilename, sizeof(state.objfilename)); strncat(state.objfilename, ".o", sizeof(state.objfilename)); } if (state.objfile == suppress) { state.obj.enabled = false; unlink(state.objfilename); } else { if (state.processor_chosen == 0) { state.obj.enabled = false; } else { state.obj.object = gp_coffgen_init(); state.obj.object->filename = strdup(state.objfilename); state.obj.object->processor = state.processor; state.obj.object->class = state.device.class; state.obj.object->isnew = state.obj.newcoff; state.obj.enabled = true; } } return; } static void _update_section_symbol(gp_section_type *section) { /* write data to the auxiliary section symbol */ section->symbol->aux_list->_aux_symbol._aux_scn.length = section->size; section->symbol->aux_list->_aux_symbol._aux_scn.nreloc = section->num_reloc; section->symbol->aux_list->_aux_symbol._aux_scn.nlineno = section->num_lineno; } static void _update_section_size(void) { if (state.obj.section == NULL) return; if (state.obj.section->flags & STYP_TEXT) { /* the section is executable, so each word is two bytes */ state.obj.section->size = (state.org - (state.obj.section->address >> _16bit_core)) * 2; } else { /* the section is data, so each word is one byte */ state.obj.section->size = (state.org - state.obj.section->address); } _update_section_symbol(state.obj.section); return; } static void _update_reloc_ptr(void) { gp_section_type *section = state.obj.object->sections; gp_symbol_type *symbol; gp_reloc_type *reloc; while (section != NULL) { reloc = section->relocations; while (reloc != NULL) { symbol = state.obj.object->symbols; while (symbol != NULL) { if (reloc->symbol_number == symbol->number) { reloc->symbol = symbol; break; } symbol = symbol->next; } reloc = reloc->next; } section = section->next; } return; } /* Copy data from c_memory into the coff section. This kludge is for the 18xx devices. Their memory is byte addressable, but words are stored in gpasm memory. The user isn't guaranteed to put the config directives in accending order. They might also skip addresses. */ static void _copy_config(void) { gp_section_type *config_section = NULL; int i; int start; int stop; int word; gp_boolean found_break; if(!state.obj.enabled) return; if (state.found_config) { config_section = gp_coffgen_findsection(state.obj.object, state.obj.object->sections, ".config"); assert(config_section != NULL); start = state.processor_info->config_addrs[0] >> _16bit_core; stop = state.processor_info->config_addrs[1] >> _16bit_core; config_section->size = (stop - start + 1) * 2; for (i = start; i <= stop; i++) { word = i_memory_get(state.c_memory, i); if (word & MEM_USED_MASK) { i_memory_put(config_section->data, i, word); } else { /* fill undefined configuration registers with 0xff */ i_memory_put(config_section->data, i, 0xffff | MEM_USED_MASK); } } _update_section_symbol(config_section); } if (state.found_devid) { config_section = gp_coffgen_findsection(state.obj.object, state.obj.object->sections, ".devid"); assert(config_section != NULL); assert(_16bit_core); i = DEVID1>>1; word = i_memory_get(state.c_memory, i); assert(word && MEM_USED_MASK); i_memory_put(config_section->data, i, word); config_section->size = 2; _update_section_symbol(config_section); } if (state.found_idlocs) { config_section = gp_coffgen_findsection(state.obj.object, state.obj.object->sections, ".idlocs"); assert(config_section != NULL); if(_16bit_core) { config_section->size = 0; start = config_section->address >> 1; stop = IDLOC7 >> 1; found_break = false; for (i = start; i <= stop; i++) { printf("address = %x\n", i); word = i_memory_get(state.c_memory, i); if (word & MEM_USED_MASK) { if (found_break) { gperror(GPE_CONTIG_IDLOC, NULL); } i_memory_put(config_section->data, i, word); config_section->size += 2; } else { found_break = true; } } } else { start = state.device.id_location; stop = start + 4; for (i = start; i < stop; i++) { word = i_memory_get(state.c_memory, i); assert(word & MEM_USED_MASK); i_memory_put(config_section->data, i, word); } config_section->size = 8; } _update_section_symbol(config_section); } return; } void coff_close_file(void) { if(!state.obj.enabled) return; /* store data from the last section */ _update_section_size(); /* update relocation symbol pointers */ _update_reloc_ptr(); /* combine overlayed sections */ gp_cofflink_combine_overlay(state.obj.object, 1); _copy_config(); if (gp_write_coff(state.obj.object, (state.num.errors + gp_num_errors)) == 1) gperror(GPE_UNKNOWN, "system error while writing object file"); gp_coffgen_free(state.obj.object); } void coff_new_section(char *name, int addr, int flags) { gp_section_type *found = NULL; gp_symbol_type *new = NULL; gp_aux_type *new_aux; int section_addr; state.obj.symbol_num += 2; /* increment the section number */ state.obj.section_num++; /* store the flags so they are available for pass 1 */ state.obj.flags = flags; if (!state.obj.enabled) { state.org = addr; return; } assert(state.obj.object != NULL); /* store data from the last section */ _update_section_size(); found = gp_coffgen_findsection(state.obj.object, state.obj.object->sections, name); if (found != NULL) { if ((flags & STYP_OVERLAY) && (found->flags & STYP_OVERLAY)) { /* Overlayed sections can be duplicated. This allows multiple code sections in the same source file to share the same data memory. */ if ((flags != found->flags) || (addr != found->address)) { gperror(GPE_CONTIG_SECTION, NULL); return; } } else { gperror(GPE_CONTIG_SECTION, NULL); return; } } if ((flags & STYP_TEXT) && (_16bit_core)) section_addr = addr << 1; else section_addr = addr; state.obj.section = gp_coffgen_addsection(state.obj.object, name); state.obj.section->address = section_addr; state.obj.section->flags = flags; /* add a section symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(name); new->value = section_addr; new->section_number = state.obj.section_num; /* Modified later. */ new->section = state.obj.section; new->type = T_NULL; new->class = C_SECTION; state.obj.section->symbol = new; new_aux = gp_coffgen_addaux(state.obj.object, new); new_aux->type = AUX_SCN; state.i_memory = state.obj.section->data; state.org = addr; return; } /* All coff data is generated on the second pass. To support forward references to symbols in the relocation table, the symbol index is stored in relocations instead of a pointer to the symbol. Before the coff is written the symbol pointer is updated. */ void coff_reloc(int symbol, short offset, unsigned short type) { gp_reloc_type *new = NULL; int origin; if ((!state.obj.enabled) || (state.obj.section == NULL)) return; if ((state.obj.section->flags & STYP_TEXT) && (_16bit_core)) origin = state.org - (state.obj.section->address >> 1); else origin = state.org - state.obj.section->address; new = gp_coffgen_addreloc(state.obj.section); if (state.obj.section->flags & STYP_DATA) { new->address = origin; } else { new->address = origin * 2; /* byte address not word */ if (packed_hi_lo) { new->address++; } } new->symbol_number = symbol; new->offset = offset; new->type = type; return; } void coff_linenum(int emitted) { gp_linenum_type *new = NULL; int i; int origin; static gp_boolean show_bad_debug = true; gp_boolean emitted_pack_byte; /* note if we're doing code_pack work */ emitted_pack_byte = state.obj.section && state.obj.section->emitted_pack_byte; if ((!state.obj.enabled) || (state.obj.section == NULL)) return; if (state.obj.section->flags & STYP_ABS) { /* If the section is absolute, use the abolute address. */ origin = state.lst.line.was_org << _16bit_core; } else { /* use the relative address */ origin = (state.lst.line.was_org - state.obj.section->address) << _16bit_core; } if (state.debug_info && (state.obj.debug_file == NULL)) { if (show_bad_debug) { gperror(GPE_UNKNOWN, ".file directive required to generate debug info"); show_bad_debug = false; } return; } for (i = 0; i < emitted + (emitted_pack_byte ? 1 : 0); i++) { new = gp_coffgen_addlinenum(state.obj.section); if (state.debug_info) { new->symbol = state.obj.debug_file; new->line_number = state.obj.debug_line; } else { new->symbol = state.src->file_symbol; new->line_number = state.src->line_number; } /* when emitting non-word aligned data, we must modify * the origin address if our initial emission was a byte * in an existing word. subsequent bytes/words then need * to subtract 2, to compensate for the fact that the * origin was off by a whole word. */ new->address = origin + (i << _16bit_core) - (emitted_pack_byte ? (i == 0 ? 1 : 2) : 0); } return; } /* Add a symbol to the coff symbol table. The calling function must increment the global symbol number. */ gp_symbol_type * coff_add_sym(char *name, int value, enum gpasmValTypes type) { gp_symbol_type *new = NULL; char message[BUFSIZ]; int section_number = 0; int class = C_EXT; if(!state.obj.enabled) return NULL; switch (type) { case gvt_extern: section_number = N_UNDEF; class = C_EXT; break; case gvt_global: section_number = state.obj.section_num; class = C_EXT; break; case gvt_static: section_number = state.obj.section_num; class = C_STAT; break; case gvt_address: section_number = state.obj.section_num; class = C_LABEL; break; case gvt_debug: section_number = N_DEBUG; class = C_NULL; break; case gvt_absolute: section_number = N_ABS; class = C_NULL; break; default: return new; } new = gp_coffgen_findsymbol(state.obj.object, name); /* verify the duplicate extern has the same properties */ if ((new != NULL) && (type == gvt_extern)) { if ((new->type != class) || (new->section_number != section_number)) { snprintf(message, sizeof(message), "Duplicate label or redefining symbol that cannot be redefined. (%s)", name); gperror(GPE_UNKNOWN, message); } } if ((new != NULL) && (type != gvt_extern) && (type != gvt_debug)) { snprintf(message, sizeof(message), "Duplicate label or redefining symbol that cannot be redefined. (%s)", name); gperror(GPE_DUPLAB, message); } else { new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(name); new->value = value; new->section_number = section_number; new->section = state.obj.section; new->type = T_NULL; new->class = class; } return new; } /* add a file symbol to the coff symbol table */ gp_symbol_type * coff_add_filesym(char *name, int isinclude) { gp_symbol_type *new = NULL; gp_aux_type *new_aux; state.obj.symbol_num += 2; if(!state.obj.enabled) return NULL; /* add .file symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(".file"); new->value = 0; new->section_number = N_DEBUG; new->section = NULL; new->type = T_NULL; new->class = C_FILE; new_aux = gp_coffgen_addaux(state.obj.object, new); new_aux->type = AUX_FILE; new_aux->_aux_symbol._aux_file.filename = strdup(name); if (isinclude == 1) new_aux->_aux_symbol._aux_file.line_number = state.src->line_number - 1; else new_aux->_aux_symbol._aux_file.line_number = 0; return new; } /* add an eof symbol to the coff symbol table */ void coff_add_eofsym(void) { gp_symbol_type *new; state.obj.symbol_num++; if(!state.obj.enabled) return; /* add .eof symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(".eof"); new->value = 0; new->section_number = N_DEBUG; new->section = NULL; new->type = T_NULL; new->class = C_EOF; return; } /* add an eof symbol to the coff symbol table */ void coff_add_listsym(void) { gp_symbol_type *new; if (state.debug_info) return; state.obj.symbol_num++; if(!state.obj.enabled) return; /* add .eof symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(".list"); new->value = state.src->line_number; new->section_number = N_DEBUG; new->section = NULL; new->type = T_NULL; new->class = C_LIST; return; } void coff_add_nolistsym(void) { gp_symbol_type *new; if (state.debug_info) return; state.obj.symbol_num++; if(!state.obj.enabled) return; /* add .nolist symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(".nolist"); new->value = state.src->line_number; new->section_number = N_DEBUG; new->section = NULL; new->type = T_NULL; new->class = C_LIST; return; } /* add a direct symbol to the coff symbol table */ void coff_add_directsym(unsigned char command, char *string) { gp_symbol_type *new = NULL; gp_aux_type *new_aux; state.obj.symbol_num += 2; if(!state.obj.enabled) return; /* add .cod symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(".direct"); new->value = state.org << _16bit_core; new->section_number = state.obj.section_num; new->section = state.obj.section; new->type = T_NULL; new->class = C_NULL; new_aux = gp_coffgen_addaux(state.obj.object, new); new_aux->type = AUX_DIRECT; new_aux->_aux_symbol._aux_direct.command = command; new_aux->_aux_symbol._aux_direct.string = strdup(string); return; } /* add a cod symbol to the coff symbol table */ void coff_add_identsym(char *string) { gp_symbol_type *new = NULL; gp_aux_type *new_aux; state.obj.symbol_num += 2; if(!state.obj.enabled) return; /* add .cod symbol */ new = gp_coffgen_addsymbol(state.obj.object); new->name = strdup(".ident"); new->value = 0; new->section_number = N_DEBUG; new->section = NULL; new->type = T_NULL; new->class = C_NULL; new_aux = gp_coffgen_addaux(state.obj.object, new); new_aux->type = AUX_IDENT; new_aux->_aux_symbol._aux_ident.string = strdup(string); return; } /* If the symbol is local, generate a modified name for the coff symbol table. */ char * coff_local_name(char *name) { struct symbol *local; gp_symbol_type *symbol; char buffer[BUFSIZ]; int count = 1; if(!state.obj.enabled) return NULL; local = get_symbol(state.stGlobal, name); if (local == NULL) { /* It isn't in the stGlobal so it must be in stTop. It's local. */ while(1) { snprintf(buffer, sizeof(buffer), "_%d%s", count, name); symbol = gp_coffgen_findsymbol(state.obj.object, buffer); if (symbol == NULL) break; count++; } } else { strncpy(buffer, name, sizeof(buffer)); } return strdup(buffer); } gputils-0.13.7/gpasm/scan.l0000644000175000017500000005245511156521302012431 00000000000000%option noyywrap %x bquote %x lnquote %x define %x definition %{ /* lexical analyser for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "parse.h" #include "scan.h" #include "deps.h" #include "gperror.h" #include "directive.h" #include "evaluate.h" #include "macro.h" #include "coff.h" #define OPERATOR(x) return (yylval.i = (x)) /* YY_UNPUT not used, suppress the warning */ #define YY_NO_UNPUT enum identtype { defines, directives, globals, macros, opcodes, unknown_type }; enum identtype identify(char *); static void push_string(char *str); static int found_end(); static int found_eof(); static char *check_defines(char *symbol); static int quoted; /* Used to prevent #define expansion in ifdef and ifndef... */ int force_decimal; /* Used to force radix to decimal for some directives */ int force_ident; /* Used to force numbers to identifiers for processor names */ %} IDENT [.]?[a-z_\x80-\xff?@#][a-z_0-9\x80-\xff.?@#]* ESCCH \\([abfnrtv\\?'"]|0[0-7]{2}|x[0-9a-f]{2}) STR_QCHAR ([^"\r\n]|{ESCCH}) STR_BCHAR ([^>\r\n]|{ESCCH}) NUMCHAR [0-9a-z] %% ^[ \t]*#?include[ \t]+ { yylval.s = "include"; BEGIN(bquote); return IDENTIFIER; } <> { if (found_eof()) yyterminate(); } end { found_end(); yyterminate(); } ^[ \t]*title[ \t]+ { BEGIN(lnquote); yylval.s = "title"; return IDENTIFIER; } ^[ \t]*(subtitle?|stitle)[ \t]+ { BEGIN(lnquote); yylval.s = "subtitle"; return IDENTIFIER; } cblock { return CBLOCK; } errorlevel { yylval.s = strdup(yytext); return ERRORLEVEL; } endc { return ENDC; } fill[ \t]*\( { /* fill with ( ) as first argument */ yylval.i = FILL; return FILL; } ^[ \t]*#define[ \t]+ { BEGIN(define); yylval.s = "#define"; return DEFINE; } {IDENT} { BEGIN(definition); yylval.s = strdup(yytext); return IDENTIFIER; } upper { yylval.i = UPPER; return UPPER; } high { yylval.i = HIGH; return HIGH; } low { yylval.i = LOW; return LOW; } list { yylval.s = strdup(yytext); return LIST; } processor { yylval.s = strdup(yytext); return PROCESSOR; } #?if { /* #if and if can appear in column 1 */ yylval.s = strdup(yytext); return IDENTIFIER; } #?else { /* #else and else can appear in column 1 */ yylval.s = strdup(yytext); return IDENTIFIER; } #?endif { /* #endif and endif can appear in column 1 */ yylval.s = strdup(yytext); return IDENTIFIER; } #?ifdef { /* #ifdef and ifdef can appear in column 1 */ quoted = 1; yylval.s = strdup(yytext); return IDENTIFIER; } #?ifndef { /* #ifndef and ifndef can appear in column 1 */ quoted = 1; yylval.s = strdup(yytext); return IDENTIFIER; } #undefine { /* #undefine can appear in column 1 */ quoted = 1; yylval.s = strdup(yytext); return IDENTIFIER; } "."line { yylval.s = strdup(yytext); return DEBUG_LINE; } ^{IDENT}#v\( { char *symbol; yytext[strlen(yytext) - 3] = '\0'; symbol = check_defines(yytext); if (symbol) { yylval.s = strdup(symbol); } else { yylval.s = strdup(yytext); } return VARLAB_BEGIN; } ^{IDENT}:? { int has_collon = 0; struct symbol *sym; struct macro_head *h; char *subst; if (yytext[strlen(yytext) - 1] == ':') { yytext[strlen(yytext) - 1] = '\0'; has_collon = 1; } yylval.s = strdup(yytext); switch(identify(yytext)) { case defines: sym = get_symbol(state.stTopDefines, yytext); subst = get_symbol_annotation(sym); push_string(subst); break; case directives: gpwarning(GPW_DIR_COLUMN_ONE, NULL); if (has_collon) gperror(GPE_BADCHAR, "Illegal character (:)"); return IDENTIFIER; break; case macros: if(asm_enabled()) { /* make sure macro definition on second pass is ignored */ sym = get_symbol(state.stMacros, yytext); h = get_symbol_annotation(sym); if (h->line_number == state.src->line_number) { return LABEL; } else { gpwarning(GPW_MACRO_COLUMN_ONE, NULL); if (has_collon) gperror(GPE_BADCHAR, "Illegal character (:)"); return IDENTIFIER; } } else { /* if assembly is not enabled don't issue warnings about macro calls in column 1, they could be an alternate definition */ return LABEL; } break; case opcodes: gpwarning(GPW_OP_COLUMN_ONE, NULL); if (has_collon) gperror(GPE_BADCHAR, "Illegal character (:)"); return IDENTIFIER; break; case unknown_type: return LABEL; default: return LABEL; } } {IDENT}#v\( { char *symbol; yytext[strlen(yytext) - 3] = '\0'; symbol = check_defines(yytext); if (symbol) { yylval.s = strdup(symbol); } else { yylval.s = strdup(yytext); } return VAR_BEGIN; } \)[a-z_0-9\x80-\xff?.]+ { char *symbol; symbol = check_defines(yytext+1); if (symbol) { yylval.s = strdup(symbol); } else { yylval.s = strdup(yytext+1); } return VAR_END; } {IDENT} { char *symbol; symbol = check_defines(yytext); if (symbol) { char buffer[BUFSIZ]; /* Make the substitution with a leading space, so it won't be a label */ sprintf(buffer, " %s", symbol); push_string(buffer); } else { yylval.s = strdup(yytext); return IDENTIFIER; } } 0x{NUMCHAR}+ { yylval.i = stringtolong(yytext + 2, 16); return NUMBER; } {NUMCHAR}+b { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else if (state.radix == 16) { yylval.i = stringtolong(yytext, 16); return NUMBER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 2); return NUMBER; } } b'-?{NUMCHAR}+' { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 2); return NUMBER; } {NUMCHAR}+[oq] { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 8); return NUMBER; } } [oq]'-?{NUMCHAR}+' { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 8); return NUMBER; } {NUMCHAR}+d { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else if (state.radix == 16) { yylval.i = stringtolong(yytext, 16); return NUMBER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 10); return NUMBER; } } d'-?[0-9]+' { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 10); return NUMBER; } "."[0-9]+ { yylval.i = stringtolong(yytext + 1, 10); return NUMBER; } {NUMCHAR}+h { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext, 16); return NUMBER; } } h'-?{NUMCHAR}+' { yytext[yyleng - 1] = '\0'; yylval.i = stringtolong(yytext + 2, 16); return NUMBER; } {NUMCHAR}+ { if (force_ident) { yylval.s = strdup(yytext); return IDENTIFIER; } else if (force_decimal) { yylval.i = stringtolong(yytext, 10); return NUMBER; } else { yylval.i = stringtolong(yytext, state.radix); return NUMBER; } } \"{STR_QCHAR}*\"? { char *pc = &yytext[yyleng - 1]; if ((yyleng > 1) && (*pc == '"')) *pc = '\0'; else gpwarning(GPW_MISSING_QUOTE, NULL); yylval.s = strdup(yytext + 1); BEGIN(INITIAL); return STRING; } '{STR_QCHAR}' { char *pc = convert_escape_chars(yytext + 1, &yylval.i); assert(pc == &yytext[yyleng - 1]); return NUMBER; } A'{STR_QCHAR}' { yylval.i = yytext[2]; return NUMBER; } \<{STR_BCHAR}*\> { yytext[yyleng - 1] = '\0'; yylval.s = strdup(&yytext[1]); BEGIN(INITIAL); return STRING; } [^ \t<>";\r\n]+ { /* unquoted (special-case) string */ yylval.s = strdup(yytext); BEGIN(INITIAL); return STRING; } \"{STR_QCHAR}*\" { /* if valid, must match with length >= unquoted token below */ yytext[yyleng - 1] = '\0'; yylval.s = strdup(&yytext[1]); BEGIN(INITIAL); return STRING; } [^ \t;\r\n]+([ \t]+[^ \t;\r\n]+)* { /* full-line (special-case) string */ /* must begin and end with non-whitespace */ yylval.s = strdup(yytext); BEGIN(INITIAL); return STRING; } "<<" OPERATOR(LSH); ">>" OPERATOR(RSH); ">=" OPERATOR(GREATER_EQUAL); "<=" OPERATOR(LESS_EQUAL); "==" OPERATOR(EQUAL); "!=" OPERATOR(NOT_EQUAL); "&&" OPERATOR(LOGICAL_AND); "||" OPERATOR(LOGICAL_OR); "+=" OPERATOR(ASSIGN_PLUS); "-=" OPERATOR(ASSIGN_MINUS); "*=" OPERATOR(ASSIGN_MULTIPLY); "/=" OPERATOR(ASSIGN_DIVIDE); "%=" OPERATOR(ASSIGN_MODULUS); "<<=" OPERATOR(ASSIGN_LSH); ">>=" OPERATOR(ASSIGN_RSH); "&=" OPERATOR(ASSIGN_AND); "|=" OPERATOR(ASSIGN_OR); "^=" OPERATOR(ASSIGN_XOR); "++" OPERATOR(INCREMENT); "--" OPERATOR(DECREMENT); "*+" OPERATOR(TBL_POST_INC); "*-" OPERATOR(TBL_POST_DEC); "+*" OPERATOR(TBL_PRE_INC); [ \t\r]* <*>[\n] { quoted = 0; force_decimal = 0; force_ident = 0; BEGIN(INITIAL); /* no multiline states yet */ return yytext[0]; } <*>;.* { } <*>. { yylval.i = yytext[0]; return yytext[0]; } %% static void search_pathes(struct source_context *new, char *name) { char tryname[BUFSIZ]; int i; for(i = 0; i < state.path_num; i++) { strncpy(tryname, state.paths[i], sizeof(tryname)); strncat(tryname, COPY_CHAR, sizeof(tryname)); strncat(tryname, name, sizeof(tryname)); new->f = fopen(tryname, "rt"); if(new->f) { new->name = strdup(tryname); break; } } return; } void open_src(char *name, int isinclude) { extern FILE *yyin; struct source_context *new = malloc(sizeof(*new)); if (state.src) state.src->yybuf = YY_CURRENT_BUFFER; new->f = fopen(name, "rt"); if(new->f) new->name = strdup(name); else if(isinclude && (strchr(name, PATH_CHAR) == 0)) { /* If include file and no PATH_CHAR in name, try searching include path */ search_pathes(new, name); if (new->f == NULL) { /* We didn't find a match so check for lower case. This is mainly for Microchip examples and some includes in which filenames were written without regard to case */ char *lower_case_name = gp_lower_case(name); search_pathes(new, lower_case_name); free(lower_case_name); if (new->f != NULL) gpwarning(GPW_UNKNOWN, "found lower case match for include filename"); } } if(new->f) new->lst.f = fopen(new->name, "rt"); yyin = new->f; if (new->f == NULL) { if (state.src) { char complaint[BUFSIZ]; snprintf(complaint, sizeof(complaint), "Unable to open file \"%s\" - %s", name, strerror(errno)); state.pass = 2; /* Ensure error actually gets displayed */ gperror(GPE_UNKNOWN, complaint); } else { perror(name); } exit(1); } if (state.src) { yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE)); } if (state.use_absolute_path) { new->name = gp_absolute_path(new->name); } new->type = src_file; new->h = NULL; new->line_number = 1; new->loop_number = 1; if (state.debug_info) { new->file_symbol = NULL; } else { new->file_symbol = coff_add_filesym(new->name, isinclude); } new->prev = state.src; state.src = new; state.src->fc = add_file(ft_src, new->name); deps_add(new->name); if (!isinclude) { /* it is the top level file so initialize the lexer */ quoted = 0; force_decimal = 0; force_ident = 0; } } void execute_macro(struct macro_head *h, int is_while) { struct source_context *new = malloc(sizeof(*new)); yy_size_t macro_src_size = 0; char *macro_src; assert(state.src != NULL); state.src->yybuf = YY_CURRENT_BUFFER; /* store the stack so it can be returned when the macro is complete */ state.src->astack = state.astack; macro_src = make_macro_buffer(h); macro_src_size = strlen(macro_src) + 2; /* create new source_context */ new->name = strdup(h->src_name); if (is_while) { new->type = src_while; } else { new->type = src_macro; } new->line_number = h->line_number + 1; new->loop_number = 1; new->file_symbol = h->file_symbol; new->f = NULL; new->h = h; new->lst.m = h->body; new->prev = state.src; state.src = new; state.src->fc = add_file(ft_src, new->name); /* scan list for fc */ yy_scan_buffer(macro_src, macro_src_size); } void repeat_while(void) { struct macro_head *h; yy_size_t macro_src_size = 0; char *macro_src; h = state.src->h; /* rebuild the macro buffer, because it may have been modified */ macro_src = make_macro_buffer(h); macro_src_size = strlen(macro_src) + 2; state.src->line_number = h->line_number + 1; state.src->loop_number++; state.src->lst.m = h->body; yy_delete_buffer(YY_CURRENT_BUFFER); yy_scan_buffer(macro_src, macro_src_size); } static void push_string(char *str) { struct source_context *new = malloc(sizeof(*new)); assert(state.src != NULL); state.src->yybuf = YY_CURRENT_BUFFER; new->name = strdup(state.src->name); new->type = src_substitution; new->line_number = state.src->line_number; new->loop_number = 1; new->file_symbol = state.src->file_symbol; new->f = NULL; new->h = NULL; new->lst.f = NULL; new->fc = add_file(ft_src, new->name); /* scan list for fc */ yy_scan_string(str); new->prev = state.src; state.src = new; } void close_file() { struct source_context *old; old = state.src; state.src = state.src->prev; if (old->type == src_file) { if (old->f != NULL) { fclose(old->f); } if (old->lst.f != NULL) fclose(old->lst.f); free(old->name); if (!state.debug_info) { coff_add_eofsym(); } } else if (old->type == src_macro) { state.stTop = pop_symbol_table(state.stTop); state.stTopDefines = pop_symbol_table(state.stTopDefines); if (state.src->astack != state.astack) { gperror(GPE_ILLEGAL_NESTING, NULL); } assert(state.stTop != NULL); assert(state.stTopDefines != NULL); free(old->name); } else if (old->type == src_while) { free(old->name); } free(old); } void execute_exitm() { struct amode *previous; struct amode *old; /* The macro is ended early, so return the stack to its previous state */ previous = state.src->prev->astack; while ((state.astack != NULL) && (state.astack != previous)) { old = state.astack; state.astack = state.astack->prev; free(old); } close_file(); if (state.src) { yy_delete_buffer(YY_CURRENT_BUFFER); yy_switch_to_buffer(state.src->yybuf); } } /* found end directive, close all files and stop the parser */ static int found_end() { if (state.while_head) { state.mac_body = NULL; state.mac_prev = NULL; state.while_head = NULL; gperror(GPE_EXPECTED, "Expected (ENDW)"); } if (state.astack != NULL) { struct amode *old; while (state.astack) { old = state.astack; state.astack = state.astack->prev; free(old); } gpwarning(GPW_EXPECTED, "Expected (ENDIF)"); } if (state.mac_prev != NULL) { gperror(GPW_EXPECTED,"Expected (ENDM)"); } /* close all open files */ while(state.src) { close_file(); } /* make sure the buffer is empty when pass 2 starts */ if (YY_CURRENT_BUFFER) yy_flush_buffer(YY_CURRENT_BUFFER); return 1; } static int found_eof() { int terminate = 0; if (state.src->type == src_while) { if (maybe_evaluate(state.src->h->parms)) { if (state.src->loop_number > 255) { gperror(GPE_BAD_WHILE_LOOP, NULL); } else { /* repeat the while loop */ repeat_while(); return 0; } } } close_file(); if (state.src) { /* Just an include file */ yy_delete_buffer(YY_CURRENT_BUFFER); yy_switch_to_buffer(state.src->yybuf); } else { gperror(GPE_ILLEGAL_COND, "Illegal condition (EOF encountered before END)"); terminate = found_end(); } return terminate; } enum identtype identify(char *text) { enum identtype type; struct symbol *sym; if ((sym = get_symbol(state.stTopDefines, text)) != NULL) { type = defines; } else if ((sym = get_symbol(state.stDirective, text)) != NULL) { type = directives; } else if ((sym = get_symbol(state.stBuiltin, text)) != NULL) { type = opcodes; } else if ((sym = get_symbol(state.stGlobal, text)) != NULL) { type = globals; } else if ((sym = get_symbol(state.stMacros, text)) != NULL) { type = macros; } else { type = unknown_type; } return type; } static char * check_defines(char *symbol) { struct symbol *sym; char *subst = NULL; /* If not quoted, check for #define substitution */ if (!quoted && (sym = get_symbol(state.stTopDefines, symbol)) != NULL) { subst = get_symbol_annotation(sym); if (subst == NULL) subst = ""; if (strcmp(symbol, subst) == 0) { /* check for a bad subsitution */ subst = NULL; } } return subst; } gputils-0.13.7/gpasm/macro.c0000644000175000017500000001752111156313231012570 00000000000000/* Implements macros Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "directive.h" #include "evaluate.h" #include "gperror.h" #include "macro.h" #include "parse.h" #define BUFFER_SIZE 520 static char arg_buffer[BUFFER_SIZE]; static int arg_index; static void cat_string(char *string) { char *ptr; int length; ptr = &arg_buffer[arg_index]; length = strlen(string); if (arg_index + length + 1 < BUFFER_SIZE) { strcpy(ptr, string); arg_index += length; } else { gperror(GPE_UNKNOWN, "macro argument exceeds buffer size"); } } static void cat_symbol(int op) { switch (op) { case '+': cat_string("+"); break; case '-': cat_string("-"); break; case '*': cat_string("*"); break; case '/': cat_string("/"); break; case '%': cat_string("%"); break; case '&': cat_string("&"); break; case '|': cat_string("|"); break; case '^': cat_string("^"); break; case LSH: cat_string("<<"); break; case RSH: cat_string(">>"); break; case '<': cat_string("<"); break; case '>': cat_string(">"); break; case '!': cat_string("!"); break; case '~': cat_string("~"); break; case EQUAL: cat_string("=="); break; case NOT_EQUAL: cat_string("!="); break; case GREATER_EQUAL: cat_string(">="); break; case LESS_EQUAL: cat_string("<="); break; case LOGICAL_AND: cat_string("&&"); break; case LOGICAL_OR: cat_string("||"); break; case '=': cat_string("="); break; case UPPER: cat_string("UPPER"); break; case HIGH: cat_string("HIGH"); break; case LOW: cat_string("LOW"); break; case INCREMENT: cat_string("++"); break; case DECREMENT: cat_string("--"); break; default: assert(0); } } /* Must convert the parm to a plain string, this will allow substitutions of labels and strings. This is a kludge. It would be better to store a copy of the raw string in the parse node. */ static void node_to_string(struct pnode *p) { char constant_buffer[64]; switch(p->tag) { case constant: if (p->value.constant < 0) { snprintf(constant_buffer, sizeof(constant_buffer), "-%#x", -p->value.constant); } else { snprintf(constant_buffer, sizeof(constant_buffer), "%#x", p->value.constant); } cat_string(constant_buffer); break; case symbol: cat_string(p->value.symbol); break; case unop: cat_string("("); cat_symbol(p->value.unop.op); cat_string(" "); node_to_string(p->value.unop.p0); cat_string(")"); break; case binop: if (p->value.binop.op == CONCAT) { cat_string(evaluate_concatenation(p)); } else { cat_string("("); node_to_string(p->value.binop.p0); cat_symbol(p->value.binop.op); node_to_string(p->value.binop.p1); cat_string(")"); } break; case string: cat_string("\""); cat_string(p->value.string); cat_string("\""); break; case list: default: assert(0); } return; } /* Create a new defines table and place the macro parms in it. */ void setup_macro(struct macro_head *h, int arity, struct pnode *parms) { if (enforce_arity(arity, list_length(h->parms))) { /* push table for the marco parms */ state.stTopDefines = push_symbol_table(state.stTopDefines, state.case_insensitive); /* Now add the macro's declared parameter list to the new defines table. */ if (arity > 0) { struct pnode *pFrom, *pFromH; struct pnode *pTo, *pToH; struct symbol *sym; pTo = parms; for (pFrom = h->parms; pFrom; pFrom = TAIL(pFrom)) { pToH = HEAD(pTo); pFromH = HEAD(pFrom); assert(pFromH->tag == symbol); arg_index = 0; arg_buffer[0] = '\0'; node_to_string(pToH); sym = add_symbol(state.stTopDefines, pFromH->value.symbol); annotate_symbol(sym, strdup(arg_buffer)); pTo = TAIL(pTo); } } state.next_state = state_macro; state.next_buffer.macro = h; state.lst.line.linetype = none; } } /* Copy the macro body to a buffer. */ void copy_macro_body(struct macro_body *b, char *buffer, size_t sizeof_buffer) { while (b) { if (b->src_line != NULL) { strncat(buffer, b->src_line, sizeof_buffer); strncat(buffer, "\n", sizeof_buffer); } b = b->next; } return; } /* Create a buffer for parser from the macro definition. */ char * make_macro_buffer(struct macro_head *h) { struct macro_body *b; unsigned int macro_src_size = 0; char *macro_src; /* determine the length of the macro body */ b = h->body; while (b) { if (b->src_line != NULL) macro_src_size += strlen(b->src_line) + 1; /* add one for \n */ b = b->next; } macro_src_size += 2; /* flex requires two extra chars at the end */ /* Allocate memory for the new buffer. yy_delete_buffer frees it */ macro_src = (char *)calloc(sizeof(char), macro_src_size); if (macro_src) { /* build the string to be scanned */ copy_macro_body(h->body, macro_src, macro_src_size); } return macro_src; } /* The symbol table is pushed at each macro call. This makes local symbols possible. Each symbol table is created once on pass 1. On pass two the old symbol table is reloaded so forward references to the local symbols are possible */ struct macro_table { struct symbol_table *table; int line_number; /* sanity check, better not change */ struct macro_table *next; }; static struct macro_table * macro_table_list = NULL; static void add_macro_table(struct symbol_table *table) { struct macro_table *new; new = (struct macro_table *)malloc(sizeof(*new)); new->table = table; new->line_number = state.src->line_number; new->next = NULL; if (macro_table_list == NULL) { macro_table_list = new; } else { struct macro_table *list = macro_table_list; /* find the end of the list */ while(list->next != NULL) { list = list->next; } list->next = new; } return; } struct symbol_table * push_macro_symbol_table(struct symbol_table *table) { struct symbol_table *new = NULL; if (state.pass == 1) { new = push_symbol_table(table, state.case_insensitive); add_macro_table(new); } else if (macro_table_list->line_number != state.src->line_number) { /* The user must have conditionally assembled a macro using a forward reference to a label. This is a very bad practice. It means that a macro wasn't executed on the first pass, but it was on the second. Probably errors will be generated. Forward references to local symbols probably won't be correct. */ new = push_symbol_table(table, state.case_insensitive); gpwarning(GPW_UNKNOWN, "macro not executed on pass 1"); } else { assert(macro_table_list != NULL); new = macro_table_list->table; new->prev = table; macro_table_list = macro_table_list->next; /* setup for next macro */ } return new; } gputils-0.13.7/gpasm/libgpasm.h0000644000175000017500000000162011156313231013263 00000000000000/* gpasm library Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __LIBGPASM_H__ #define __LIBGPASM_H__ void process_args( int argc, char *argv[]); void init(void); int assemble(void); #endif gputils-0.13.7/gpasm/Makefile.in0000644000175000017500000004012411156521302013363 00000000000000# Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ srcdir = @srcdir@ top_srcdir = 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installcheck-am installdirs \ maintainer-clean maintainer-clean-generic mostlyclean \ mostlyclean-compile mostlyclean-generic pdf pdf-am ps ps-am \ tags uninstall uninstall-am uninstall-binPROGRAMS \ uninstall-info-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: gputils-0.13.7/gpasm/parse.h0000644000175000017500000000775611156521335012625 00000000000000/* A Bison parser, made by GNU Bison 2.3. */ /* Skeleton interface for Bison's Yacc-like parsers in C Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ /* As a special exception, you may create a larger work that contains part or all of the Bison parser skeleton and distribute that work under terms of your choice, so long as that work isn't itself a parser generator using the skeleton or a modified version thereof as a parser skeleton. Alternatively, if you modify or redistribute the parser skeleton itself, you may (at your option) remove this special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ /* Tokens. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE /* Put the tokens into the symbol table, so that GDB and other debuggers know about them. */ enum yytokentype { LABEL = 258, IDENTIFIER = 259, CBLOCK = 260, DEBUG_LINE = 261, ENDC = 262, ERRORLEVEL = 263, FILL = 264, LIST = 265, NUMBER = 266, PROCESSOR = 267, STRING = 268, DEFINE = 269, UPPER = 270, HIGH = 271, LOW = 272, LSH = 273, RSH = 274, GREATER_EQUAL = 275, LESS_EQUAL = 276, EQUAL = 277, NOT_EQUAL = 278, LOGICAL_AND = 279, LOGICAL_OR = 280, ASSIGN_PLUS = 281, ASSIGN_MINUS = 282, ASSIGN_MULTIPLY = 283, ASSIGN_DIVIDE = 284, ASSIGN_MODULUS = 285, ASSIGN_LSH = 286, ASSIGN_RSH = 287, ASSIGN_AND = 288, ASSIGN_OR = 289, ASSIGN_XOR = 290, INCREMENT = 291, DECREMENT = 292, TBL_NO_CHANGE = 293, TBL_POST_INC = 294, TBL_POST_DEC = 295, TBL_PRE_INC = 296, CONCAT = 297, VAR = 298, VARLAB_BEGIN = 299, VAR_BEGIN = 300, VAR_END = 301 }; #endif /* Tokens. */ #define LABEL 258 #define IDENTIFIER 259 #define CBLOCK 260 #define DEBUG_LINE 261 #define ENDC 262 #define ERRORLEVEL 263 #define FILL 264 #define LIST 265 #define NUMBER 266 #define PROCESSOR 267 #define STRING 268 #define DEFINE 269 #define UPPER 270 #define HIGH 271 #define LOW 272 #define LSH 273 #define RSH 274 #define GREATER_EQUAL 275 #define LESS_EQUAL 276 #define EQUAL 277 #define NOT_EQUAL 278 #define LOGICAL_AND 279 #define LOGICAL_OR 280 #define ASSIGN_PLUS 281 #define ASSIGN_MINUS 282 #define ASSIGN_MULTIPLY 283 #define ASSIGN_DIVIDE 284 #define ASSIGN_MODULUS 285 #define ASSIGN_LSH 286 #define ASSIGN_RSH 287 #define ASSIGN_AND 288 #define ASSIGN_OR 289 #define ASSIGN_XOR 290 #define INCREMENT 291 #define DECREMENT 292 #define TBL_NO_CHANGE 293 #define TBL_POST_INC 294 #define TBL_POST_DEC 295 #define TBL_PRE_INC 296 #define CONCAT 297 #define VAR 298 #define VARLAB_BEGIN 299 #define VAR_BEGIN 300 #define VAR_END 301 #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED typedef union YYSTYPE #line 208 "parse.y" { gpasmVal i; char *s; struct pnode *p; } /* Line 1489 of yacc.c. */ #line 147 "parse.h" YYSTYPE; # define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 # define YYSTYPE_IS_TRIVIAL 1 #endif extern YYSTYPE yylval; gputils-0.13.7/gpasm/evaluate.c0000644000175000017500000003557311156313231013304 00000000000000/* evaluates variables Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "evaluate.h" #include "directive.h" #include "gperror.h" #include "parse.h" #include "coff.h" extern int _16bit_core; int enforce_arity(int arity, int must_be) { if (arity == must_be) return 1; else { if (arity < must_be) { gperror(GPE_MISSING_ARGU, NULL); } else { gperror(GPE_TOO_MANY_ARGU, NULL); } return 0; } } int enforce_simple(struct pnode *p) { if (p->tag == symbol) { return 1; } else { gperror(GPE_ILLEGAL_ARGU, NULL); return 0; } } int list_length(struct pnode *L) { if (L == NULL) { return 0; } else { return 1 + list_length(TAIL(L)); } } int can_evaluate_concatenation(struct pnode *p) { char buf[BUFSIZ]; switch (p->tag) { case constant: return 1; case offset: return can_evaluate_concatenation(p->value.offset); case symbol: return 1; case unop: return can_evaluate_concatenation(p->value.unop.p0); case binop: return can_evaluate_concatenation(p->value.binop.p0) && can_evaluate_concatenation(p->value.binop.p1); case string: snprintf(buf, sizeof(buf), "Illegal argument (%s).", p->value.string); gperror(GPE_ILLEGAL_ARGU, buf); return 0; default: assert(0); } return 0; } char *evaluate_concatenation(struct pnode *p) { switch (p->tag) { case symbol: return p->value.symbol; case binop: assert(p->value.binop.op == CONCAT); { char *s[2], *new; size_t sizeof_new; s[0] = evaluate_concatenation(p->value.binop.p0); s[1] = evaluate_concatenation(p->value.binop.p1); sizeof_new =strlen(s[0]) + 1 + strlen(s[1]) + 1; new = malloc(sizeof_new); if (new) { strncpy(new, s[0], sizeof_new); strncat(new, s[1], sizeof_new); } return new; } case unop: assert(p->value.unop.op == VAR); { char buf[80]; snprintf(buf, sizeof(buf), "%d", maybe_evaluate(p->value.unop.p0)); return (strdup(buf)); } default: assert(0); } return NULL; } /* Attempt to evaluate concatenation 'p'. Return its value if * successful, otherwise generate an error message and return NULL. */ char *maybe_evaluate_concat(struct pnode *p) { char *r = NULL; if (((p->tag == unop) && (p->value.unop.op != VAR)) || ((p->tag == binop) && (p->value.binop.op != CONCAT))) { gperror(GPE_ILLEGAL_ARGU, NULL); } else if (p && can_evaluate_concatenation(p)) { r = evaluate_concatenation(p); } return r; } int can_evaluate(struct pnode *p) { char buf[BUFSIZ]; if ((p->tag == binop) && (p->value.binop.op == CONCAT)) { return can_evaluate_concatenation(p); } switch (p->tag) { case constant: return 1; case offset: if (state.extended_pic16e == false) { gperror(GPE_BADCHAR, "Illegal character ([)"); } return can_evaluate(p->value.offset); case symbol: { struct symbol *s; /* '$' means current org, which we can always evaluate */ if (strcmp(p->value.symbol, "$") == 0) { return 1; } else { struct variable *var = NULL; /* Otherwise look it up */ s = get_symbol(state.stTop, p->value.symbol); if (s == NULL) { snprintf(buf, sizeof(buf), "Symbol not previously defined (%s).", p->value.symbol); gperror(GPE_NOSYM, buf); } else { var = get_symbol_annotation(s); if (var == NULL) { snprintf(buf, sizeof(buf), "Symbol not assigned a value (%s).", p->value.symbol); gpwarning(GPW_UNKNOWN, buf); } } return ((s != NULL) && (var != NULL)); } } case unop: return can_evaluate(p->value.unop.p0); case binop: return can_evaluate(p->value.binop.p0) && can_evaluate(p->value.binop.p1); case string: snprintf(buf, sizeof(buf), "Illegal argument (%s).", p->value.string); gperror(GPE_ILLEGAL_ARGU, buf); return 0; default: assert(0); } return 0; } gpasmVal evaluate(struct pnode *p) { struct variable *var; gpasmVal p0, p1; if (((p->tag == binop) && (p->value.binop.op == CONCAT)) || ((p->tag == unop) && (p->value.unop.op == VAR))) { char *string = evaluate_concatenation(p); struct symbol *s; s = get_symbol(state.stTop, string); if (s == NULL) { char buf[BUFSIZ]; snprintf(buf, sizeof(buf), "Symbol not previously defined (%s).", string); gperror(GPE_NOSYM, buf); return 0; } else { var = get_symbol_annotation(s); assert(var != NULL); return var->value; } } switch (p->tag) { case constant: return p->value.constant; case offset: return evaluate(p->value.offset); case symbol: { struct symbol *s; if (strcmp(p->value.symbol, "$") == 0) { return state.org << _16bit_core; } else { s = get_symbol(state.stTop, p->value.symbol); var = get_symbol_annotation(s); assert(var != NULL); return var->value; } } case unop: switch (p->value.unop.op) { case '!': return !evaluate(p->value.unop.p0); case '+': return evaluate(p->value.unop.p0); case '-': return -evaluate(p->value.unop.p0); case '~': return ~evaluate(p->value.unop.p0); case UPPER: return (evaluate(p->value.unop.p0) >> 16) & 0xff; case HIGH: return (evaluate(p->value.unop.p0) >> 8) & 0xff; case LOW: return evaluate(p->value.unop.p0) & 0xff; case INCREMENT: return evaluate(p->value.unop.p0) + 1; case DECREMENT: return evaluate(p->value.unop.p0) - 1; default: assert(0); } case binop: p0 = evaluate(p->value.binop.p0); p1 = evaluate(p->value.binop.p1); switch (p->value.binop.op) { case '+': return p0 + p1; case '-': return p0 - p1; case '*': return p0 * p1; case '/': if (p1 == 0){ gperror(GPE_DIVBY0, NULL); return 0; } else { return p0 / p1; } case '%': if (p1 == 0){ gperror(GPE_DIVBY0, NULL); return 0; } else { return p0 % p1; } case '&': return p0 & p1; case '|': return p0 | p1; case '^': return p0 ^ p1; case LSH: return p0 << p1; case RSH: return p0 >> p1; case EQUAL: return p0 == p1; case '<': return p0 < p1; case '>': return p0 > p1; case NOT_EQUAL: return p0 != p1; case GREATER_EQUAL: return p0 >= p1; case LESS_EQUAL: return p0 <= p1; case LOGICAL_AND: return p0 && p1; case LOGICAL_OR: return p0 || p1; case '=': gperror(GPE_BADCHAR, "Illegal character (=)"); return 0; default: assert(0); /* Unhandled binary operator */ } default: assert(0); /* Unhandled parse node tag */ } return (0); /* Should never reach here */ } /* Attempt to evaluate expression 'p'. Return its value if * successful, otherwise generate an error message and return 0. */ gpasmVal maybe_evaluate(struct pnode *p) { gpasmVal r; if (p && can_evaluate(p)) { r = evaluate(p); } else { r = 0; } return r; } /* count the number of relocatable addesses in the expression */ int count_reloc(struct pnode *p) { struct symbol *s; struct variable *var; char *string; if (state.mode == absolute) return 0; if ((p->tag == binop) && (p->value.binop.op == CONCAT)) { string = evaluate_concatenation(p); s = get_symbol(state.stTop, string); if (s != NULL) { var = get_symbol_annotation(s); assert(var != NULL); switch(var->type) { case gvt_extern: case gvt_global: case gvt_static: case gvt_address: return 1; default: return 0; } } return 0; } switch (p->tag) { case constant: return 0; case offset: return count_reloc(p->value.offset); case symbol: if (strcmp(p->value.symbol, "$") == 0) { return 1; } else { s = get_symbol(state.stTop, p->value.symbol); if (s != NULL) { var = get_symbol_annotation(s); if (var != NULL) { switch(var->type) { case gvt_extern: case gvt_global: case gvt_static: case gvt_address: return 1; default: return 0; } } } } return 0; case unop: return count_reloc(p->value.unop.p0); case binop: return count_reloc(p->value.binop.p0) + count_reloc(p->value.binop.p1); default: assert(0); } return 0; } /* When generating object files, operands with relocatable addresses can only be [UPPER|HIGH|LOW]([] + []) */ static void add_reloc(struct pnode *p, short offset, unsigned short type) { char *string = NULL; struct symbol *s = NULL; struct variable *var = NULL; if ((p->tag == binop) && (p->value.binop.op == CONCAT)) { string = evaluate_concatenation(p); s = get_symbol(state.stTop, string); if (s != NULL) { var = get_symbol_annotation(s); assert(var != NULL); switch(var->type) { case gvt_extern: case gvt_global: case gvt_static: case gvt_address: coff_reloc(var->coff_num, offset, type); return; default: return; } } return; } switch (p->tag) { case symbol: if (strcmp(p->value.symbol, "$") == 0) { char buffer[BUFSIZ]; snprintf(buffer, sizeof(buffer), "_%s_%06x", state.obj.new_sec_name, state.org << _16bit_core); set_global(buffer, state.org << _16bit_core, PERMANENT, gvt_static); s = get_symbol(state.stTop, buffer); } else { s = get_symbol(state.stTop, p->value.symbol); } if (s != NULL) { var = get_symbol_annotation(s); if (var != NULL) { switch(var->type) { case gvt_extern: case gvt_global: case gvt_static: case gvt_address: coff_reloc(var->coff_num, offset, type); return; default: return; } } } return; case unop: switch (p->value.unop.op) { case UPPER: add_reloc(p->value.unop.p0, offset, RELOCT_UPPER); return; case HIGH: add_reloc(p->value.unop.p0, offset, RELOCT_HIGH); return; case LOW: add_reloc(p->value.unop.p0, offset, RELOCT_LOW); return; case '!': case '+': case '-': case '~': case INCREMENT: case DECREMENT: gperror(GPE_UNRESOLVABLE, NULL); return; default: assert(0); } case binop: switch (p->value.binop.op) { case '+': /* The symbol can be in either position */ if (count_reloc(p->value.binop.p0) == 1) { add_reloc(p->value.binop.p0, offset + maybe_evaluate(p->value.binop.p1), type); } else { add_reloc(p->value.binop.p1, offset + maybe_evaluate(p->value.binop.p0), type); } return; case '-': /* The symbol has to be first */ if (count_reloc(p->value.binop.p0) == 1) { add_reloc(p->value.binop.p0, offset - maybe_evaluate(p->value.binop.p1), type); } else { gperror(GPE_UNRESOLVABLE, NULL); } return; case '*': case '/': case '%': case '&': case '|': case '^': case LSH: case RSH: case EQUAL: case '<': case '>': case NOT_EQUAL: case GREATER_EQUAL: case LESS_EQUAL: case LOGICAL_AND: case LOGICAL_OR: case '=': gperror(GPE_UNRESOLVABLE, NULL); return; default: assert(0); /* Unhandled binary operator */ } return; case constant: default: assert(0); } return; } /* Determine if the expression is the difference between two symbols in the same section. If so, calculate the offset and don't generate a relocation. [UPPER|HIGH|LOW]([] - []) */ static int same_section(struct pnode *p) { struct pnode *p0; struct pnode *p1; struct symbol *sym0; struct symbol *sym1; struct variable *var0; struct variable *var1; if(!state.obj.enabled) return 0; if ((p->tag == unop) && ((p->value.unop.op == UPPER) || (p->value.unop.op == HIGH) || (p->value.unop.op == LOW))) { p = p->value.unop.p0; } if ((p->tag != binop) || (p->value.binop.op != '-') || (count_reloc(p->value.binop.p0) != 1)) return 0; p0 = p->value.binop.p0; p1 = p->value.binop.p1; if ((p0->tag != symbol) || (p1->tag != symbol)) return 0; sym0 = get_symbol(state.stTop, p0->value.symbol); sym1 = get_symbol(state.stTop, p1->value.symbol); var0 = get_symbol_annotation(sym0); var1 = get_symbol_annotation(sym1); /* They must come from the same section. Debug symbols are not placed in the global symbol table, so don't worry about symbol type. */ if (var0->coff_section_num != var1->coff_section_num) return 0; return 1; } gpasmVal reloc_evaluate(struct pnode *p, unsigned short type) { gpasmVal r = 0; int count = 0; if (state.mode == absolute) { r = maybe_evaluate(p); } else { count = count_reloc(p); if (count == 0) { /* no relocatable addresses */ r = maybe_evaluate(p); } else if (count > 1) { if ((count == 2) && (same_section(p))) { /* It is valid to take the difference between two symbols in the same section. Evaluate, but don't add a relocation. */ r = maybe_evaluate(p); } else { /* too many relocatable addresses */ gperror(GPE_UNRESOLVABLE, NULL); r = 0; } } else { /* add the coff relocation */ add_reloc(p, 0, type); r = 0; } } return r; } /* evaluate the number of passes for the "fill" directive*/ int eval_fill_number(struct pnode *p) { int number; number = maybe_evaluate(p); if(_16bit_core) { /* For 16 bit core devices number is bytes not words */ if ((number & 0x1) == 1){ /* The number is divided by two, so it can't be odd */ gperror(GPE_FILL_ODD, NULL); } else { number = number / 2; } } return number; } gputils-0.13.7/gpasm/gperror.h0000644000175000017500000001135311156313231013151 00000000000000/* Error handling Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPERROR_H__ #define __GPERROR_H__ void gperror(unsigned int code, char *message); void gpwarning(unsigned int code, char *message); void gpmessage(unsigned int code, char *message); /* Alternate message functions. Only the prototypes are provided, the user must link their own function into gpasm. */ void user_error(unsigned int code, char *message); void user_warning(unsigned int code, char *message); void user_message(unsigned int code, char *message); void add_code(int code); /* Error codes * * The error codes gpasm defines here are identical to MPASM's * definitions. Additional gpasm definitions follow the last * MPASM definition. * */ enum GPE_codes { GPE_USER = 101, GPE_NOMEM = 102, GPE_SYMFULL = 103, GPE_TEMPFILE = 104, GPE_NOENT = 105, /* File or directory not found */ GPE_STRCPLX = 106, GPE_BADDIGIT = 107, GPE_BADCHAR = 108, GPE_OPENPAR = 109, /* Mis-matched open parenthesis */ GPE_CLOSEPAR = 110, /* Mis-matched closed parenthesis */ GPE_MISSYM = 111, /* No symbol in an EQU or SET */ GPE_NOOP = 112, /* Missing an arithmetic operator */ GPE_NOSYM = 113, /* Symbol has not been defined */ GPE_DIVBY0 = 114, GPE_DUPLAB = 115, GPE_DIFFLAB = 116, GPE_ADDROVF = 117, /* address overflow */ GPE_ADDROVR = 118, /* overwriting a previously written address */ GPE_BAD_CALL_ADDR = 120, GPE_ILLEGAL_LABEL = 121, GPE_ILLEGAL_DIR = 123, GPE_ILLEGAL_ARGU = 124, GPE_ILLEGAL_COND = 125, GPE_RANGE = 126, /* Argument out of range */ GPE_TOO_MANY_ARGU = 127, GPE_MISSING_ARGU = 128, GPE_EXPECTED = 129, GPE_EXTRA_PROC = 130, GPE_UNDEF_PROC = 131, GPE_UNKNOWN_PROC = 132, GPE_IHEX = 133, /* Hex file format is too small for code */ GPE_NO_MACRO_NAME = 135, GPE_DUPLICATE_MACRO = 136, GPE_BAD_WHILE_LOOP = 140, GPE_ILLEGAL_NESTING = 143, GPE_UNMATCHED_ENDM = 145, GPE_OBJECT_ONLY = 149, GPE_UNRESOLVABLE = 151, GPE_WRONG_SECTION = 152, GPE_CONTIG_SECTION = 154, GPE_MUST_BE_LABEL = 156, GPE_ORG_ODD = 157, GPE_FILL_ODD = 159, GPE_CONTIG_CONFIG = 163, GPE_CONTIG_IDLOC = 164, GPE_MISSING_BRACKET = 168, GPE_CONFIG_UNKNOWN = 176, GPE_CONFIG_usCONFIG = 177, GPE_UNKNOWN = 179 }; /* Warning codes * * The warning codes gpasm defines here are identical to MPASM's * definitions. Additional gpasm definitions follow the last * MPASM definition. * */ enum GPW_codes { GPW_NOT_DEFINED = 201, GPW_RANGE = 202, /* Argument out of range */ GPW_OP_COLUMN_ONE = 203, GPW_DIR_COLUMN_ONE = 205, GPW_MACRO_COLUMN_ONE = 206, GPW_LABEL_COLUMN = 207, GPW_MISSING_QUOTE = 209, GPW_EXTRANEOUS = 211, GPW_EXPECTED = 212, GPW_CMDLINE_PROC = 215, GPW_CMDLINE_RADIX = 216, GPW_CMDLINE_HEXFMT = 217, GPW_RADIX = 218, GPW_INVALID_RAM = 219, GPW_EXCEED_ROM = 220, GPW_DISABLE_ERROR = 222, GPW_REDEFINING_PROC = 223, GPW_NOT_RECOMMENDED = 224, GPW_INVALID_ROM = 228, GPW_UNKNOWN = 231 }; /* Message codes * * The message codes gpasm defines here are identical to MPASM's * definitions. Additional gpasm definitions follow the last * MPASM definition. * */ enum GPM_codes { GPM_USER = 301, /* User supplied message */ GPM_BANK = 302, GPM_RANGE = 303, GPM_IDLOC = 304, GPM_NOF = 305, GPM_PAGE = 306, GPM_PAGEBITS = 307, GPM_SUPVAL = 308, GPM_SUPLIN = 309, GPM_SUPRAM = 310, GPM_EXTPAGE = 312, GPM_CBLOCK = 313, GPM_W_MODIFIED = 316, GPM_SPECIAL_MNEMONIC = 318, GPM_UNKNOWN = 319 }; #endif gputils-0.13.7/gpasm/coff.h0000644000175000017500000000262711156313231012412 00000000000000/* Generate coff file Copyright (C) 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __COFF_H__ #define __COFF_H__ #define SECTION_FLAGS state.obj.flags void coff_init(void); void coff_close_file(void); void coff_new_section(char *name, int addr, int flags); gp_symbol_type *coff_add_sym(char *name, int value, enum gpasmValTypes type); void coff_reloc(int symbol, short offset, unsigned short type); void coff_linenum(int emitted); gp_symbol_type *coff_add_filesym(char *name, int isinclude); void coff_add_eofsym(void); void coff_add_listsym(void); void coff_add_nolistsym(void); void coff_add_directsym(unsigned char command, char *string); void coff_add_identsym(char *string); char *coff_local_name(char *name); #endif gputils-0.13.7/gpasm/special.c0000644000175000017500000002355411156521302013112 00000000000000/* Implements special instruction mnemonics Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "gperror.h" #include "special.h" #include "directive.h" #include "evaluate.h" extern struct pnode *mk_constant(int value); extern struct pnode *mk_list(struct pnode *head, struct pnode *tail); struct pnode *make_constant_list(int value1, int value2) { return mk_list(mk_constant(value1), mk_list(mk_constant(value2), NULL)); } struct pnode *add_symbol_constant(struct pnode *parms, int value) { return mk_list(HEAD(parms), mk_list(mk_constant(value), NULL)); } /**************************************************************************/ static gpasmVal do_addcf(gpasmVal r, char *name, int arity, struct pnode *parms) { gpmessage(GPM_SPECIAL_MNEMONIC, NULL); do_insn("btfsc", make_constant_list(3, 0)); do_insn("incf", parms); return r; } static gpasmVal do_adddcf(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfsc", make_constant_list(3, 1)); do_insn("incf", parms); return r; } static gpasmVal do_b(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("goto", parms); return r; } static gpasmVal do_bc(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfsc", make_constant_list(3, 0)); do_insn("goto", parms); return r; } static gpasmVal do_bdc(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfsc", make_constant_list(3, 1)); do_insn("goto", parms); return r; } static gpasmVal do_bz(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfsc", make_constant_list(3, 2)); do_insn("goto", parms); return r; } static gpasmVal do_bnc(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfss", make_constant_list(3, 0)); do_insn("goto", parms); return r; } static gpasmVal do_bndc(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfss", make_constant_list(3, 1)); do_insn("goto", parms); return r; } static gpasmVal do_bnz(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfss", make_constant_list(3, 2)); do_insn("goto", parms); return r; } static gpasmVal do_clrc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("bcf", make_constant_list(3, 0)); return r; } static gpasmVal do_clrdc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("bcf", make_constant_list(3, 1)); return r; } static gpasmVal do_clrz(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("bcf", make_constant_list(3, 2)); return r; } static gpasmVal do_lcall(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("pagesel", parms); do_insn("call", parms); return r; } static gpasmVal do_lgoto(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("pagesel", parms); do_insn("goto", parms); return r; } static gpasmVal do_movfw(gpasmVal r, char *name, int arity, struct pnode *parms) { if (enforce_arity(arity, 1)) { do_insn("movf", add_symbol_constant(parms, 0)); } return r; } static gpasmVal do_negf(gpasmVal r, char *name, int arity, struct pnode *parms) { if ((arity == 1) || (arity == 2)) { do_insn("comf", add_symbol_constant(parms, 1)); do_insn("incf", parms); } else { enforce_arity(arity, 2); } return r; } static gpasmVal do_setc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("bsf", make_constant_list(3, 0)); return r; } static gpasmVal do_setdc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("bsf", make_constant_list(3, 1)); return r; } static gpasmVal do_setz(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("bsf", make_constant_list(3, 2)); return r; } static gpasmVal do_skpc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("btfss", make_constant_list(3, 0)); return r; } static gpasmVal do_skpdc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("btfss", make_constant_list(3, 1)); return r; } static gpasmVal do_skpz(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("btfss", make_constant_list(3, 2)); return r; } static gpasmVal do_skpnc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("btfsc", make_constant_list(3, 0)); return r; } static gpasmVal do_skpndc(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("btfsc", make_constant_list(3, 1)); return r; } static gpasmVal do_skpnz(gpasmVal r, char *name, int arity, struct pnode *parms) { if (arity) { gperror(GPE_TOO_MANY_ARGU, NULL); } do_insn("btfsc", make_constant_list(3, 2)); return r; } static gpasmVal do_subcf(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfsc", make_constant_list(3, 0)); do_insn("decf", parms); return r; } static gpasmVal do_subdcf(gpasmVal r, char *name, int arity, struct pnode *parms) { do_insn("btfsc", make_constant_list(3, 1)); do_insn("decf", parms); return r; } static gpasmVal do_tstf(gpasmVal r, char *name, int arity, struct pnode *parms) { if (enforce_arity(arity, 1)) { do_insn("movf", add_symbol_constant(parms, 1)); } return r; } static gpasmVal do_mode(gpasmVal r, char *name, int arity, struct pnode *parms) { if (enforce_arity(arity, 1)) { struct pnode* val = HEAD(parms); if ((val->tag == constant) && (val->value.constant > 0x1f)) { gpwarning(GPW_RANGE, NULL); val->value.constant &= 0x1f; } do_insn("movlw", parms); do_insn("movwm", NULL); } return r; } /* PIC 12-bit and 14-bit "Special" instruction set */ struct insn special[] = { { "addcf", 0, (long int)do_addcf, INSN_CLASS_FUNC, 0 }, { "adddcf", 0, (long int)do_adddcf, INSN_CLASS_FUNC, 0 }, { "b", 0, (long int)do_b, INSN_CLASS_FUNC, 0 }, { "bc", 0, (long int)do_bc, INSN_CLASS_FUNC, 0 }, { "bdc", 0, (long int)do_bdc, INSN_CLASS_FUNC, 0 }, { "bz", 0, (long int)do_bz, INSN_CLASS_FUNC, 0 }, { "bnc", 0, (long int)do_bnc, INSN_CLASS_FUNC, 0 }, { "bndc", 0, (long int)do_bndc, INSN_CLASS_FUNC, 0 }, { "bnz", 0, (long int)do_bnz, INSN_CLASS_FUNC, 0 }, { "clrc", 0, (long int)do_clrc, INSN_CLASS_FUNC, 0 }, { "clrdc", 0, (long int)do_clrdc, INSN_CLASS_FUNC, 0 }, { "clrz", 0, (long int)do_clrz, INSN_CLASS_FUNC, 0 }, { "lcall", 0, (long int)do_lcall, INSN_CLASS_FUNC, 0 }, { "lgoto", 0, (long int)do_lgoto, INSN_CLASS_FUNC, 0 }, { "movfw", 0, (long int)do_movfw, INSN_CLASS_FUNC, 0 }, { "negf", 0, (long int)do_negf, INSN_CLASS_FUNC, 0 }, { "setc", 0, (long int)do_setc, INSN_CLASS_FUNC, 0 }, { "setdc", 0, (long int)do_setdc, INSN_CLASS_FUNC, 0 }, { "setz", 0, (long int)do_setz, INSN_CLASS_FUNC, 0 }, { "skpc", 0, (long int)do_skpc, INSN_CLASS_FUNC, 0 }, { "skpdc", 0, (long int)do_skpdc, INSN_CLASS_FUNC, 0 }, { "skpz", 0, (long int)do_skpz, INSN_CLASS_FUNC, 0 }, { "skpnc", 0, (long int)do_skpnc, INSN_CLASS_FUNC, 0 }, { "skpndc", 0, (long int)do_skpndc, INSN_CLASS_FUNC, 0 }, { "skpnz", 0, (long int)do_skpnz, INSN_CLASS_FUNC, 0 }, { "subcf", 0, (long int)do_subcf, INSN_CLASS_FUNC, 0 }, { "subdcf", 0, (long int)do_subdcf, INSN_CLASS_FUNC, 0 }, { "tstf", 0, (long int)do_tstf, INSN_CLASS_FUNC, 0 } }; const int num_op_special = TABLE_SIZE(special); struct insn op_sx_mode = { "mode", 0, (long int)do_mode, INSN_CLASS_FUNC, 0 }; gputils-0.13.7/gpasm/processor.h0000644000175000017500000000162511156313231013511 00000000000000/* PIC Processor selection Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __PROCESSOR_H__ #define __PROCESSOR_H__ void select_processor(char *name); #endif gputils-0.13.7/gpasm/deps.c0000644000175000017500000000361211156313231012416 00000000000000/* dependency file generation Copyright (C) 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" void deps_init(void) { char output_file[BUFSIZ]; if (state.depfile != named) { strncpy(state.depfilename, state.basefilename, sizeof(state.depfilename)); strncat(state.depfilename, ".d", sizeof(state.depfilename)); } if (state.depfile == suppress) { state.dep.enabled = false; unlink(state.depfilename); } else { state.dep.f = fopen(state.depfilename, "w"); if (state.dep.f == NULL) { perror(state.depfilename); exit(1); } state.dep.enabled = true; /* output file names may not be setup, so make one */ strncpy(output_file, state.basefilename, sizeof(output_file)); if (state.mode == relocatable) { strncat(output_file, ".o", sizeof(output_file)); } else { strncat(output_file, ".hex", sizeof(output_file)); } fprintf(state.dep.f, "%s : ", output_file); } } void deps_add(char *file_name) { if (state.dep.enabled) { fprintf(state.dep.f, " \\\n %s", file_name); } } void deps_close(void) { if (state.dep.enabled) { fprintf(state.dep.f, "\n"); fclose(state.dep.f); } } gputils-0.13.7/gpasm/parse.y0000644000175000017500000004156311156521302012632 00000000000000%{ /* Parser for gpasm Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #include "gpasm.h" #include "evaluate.h" #include "gperror.h" #include "directive.h" #include "lst.h" #include "macro.h" #include "coff.h" #include "scan.h" void yyerror(char *message) { gperror(103, message); } int yylex(void); extern int _16bit_core; extern gp_boolean _16packed_byte_acc; static gp_boolean _16packed_offset_labels; /************************************************************************/ /* Some simple functions for building parse trees */ static struct pnode *mk_pnode(enum pnode_tag tag) { struct pnode *new = malloc(sizeof(*new)); new->tag = tag; return new; } struct pnode *mk_constant(int value) { struct pnode *new = mk_pnode(constant); new->value.constant = value; return new; } struct pnode *mk_offset(struct pnode *p) { struct pnode *new = mk_pnode(offset); new->value.offset = p; return new; } static struct pnode *mk_symbol(char *value) { struct pnode *new = mk_pnode(symbol); new->value.symbol = value; return new; } static struct pnode *mk_string(char *value) { struct pnode *new = mk_pnode(string); new->value.string = value; return new; } struct pnode *mk_list(struct pnode *head, struct pnode *tail) { struct pnode *new = mk_pnode(list); new->value.list.head = head; new->value.list.tail = tail; return new; } static struct pnode *mk_2op(int op, struct pnode *p0, struct pnode *p1) { struct pnode *new = mk_pnode(binop); new->value.binop.op = op; new->value.binop.p0 = p0; new->value.binop.p1 = p1; return new; } static struct pnode *mk_1op(int op, struct pnode *p0) { struct pnode *new = mk_pnode(unop); new->value.unop.op = op; new->value.unop.p0 = p0; return new; } /************************************************************************/ /* shared functions */ gpasmVal set_label(char *label, struct pnode *parms) { gpasmVal value = 0; if (asm_enabled()) { value = do_or_append_insn("set", parms); if (!state.mac_prev) { set_global(label, value, TEMPORARY, gvt_constant); } } return value; } int return_op(int operation); void next_line(int value) { char l[BUFSIZ]; char *e = l; if ((state.src->type == src_macro) || (state.src->type == src_while)) { /* while loops can be defined inside a macro or nested */ if (state.mac_prev) { state.lst.line.linetype = none; if (state.mac_body) state.mac_body->src_line = strdup(state.src->lst.m->src_line); } if (((state.src->type == src_while) || (state.lst.expand)) && (state.pass == 2)) { assert(state.src->lst.m->src_line != NULL); lst_format_line(state.src->lst.m->src_line, value); } if (state.src->lst.m->next) { state.src->lst.m = state.src->lst.m->next; } } else if ((state.src->type == src_file) && (state.src->lst.f != NULL)) { fgets(l, BUFSIZ, state.src->lst.f); l[strlen(l) - 1] = '\0'; /* Eat the trailing newline */ if (state.mac_prev) { state.lst.line.linetype = none; if (state.mac_body) state.mac_body->src_line = strdup(l); } if (state.pass == 2) { lst_format_line(e, value); } } state.src->line_number++; switch (state.next_state) { case state_exitmacro: execute_exitm(); break; case state_include: open_src(state.next_buffer.file, 1); free(state.next_buffer.file); break; case state_macro: /* push the label for local directive */ state.stTop = push_macro_symbol_table(state.stTop); execute_macro(state.next_buffer.macro, 0); break; case state_section: /* create a new coff section */ coff_new_section(state.obj.new_sec_name, state.obj.new_sec_addr, state.obj.new_sec_flags); break; case state_while: execute_macro(state.next_buffer.macro, 1); break; default: break; } } /************************************************************************/ %} /* Bison declarations */ %union { gpasmVal i; char *s; struct pnode *p; } %token LABEL %token IDENTIFIER %token CBLOCK %token DEBUG_LINE %token ENDC %token ERRORLEVEL %token FILL %token LIST %token NUMBER %token PROCESSOR %token STRING %token DEFINE %token UPPER %token HIGH %token LOW %token LSH %token RSH %token GREATER_EQUAL %token LESS_EQUAL %token EQUAL %token NOT_EQUAL %token '<' %token '>' %token '&' %token '|' %token '^' %token LOGICAL_AND %token LOGICAL_OR %token '=' %token ASSIGN_PLUS %token ASSIGN_MINUS %token ASSIGN_MULTIPLY %token ASSIGN_DIVIDE %token ASSIGN_MODULUS %token ASSIGN_LSH %token ASSIGN_RSH %token ASSIGN_AND %token ASSIGN_OR %token ASSIGN_XOR %token INCREMENT %token DECREMENT %token TBL_NO_CHANGE %token TBL_POST_INC %token TBL_POST_DEC %token TBL_PRE_INC %token CONCAT %token VAR %token VARLAB_BEGIN %token VAR_BEGIN %token VAR_END %token '[' %token ']' %type '+' %type '-' %type '*' %type '/' %type '%' %type '!' %type '~' %type line %type label_concat %type decimal_ops %type statement %type

parameter_list %type

expr %type

e0 %type

e1 %type

e2 %type

e3 %type

e4 %type

e5 %type

e6 %type

e7 %type

e8 %type

cidentifier %type e1op %type e2op %type e3op %type e4op %type e5op %type e6op %type e7op %type e8op %type e9op %type assign_equal_ops %type

list_block %type

list_expr %% /* Grammar rules */ program: /* can be nothing */ | program { state.lst.line.was_org = state.org; state.lst.line.linetype = none; state.next_state = state_nochange; } line | program error '\n' { next_line(0); } ; line: label_concat assign_equal_ops expr '\n' { struct pnode *parms; int exp_result; exp_result = do_insn("set", mk_list($3, NULL)); parms = mk_list(mk_2op(return_op($2), mk_symbol($1), mk_constant(exp_result)), NULL); next_line(set_label($1, parms)); } | label_concat '=' expr '\n' { struct pnode *parms; /* implements i = 6 + 1 */ parms = mk_list($3, NULL); next_line(set_label($1, parms)); } | label_concat DECREMENT '\n' { struct pnode *parms; /* implements i-- */ parms = mk_list(mk_1op(DECREMENT, mk_symbol($1)), NULL); next_line(set_label($1, parms)); } | label_concat INCREMENT '\n' { struct pnode *parms; /* implements i++ */ parms = mk_list(mk_1op(INCREMENT, mk_symbol($1)), NULL); next_line(set_label($1, parms)); } | label_concat statement { if (asm_enabled() && (state.lst.line.linetype == none)) { if ((state.mode == relocatable) && (SECTION_FLAGS & (STYP_BSS | STYP_DATA))) /* alias to next definition */ state.lst.line.linetype = res; else state.lst.line.linetype = insn; } if (asm_enabled()) { if (state.mac_head) { /* This is a macro definition. Set it up */ struct symbol *mac; struct macro_head *h = NULL; mac = get_symbol(state.stMacros, $1); if (mac) h = get_symbol_annotation(mac); /* It's not an error if macro was defined on pass 1 and we're in pass 2. */ if (h && !((h->pass == 1) && (state.pass == 2))) { gperror(GPE_DUPLICATE_MACRO, NULL); } else { if (!mac) mac = add_symbol(state.stMacros, $1); annotate_symbol(mac, state.mac_head); h = state.mac_head; h->line_number = state.src->line_number; h->file_symbol = state.src->file_symbol; } h->pass = state.pass; /* The macro is defined so allow calls. */ if (state.pass == 2) h->defined = 1; state.mac_head = NULL; } else if (!state.mac_prev) { /* Outside a macro, just define the label. */ switch (state.lst.line.linetype) { case sec: strncpy(state.obj.new_sec_name, $1, 78); break; case set: set_global($1, $2, TEMPORARY, gvt_constant); break; case org: case equ: set_global($1, $2, PERMANENT, gvt_constant); break; case insn: set_global($1, ($2 << _16bit_core) - _16packed_offset_labels, PERMANENT, gvt_address); break; case res: set_global($1, $2, PERMANENT, gvt_static); break; case dir: gperror(GPE_ILLEGAL_LABEL, NULL); break; default: break; } } } next_line($2); } | statement { if (state.mac_head) { /* This is a macro definition, but the label was missing */ state.mac_head = NULL; gperror(GPE_NO_MACRO_NAME, NULL); } else { next_line(0); } } ; decimal_ops: ERRORLEVEL | DEBUG_LINE; statement: '\n' { if (!state.mac_prev) { $$ = state.org; } else { macro_append(); } } | PROCESSOR { force_ident = 1; } IDENTIFIER '\n' { $$ = do_or_append_insn($1, mk_list(mk_symbol($3), NULL)); force_ident = 0; } | LIST '\n' { $$ = do_or_append_insn($1, NULL); } | LIST { force_decimal = 1; } list_block '\n' { $$ = do_or_append_insn($1, $3); force_decimal = 0; } | decimal_ops { force_decimal = 1; } parameter_list '\n' { $$ = do_or_append_insn($1, $3); force_decimal = 0; } | DEFINE IDENTIFIER STRING '\n' { $$ = do_or_append_insn($1, mk_list(mk_string($2), mk_list(mk_string($3), NULL))); } | DEFINE IDENTIFIER '\n' { $$ = do_or_append_insn($1, mk_list(mk_string($2), NULL)); } | DEFINE '\n' { $$ = do_or_append_insn($1, NULL); } | IDENTIFIER '\n' { $$ = do_or_append_insn($1, NULL); } | IDENTIFIER parameter_list '\n' { $$ = do_or_append_insn($1, $2); } | FILL IDENTIFIER ')' ',' expr '\n' { int number; int i; if (!state.mac_prev) { number = eval_fill_number($5); for (i = 0; i < number; i++) { $$ = do_insn($2, NULL); } } else { macro_append(); } } | FILL IDENTIFIER parameter_list ')' ',' expr '\n' { int number; int i; if (!state.mac_prev) { number = eval_fill_number($6); for (i = 0; i < number; i++) { $$ = do_insn($2, $3); } } else { macro_append(); } } | CBLOCK expr '\n' { if (!state.mac_prev) { begin_cblock($2); } else { macro_append(); } next_line(0); } const_block ENDC '\n' { if (state.mac_prev) { macro_append(); } $$ = 0; } | CBLOCK '\n' { if (!state.mac_prev) { continue_cblock(); } else { macro_append(); } next_line(0); } const_block ENDC '\n' { if (state.mac_prev) { macro_append(); } $$ = 0; } | CBLOCK error ENDC '\n' { $$ = 0; } ; const_block: | const_block const_line { next_line(0); } ; const_line: '\n' | const_def_list '\n' { if (state.mac_prev) { macro_append(); } } | label_concat '\n' { if (!state.mac_prev) { cblock_expr(mk_symbol($1)); } else { macro_append(); } } | label_concat expr '\n' { if (!state.mac_prev) { cblock_expr_incr(mk_symbol($1), $2); } else { macro_append(); } } ; const_def_list: const_def | const_def_list ',' const_def ; const_def: cidentifier { if (!state.mac_prev) { cblock_expr($1); } } | cidentifier ':' expr { if (!state.mac_prev) { cblock_expr_incr($1, $3); } } ; assign_equal_ops: ASSIGN_PLUS | ASSIGN_MINUS | ASSIGN_MULTIPLY | ASSIGN_DIVIDE | ASSIGN_MODULUS | ASSIGN_LSH | ASSIGN_RSH | ASSIGN_AND | ASSIGN_OR | ASSIGN_XOR; parameter_list: expr { $$ = mk_list($1, NULL); } | expr ',' { $$ = mk_list($1, mk_list(mk_symbol(""), NULL)); } | expr ',' parameter_list { $$ = mk_list($1, $3); } | ',' parameter_list { $$ = mk_list(mk_symbol(""), $2); } | ',' { $$ = mk_list(mk_symbol(""), mk_list(mk_symbol(""), NULL)); } ; expr: e8 | expr e9op e8 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e9op: '=' ; e8: e7 | e8 e8op e7 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e8op: LOGICAL_OR ; e7: e6 | e7 e7op e6 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e7op: LOGICAL_AND; e6: e5 | e6 e6op e5 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e6op: '&' | '|' | '^' ; e5: e4 | e5 e5op e4 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e5op: '<' | '>' | EQUAL | NOT_EQUAL | GREATER_EQUAL | LESS_EQUAL ; e4: e3 | e4 e4op e3 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e4op: LSH | RSH ; e3: e2 | e3 e3op e2 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e3op: '+' | '-' ; e2: e1 | e2 e2op e1 { coerce_str1($1); coerce_str1($3); $$ = mk_2op($2, $1, $3); } ; e2op: '*' | '/' | '%'; e1: e0 | e1op e0 { coerce_str1($2); $$ = mk_1op($1, $2); } ; e1op: UPPER | HIGH | LOW | '-' | '!' | '~' | '+'; e0: cidentifier { $$ = $1; } | NUMBER { $$ = mk_constant($1); } | '$' { $$ = mk_symbol("$"); } | STRING { $$ = mk_string($1); } | '(' expr ')' { $$ = $2; } | '[' expr ']' { $$ = mk_offset($2); } | '*' { $$ = mk_constant(TBL_NO_CHANGE); } | TBL_POST_INC { $$ = mk_constant($1); } | TBL_POST_DEC { $$ = mk_constant($1); } | TBL_PRE_INC { $$ = mk_constant($1); } ; cidentifier: IDENTIFIER { $$ = mk_symbol($1); } | VAR_BEGIN expr ')' { $$ = mk_2op(CONCAT, mk_symbol($1), mk_1op(VAR, $2)); } | VAR_BEGIN expr VAR_END { $$ = mk_2op(CONCAT, mk_symbol($1), mk_2op(CONCAT, mk_1op(VAR, $2), mk_symbol($3))); } ; label_concat: LABEL { $$ = $1; /* * statements return their org - but, with 16bit cores, org is a word * address. for us to know whether a label points at a non word aligned * address, we must get status from the directive.c module through a * back channel. however, we must make sure to store this status before * any statement on the current line is processed, so we must save it here * before the statement rules run. */ _16packed_offset_labels = _16packed_byte_acc; } | VARLAB_BEGIN expr ')' { if (asm_enabled() && !state.mac_prev) { $$ = evaluate_concatenation(mk_2op(CONCAT, mk_symbol($1), mk_1op(VAR, $2))); _16packed_offset_labels = _16packed_byte_acc; } } | VARLAB_BEGIN expr VAR_END { if (asm_enabled() && !state.mac_prev) { $$ = evaluate_concatenation(mk_2op(CONCAT, mk_symbol($1), mk_2op(CONCAT, mk_1op(VAR, $2), mk_symbol($3)))); _16packed_offset_labels = _16packed_byte_acc; } } ; list_block: list_expr { $$ = mk_list($1, NULL); } | list_expr ',' list_block { $$ = mk_list($1, $3); } ; list_expr: IDENTIFIER { if ((strcasecmp($1, "p") == 0) || (strcasecmp($1, "pe") == 0)) { force_ident = 1; } } e9op e8 { $$ = mk_2op($3, mk_symbol($1), $4); force_ident = 0; } | e8 { $$ = $1; } ; %% int return_op(int operation) { /* returns an operator for the replacement of i+=1 with i=i+1*/ switch(operation) { case ASSIGN_PLUS: return '+'; case ASSIGN_MINUS: return '-'; case ASSIGN_MULTIPLY: return '*'; case ASSIGN_DIVIDE: return '/'; case ASSIGN_MODULUS: return '%'; case ASSIGN_LSH: return LSH; case ASSIGN_RSH: return RSH; case ASSIGN_AND: return '&'; case ASSIGN_OR: return '|'; case ASSIGN_XOR: return '^'; default: assert(0); /* Unhandled operator */ } return 0; } gputils-0.13.7/NEWS0000644000175000017500000000001311156313233010701 00000000000000see README gputils-0.13.7/README0000644000175000017500000000431411156313233011072 00000000000000This is a collection of development tools for Microchip (TM) PIC (TM) microcontrollers. This is ALPHA software: there may be serious bugs in it, and it's nowhere near complete. gputils currently only implements a subset of the features available with Microchip's tools. See the documentation for an up-to-date list of what gputils can do. Installation instructions are constained in the INSTALL document. Documentation is in the "doc" directory. The user manual is "gputils.lyx", it's ready for a postscript printer as "gputils.ps" or viewing using Adobe (TM) Acrobat (TM) as "gputils.pdf". Lyx is available from http://www.lyx.org Send any bug reports to the bug tracking system at: https://sourceforge.net/projects/gputils/ Please verify a bug report has not already been submitted before creating a new one. In the report, please state which version of gputils you're using, the machine and OS you've built it for (or not), and enough source code to reproduce the problem. If you're trying to build gputils on a machine/OS but can't, you might want to take a look at 'stdhdr.h' and see if you can fix the problem there. Please send any patches you wish to be considered for the next gputils release, to one of the Project Administrators listed at sourceforge. Win32 Support ============= Although gputils was primarily intended for GNU systems, it can be compiled on a win32 system (Win98, WinNT, ...). This has been performed using the Borland C Compiler and Microsoft Visual C. The gputils supported win32 compiler is MinGW. It is available at: http://www.mingw.org/ MinGW was selected because it is based on the GNU C compiler. Additionally, it can easily be used as a cross compiler on GNU systems. A native win32 version of MinGW is available. However, the process for compiling on a win32 system has not been developed. This will be provided some time in the future. Until then, offical gputils ports to win32 will be generated using a cross compiler on a Linux system. The following scripts will configure gputils to cross compile to win32 using a Linux system: mkdir cross && \ cd cross && \ CC=i386-mingw32msvc-gcc ../configure \ --srcdir=.. \ --build=i586-pc-linux-gnu \ --host=i386-mingw32msvc gputils-0.13.7/COPYING0000644000175000017500000004310611156313233011247 00000000000000 GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.) You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. The precise terms and conditions for copying, distribution and modification follow. GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION 0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. 2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. 3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. 4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. 5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. 6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. 7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. 8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS Appendix: How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) 19yy This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) 19yy name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. , 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Library General Public License instead of this License. gputils-0.13.7/lkr/0000777000175000017500000000000011156521345011071 500000000000000gputils-0.13.7/lkr/18f66j60i.lkr0000644000175000017500000000315611156521271012765 00000000000000// File: 18f66j60i.lkr // Sample ICD2 linker script for the PIC18F66J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8410i.lkr0000644000175000017500000000203211156521271012576 00000000000000// File: 18f8410i.lkr // Sample ICD2 linker script for the PIC18F8410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j10i_e.lkr0000644000175000017500000000304411156521271013261 00000000000000// File: 18f67j10i_e.lkr // Sample ICD2 linker script for the PIC18F67J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j10_e.lkr0000644000175000017500000000272111156521271013111 00000000000000// File: 18f67j10_e.lkr // Sample linker script for the PIC18F67J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4431i.lkr0000644000175000017500000000203511156521271012600 00000000000000// File: 18f4431i.lkr // Sample ICD2 linker script for the PIC18F4431 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6628i.lkr0000644000175000017500000000342011156521271012611 00000000000000// File: 18f6628i.lkr // Sample ICD2 linker script for the PIC18F6628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4585_e.lkr0000644000175000017500000000315611156521271012752 00000000000000// File: 18f4585_e.lkr // Sample linker script for the PIC18F4585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8390_e.lkr0000644000175000017500000000157111156521271012747 00000000000000// File: 18f8390_e.lkr // Sample linker script for the PIC18F8390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f96j65_e.lkr0000644000175000017500000000303611156521271013125 00000000000000// File: 18f96j65_e.lkr // Sample linker script for the PIC18F96J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j16.lkr0000644000175000017500000000303411156521271012610 00000000000000// File: 18f66j16.lkr // Sample linker script for the PIC18F66J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f84j90.lkr0000644000175000017500000000142611156521271012615 00000000000000// File: 18f84j90.lkr // Sample linker script for the PIC18F84J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f884.lkr0000644000175000017500000000231411156521271012355 00000000000000// Sample linker command file for 16F884 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4685.lkr0000644000175000017500000000324611156521271012447 00000000000000// File: 18f4685.lkr // Sample linker script for the PIC18F4685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4450i.lkr0000644000175000017500000000174011156521271012603 00000000000000// File: 18f4450i.lkr // Sample ICD2 linker script for the PIC18F4450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j65.lkr0000644000175000017500000000303411156521271012616 00000000000000// File: 18f86j65.lkr // Sample linker script for the PIC18F86J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j50.lkr0000644000175000017500000000303311156521271012606 00000000000000// File: 18f85j50.lkr // Sample linker script for the PIC18F85J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f258i.lkr0000644000175000017500000000242611156521271012527 00000000000000// File: 18f258i.lkr // Sample ICD2 linker script for the PIC18F258 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2331i.lkr0000644000175000017500000000203511156521271012575 00000000000000// File: 18f2331i.lkr // Sample ICD2 linker script for the PIC18F2331 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12cr509a.lkr0000644000175000017500000000076711156521271012675 00000000000000// Sample linker command file for 12CR509A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gpr0 START=0x07 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f724.lkr0000644000175000017500000000212711156521271012350 00000000000000// Sample linker command file for 16F724 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x12F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f65j11i.lkr0000644000175000017500000000212111156521271012747 00000000000000// File: 18f65j11i.lkr // Sample ICD2 linker script for the PIC18F65J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j10i.lkr0000644000175000017500000000212111156521271012747 00000000000000// File: 18f66j10i.lkr // Sample ICD2 linker script for the PIC18F66J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f913.lkr0000644000175000017500000000231411156521271012346 00000000000000// Sample linker command file for 16F913 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/12f635i.lkr0000644000175000017500000000300011156521271012505 00000000000000// Sample ICD2 linker command file for 12F635 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x0 END=0x0F PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x80 END=0x9D PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x180 END=0x19D PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x1A PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x114 PROTECTED DATABANK NAME=gpr START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2580_e.lkr0000644000175000017500000000233011156521271012734 00000000000000// File: 18f2580_e.lkr // Sample linker script for the PIC18F2580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c452.lkr0000644000175000017500000000172611156521271012351 00000000000000// File: 18c452.lkr // Sample linker script for the PIC18C452 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x300007 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f1933.lkr0000644000175000017500000001331211156521271012431 00000000000000// File: 16f1933_g.lkr // Generic linker script for the PIC16F1933 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8393_e.lkr0000644000175000017500000000157111156521271012752 00000000000000// File: 18f8393_e.lkr // Sample linker script for the PIC18F8393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6525.lkr0000644000175000017500000000306211156521271012436 00000000000000// File: 18f6525.lkr // Sample linker script for the PIC18F6525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2685i.lkr0000644000175000017500000000351111156521271012611 00000000000000// File: 18f2685i.lkr // Sample ICD2 linker script for the PIC18F2685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6493i_e.lkr0000644000175000017500000000203411156521271013115 00000000000000// File: 18f6493i_e.lkr // Sample ICD2 linker script for the PIC18F6493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4523i_e.lkr0000644000175000017500000000240611156521271013110 00000000000000// File: 18f4523i_e.lkr // Sample ICD2 linker script for the PIC18F4523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f44k20i.lkr0000644000175000017500000000203711156521271012753 00000000000000// File: 18f44k20i.lkr // Sample ICD2 linker script for the PIC18F44K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8393.lkr0000644000175000017500000000156711156521271012453 00000000000000// File: 18f8393.lkr // Sample linker script for the PIC18F8393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c858.lkr0000644000175000017500000000204311156521271012354 00000000000000// File: 18c858.lkr // Sample linker script for the PIC18C858 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x300007 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2682i.lkr0000644000175000017500000000351111156521271012606 00000000000000// File: 18f2682i.lkr // Sample ICD2 linker script for the PIC18F2682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13D7F CODEPAGE NAME=debug START=0x13D80 END=0x13FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr56a.lkr0000644000175000017500000000111111156521271012576 00000000000000// Sample linker command file for 16CR56A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/12hv615i.lkr0000644000175000017500000000161611156521271012706 00000000000000// Sample ICD2 linker command file for 12HV615 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16lf724.lkr0000644000175000017500000000213011156521271012516 00000000000000// Sample linker command file for 16LF724 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x12F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2220i.lkr0000644000175000017500000000174211156521271012576 00000000000000// File: 18f2220i.lkr // Sample ICD2 linker script for the PIC18F2220 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xDBF CODEPAGE NAME=debug START=0xDC0 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2515i_e.lkr0000644000175000017500000000337211156521271013112 00000000000000// File: 18f2515i_e.lkr // Sample ICD2 linker script for the PIC18F2515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f676i.lkr0000644000175000017500000000257411156521271012535 00000000000000// Sample ICD2 linker command file for 16F676 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x53 SHAREBANK NAME=dbgspr0 START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0 START=0xA0 END=0xD3 PROTECTED SHAREBANK NAME=dbgspr0 START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=oscval // Oscillator value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16hv610.lkr0000644000175000017500000000123011156521271012524 00000000000000// Sample linker command file for 16HV610 // Based on 16F610 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f64j11i.lkr0000644000175000017500000000155111156521271012754 00000000000000// File: 18f64j11i.lkr // Sample ICD2 linker script for the PIC18F64J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr64.lkr0000644000175000017500000000107311156521271012443 00000000000000// Sample linker command file fo 16CR64 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c557.lkr0000644000175000017500000000125511156521271012352 00000000000000// Sample linker command file for 16C557 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8628_e.lkr0000644000175000017500000000315711156521271012755 00000000000000// File: 18f8628_e.lkr // Sample linker script for the PIC18F8628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c42a.lkr0000644000175000017500000000254411156521271012423 00000000000000// Sample linker command file for 17C42A // $Id: 17c42a.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18f2585i_e.lkr0000644000175000017500000000342111156521271013114 00000000000000// File: 18f2585i_e.lkr // Sample ICD2 linker script for the PIC18F2585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2550i.lkr0000644000175000017500000000261311156521271012602 00000000000000// File: 18f2550i.lkr // Sample ICD2 linker script for the PIC18F2550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf14k22_e.lkr0000644000175000017500000000162311156521271013261 00000000000000// File: 18lf14k22_e.lkr // Sample linker script for the PIC18LF14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c771.lkr0000644000175000017500000000213011156521271012341 00000000000000// Sample linker command file for 16C771 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0x1000 CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f452.lkr0000644000175000017500000000204611156521271012350 00000000000000// File: 18f452.lkr // Sample linker script for the PIC18F452 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j65.lkr0000644000175000017500000000303411156521271012614 00000000000000// File: 18f66j65.lkr // Sample linker script for the PIC18F66J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2410i.lkr0000644000175000017500000000171511156521271012577 00000000000000// File: 18f2410i.lkr // Sample ICD2 linker script for the PIC18F2410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/12c508a.lkr0000644000175000017500000000070611156521271012503 00000000000000// Sample linker command file for 12C508A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gprs START=0x07 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f45j10_e.lkr0000644000175000017500000000152111156521271013102 00000000000000// File: 18f45j10_e.lkr // Sample linker script for the PIC18F45J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j60.lkr0000644000175000017500000000303411156521271012612 00000000000000// File: 18f87j60.lkr // Sample linker script for the PIC18F87J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf26j11.lkr0000644000175000017500000000300111156521271012745 00000000000000// File: 18lf26j11_g.lkr // Generic linker script for the PIC18LF26J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f627.lkr0000644000175000017500000000214211156521271012347 00000000000000// Sample linker command file for 16F627 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x14F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f8620.lkr0000644000175000017500000000306211156521271012434 00000000000000// File: 18f8620.lkr // Sample linker script for the PIC18F8620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f252.lkr0000644000175000017500000000204611156521271012346 00000000000000// File: 18f252.lkr // Sample linker script for the PIC18F252 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4480_e.lkr0000644000175000017500000000205211156521271012736 00000000000000// File: 18f4480_e.lkr // Sample linker script for the PIC18F4480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f676.lkr0000644000175000017500000000227011156521271012355 00000000000000// Sample linker command file for 16F676 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x5F SHAREBANK NAME=gpr0 START=0xA0 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=oscval // Oscillator value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16lf1936.lkr0000644000175000017500000001443411156521271012616 00000000000000// File: 16lf1936_g.lkr // Generic linker script for the PIC16LF1936 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x1A0 END=0x1EF DATABANK NAME=gpr4 START=0x220 END=0x26F DATABANK NAME=gpr5 START=0x2A0 END=0x2EF DATABANK NAME=gpr6 START=0x320 END=0x32F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=PROG2 ROM=page2 // ROM code space - page2 SECTION NAME=PROG3 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2580i_e.lkr0000644000175000017500000000257311156521271013116 00000000000000// File: 18f2580i_e.lkr // Sample ICD2 linker script for the PIC18F2580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f886i.lkr0000644000175000017500000000355311156521271012536 00000000000000// Sample ICD2 linker command file for 16F886 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbgspr START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2455.lkr0000644000175000017500000000235011156521271012433 00000000000000// File: 18f2455.lkr // Sample linker script for the PIC18F2455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f873a.lkr0000644000175000017500000000206011156521271012512 00000000000000// Sample linker command file for 16F873 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7F SHAREBANK NAME=gpr0 START=0x120 END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xFF SHAREBANK NAME=gpr1 START=0x1A0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c65.lkr0000644000175000017500000000127011156521271012261 00000000000000// Sample linker command file for 16C65 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f85j90_e.lkr0000644000175000017500000000200011156521271013107 00000000000000// File: 18f85j90_e.lkr // Sample linker script for the PIC18F85J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j50i_e.lkr0000644000175000017500000000316011156521271013263 00000000000000// File: 18f66j50i_e.lkr // Sample ICD2 linker script for the PIC18F66J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr58a.lkr0000644000175000017500000000255711156521271012617 00000000000000// Sample linker command file for 16CR58A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x6 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x46 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x66 PROTECTED SHAREBANK NAME=gprnobnk START=0x7 END=0xF SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x47 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x67 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4682i_e.lkr0000644000175000017500000000342211156521271013115 00000000000000// File: 18f4682i_e.lkr // Sample ICD2 linker script for the PIC18F4682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13D7F CODEPAGE NAME=debug START=0x13D80 END=0x13FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f508.lkr0000644000175000017500000000070611156313115012341 00000000000000// Sample linker command file for 12F508 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gprs START=0x07 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j55i.lkr0000644000175000017500000000315711156521271012774 00000000000000// File: 18f86j55i.lkr // Sample ICD2 linker script for the PIC18F86J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f615.lkr0000644000175000017500000000120511156521271012337 00000000000000// Sample linker command file for 12F615 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c72.lkr0000644000175000017500000000107311156521271012260 00000000000000// Sample linker command file for 16C72 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2580.lkr0000644000175000017500000000241711156521271012436 00000000000000// File: 18f2580.lkr // Sample linker script for the PIC18F2580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f946.lkr0000644000175000017500000000275111156521271012361 00000000000000// Sample linker command file for 16F946 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x1A0 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f24j10_e.lkr0000644000175000017500000000152111156521271013077 00000000000000// File: 18f24j10_e.lkr // Sample linker script for the PIC18F24J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2455_e.lkr0000644000175000017500000000226111156521271012740 00000000000000// File: 18f2455_e.lkr // Sample linker script for the PIC18F2455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4680.lkr0000644000175000017500000000324511156521271012441 00000000000000// File: 18f4680.lkr // Sample linker script for the PIC18F4680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/10f200.lkr0000644000175000017500000000070511156313115012323 00000000000000// Sample linker command file for 10F200 LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFF CODEPAGE NAME=.idlocs START=0x100 END=0x103 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x10 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18lf13k22i.lkr0000644000175000017500000000153511156521271013127 00000000000000// File: 18lf13k22i.lkr // Sample ICD2 linker script for the PIC18LF13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f630i.lkr0000644000175000017500000000256511156521271012523 00000000000000// Sample ICD2 linker command file for 16F630 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x53 SHAREBANK NAME=dbgspr0 START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0 START=0xA0 END=0xD3 PROTECTED SHAREBANK NAME=dbgspr0 START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=oscval // Oscillator value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f46k20_g.lkr0000644000175000017500000000501111156521271013105 00000000000000// File: 18f46k20_g.lkr // Generic linker script for the PIC18F46K20 processor #DEFINE _CODEEND _DEBUGCODESTART - 1 #DEFINE _CEND _CODEEND + _DEBUGCODELEN #DEFINE _DATAEND _DEBUGDATASTART - 1 #DEFINE _DEND _DATAEND + _DEBUGDATALEN LIBPATH . #IFDEF _CRUNTIME #IFDEF _EXTENDEDMODE FILES c018i_e.o FILES clib_e.lib FILES p18f46k20_e.lib #ELSE FILES c018i.o FILES clib.lib FILES p18f46k20.lib #FI #FI #IFDEF _DEBUGCODESTART CODEPAGE NAME=page START=0x0 END=_CODEEND CODEPAGE NAME=debug START=_DEBUGCODESTART END=_CEND PROTECTED #ELSE CODEPAGE NAME=page START=0x0 END=0xFFFF #FI CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED #IFDEF _EXTENDEDMODE DATABANK NAME=gpre START=0x0 END=0x5F #ELSE ACCESSBANK NAME=accessram START=0x0 END=0x5F #FI DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF #IFDEF _DEBUGDATASTART DATABANK NAME=gpr14 START=0xE00 END=_DATAEND DATABANK NAME=dbgspr START=_DEBUGDATASTART END=_DEND PROTECTED #ELSE //no debug DATABANK NAME=gpr14 START=0xE00 END=0xEFF #FI DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED #IFDEF _CRUNTIME SECTION NAME=CONFIG ROM=config #IFDEF _DEBUGDATASTART STACK SIZE=0x100 RAM=gpr13 #ELSE STACK SIZE=0x100 RAM=gpr14 #FI #FI gputils-0.13.7/lkr/18f2321_e.lkr0000644000175000017500000000157311156521271012735 00000000000000// File: 18f2321_e.lkr // Sample linker script for the PIC18F2321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f258.lkr0000644000175000017500000000216311156521271012354 00000000000000// File: 18f258.lkr // Sample linker script for the PIC18F258 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j16i.lkr0000644000175000017500000000315711156521271012771 00000000000000// File: 18f86j16i.lkr // Sample ICD2 linker script for the PIC18F86J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4458i_e.lkr0000644000175000017500000000252411156521271013120 00000000000000// File: 18f4458i_e.lkr // Sample ICD2 linker script for the PIC18F4458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f635.lkr0000644000175000017500000000227611156521271012352 00000000000000// Sample linker command file for 12F635 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x0 END=0x0B PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x100 END=0x10B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x80 END=0x8B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x180 END=0x18B PROTECTED DATABANK NAME=sfr0 START=0x0C END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x8C END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x10C END=0x11F PROTECTED DATABANK NAME=gpr START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6527i.lkr0000644000175000017500000000341711156521271012615 00000000000000// File: 18f6527i.lkr // Sample ICD2 linker script for the PIC18F6527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f54.lkr0000644000175000017500000000071311156313115012257 00000000000000// Sample linker command file for 16F54 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8628i_e.lkr0000644000175000017500000000342211156521271013121 00000000000000// File: 18f8628i_e.lkr // Sample ICD2 linker script for the PIC18F8628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j90.lkr0000644000175000017500000000275411156521271012622 00000000000000// File: 18f66j90_g.lkr // Generic linker script for the PIC18F66J90 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF53 DATABANK NAME=sfr15 START=0xF54 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4520.lkr0000644000175000017500000000205011156521271012423 00000000000000// File: 18f4520.lkr // Sample linker script for the PIC18F4520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16lf723.lkr0000644000175000017500000000213011156521271012515 00000000000000// Sample linker command file for 16LF723 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x12F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/12f683.lkr0000644000175000017500000000145711156521271012355 00000000000000// Sample linker command file for 12F683 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4682i.lkr0000644000175000017500000000351111156521271012610 00000000000000// File: 18f4682i.lkr // Sample ICD2 linker script for the PIC18F4682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13D7F CODEPAGE NAME=debug START=0x13D80 END=0x13FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f685.lkr0000644000175000017500000000252011156521271012353 00000000000000// Sample linker command file for 16F685 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c782.lkr0000644000175000017500000000166111156521271012353 00000000000000// Sample linker command file for 16C782 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18C PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j15i.lkr0000644000175000017500000000304211156521271012761 00000000000000// File: 18f86j15i.lkr // Sample ICD2 linker script for the PIC18F86J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j60_e.lkr0000644000175000017500000000303511156521271013116 00000000000000// File: 18f86j60_e.lkr // Sample linker script for the PIC18F86J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6410_e.lkr0000644000175000017500000000157111156521271012736 00000000000000// File: 18f6410_e.lkr // Sample linker script for the PIC18F6410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j65i.lkr0000644000175000017500000000315711156521271012775 00000000000000// File: 18f86j65i.lkr // Sample ICD2 linker script for the PIC18F86J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f636.lkr0000644000175000017500000000236011156521271012351 00000000000000// Sample linker command file for 16F636 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x0 END=0x0B PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x100 END=0x10B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x80 END=0x8B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x180 END=0x18B PROTECTED DATABANK NAME=sfr0 START=0x0C END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x8C END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x10C END=0x11F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c65a.lkr0000644000175000017500000000127111156521271012423 00000000000000// Sample linker command file for 16C65A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16lf724i.lkr0000644000175000017500000000303211156521271012671 00000000000000// Sample ICD2 linker command file for 16LF724 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x124 DATABANK NAME=gpr2dbg START=0x125 END=0x12F PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c71.lkr0000644000175000017500000000101211156521271012250 00000000000000// Sample linker command file for 16C71 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x0B PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0x0C END=0x2F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f87j11.lkr0000644000175000017500000000303411156521271012606 00000000000000// File: 18f87j11.lkr // Sample linker script for the PIC18F87J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c57c.lkr0000644000175000017500000000255611156521271012435 00000000000000// Sample linker command file for 16C57C LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f85j10i_e.lkr0000644000175000017500000000212311156521271013256 00000000000000// File: 18f85j10i_e.lkr // Sample ICD2 linker script for the PIC18F85J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f629i.lkr0000644000175000017500000000240011156521271012513 00000000000000// Sample ICD2 linker command file for 12F629 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x53 SHAREBANK NAME=dbgspr START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xD3 PROTECTED SHAREBANK NAME=dbgspr START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4221.lkr0000644000175000017500000000147711156521271012435 00000000000000// File: 18f4221.lkr // Sample linker script for the PIC18F4221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f45k20.lkr0000644000175000017500000000205211156521271012600 00000000000000// File: 18f45k20.lkr // Sample linker script for the PIC18F45K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c64a.lkr0000644000175000017500000000107411156521271012423 00000000000000// Sample linker command file for 16C64A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f722i.lkr0000644000175000017500000000255211156521271012521 00000000000000// Sample ICD2 linker command file for 16F722 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xB4 DATABANK NAME=gpr1dbg START=0xB5 END=0xBF PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4431.lkr0000644000175000017500000000157211156521271012434 00000000000000// File: 18f4431.lkr // Sample linker script for the PIC18F4431 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4620.lkr0000644000175000017500000000315411156521271012432 00000000000000// File: 18f4620.lkr // Sample linker script for the PIC18F4620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4515.lkr0000644000175000017500000000303411156521271012432 00000000000000// File: 18f4515.lkr // Sample linker script for the PIC18F4515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2410.lkr0000644000175000017500000000145211156521271012424 00000000000000// File: 18f2410.lkr // Sample linker script for the PIC18F2410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2550i_e.lkr0000644000175000017500000000252411156521271013107 00000000000000// File: 18f2550i_e.lkr // Sample ICD2 linker script for the PIC18F2550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f57.lkr0000644000175000017500000000255511156521271012274 00000000000000// Sample linker command file for 16F57 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4620i_e.lkr0000644000175000017500000000351211156521271013105 00000000000000// File: 18f4620i_e.lkr // Sample ICD2 linker script for the PIC18F4620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf14k50i_e.lkr0000644000175000017500000000172311156521271013434 00000000000000// File: 18lf14k50i_e.lkr // Sample ICD2 linker script for the PIC18LF14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4220.lkr0000644000175000017500000000147711156521271012434 00000000000000// File: 18f4220.lkr // Sample linker script for the PIC18F4220 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f767i.lkr0000644000175000017500000000412511156521271012530 00000000000000// Sample ICD2 linker command file for 16F767 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x164 DATABANK NAME=dbgspr2 START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=dbgspr START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprs START=0x71 END=0x7F SHAREBANK NAME=gprs START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=PROG2 ROM=page2 // ROM code space SECTION NAME=PROG3 ROM=page3 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/16c58b.lkr0000644000175000017500000000255611156521271012435 00000000000000// Sample linker command file for 16C58B LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x6 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x46 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x66 PROTECTED SHAREBANK NAME=gprnobnk START=0x7 END=0xF SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x47 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x67 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f1220i.lkr0000644000175000017500000000165011156521271012573 00000000000000// File: 18f1220i.lkr // Sample ICD2 linker script for the PIC18F1220 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xE3F CODEPAGE NAME=debug START=0xE40 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xF3 DATABANK NAME=dbgspr START=0xF4 END=0xFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8720i.lkr0000644000175000017500000000332611156521271012611 00000000000000// File: 18f8720i.lkr // Sample ICD2 linker script for the PIC18F8720 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f458i.lkr0000644000175000017500000000242611156521271012531 00000000000000// File: 18f458i.lkr // Sample ICD2 linker script for the PIC18F458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8621.lkr0000644000175000017500000000306211156521271012435 00000000000000// File: 18f8621.lkr // Sample linker script for the PIC18F8621 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c712.lkr0000644000175000017500000000107411156521271012342 00000000000000// Sample linker command file for 16C712 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6621i.lkr0000644000175000017500000000332511156521271012606 00000000000000// File: 18f6621i.lkr // Sample ICD2 linker script for the PIC18F6621 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j10_e.lkr0000644000175000017500000000200011156521271013076 00000000000000// File: 18f66j10_e.lkr // Sample linker script for the PIC18F66J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf45j11.lkr0000644000175000017500000000300111156521271012746 00000000000000// File: 18lf45j11_g.lkr // Generic linker script for the PIC18LF45J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c642.lkr0000644000175000017500000000145111156521271012343 00000000000000// Sample linker command file for 16C642 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/10f204.lkr0000644000175000017500000000070511156313115012327 00000000000000// Sample linker command file for 10F204 LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFF CODEPAGE NAME=.idlocs START=0x100 END=0x103 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x10 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c65b.lkr0000644000175000017500000000127011156521271012423 00000000000000// Sample linker command file for 16C65B LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f1230i.lkr0000644000175000017500000000165011156521271012574 00000000000000// File: 18f1230i.lkr // Sample ICD2 linker script for the PIC18F1230 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xE3F CODEPAGE NAME=debug START=0xE40 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xF3 DATABANK NAME=dbgspr START=0xF4 END=0xFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j50_e.lkr0000644000175000017500000000303511156521271013113 00000000000000// File: 18f66j50_e.lkr // Sample linker script for the PIC18F66J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f63j11i.lkr0000644000175000017500000000155111156521271012753 00000000000000// File: 18f63j11i.lkr // Sample ICD2 linker script for the PIC18F63J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k50i.lkr0000644000175000017500000000162711156521271013132 00000000000000// File: 18lf13k50i.lkr // Sample ICD2 linker script for the PIC18LF13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12c509a.lkr0000644000175000017500000000076611156521271012512 00000000000000// Sample linker command file for 12C509A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gpr0 START=0x07 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f87j60i_e.lkr0000644000175000017500000000316111156521271013270 00000000000000// File: 18f87j60i_e.lkr // Sample ICD2 linker script for the PIC18F87J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f45k20_e.lkr0000644000175000017500000000205411156521271013106 00000000000000// File: 18f45k20_e.lkr // Sample linker script for the PIC18F45K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j60_e.lkr0000644000175000017500000000303611156521271013120 00000000000000// File: 18f87j60_e.lkr // Sample linker script for the PIC18F87J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c62a.lkr0000644000175000017500000000107411156521271012421 00000000000000// Sample linker command file for 16C62A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f45j10i_e.lkr0000644000175000017500000000164411156521271013261 00000000000000// File: 18f45j10i_e.lkr // Sample ICD2 linker script for the PIC18F45J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f884i.lkr0000644000175000017500000000311411156521271012525 00000000000000// Sample ICD2 linker command file for 16F884 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbgspr START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c77.lkr0000644000175000017500000000256211156521271012271 00000000000000// Sample linker command file for 16C77 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8622_e.lkr0000644000175000017500000000315611156521271012746 00000000000000// File: 18f8622_e.lkr // Sample linker script for the PIC18F8622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f628.lkr0000644000175000017500000000214211156521271012350 00000000000000// Sample linker command file for 16F628 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x14F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18lf14k50.lkr0000644000175000017500000000171311156521271012756 00000000000000// File: 18lf14k50.lkr // Sample linker script for the PIC18LF14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c54c.lkr0000644000175000017500000000071411156521271012424 00000000000000// Sample linker command file for 16C54C LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f876ai.lkr0000644000175000017500000000354111156521271012673 00000000000000// Sample linker command file for 16f876a used with the ICD LIBPATH . CODEPAGE NAME=page0 START=0x0000 END=0x07FF CODEPAGE NAME=page1 START=0x0800 END=0x0FFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug3 START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 CODEPAGE NAME=.config START=0x2007 END=0x2007 CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=dbgspr0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=dbgspr0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x020 END=0x06F DATABANK NAME=gpr1 START=0x0A0 END=0x0EF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbggpr3 START=0x1E5 END=0x1EF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16cr54.lkr0000644000175000017500000000071411156521271012443 00000000000000// Sample linker command file for 16CR54 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j11_e.lkr0000644000175000017500000000303511156521271013112 00000000000000// File: 18f86j11_e.lkr // Sample linker script for the PIC18F86J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf14k22i_e.lkr0000644000175000017500000000163111156521271013431 00000000000000// File: 18lf14k22i_e.lkr // Sample ICD2 linker script for the PIC18LF14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j50_e.lkr0000644000175000017500000000303611156521271013115 00000000000000// File: 18f67j50_e.lkr // Sample linker script for the PIC18F67J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2320.lkr0000644000175000017500000000150011156521271012416 00000000000000// File: 18f2320.lkr // Sample linker script for the PIC18F2320 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4580_e.lkr0000644000175000017500000000233011156521271012736 00000000000000// File: 18f4580_e.lkr // Sample linker script for the PIC18F4580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k50i_e.lkr0000644000175000017500000000163111156521271013431 00000000000000// File: 18lf13k50i_e.lkr // Sample ICD2 linker script for the PIC18LF13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c58a.lkr0000644000175000017500000000255611156521271012434 00000000000000// Sample linker command file for 16C58A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x6 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x46 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x66 PROTECTED SHAREBANK NAME=gprnobnk START=0x7 END=0xF SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x47 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x67 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/10f222i.lkr0000644000175000017500000000113111156521271012476 00000000000000// Sample linker command file for 10F222 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 10F222.lkr but named 10F222i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x08 PROTECTED DATABANK NAME=gprs START=0x09 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/10f220i.lkr0000644000175000017500000000113111156521271012474 00000000000000// Sample linker command file for 10F220 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 10F220.lkr but named 10F220i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0x0FF CODEPAGE NAME=.idlocs START=0x100 END=0x103 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x08 PROTECTED DATABANK NAME=gprs START=0x10 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f73.lkr0000644000175000017500000000146511156521271012271 00000000000000// Sample linker command file for 16F73 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4331.lkr0000644000175000017500000000157211156521271012433 00000000000000// File: 18f4331.lkr // Sample linker script for the PIC18F4331 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j65_e.lkr0000644000175000017500000000303611156521271013122 00000000000000// File: 18f66j65_e.lkr // Sample linker script for the PIC18F66J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2553_e.lkr0000644000175000017500000000226111156521271012737 00000000000000// File: 18f2553_e.lkr // Sample linker script for the PIC18F2553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2520i.lkr0000644000175000017500000000231311156521271012574 00000000000000// File: 18f2520i.lkr // Sample ICD2 linker script for the PIC18F2520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c67.lkr0000644000175000017500000000256211156521271012270 00000000000000// Sample linker command file for 16C67 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f726i.lkr0000644000175000017500000000346511156521271012531 00000000000000// Sample ICD2 linker command file for 16F726 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=gpr3dbg START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c923.lkr0000644000175000017500000000204511156521271012345 00000000000000// Sample linker command file for 16C923 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f916.lkr0000644000175000017500000000275011156521271012355 00000000000000// Sample linker command file for 16F916 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6527.lkr0000644000175000017500000000315411156521271012442 00000000000000// File: 18f6527.lkr // Sample linker script for the PIC18F6527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j15_e.lkr0000644000175000017500000000272111156521271013115 00000000000000// File: 18f66j15_e.lkr // Sample linker script for the PIC18F66J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1330i.lkr0000644000175000017500000000165111156521271012576 00000000000000// File: 18f1330i.lkr // Sample ICD2 linker script for the PIC18F1330 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1E3F CODEPAGE NAME=debug START=0x1E40 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xF3 DATABANK NAME=dbgspr START=0xF4 END=0xFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2510_e.lkr0000644000175000017500000000202311156521271012724 00000000000000// File: 18f2510_e.lkr // Sample linker script for the PIC18F2510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6520i.lkr0000644000175000017500000000247711156521271012613 00000000000000// File: 18f6520i.lkr // Sample ICD2 linker script for the PIC18F6520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7D7F CODEPAGE NAME=debug START=0x7D80 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24j11.lkr0000644000175000017500000000277711156521271012612 00000000000000// File: 18f24j11_g.lkr // Generic linker script for the PIC18F24J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4480i_e.lkr0000644000175000017500000000231511156521271013111 00000000000000// File: 18f4480i_e.lkr // Sample ICD2 linker script for the PIC18F4480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/10f200i.lkr0000644000175000017500000000113611156313115012473 00000000000000// Sample ICD2 linker command file for 10F200 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 10F200.lkr but named 10F200i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFF CODEPAGE NAME=.idlocs START=0x100 END=0x103 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x10 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c925.lkr0000644000175000017500000000204511156521271012347 00000000000000// Sample linker command file for 16C925 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/12ce673.lkr0000644000175000017500000000127311156521271012512 00000000000000// Sample linker command file for 12CE673 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8310i_e.lkr0000644000175000017500000000203411156521271013103 00000000000000// File: 18f8310i_e.lkr // Sample ICD2 linker script for the PIC18F8310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8525.lkr0000644000175000017500000000306211156521271012440 00000000000000// File: 18f8525.lkr // Sample linker script for the PIC18F8525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f88i.lkr0000644000175000017500000000345411156521271012450 00000000000000// Sample ICD2 linker command file for 16F88 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=sfrnobnk START=0x71 END=0x7F SHAREBANK NAME=sfrnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=sfrnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=sfrnobnk START=0x1F1 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbg3 START=0x1E5 END=0x1EF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=DEBUG ROM=debug // ICD debug executive SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/rf509af.lkr0000644000175000017500000000106611156521271012674 00000000000000// Sample linker command file for rfPIC12C509AF // $Id: rf509af.lkr,v 1.3 2006/02/04 00:06:47 nairnj Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gpr0 START=0x07 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/mcv14a.lkr0000644000175000017500000000235511156521271012615 00000000000000// Sample linker command file for MCV14A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=flashmem START=0x400 END=0x43F PROTECTED CODEPAGE NAME=.idlocs START=0x440 END=0x443 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x0C PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x2C PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x4C PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x6C PROTECTED SHAREBANK NAME=gprnobnk START=0x0D END=0x0F SHAREBANK NAME=gprnobnk START=0x2D END=0x2F SHAREBANK NAME=gprnobnk START=0x4D END=0x4F SHAREBANK NAME=gprnobnk START=0x6D END=0x6F DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=FLASHDATA ROM=flashmem // Flash Data Memory SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4515i.lkr0000644000175000017500000000327711156521271012614 00000000000000// File: 18f4515i.lkr // Sample ICD2 linker script for the PIC18F4515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26k20.lkr0000644000175000017500000000315611156521271012605 00000000000000// File: 18f26k20.lkr // Sample linker script for the PIC18F26K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8720.lkr0000644000175000017500000000306311156521271012436 00000000000000// File: 18f8720.lkr // Sample linker script for the PIC18F8720 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4423.lkr0000644000175000017500000000157211156521271012435 00000000000000// File: 18f4423.lkr // Sample linker script for the PIC18F4423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2458i.lkr0000644000175000017500000000261311156521271012611 00000000000000// File: 18f2458i.lkr // Sample ICD2 linker script for the PIC18F2458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/rf675ki.lkr0000644000175000017500000000237111156313115012711 00000000000000// Sample ICD2 linker command file for rfPIC12F675K LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x53 SHAREBANK NAME=dbgspr START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xD3 SHAREBANK NAME=dbgspr START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/10f202i.lkr0000644000175000017500000000113711156313115012476 00000000000000// Sample ICD2 linker command file for 10F202 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 10F202.lkr but named 10F202i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x08 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4523.lkr0000644000175000017500000000205011156521271012426 00000000000000// File: 18f4523.lkr // Sample linker script for the PIC18F4523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4539.lkr0000644000175000017500000000205011156521271012435 00000000000000// File: 18f4539.lkr // Sample linker script for the PIC18F4539 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x57F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/rf675h.lkr0000644000175000017500000000207311156313115012534 00000000000000// Sample linker command file for the rfPIC12F675H LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x5F SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xDF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18lf44j50.lkr0000644000175000017500000000300111156521271012750 00000000000000// File: 18lf44j50_g.lkr // Generic linker script for the PIC18LF44J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f97j60.lkr0000644000175000017500000000303411156521271012613 00000000000000// File: 18f97j60.lkr // Sample linker script for the PIC18F97J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2620_e.lkr0000644000175000017500000000324711156521271012737 00000000000000// File: 18f2620_e.lkr // Sample linker script for the PIC18F2620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr57c.lkr0000644000175000017500000000255711156521271012620 00000000000000// Sample linker command file for 16CR57C LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c63.lkr0000644000175000017500000000126711156521271012265 00000000000000// Sample linker command file for 16C63 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c622.lkr0000644000175000017500000000107411156521271012342 00000000000000// Sample linker command file for 16C622 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f65j50.lkr0000644000175000017500000000303311156521271012604 00000000000000// File: 18f65j50.lkr // Sample linker script for the PIC18F65J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24k20_e.lkr0000644000175000017500000000157611156521271013113 00000000000000// File: 18f24k20_e.lkr // Sample linker script for the PIC18F24K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j60.lkr0000644000175000017500000000303411156521271012610 00000000000000// File: 18f67j60.lkr // Sample linker script for the PIC18F67J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f917.lkr0000644000175000017500000000275011156521271012356 00000000000000// Sample linker command file for 16F917 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f8722i_e.lkr0000644000175000017500000000342211156521271013114 00000000000000// File: 18f8722i_e.lkr // Sample ICD2 linker script for the PIC18F8722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr54a.lkr0000644000175000017500000000071511156521271012605 00000000000000// Sample linker command file for 16CR54A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8628i.lkr0000644000175000017500000000342011156521271012613 00000000000000// File: 18f8628i.lkr // Sample ICD2 linker script for the PIC18F8628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4450.lkr0000644000175000017500000000147511156521271012437 00000000000000// File: 18f4450.lkr // Sample linker script for the PIC18F4450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8585.lkr0000644000175000017500000000324511156521271012451 00000000000000// File: 18f8585.lkr // Sample linker script for the PIC18F8585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2520_e.lkr0000644000175000017500000000214311156521271012730 00000000000000// File: 18f2520_e.lkr // Sample linker script for the PIC18F2520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j15.lkr0000644000175000017500000000177611156521271012623 00000000000000// File: 18f85j15.lkr // Sample linker script for the PIC18F85J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16hv540.lkr0000644000175000017500000000071511156521271012535 00000000000000// Sample linker command file for 16HV540 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18lf24j50.lkr0000644000175000017500000000300111156521271012746 00000000000000// File: 18lf24j50_g.lkr // Generic linker script for the PIC18LF24J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2553i.lkr0000644000175000017500000000261311156521271012605 00000000000000// File: 18f2553i.lkr // Sample ICD2 linker script for the PIC18F2553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c621a.lkr0000644000175000017500000000117511156521271012504 00000000000000// Sample linker command file for 16C621A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f96j65.lkr0000644000175000017500000000303411156521271012617 00000000000000// File: 18f96j65.lkr // Sample linker script for the PIC18F96J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j15i_e.lkr0000644000175000017500000000212311156521271013263 00000000000000// File: 18f85j15i_e.lkr // Sample ICD2 linker script for the PIC18F85J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f887i.lkr0000644000175000017500000000355011156521271012534 00000000000000// Sample ICD2 linker command file for 16F887 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbgspr START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f96j65i.lkr0000644000175000017500000000315711156521271012776 00000000000000// File: 18f96j65i.lkr // Sample ICD2 linker script for the PIC18F96J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c432.lkr0000644000175000017500000000127011156521271012337 00000000000000// Sample linker command file for 16C432 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c621.lkr0000644000175000017500000000101311156521271012332 00000000000000// Sample linker command file for 16C621 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f63j90_e.lkr0000644000175000017500000000143011156521271013111 00000000000000// File: 18f63j90_e.lkr // Sample linker script for the PIC18F63J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j16i_e.lkr0000644000175000017500000000316111156521271013266 00000000000000// File: 18f66j16i_e.lkr // Sample ICD2 linker script for the PIC18F66J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6390_e.lkr0000644000175000017500000000157111156521271012745 00000000000000// File: 18f6390_e.lkr // Sample linker script for the PIC18F6390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2525.lkr0000644000175000017500000000315411156521271012434 00000000000000// File: 18f2525.lkr // Sample linker script for the PIC18F2525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1330_e.lkr0000644000175000017500000000150111156521271012723 00000000000000// File: 18f1330_e.lkr // Sample linker script for the PIC18F1330 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2423i_e.lkr0000644000175000017500000000213011156521271013077 00000000000000// File: 18f2423i_e.lkr // Sample ICD2 linker script for the PIC18F2423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f84.lkr0000644000175000017500000000120011156521271012256 00000000000000// Sample linker command file for 16F84 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x4F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f13k50.lkr0000644000175000017500000000161711156521271012604 00000000000000// File: 18f13k50.lkr // Sample linker script for the PIC18F13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf46j11.lkr0000644000175000017500000000300111156521271012747 00000000000000// File: 18lf46j11_g.lkr // Generic linker script for the PIC18LF46J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2455i.lkr0000644000175000017500000000261311156521271012606 00000000000000// File: 18f2455i.lkr // Sample ICD2 linker script for the PIC18F2455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f716i.lkr0000644000175000017500000000166411156521271012527 00000000000000// Sample ICD2 linker command file for 16f716 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4580i.lkr0000644000175000017500000000266211156521271012613 00000000000000// File: 18f4580i.lkr // Sample ICD2 linker script for the PIC18F4580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f97j60_e.lkr0000644000175000017500000000303611156521271013121 00000000000000// File: 18f97j60_e.lkr // Sample linker script for the PIC18F97J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16hv785i.lkr0000644000175000017500000000305511156521271012721 00000000000000// Sample ICD2 linker command file for 16HV785 // Based on 16F785 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=dbgspr0 START=0x65 END=0x6F PROTECTED DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=dbgspr2 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr2 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr2 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr2 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gpr2 START=0x71 END=0x7F SHAREBANK NAME=gpr2 START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gpr2 START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gpr2 START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f87j50.lkr0000644000175000017500000000303411156521271012611 00000000000000// File: 18f87j50.lkr // Sample linker script for the PIC18F87J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17cr42.lkr0000644000175000017500000000254411156521271012444 00000000000000// Sample linker command file for 17CR42 // $Id: 17cr42.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18f2525i.lkr0000644000175000017500000000341711156521271012607 00000000000000// File: 18f2525i.lkr // Sample ICD2 linker script for the PIC18F2525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j50i.lkr0000644000175000017500000000315611156521271012763 00000000000000// File: 18f65j50i.lkr // Sample ICD2 linker script for the PIC18F65J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f631i.lkr0000644000175000017500000000300211156521271012507 00000000000000// Sample ICD2 linker command file for 16F677 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f877i.lkr0000644000175000017500000000354411156521271012536 00000000000000// Sample linker command file for 16f877 used with the ICD LIBPATH . CODEPAGE NAME=page0 START=0x0000 END=0x07FF CODEPAGE NAME=page1 START=0x0800 END=0x0FFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug3 START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 CODEPAGE NAME=.config START=0x2007 END=0x2007 CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=dbgspr0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=dbgspr0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x020 END=0x06F DATABANK NAME=gpr1 START=0x0A0 END=0x0EF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbggpr3 START=0x1E5 END=0x1EF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f914i.lkr0000644000175000017500000000325011156521271012520 00000000000000// Sample ICD2 linker command file for 16F914 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=gpr2dbg START=0x165 END=0x16F PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c620.lkr0000644000175000017500000000101311156521271012331 00000000000000// Sample linker command file for 16C620 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f677.lkr0000644000175000017500000000225711156521271012363 00000000000000// Sample linker command file for 16F677 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4550i.lkr0000644000175000017500000000261311156521271012604 00000000000000// File: 18f4550i.lkr // Sample ICD2 linker script for the PIC18F4550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26k20_e.lkr0000644000175000017500000000316011156521271013104 00000000000000// File: 18f26k20_e.lkr // Sample linker script for the PIC18F26K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4585i.lkr0000644000175000017500000000351011156521271012611 00000000000000// File: 18f4585i.lkr // Sample ICD2 linker script for the PIC18F4585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c52.lkr0000644000175000017500000000071311156521271012256 00000000000000// Sample linker command file for 16c52 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17F CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x180 END=0x183 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f13k22_e.lkr0000644000175000017500000000152711156521271013107 00000000000000// File: 18f13k22_e.lkr // Sample linker script for the PIC18F13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26k20i_e.lkr0000644000175000017500000000342311156521271013257 00000000000000// File: 18f26k20i_e.lkr // Sample ICD2 linker script for the PIC18F26K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f14k22i.lkr0000644000175000017500000000162511156521271012754 00000000000000// File: 18f14k22i.lkr // Sample ICD2 linker script for the PIC18F14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f63j90i.lkr0000644000175000017500000000155111156521271012762 00000000000000// File: 18f63j90i.lkr // Sample ICD2 linker script for the PIC18F63J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf46j50.lkr0000644000175000017500000000300111156521271012752 00000000000000// File: 18lf46j50_g.lkr // Generic linker script for the PIC18LF46J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4420.lkr0000644000175000017500000000157211156521271012432 00000000000000// File: 18f4420.lkr // Sample linker script for the PIC18F4420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/12hv609.lkr0000644000175000017500000000123111156521271012531 00000000000000// Sample linker command file for 12HV609 // Based on 12F609 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16hv785.lkr0000644000175000017500000000224611156521271012551 00000000000000// Sample linker command file for 16HV785 // Based on 16F785 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gpr2 START=0x70 END=0x7F SHAREBANK NAME=gpr2 START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gpr2 START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gpr2 START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f85j50i.lkr0000644000175000017500000000315611156521271012765 00000000000000// File: 18f85j50i.lkr // Sample ICD2 linker script for the PIC18F85J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16ce625.lkr0000644000175000017500000000126211156521271012511 00000000000000// Sample linker command file for 16CE625 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f25j10i_e.lkr0000644000175000017500000000164411156521271013257 00000000000000// File: 18f25j10i_e.lkr // Sample ICD2 linker script for the PIC18F25J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf45j50.lkr0000644000175000017500000000300111156521271012751 00000000000000// File: 18lf45j50_g.lkr // Generic linker script for the PIC18LF45J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4553i_e.lkr0000644000175000017500000000252411156521271013114 00000000000000// File: 18f4553i_e.lkr // Sample ICD2 linker script for the PIC18F4553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/rf509ag.lkr0000644000175000017500000000106611156521271012675 00000000000000// Sample linker command file for rfPIC12C509AG // $Id: rf509ag.lkr,v 1.3 2006/02/04 00:06:47 nairnj Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gpr0 START=0x07 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16lf722i.lkr0000644000175000017500000000255311156521271012676 00000000000000// Sample ICD2 linker command file for 16LF722 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xB4 DATABANK NAME=gpr1dbg START=0xB5 END=0xBF PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f14k50.lkr0000644000175000017500000000171111156521271012600 00000000000000// File: 18f14k50.lkr // Sample linker script for the PIC18F14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f506i.lkr0000644000175000017500000000236711156521271012525 00000000000000// Sample linker command file for 16f506 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 16F506.lkr but named 16F506i.lkr LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x0C PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x2C PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x4C PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x6C PROTECTED SHAREBANK NAME=gprnobnk START=0x0D END=0x0F SHAREBANK NAME=gprnobnk START=0x2D END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x4D END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x6D END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4610i_e.lkr0000644000175000017500000000337211156521271013110 00000000000000// File: 18f4610i_e.lkr // Sample ICD2 linker script for the PIC18F4610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j50i_e.lkr0000644000175000017500000000316011156521271013262 00000000000000// File: 18f65j50i_e.lkr // Sample ICD2 linker script for the PIC18F65J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f876i.lkr0000644000175000017500000000354011156521271012531 00000000000000// Sample linker command file for 16f876 used with the ICD LIBPATH . CODEPAGE NAME=page0 START=0x0000 END=0x07FF CODEPAGE NAME=page1 START=0x0800 END=0x0FFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug3 START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 CODEPAGE NAME=.config START=0x2007 END=0x2007 CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=dbgspr0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=dbgspr0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x020 END=0x06F DATABANK NAME=gpr1 START=0x0A0 END=0x0EF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbggpr3 START=0x1E5 END=0x1EF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f727.lkr0000644000175000017500000000256311156521271012357 00000000000000// Sample linker command file for 16F727 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8527.lkr0000644000175000017500000000315411156521271012444 00000000000000// File: 18f8527.lkr // Sample linker script for the PIC18F8527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f785i.lkr0000644000175000017500000000302711156521271012530 00000000000000// Sample ICD2 linker command file for 16F785 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=dbgspr0 START=0x65 END=0x6F PROTECTED DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=dbgspr2 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr2 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr2 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr2 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gpr2 START=0x71 END=0x7F SHAREBANK NAME=gpr2 START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gpr2 START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gpr2 START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f913i.lkr0000644000175000017500000000325111156521271012520 00000000000000// Sample ICD2 linker command file for 16F913 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=gpr2dbg START=0x165 END=0x16F PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c716.lkr0000644000175000017500000000107411156521271012346 00000000000000// Sample linker command file for 16C716 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16lf1933.lkr0000644000175000017500000001331411156521271012607 00000000000000// File: 16lf1933_g.lkr // Generic linker script for the PIC16LF1933 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f747.lkr0000644000175000017500000000274711156521271012365 00000000000000// Sample linker command file for 16F747 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprs START=0x70 END=0x7F SHAREBANK NAME=gprs START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/16f84a.lkr0000644000175000017500000000120111156521271012420 00000000000000// Sample linker command file for 16F84A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x4F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f684i.lkr0000644000175000017500000000314411156521271012526 00000000000000// Sample ICD2 linker command file for 16F684 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=gpr0dbg START=0x65 END=0x6F PROTECTED DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=CALIBR ROM=.config // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/12f615i.lkr0000644000175000017500000000161511156521271012515 00000000000000// Sample ICD2 linker command file for 12F615 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f45j10.lkr0000644000175000017500000000142611156521271012602 00000000000000// File: 18f45j10.lkr // Sample linker script for the PIC18F45J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f44j11.lkr0000644000175000017500000000277711156521271012614 00000000000000// File: 18f44j11_g.lkr // Generic linker script for the PIC18F44J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k50.lkr0000644000175000017500000000162111156521271012753 00000000000000// File: 18lf13k50.lkr // Sample linker script for the PIC18LF13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f84j90_e.lkr0000644000175000017500000000143011156521271013114 00000000000000// File: 18f84j90_e.lkr // Sample linker script for the PIC18F84J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12ce519.lkr0000644000175000017500000000076611156521271012517 00000000000000// Sample linker command file for 12CE519 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gpr0 START=0x07 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4685_e.lkr0000644000175000017500000000315711156521271012754 00000000000000// File: 18f4685_e.lkr // Sample linker script for the PIC18F4685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2680.lkr0000644000175000017500000000324511156521271012437 00000000000000// File: 18f2680.lkr // Sample linker script for the PIC18F2680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c74b.lkr0000644000175000017500000000127011156521271012423 00000000000000// Sample linker command file for 16C74B LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8520i.lkr0000644000175000017500000000247711156521271012615 00000000000000// File: 18f8520i.lkr // Sample ICD2 linker script for the PIC18F8520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7D7F CODEPAGE NAME=debug START=0x7D80 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f44k20i_e.lkr0000644000175000017500000000204111156521271013252 00000000000000// File: 18f44k20i_e.lkr // Sample ICD2 linker script for the PIC18F44K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f872i.lkr0000644000175000017500000000317511156521271012531 00000000000000// Sample linker command file for 16f872 used with the ICD LIBPATH . CODEPAGE NAME=page0 START=0x0000 END=0x06FF CODEPAGE NAME=debug3 START=0x0700 END=0x07FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 CODEPAGE NAME=.config START=0x2007 END=0x2007 CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED SHAREBANK NAME=dbgspr0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=dbgspr0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SHAREBANK NAME=gprnobnk0 START=0x020 END=0x06F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x16F PROTECTED SHAREBANK NAME=gprnobnk1 START=0x0A0 END=0x0B4 SHAREBANK NAME=dbggpr3 START=0x0B5 END=0x0BF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1A0 END=0x1B4 PROTECTED SHAREBANK NAME=dbggpr3 START=0x1B5 END=0x1BF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c620a.lkr0000644000175000017500000000117511156521271012503 00000000000000// Sample linker command file for 16C620A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f65j15.lkr0000644000175000017500000000177611156521271012621 00000000000000// File: 18f65j15.lkr // Sample linker script for the PIC18F65J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j55_e.lkr0000644000175000017500000000303611156521271013121 00000000000000// File: 18f66j55_e.lkr // Sample linker script for the PIC18F66J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2458i_e.lkr0000644000175000017500000000252411156521271013116 00000000000000// File: 18f2458i_e.lkr // Sample ICD2 linker script for the PIC18F2458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j16_e.lkr0000644000175000017500000000303611156521271013120 00000000000000// File: 18f86j16_e.lkr // Sample linker script for the PIC18F86J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2682i_e.lkr0000644000175000017500000000342211156521271013113 00000000000000// File: 18f2682i_e.lkr // Sample ICD2 linker script for the PIC18F2682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13D7F CODEPAGE NAME=debug START=0x13D80 END=0x13FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c442.lkr0000644000175000017500000000135611156521271012347 00000000000000// File: 18c442.lkr // Sample linker script for the PIC18C442 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x300007 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f63j90i_e.lkr0000644000175000017500000000155311156521271013270 00000000000000// File: 18f63j90i_e.lkr // Sample ICD2 linker script for the PIC18F63J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4423i_e.lkr0000644000175000017500000000213011156521271013101 00000000000000// File: 18f4423i_e.lkr // Sample ICD2 linker script for the PIC18F4423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f63j11.lkr0000644000175000017500000000142611156521271012603 00000000000000// File: 18f63j11.lkr // Sample linker script for the PIC18F63J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j60i.lkr0000644000175000017500000000315711156521271012771 00000000000000// File: 18f87j60i.lkr // Sample ICD2 linker script for the PIC18F87J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4455.lkr0000644000175000017500000000235011156521271012435 00000000000000// File: 18f4455.lkr // Sample linker script for the PIC18F4455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6723i_e.lkr0000644000175000017500000000342211156521271013113 00000000000000// File: 18f6723i_e.lkr // Sample ICD2 linker script for the PIC18F6723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4331i.lkr0000644000175000017500000000203511156521271012577 00000000000000// File: 18f4331i.lkr // Sample ICD2 linker script for the PIC18F4331 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/mcv08a.lkr0000644000175000017500000000137611156521271012622 00000000000000// Sample linker command file for MCV08A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x09 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x29 PROTECTED SHAREBANK NAME=gprnobnk START=0x0A END=0x0F SHAREBANK NAME=gprnobnk START=0x2A END=0x2F DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j55i_e.lkr0000644000175000017500000000316111156521271013273 00000000000000// File: 18f86j55i_e.lkr // Sample ICD2 linker script for the PIC18F86J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j55_e.lkr0000644000175000017500000000303611156521271013123 00000000000000// File: 18f86j55_e.lkr // Sample linker script for the PIC18F86J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f44j10i.lkr0000644000175000017500000000155111156521271012751 00000000000000// File: 18f44j10i.lkr // Sample ICD2 linker script for the PIC18F44J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j11i_e.lkr0000644000175000017500000000212311156521271013255 00000000000000// File: 18f65j11i_e.lkr // Sample ICD2 linker script for the PIC18F65J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j11_e.lkr0000644000175000017500000000303611156521271013114 00000000000000// File: 18f87j11_e.lkr // Sample linker script for the PIC18F87J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8493i_e.lkr0000644000175000017500000000203411156521271013117 00000000000000// File: 18f8493i_e.lkr // Sample ICD2 linker script for the PIC18F8493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2610.lkr0000644000175000017500000000303411156521271012424 00000000000000// File: 18f2610.lkr // Sample linker script for the PIC18F2610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f690.lkr0000644000175000017500000000252011156521271012347 00000000000000// Sample linker command file for 16F690 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4610i.lkr0000644000175000017500000000327711156521271012610 00000000000000// File: 18f4610i.lkr // Sample ICD2 linker script for the PIC18F4610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/rf675f.lkr0000644000175000017500000000207411156313115012533 00000000000000// Sample linker command file for the rfPIC12F675F LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x5F SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xDF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2539i.lkr0000644000175000017500000000217611156521271012615 00000000000000// File: 18f2539i.lkr // Sample ICD2 linker script for the PIC18F2539 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x57F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c658.lkr0000644000175000017500000000204311156521271012352 00000000000000// File: 18c658.lkr // Sample linker script for the PIC18C658 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x300007 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/10f222.lkr0000644000175000017500000000070611156313115012330 00000000000000// Sample linker command file for 10F222 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x08 PROTECTED DATABANK NAME=gprs START=0x09 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2450i.lkr0000644000175000017500000000174011156521271012601 00000000000000// File: 18f2450i.lkr // Sample ICD2 linker script for the PIC18F2450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j90.lkr0000644000175000017500000000275511156521271012626 00000000000000// File: 18f87j90_g.lkr // Generic linker script for the PIC18F87J90 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF53 DATABANK NAME=sfr15 START=0xF54 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c56.lkr0000644000175000017500000000110711156521271012260 00000000000000// Sample linker command file for 16C56 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c710.lkr0000644000175000017500000000101311156521271012331 00000000000000// Sample linker command file for 16C710 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x0B PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0x0C END=0x2F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4585i_e.lkr0000644000175000017500000000342111156521271013116 00000000000000// File: 18f4585i_e.lkr // Sample ICD2 linker script for the PIC18F4585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4423_e.lkr0000644000175000017500000000166511156521271012744 00000000000000// File: 18f4423_e.lkr // Sample linker script for the PIC18F4423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4420i_e.lkr0000644000175000017500000000213011156521271013076 00000000000000// File: 18f4420i_e.lkr // Sample ICD2 linker script for the PIC18F4420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4620i.lkr0000644000175000017500000000341711156521271012605 00000000000000// File: 18f4620i.lkr // Sample ICD2 linker script for the PIC18F4620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c765.lkr0000644000175000017500000000272611156521271012357 00000000000000// Sample linker command file for 16C765 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.usrlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=usbport START=0x1A0 END=0x1DF PROTECTED SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=USRLOCS ROM=.usrlocs // User-configurable locations SECTION NAME=DEVICEID ROM=.device_id // Device ID gputils-0.13.7/lkr/18f83j11_e.lkr0000644000175000017500000000143011156521271013104 00000000000000// File: 18f83j11_e.lkr // Sample linker script for the PIC18F83J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/ps500.lkr0000644000175000017500000000140711156521271012366 00000000000000// File: PS500.lkr // Sample linker script for the PS500 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x3BFFFF PROTECTED CODEPAGE NAME=test START=0x3C0000 END=0x3FFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f685i.lkr0000644000175000017500000000332211156521271012525 00000000000000// Sample ICD2 linker command file for 16F685 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbgspr START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f85j90.lkr0000644000175000017500000000177611156521271012626 00000000000000// File: 18f85j90.lkr // Sample linker script for the PIC18F85J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25k20i.lkr0000644000175000017500000000231511156521271012751 00000000000000// File: 18f25k20i.lkr // Sample ICD2 linker script for the PIC18F25K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf44j11.lkr0000644000175000017500000000300111156521271012745 00000000000000// File: 18lf44j11_g.lkr // Generic linker script for the PIC18LF44J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j11i_e.lkr0000644000175000017500000000212311156521271013257 00000000000000// File: 18f85j11i_e.lkr // Sample ICD2 linker script for the PIC18F85J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j60_e.lkr0000644000175000017500000000303511156521271013114 00000000000000// File: 18f66j60_e.lkr // Sample linker script for the PIC18F66J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j16_e.lkr0000644000175000017500000000303611156521271013116 00000000000000// File: 18f66j16_e.lkr // Sample linker script for the PIC18F66J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f72.lkr0000644000175000017500000000165011156521271012264 00000000000000// Sample linker command file for 16F72 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x3F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x40 END=0x7F SHAREBANK NAME=gprnobnk START=0xC0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x140 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1C0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2221i.lkr0000644000175000017500000000174211156521271012577 00000000000000// File: 18f2221i.lkr // Sample ICD2 linker script for the PIC18F2221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xDBF CODEPAGE NAME=debug START=0xDC0 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f876a.lkr0000644000175000017500000000275011156521271012523 00000000000000// Sample linker command file for 16F876 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f66j15i_e.lkr0000644000175000017500000000304411156521271013265 00000000000000// File: 18f66j15i_e.lkr // Sample ICD2 linker script for the PIC18F66J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f63j11i_e.lkr0000644000175000017500000000155311156521271013261 00000000000000// File: 18f63j11i_e.lkr // Sample ICD2 linker script for the PIC18F63J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j10_e.lkr0000644000175000017500000000272111156521271013113 00000000000000// File: 18f87j10_e.lkr // Sample linker script for the PIC18F87J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4420i.lkr0000644000175000017500000000203511156521271012576 00000000000000// File: 18f4420i.lkr // Sample ICD2 linker script for the PIC18F4420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8585i.lkr0000644000175000017500000000351011156521271012615 00000000000000// File: 18f8585i.lkr // Sample ICD2 linker script for the PIC18F8585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8628.lkr0000644000175000017500000000315511156521271012447 00000000000000// File: 18f8628.lkr // Sample linker script for the PIC18F8628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c54.lkr0000644000175000017500000000071311156521271012260 00000000000000// Sample linker command file for 16C54 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f67j10.lkr0000644000175000017500000000271711156521271012612 00000000000000// File: 18f67j10.lkr // Sample linker script for the PIC18F67J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f722.lkr0000644000175000017500000000165011156521271012346 00000000000000// Sample linker command file for 16F722 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8620i.lkr0000644000175000017500000000332511156521271012607 00000000000000// File: 18f8620i.lkr // Sample ICD2 linker script for the PIC18F8620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j90i_e.lkr0000644000175000017500000000212311156521271013266 00000000000000// File: 18f85j90i_e.lkr // Sample ICD2 linker script for the PIC18F85J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8621i.lkr0000644000175000017500000000332511156521271012610 00000000000000// File: 18f8621i.lkr // Sample ICD2 linker script for the PIC18F8621 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6493_e.lkr0000644000175000017500000000157111156521271012751 00000000000000// File: 18f6493_e.lkr // Sample linker script for the PIC18F6493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6390.lkr0000644000175000017500000000156711156521271012446 00000000000000// File: 18f6390.lkr // Sample linker script for the PIC18F6390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c756a.lkr0000644000175000017500000000462511156521271012521 00000000000000// Sample linker command file for 17C756A // $Id: 17c756a.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED SHAREBANK NAME=sfrnobnk START=0x400 END=0x40F PROTECTED SHAREBANK NAME=sfrnobnk START=0x500 END=0x50F PROTECTED SHAREBANK NAME=sfrnobnk START=0x600 END=0x60F PROTECTED SHAREBANK NAME=sfrnobnk START=0x700 END=0x70F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED DATABANK NAME=sfr4 START=0x410 END=0x417 PROTECTED DATABANK NAME=sfr5 START=0x510 END=0x517 PROTECTED DATABANK NAME=sfr6 START=0x610 END=0x617 PROTECTED DATABANK NAME=sfr7 START=0x710 END=0x717 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=sfrprod START=0x418 END=0x419 PROTECTED SHAREBANK NAME=sfrprod START=0x518 END=0x519 PROTECTED SHAREBANK NAME=sfrprod START=0x618 END=0x619 PROTECTED SHAREBANK NAME=sfrprod START=0x718 END=0x719 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F SHAREBANK NAME=registers START=0x41A END=0x41F SHAREBANK NAME=registers START=0x51A END=0x51F SHAREBANK NAME=registers START=0x61A END=0x61F SHAREBANK NAME=registers START=0x71A END=0x71F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF DATABANK NAME=gpr2 START=0x220 END=0x2FF DATABANK NAME=gpr3 START=0x320 END=0x3FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18f6310i_e.lkr0000644000175000017500000000203411156521271013101 00000000000000// File: 18f6310i_e.lkr // Sample ICD2 linker script for the PIC18F6310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f84j90i.lkr0000644000175000017500000000155111156521271012765 00000000000000// File: 18f84j90i.lkr // Sample ICD2 linker script for the PIC18F84J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f46j11.lkr0000644000175000017500000000277711156521271012616 00000000000000// File: 18f46j11_g.lkr // Generic linker script for the PIC18F46J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6490.lkr0000644000175000017500000000156711156521271012447 00000000000000// File: 18f6490.lkr // Sample linker script for the PIC18F6490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2450i_e.lkr0000644000175000017500000000165111156521271013106 00000000000000// File: 18f2450i_e.lkr // Sample ICD2 linker script for the PIC18F2450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25j10_e.lkr0000644000175000017500000000152111156521271013100 00000000000000// File: 18f25j10_e.lkr // Sample linker script for the PIC18F25J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4585.lkr0000644000175000017500000000324511156521271012445 00000000000000// File: 18f4585.lkr // Sample linker script for the PIC18F4585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j10_e.lkr0000644000175000017500000000200011156521271013077 00000000000000// File: 18f85j10_e.lkr // Sample linker script for the PIC18F85J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2331.lkr0000644000175000017500000000157211156521271012431 00000000000000// File: 18f2331.lkr // Sample linker script for the PIC18F2331 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6628i_e.lkr0000644000175000017500000000342211156521271013117 00000000000000// File: 18f6628i_e.lkr // Sample ICD2 linker script for the PIC18F6628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j15_e.lkr0000644000175000017500000000200011156521271013102 00000000000000// File: 18f65j15_e.lkr // Sample linker script for the PIC18F65J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16lf1937.lkr0000644000175000017500000001443411156521271012617 00000000000000// File: 16lf1937_g.lkr // Generic linker script for the PIC16LF1937 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x1A0 END=0x1EF DATABANK NAME=gpr4 START=0x220 END=0x26F DATABANK NAME=gpr5 START=0x2A0 END=0x2EF DATABANK NAME=gpr6 START=0x320 END=0x32F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=PROG2 ROM=page2 // ROM code space - page2 SECTION NAME=PROG3 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2510i_e.lkr0000644000175000017500000000226611156521271013106 00000000000000// File: 18f2510i_e.lkr // Sample ICD2 linker script for the PIC18F2510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4610_e.lkr0000644000175000017500000000312711156521271012735 00000000000000// File: 18f4610_e.lkr // Sample linker script for the PIC18F4610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j90.lkr0000644000175000017500000000275411156521271012624 00000000000000// File: 18f86j90_g.lkr // Generic linker script for the PIC18F86J90 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF53 DATABANK NAME=sfr15 START=0xF54 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f505.lkr0000644000175000017500000000214411156521271012344 00000000000000// Sample linker command file for 16f505 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x07 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x08 END=0x0F SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c74.lkr0000644000175000017500000000126711156521271012267 00000000000000// Sample linker command file for 16C74 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6627i_e.lkr0000644000175000017500000000342211156521271013116 00000000000000// File: 18f6627i_e.lkr // Sample ICD2 linker script for the PIC18F6627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c601.lkr0000644000175000017500000000160711156521271012343 00000000000000// File: 18c601.lkr // Sample linker script for the PIC18C601 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFFF CODEPAGE NAME=config START=0x300000 END=0x300006 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2685i_e.lkr0000644000175000017500000000342211156521271013116 00000000000000// File: 18f2685i_e.lkr // Sample ICD2 linker script for the PIC18F2685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c433.lkr0000644000175000017500000000127011156521271012340 00000000000000// Sample linker command file for 16C433 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4550.lkr0000644000175000017500000000235011156521271012431 00000000000000// File: 18f4550.lkr // Sample linker script for the PIC18F4550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1230_e.lkr0000644000175000017500000000150011156521271012721 00000000000000// File: 18f1230_e.lkr // Sample linker script for the PIC18F1230 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2439.lkr0000644000175000017500000000157211156521271012442 00000000000000// File: 18f2439.lkr // Sample linker script for the PIC18F2439 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x27F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c76.lkr0000644000175000017500000000256211156521271012270 00000000000000// Sample linker command file for 16C76 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c505.lkr0000644000175000017500000000177211156521271012347 00000000000000// Sample linker command file for 16C505 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=shr0 START=0x08 END=0x0F SHAREBANK NAME=shr0 START=0x28 END=0x2F PROTECTED SHAREBANK NAME=shr0 START=0x48 END=0x4F PROTECTED SHAREBANK NAME=shr0 START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/12f683i.lkr0000644000175000017500000000217411156521271012523 00000000000000// Sample ICD2 linker command file for 12F683 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=gpr0dbg START=0x65 END=0x6F PROTECTED DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f448.lkr0000644000175000017500000000170511156521271012356 00000000000000// File: 18f448.lkr // Sample linker script for the PIC18F448 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f873i.lkr0000644000175000017500000000254611156521271012533 00000000000000// Sample ICD2 linker command file for 16F873 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7D SHAREBANK NAME=dbg0 START=0x7E END=0x7F PROTECTED SHAREBANK NAME=gpr0 START=0x120 END=0x17D PROTECTED SHAREBANK NAME=dbg0 START=0x17E END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xF3 SHAREBANK NAME=dbg1 START=0xF4 END=0xFF PROTECTED SHAREBANK NAME=gpr1 START=0x1A0 END=0x1F3 PROTECTED SHAREBANK NAME=dbg1 START=0x1F4 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f84j11i_e.lkr0000644000175000017500000000155311156521271013264 00000000000000// File: 18f84j11i_e.lkr // Sample ICD2 linker script for the PIC18F84J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr620a.lkr0000644000175000017500000000101511156521271012656 00000000000000// Sample linker command file for 16CR620A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f723.lkr0000644000175000017500000000212711156521271012347 00000000000000// Sample linker command file for 16F723 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x12F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8527_e.lkr0000644000175000017500000000315611156521271012752 00000000000000// File: 18f8527_e.lkr // Sample linker script for the PIC18F8527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f648a.lkr0000644000175000017500000000310611156521271012514 00000000000000// Sample linker command file for 16F648A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.oscval START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=.test START=0x2009 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space SECTION NAME=PROG2 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVID ROM=.devid // device id SECTION NAME=OSCVAL ROM=.oscval // Oscillator value SECTION NAME=TEST ROM=.test // Test program memory SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4550i_e.lkr0000644000175000017500000000252411156521271013111 00000000000000// File: 18f4550i_e.lkr // Sample ICD2 linker script for the PIC18F4550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24k20i_e.lkr0000644000175000017500000000204111156521271013250 00000000000000// File: 18f24k20i_e.lkr // Sample ICD2 linker script for the PIC18F24K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2550.lkr0000644000175000017500000000235011156521271012427 00000000000000// File: 18f2550.lkr // Sample linker script for the PIC18F2550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2321.lkr0000644000175000017500000000150011156521271012417 00000000000000// File: 18f2321.lkr // Sample linker script for the PIC18F2321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f43k20.lkr0000644000175000017500000000141211156521271012575 00000000000000// File: 18f43k20_g.lkr // Generic linker script for the PIC18F43K20 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr57a.lkr0000644000175000017500000000255711156521271012616 00000000000000// Sample linker command file for 16CR57A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f97j60i_e.lkr0000644000175000017500000000316111156521271013271 00000000000000// File: 18f97j60i_e.lkr // Sample ICD2 linker script for the PIC18F97J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f723i.lkr0000644000175000017500000000303111156521271012513 00000000000000// Sample ICD2 linker command file for 16F723 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x124 DATABANK NAME=gpr2dbg START=0x125 END=0x12F PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4520i.lkr0000644000175000017500000000231311156521271012576 00000000000000// File: 18f4520i.lkr // Sample ICD2 linker script for the PIC18F4520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f96j60i.lkr0000644000175000017500000000315611156521271012770 00000000000000// File: 18f96j60i.lkr // Sample ICD2 linker script for the PIC18F96J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4520i_e.lkr0000644000175000017500000000240611156521271013105 00000000000000// File: 18f4520i_e.lkr // Sample ICD2 linker script for the PIC18F4520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c54a.lkr0000644000175000017500000000071411156521271012422 00000000000000// Sample linker command file for 16C54A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2610i.lkr0000644000175000017500000000327711156521271012606 00000000000000// File: 18f2610i.lkr // Sample ICD2 linker script for the PIC18F2610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f688i.lkr0000644000175000017500000000417411156521271012536 00000000000000// Sample ICD2 linker command file for 16F688 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbgspr2 START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgspr START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=DEBUG ROM=debug // ICD2 debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f8622i_e.lkr0000644000175000017500000000342111156521271013112 00000000000000// File: 18f8622i_e.lkr // Sample ICD2 linker script for the PIC18F8622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6627_e.lkr0000644000175000017500000000315711156521271012752 00000000000000// File: 18f6627_e.lkr // Sample linker script for the PIC18F6627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12hv609i.lkr0000644000175000017500000000161611156521271012711 00000000000000// Sample ICD2 linker command file for 12HV609 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8722i.lkr0000644000175000017500000000342011156521271012606 00000000000000// File: 18f8722i.lkr // Sample ICD2 linker script for the PIC18F8722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6520.lkr0000644000175000017500000000223411156521271012431 00000000000000// File: 18f6520.lkr // Sample linker script for the PIC18F6520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8627_e.lkr0000644000175000017500000000315711156521271012754 00000000000000// File: 18f8627_e.lkr // Sample linker script for the PIC18F8627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f874i.lkr0000644000175000017500000000252011156521271012524 00000000000000// Sample ICD2 linker command file for 16F874 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7D SHAREBANK NAME=dbg0 START=0x7E END=0x7F PROTECTED SHAREBANK NAME=gpr0 START=0x120 END=0x17D SHAREBANK NAME=dbg0 START=0x17E END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xF3 SHAREBANK NAME=dbg1 START=0xF4 END=0xFF PROTECTED SHAREBANK NAME=gpr1 START=0x1A0 END=0x1F3 SHAREBANK NAME=dbg1 START=0x1F4 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/10f206i.lkr0000644000175000017500000000113711156313115012502 00000000000000// Sample ICD2 linker command file for 10F206 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 10F206.lkr but named 10F206i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x08 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/hcs1370.lkr0000644000175000017500000000244511156521271012612 00000000000000// Sample linker command file for HCS1370 // $Id: hcs1370.lkr,v 1.4 2006/02/04 00:06:47 nairnj Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0x7FF END=0x7FF PROTECTED SHAREBANK NAME=sfr_shr START=0x0 END=0x4 PROTECTED SHAREBANK NAME=sfr_shr START=0x20 END=0x24 PROTECTED SHAREBANK NAME=sfr_shr START=0x40 END=0x44 PROTECTED SHAREBANK NAME=sfr_shr START=0x60 END=0x64 PROTECTED DATABANK NAME=sfr_bnk0 START=0x5 END=0x7 PROTECTED DATABANK NAME=sfr_bnk1 START=0x25 END=0x27 PROTECTED DATABANK NAME=sfr_bnk2 START=0x45 END=0x47 PROTECTED DATABANK NAME=sfr_bnk3 START=0x65 END=0x67 PROTECTED SHAREBANK NAME=gpr_shr START=0x8 END=0xF SHAREBANK NAME=gpr_shr START=0x28 END=0x2F SHAREBANK NAME=gpr_shr START=0x48 END=0x4F SHAREBANK NAME=gpr_shr START=0x68 END=0x6F DATABANK NAME=gpr_bnk0 START=0x10 END=0x1F DATABANK NAME=gpr_bnk1 START=0x30 END=0x3F DATABANK NAME=gpr_bnk2 START=0x50 END=0x5F DATABANK NAME=gpr_bnk3 START=0x70 END=0x7F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f44k20_e.lkr0000644000175000017500000000157611156521271013115 00000000000000// File: 18f44k20_e.lkr // Sample linker script for the PIC18F44K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j55.lkr0000644000175000017500000000303411156521271012615 00000000000000// File: 18f86j55.lkr // Sample linker script for the PIC18F86J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c622a.lkr0000644000175000017500000000125611156521271012505 00000000000000// Sample linker command file for 16C622A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18c601i.lkr0000644000175000017500000000154611156521271012516 00000000000000// File: 18c601i.lkr // Sample ICD2 linker script for the PIC18C601 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFFF CODEPAGE NAME=config START=0x300000 END=0x300006 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c56a.lkr0000644000175000017500000000111011156521271012413 00000000000000// Sample linker command file for 16C56A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c770.lkr0000644000175000017500000000174311156521271012351 00000000000000// Sample linker command file for 16C770 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4455i.lkr0000644000175000017500000000261311156521271012610 00000000000000// File: 18f4455i.lkr // Sample ICD2 linker script for the PIC18F4455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4523_e.lkr0000644000175000017500000000214311156521271012735 00000000000000// File: 18f4523_e.lkr // Sample linker script for the PIC18F4523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f83.lkr0000644000175000017500000000120011156521271012255 00000000000000// Sample linker command file for 16F83 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x2F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4439.lkr0000644000175000017500000000157211156521271012444 00000000000000// File: 18f4439.lkr // Sample linker script for the PIC18F4439 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x27F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2680i_e.lkr0000644000175000017500000000342111156521271013110 00000000000000// File: 18f2680i_e.lkr // Sample ICD2 linker script for the PIC18F2680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6628.lkr0000644000175000017500000000315511156521271012445 00000000000000// File: 18f6628.lkr // Sample linker script for the PIC18F6628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2321i_e.lkr0000644000175000017500000000203611156521271013101 00000000000000// File: 18f2321i_e.lkr // Sample ICD2 linker script for the PIC18F2321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f87i.lkr0000644000175000017500000000345411156521271012447 00000000000000// Sample ICD2 linker command file for 16F87 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=sfrnobnk START=0x71 END=0x7F SHAREBANK NAME=sfrnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=sfrnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=sfrnobnk START=0x1F1 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbg3 START=0x1E5 END=0x1EF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=DEBUG ROM=debug // ICD debug executive SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2431.lkr0000644000175000017500000000157211156521271012432 00000000000000// File: 18f2431.lkr // Sample linker script for the PIC18F2431 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j10.lkr0000644000175000017500000000177611156521271012614 00000000000000// File: 18f65j10.lkr // Sample linker script for the PIC18F65J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f84j11i.lkr0000644000175000017500000000155111156521271012756 00000000000000// File: 18f84j11i.lkr // Sample ICD2 linker script for the PIC18F84J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4439i.lkr0000644000175000017500000000172011156521271012610 00000000000000// File: 18f4439i.lkr // Sample ICD2 linker script for the PIC18F4439 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2DBF CODEPAGE NAME=debug START=0x2DC0 END=0x2FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x27F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4525.lkr0000644000175000017500000000315411156521271012436 00000000000000// File: 18f4525.lkr // Sample linker script for the PIC18F4525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf26j50.lkr0000644000175000017500000000300111156521271012750 00000000000000// File: 18lf26j50_g.lkr // Generic linker script for the PIC18LF26J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6723.lkr0000644000175000017500000000315511156521271012441 00000000000000// File: 18f6723.lkr // Sample linker script for the PIC18F6723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f689i.lkr0000644000175000017500000000332411156521271012533 00000000000000// Sample ICD2 linker command file for 16F689 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbgspr START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/ps810.lkr0000644000175000017500000000127211156521271012372 00000000000000// File: PS810.lkr // Sample linker script for the PS810 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=dpram START=0xE00 END=0xE3F PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6723i.lkr0000644000175000017500000000342011156521271012605 00000000000000// File: 18f6723i.lkr // Sample ICD2 linker script for the PIC18F6723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8527i_e.lkr0000644000175000017500000000342111156521271013116 00000000000000// File: 18f8527i_e.lkr // Sample ICD2 linker script for the PIC18F8527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c44.lkr0000644000175000017500000000254311156521271012263 00000000000000// Sample linker command file for 17C44 // $Id: 17c44.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/16f88.lkr0000644000175000017500000000256511156521271012301 00000000000000// Sample linker command file for 16F88 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=sfrnobnk START=0x70 END=0x7F SHAREBANK NAME=sfrnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=sfrnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=sfrnobnk START=0x1F0 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6525i.lkr0000644000175000017500000000332511156521271012611 00000000000000// File: 18f6525i.lkr // Sample ICD2 linker script for the PIC18F6525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j15i_e.lkr0000644000175000017500000000304411156521271013267 00000000000000// File: 18f86j15i_e.lkr // Sample ICD2 linker script for the PIC18F86J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6393i_e.lkr0000644000175000017500000000203411156521271013114 00000000000000// File: 18f6393i_e.lkr // Sample ICD2 linker script for the PIC18F6393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4580i_e.lkr0000644000175000017500000000257311156521271013120 00000000000000// File: 18f4580i_e.lkr // Sample ICD2 linker script for the PIC18F4580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f629.lkr0000644000175000017500000000207711156521271012354 00000000000000// Sample linker command file for 12F629 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x5F SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f66j10.lkr0000644000175000017500000000177611156521271012615 00000000000000// File: 18f66j10.lkr // Sample linker script for the PIC18F66J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f45k20i_e.lkr0000644000175000017500000000231711156521271013261 00000000000000// File: 18f45k20i_e.lkr // Sample ICD2 linker script for the PIC18F45K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1330i_e.lkr0000644000175000017500000000174411156521271013105 00000000000000// File: 18f1330i_e.lkr // Sample ICD2 linker script for the PIC18F1330 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1E3F CODEPAGE NAME=debug START=0x1E40 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xF3 DATABANK NAME=dbgspr START=0xF4 END=0xFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4685i.lkr0000644000175000017500000000351111156521271012613 00000000000000// File: 18f4685i.lkr // Sample ICD2 linker script for the PIC18F4685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f13k22.lkr0000644000175000017500000000152511156521271012601 00000000000000// File: 18f13k22.lkr // Sample linker script for the PIC18F13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4221i.lkr0000644000175000017500000000174211156521271012601 00000000000000// File: 18f4221i.lkr // Sample ICD2 linker script for the PIC18F4221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xDBF CODEPAGE NAME=debug START=0xDC0 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4520_e.lkr0000644000175000017500000000214311156521271012732 00000000000000// File: 18f4520_e.lkr // Sample linker script for the PIC18F4520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f510.lkr0000644000175000017500000000141411156521271012333 00000000000000// Sample linker command file for 12F510 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x09 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x29 PROTECTED SHAREBANK NAME=gprnobnk START=0x0A END=0x0F SHAREBANK NAME=gprnobnk START=0x2A END=0x2F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6723_e.lkr0000644000175000017500000000315711156521271012747 00000000000000// File: 18f6723_e.lkr // Sample linker script for the PIC18F6723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f874.lkr0000644000175000017500000000205411156521271012355 00000000000000// Sample linker command file for 16F873 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7F SHAREBANK NAME=gpr0 START=0x120 END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xFF SHAREBANK NAME=gpr1 START=0x1A0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4410_e.lkr0000644000175000017500000000154511156521271012735 00000000000000// File: 18f4410_e.lkr // Sample linker script for the PIC18F4410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f882i.lkr0000644000175000017500000000264611156521271012534 00000000000000// Sample IDC2 linker command file for 16F882 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x66F CODEPAGE NAME=debug START=0x670 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18D PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xB3 DATABANK NAME=dbgspr START=0xB4 END=0xBF PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f64j90_e.lkr0000644000175000017500000000143011156521271013112 00000000000000// File: 18f64j90_e.lkr // Sample linker script for the PIC18F64J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8627.lkr0000644000175000017500000000315511156521271012446 00000000000000// File: 18f8627.lkr // Sample linker script for the PIC18F8627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4515_e.lkr0000644000175000017500000000312711156521271012741 00000000000000// File: 18f4515_e.lkr // Sample linker script for the PIC18F4515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1330.lkr0000644000175000017500000000140611156521271012423 00000000000000// File: 18f1330.lkr // Sample linker script for the PIC18F1330 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4682.lkr0000644000175000017500000000324611156521271012444 00000000000000// File: 18f4682.lkr // Sample linker script for the PIC18F4682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f675i.lkr0000644000175000017500000000240011156521271012514 00000000000000// Sample ICD2 linker command file for 12F675 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x53 SHAREBANK NAME=dbgspr START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xD3 PROTECTED SHAREBANK NAME=dbgspr START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f242.lkr0000644000175000017500000000157011156521271012346 00000000000000// File: 18f242.lkr // Sample linker script for the PIC18F242 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6390i.lkr0000644000175000017500000000203211156521271012603 00000000000000// File: 18f6390i.lkr // Sample ICD2 linker script for the PIC18F6390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2610_e.lkr0000644000175000017500000000312711156521271012733 00000000000000// File: 18f2610_e.lkr // Sample linker script for the PIC18F2610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8390i.lkr0000644000175000017500000000203211156521271012605 00000000000000// File: 18f8390i.lkr // Sample ICD2 linker script for the PIC18F8390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/14000.lkr0000644000175000017500000000146411156521271012166 00000000000000// Sample linker command file for 14000 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x07FF CODEPAGE NAME=page1 START=0x0800 END=0x0FBF CODEPAGE NAME=caldata START=0x0FC0 END=0x0FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=CALDATA ROM=caldata // Calibration data SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8627i_e.lkr0000644000175000017500000000342211156521271013120 00000000000000// File: 18f8627i_e.lkr // Sample ICD2 linker script for the PIC18F8627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f84j90i_e.lkr0000644000175000017500000000155311156521271013273 00000000000000// File: 18f84j90i_e.lkr // Sample ICD2 linker script for the PIC18F84J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f13k50_e.lkr0000644000175000017500000000162111156521271013103 00000000000000// File: 18f13k50_e.lkr // Sample linker script for the PIC18F13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c801.lkr0000644000175000017500000000161011156521271012337 00000000000000// File: 18c801.lkr // Sample linker script for the PIC18C801 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFFF CODEPAGE NAME=config START=0x300000 END=0x300006 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6310i.lkr0000644000175000017500000000203211156521271012573 00000000000000// File: 18f6310i.lkr // Sample ICD2 linker script for the PIC18F6310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2420_e.lkr0000644000175000017500000000166511156521271012737 00000000000000// File: 18f2420_e.lkr // Sample linker script for the PIC18F2420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j50i.lkr0000644000175000017500000000315611156521271012766 00000000000000// File: 18f86j50i.lkr // Sample ICD2 linker script for the PIC18F86J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j11.lkr0000644000175000017500000000303311156521271012602 00000000000000// File: 18f66j11.lkr // Sample linker script for the PIC18F66J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4685i_e.lkr0000644000175000017500000000342211156521271013120 00000000000000// File: 18f4685i_e.lkr // Sample ICD2 linker script for the PIC18F4685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6310_e.lkr0000644000175000017500000000157111156521271012735 00000000000000// File: 18f6310_e.lkr // Sample linker script for the PIC18F6310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2221.lkr0000644000175000017500000000147711156521271012433 00000000000000// File: 18f2221.lkr // Sample linker script for the PIC18F2221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2480i_e.lkr0000644000175000017500000000231511156521271013107 00000000000000// File: 18f2480i_e.lkr // Sample ICD2 linker script for the PIC18F2480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f1934.lkr0000644000175000017500000001331211156521271012432 00000000000000// File: 16f1934_g.lkr // Generic linker script for the PIC16F1934 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8680.lkr0000644000175000017500000000324511156521271012445 00000000000000// File: 18f8680.lkr // Sample linker script for the PIC18F8680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6722.lkr0000644000175000017500000000315511156521271012440 00000000000000// File: 18f6722.lkr // Sample linker script for the PIC18F6722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/10f220.lkr0000644000175000017500000000070611156313115012326 00000000000000// Sample linker command file for 10F220 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x0FF CODEPAGE NAME=.idlocs START=0x100 END=0x103 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x08 PROTECTED DATABANK NAME=gprs START=0x10 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f14k50_e.lkr0000644000175000017500000000171311156521271013106 00000000000000// File: 18f14k50_e.lkr // Sample linker script for the PIC18F14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24j10.lkr0000644000175000017500000000142611156521271012577 00000000000000// File: 18f24j10.lkr // Sample linker script for the PIC18F24J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c715.lkr0000644000175000017500000000107411156521271012345 00000000000000// Sample linker command file for 16C715 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16cr54c.lkr0000644000175000017500000000071511156521271012607 00000000000000// Sample linker command file for 16CR54C LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f66j11i.lkr0000644000175000017500000000315611156521271012761 00000000000000// File: 18f66j11i.lkr // Sample ICD2 linker script for the PIC18F66J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f74.lkr0000644000175000017500000000146511156521271012272 00000000000000// Sample linker command file for 16F74 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f66j16i.lkr0000644000175000017500000000315711156521271012767 00000000000000// File: 18f66j16i.lkr // Sample ICD2 linker script for the PIC18F66J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f448i.lkr0000644000175000017500000000215011156521271012522 00000000000000// File: 18f448i.lkr // Sample ICD2 linker script for the PIC18F448 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f627a.lkr0000644000175000017500000000272411156521271012516 00000000000000// Sample linker command file for 16F627A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10B PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x14F SHAREBANK NAME=gprnobnk0 START=0x70 END=0x7E SHAREBANK NAME=gprnobnk0 START=0xF0 END=0xFE PROTECTED SHAREBANK NAME=gprnobnk0 START=0x170 END=0x17E PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1F0 END=0x1FE PROTECTED SHAREBANK NAME=gprnobnk1 START=0x7F END=0x7F SHAREBANK NAME=gprnobnk1 START=0xFF END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x17F END=0x17F PROTECTED DATABANK NAME=testreg START=0x1FF END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f877ai.lkr0000644000175000017500000000354511156521271012700 00000000000000// Sample linker command file for 16f877a used with the ICD LIBPATH . CODEPAGE NAME=page0 START=0x0000 END=0x07FF CODEPAGE NAME=page1 START=0x0800 END=0x0FFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug3 START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 CODEPAGE NAME=.config START=0x2007 END=0x2007 CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=dbgspr0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=dbgspr0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x020 END=0x06F DATABANK NAME=gpr1 START=0x0A0 END=0x0EF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=dbggpr3 START=0x1E5 END=0x1EF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16cr58b.lkr0000644000175000017500000000255711156521271012620 00000000000000// Sample linker command file for 16CR58B LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x6 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x46 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x66 PROTECTED SHAREBANK NAME=gprnobnk START=0x7 END=0xF SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x47 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x67 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8493i.lkr0000644000175000017500000000203211156521271012611 00000000000000// File: 18f8493i.lkr // Sample ICD2 linker script for the PIC18F8493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c55a.lkr0000644000175000017500000000071411156521271012423 00000000000000// Sample linker command file for 16C55A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x7 PROTECTED DATABANK NAME=gprs START=0x8 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4510.lkr0000644000175000017500000000173011156521271012426 00000000000000// File: 18f4510.lkr // Sample linker script for the PIC18F4510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j10i_e.lkr0000644000175000017500000000212311156521271013254 00000000000000// File: 18f65j10i_e.lkr // Sample ICD2 linker script for the PIC18F65J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6720.lkr0000644000175000017500000000306311156521271012434 00000000000000// File: 18f6720.lkr // Sample linker script for the PIC18F6720 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8410i_e.lkr0000644000175000017500000000203411156521271013104 00000000000000// File: 18f8410i_e.lkr // Sample ICD2 linker script for the PIC18F8410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1320.lkr0000644000175000017500000000140611156521271012422 00000000000000// File: 18f1320.lkr // Sample linker script for the PIC18F1320 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j50_e.lkr0000644000175000017500000000303611156521271013117 00000000000000// File: 18f87j50_e.lkr // Sample linker script for the PIC18F87J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c554.lkr0000644000175000017500000000101311156521271012337 00000000000000// Sample linker command file for 16C554 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f87.lkr0000644000175000017500000000257211156521271012276 00000000000000// Sample linker command file for 16F87 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=sfrnobnk START=0x70 END=0x7F SHAREBANK NAME=sfrnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=sfrnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=sfrnobnk START=0x1F0 END=0x1FF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f65j90.lkr0000644000175000017500000000177611156521271012624 00000000000000// File: 18f65j90.lkr // Sample linker script for the PIC18F65J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12c508.lkr0000644000175000017500000000070711156521271012343 00000000000000// Sample linker command file for 12C508 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gprs START=0x07 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2585i.lkr0000644000175000017500000000351011156521271012607 00000000000000// File: 18f2585i.lkr // Sample ICD2 linker script for the PIC18F2585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8310i.lkr0000644000175000017500000000203211156521271012575 00000000000000// File: 18f8310i.lkr // Sample ICD2 linker script for the PIC18F8310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j90i.lkr0000644000175000017500000000212111156521271012756 00000000000000// File: 18f65j90i.lkr // Sample ICD2 linker script for the PIC18F65J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j50_e.lkr0000644000175000017500000000303511156521271013114 00000000000000// File: 18f85j50_e.lkr // Sample linker script for the PIC18F85J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4410i.lkr0000644000175000017500000000171511156521271012601 00000000000000// File: 18f4410i.lkr // Sample ICD2 linker script for the PIC18F4410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c61.lkr0000644000175000017500000000101211156521271012247 00000000000000// Sample linker command file for 16C61 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x2F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4423i.lkr0000644000175000017500000000203511156521271012601 00000000000000// File: 18f4423i.lkr // Sample ICD2 linker script for the PIC18F4423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2585_e.lkr0000644000175000017500000000315611156521271012750 00000000000000// File: 18f2585_e.lkr // Sample linker script for the PIC18F2585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f44j10.lkr0000644000175000017500000000142611156521271012601 00000000000000// File: 18f44j10.lkr // Sample linker script for the PIC18F44J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f526.lkr0000644000175000017500000000242711156521271012353 00000000000000// Sample linker command file for 16F526 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=flashmem START=0x400 END=0x43F PROTECTED CODEPAGE NAME=.idlocs START=0x440 END=0x443 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x0C PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x2C PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x4C PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x6C PROTECTED SHAREBANK NAME=gprnobnk START=0x0D END=0x0F SHAREBANK NAME=gprnobnk START=0x2D END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x4D END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x6D END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=FLASHDATA ROM=flashmem // Flash Data Memory SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4510i_e.lkr0000644000175000017500000000226611156521271013110 00000000000000// File: 18f4510i_e.lkr // Sample ICD2 linker script for the PIC18F4510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j10_e.lkr0000644000175000017500000000200011156521271013075 00000000000000// File: 18f65j10_e.lkr // Sample linker script for the PIC18F65J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f64j90.lkr0000644000175000017500000000142611156521271012613 00000000000000// File: 18f64j90.lkr // Sample linker script for the PIC18F64J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2685.lkr0000644000175000017500000000324611156521271012445 00000000000000// File: 18f2685.lkr // Sample linker script for the PIC18F2685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8310.lkr0000644000175000017500000000156711156521271012440 00000000000000// File: 18f8310.lkr // Sample linker script for the PIC18F8310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j11i_e.lkr0000644000175000017500000000316011156521271013260 00000000000000// File: 18f66j11i_e.lkr // Sample ICD2 linker script for the PIC18F66J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4458i.lkr0000644000175000017500000000261311156521271012613 00000000000000// File: 18f4458i.lkr // Sample ICD2 linker script for the PIC18F4458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6680.lkr0000644000175000017500000000324511156521271012443 00000000000000// File: 18f6680.lkr // Sample linker script for the PIC18F6680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2410_e.lkr0000644000175000017500000000154511156521271012733 00000000000000// File: 18f2410_e.lkr // Sample linker script for the PIC18F2410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f242i.lkr0000644000175000017500000000203311156521271012512 00000000000000// File: 18f242i.lkr // Sample ICD2 linker script for the PIC18F242 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f886.lkr0000644000175000017500000000275011156521271012363 00000000000000// Sample linker command file for 16F886 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c711.lkr0000644000175000017500000000101311156521271012332 00000000000000// Sample linker command file for 16C711 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x0B PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0x0C END=0x4F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8393i.lkr0000644000175000017500000000203211156521271012610 00000000000000// File: 18f8393i.lkr // Sample ICD2 linker script for the PIC18F8393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j11i.lkr0000644000175000017500000000212111156521271012751 00000000000000// File: 18f85j11i.lkr // Sample ICD2 linker script for the PIC18F85J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12c671.lkr0000644000175000017500000000127211156521271012342 00000000000000// Sample linker command file for 12C671 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/12f675.lkr0000644000175000017500000000207711156521271012355 00000000000000// Sample linker command file for 12F675 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x5F SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f8490i_e.lkr0000644000175000017500000000203411156521271013114 00000000000000// File: 18f8490i_e.lkr // Sample ICD2 linker script for the PIC18F8490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2680_e.lkr0000644000175000017500000000315611156521271012744 00000000000000// File: 18f2680_e.lkr // Sample linker script for the PIC18F2680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f688.lkr0000644000175000017500000000330111156521271012354 00000000000000// Sample linker command file for 16F688 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f96j60.lkr0000644000175000017500000000303311156521271012611 00000000000000// File: 18f96j60.lkr // Sample linker script for the PIC18F96J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f46k20_e.lkr0000644000175000017500000000316011156521271013106 00000000000000// File: 18f46k20_e.lkr // Sample linker script for the PIC18F46K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2410i_e.lkr0000644000175000017500000000201011156521271013070 00000000000000// File: 18f2410i_e.lkr // Sample ICD2 linker script for the PIC18F2410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2480i.lkr0000644000175000017500000000240411156521271012602 00000000000000// File: 18f2480i.lkr // Sample ICD2 linker script for the PIC18F2480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c64.lkr0000644000175000017500000000107311156521271012261 00000000000000// Sample linker command file for 16C64 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2420i.lkr0000644000175000017500000000203511156521271012574 00000000000000// File: 18f2420i.lkr // Sample ICD2 linker script for the PIC18F2420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2525_e.lkr0000644000175000017500000000324711156521271012743 00000000000000// File: 18f2525_e.lkr // Sample linker script for the PIC18F2525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j50i_e.lkr0000644000175000017500000000316011156521271013264 00000000000000// File: 18f85j50i_e.lkr // Sample ICD2 linker script for the PIC18F85J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j11i.lkr0000644000175000017500000000315611156521271012763 00000000000000// File: 18f86j11i.lkr // Sample ICD2 linker script for the PIC18F86J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f83j90i_e.lkr0000644000175000017500000000155311156521271013272 00000000000000// File: 18f83j90i_e.lkr // Sample ICD2 linker script for the PIC18F83J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c781.lkr0000644000175000017500000000166111156521271012352 00000000000000// Sample linker command file for 16C781 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18C PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6585.lkr0000644000175000017500000000324511156521271012447 00000000000000// File: 18f6585.lkr // Sample linker script for the PIC18F6585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f914.lkr0000644000175000017500000000231411156521271012347 00000000000000// Sample linker command file for 16F914 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f67j60_e.lkr0000644000175000017500000000303611156521271013116 00000000000000// File: 18f67j60_e.lkr // Sample linker script for the PIC18F67J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f687i.lkr0000644000175000017500000000306311156521271012531 00000000000000// Sample ICD2 linker command file for 16F687 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=gpr1 START=0xA0 END=0xBF DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6622.lkr0000644000175000017500000000315411156521271012436 00000000000000// File: 18f6622.lkr // Sample linker script for the PIC18F6622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c745.lkr0000644000175000017500000000272611156521271012355 00000000000000// Sample linker command file for 16C745 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.usrlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=usbport START=0x1A0 END=0x1DF PROTECTED SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=USRLOCS ROM=.usrlocs // User-configurable locations SECTION NAME=DEVICEID ROM=.device_id // Device ID gputils-0.13.7/lkr/18f87j50i.lkr0000644000175000017500000000315711156521271012770 00000000000000// File: 18f87j50i.lkr // Sample ICD2 linker script for the PIC18F87J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f737.lkr0000644000175000017500000000274711156521271012364 00000000000000// Sample linker command file for 16F737 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprs START=0x70 END=0x7F SHAREBANK NAME=gprs START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/18f45j10i.lkr0000644000175000017500000000155111156521271012752 00000000000000// File: 18f45j10i.lkr // Sample ICD2 linker script for the PIC18F45J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4320.lkr0000644000175000017500000000150011156521271012420 00000000000000// File: 18f4320.lkr // Sample linker script for the PIC18F4320 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j60.lkr0000644000175000017500000000303311156521271012606 00000000000000// File: 18f66j60.lkr // Sample linker script for the PIC18F66J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c801i.lkr0000644000175000017500000000154711156521271012521 00000000000000// File: 18c801i.lkr // Sample ICD2 linker script for the PIC18C801 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFFF CODEPAGE NAME=config START=0x300000 END=0x300006 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4410i_e.lkr0000644000175000017500000000201011156521271013072 00000000000000// File: 18f4410i_e.lkr // Sample ICD2 linker script for the PIC18F4410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25j10i.lkr0000644000175000017500000000155111156521271012750 00000000000000// File: 18f25j10i.lkr // Sample ICD2 linker script for the PIC18F25J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25j50.lkr0000644000175000017500000000277711156521271012616 00000000000000// File: 18f25j50_g.lkr // Generic linker script for the PIC18F25J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c42.lkr0000644000175000017500000000177311156521271012265 00000000000000// Sample linker command file for 17C42 // $Id: 17c42.lkr,v 1.3 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED SHAREBANK NAME=gprs START=0x18 END=0xFF SHAREBANK NAME=gprs START=0x118 END=0x1FF SHAREBANK NAME=gprs START=0x218 END=0x2FF SHAREBANK NAME=gprs START=0x318 END=0x3FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18lf25j11.lkr0000644000175000017500000000300111156521271012744 00000000000000// File: 18lf25j11_g.lkr // Generic linker script for the PIC18LF25J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f747i.lkr0000644000175000017500000000355311156521271012532 00000000000000// Sample ICD2 linker command file for 16F747 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x164 DATABANK NAME=dbgspr2 START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=dbgspr START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprs START=0x71 END=0x7F SHAREBANK NAME=gprs START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/16c62.lkr0000644000175000017500000000107311156521271012257 00000000000000// Sample linker command file for 16C62 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f874ai.lkr0000644000175000017500000000254711156521271012676 00000000000000// Sample ICD2 linker command file for 16F874a LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7D SHAREBANK NAME=dbg0 START=0x7E END=0x7F PROTECTED SHAREBANK NAME=gpr0 START=0x120 END=0x17D PROTECTED SHAREBANK NAME=dbg0 START=0x17E END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xF3 SHAREBANK NAME=dbg1 START=0xF4 END=0xFF PROTECTED SHAREBANK NAME=gpr1 START=0x1A0 END=0x1F3 PROTECTED SHAREBANK NAME=dbg1 START=0x1F4 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/rf675k.lkr0000644000175000017500000000207311156313115012537 00000000000000// Sample linker command file for the rfPIC12F675K LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x5F SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xDF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f8490i.lkr0000644000175000017500000000203211156521271012606 00000000000000// File: 18f8490i.lkr // Sample ICD2 linker script for the PIC18F8490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f77.lkr0000644000175000017500000000256211156521271012274 00000000000000// Sample linker command file for 16F77 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6722_e.lkr0000644000175000017500000000315711156521271012746 00000000000000// File: 18f6722_e.lkr // Sample linker script for the PIC18F6722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr72.lkr0000644000175000017500000000107411156521271012443 00000000000000// Sample linker command file for 16CR72 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4321i.lkr0000644000175000017500000000174311156521271012603 00000000000000// File: 18f4321i.lkr // Sample ICD2 linker script for the PIC18F4321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6393_e.lkr0000644000175000017500000000157111156521271012750 00000000000000// File: 18f6393_e.lkr // Sample linker script for the PIC18F6393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f45j50.lkr0000644000175000017500000000277711156521271012620 00000000000000// File: 18f45j50_g.lkr // Generic linker script for the PIC18F45J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2523i_e.lkr0000644000175000017500000000240611156521271013106 00000000000000// File: 18f2523i_e.lkr // Sample ICD2 linker script for the PIC18F2523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f63j11_e.lkr0000644000175000017500000000143011156521271013102 00000000000000// File: 18f63j11_e.lkr // Sample linker script for the PIC18F63J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8622.lkr0000644000175000017500000000315411156521271012440 00000000000000// File: 18f8622.lkr // Sample linker script for the PIC18F8622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6720i.lkr0000644000175000017500000000332611156521271012607 00000000000000// File: 18f6720i.lkr // Sample ICD2 linker script for the PIC18F6720 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f871i.lkr0000644000175000017500000000323211156521271012522 00000000000000// Sample ICD2 linker command file for 16F871 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x20 END=0x6F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x16F PROTECTED SHAREBANK NAME=gprnobnk1 START=0xA0 END=0xB4 SHAREBANK NAME=dbgspr1 START=0xB5 END=0xBF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1A0 END=0x1B4 PROTECTED SHAREBANK NAME=dbgspr1 START=0x1B5 END=0x1BF PROTECTED SHAREBANK NAME=dbgspr2 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x71 END=0x7F SHAREBANK NAME=dbgspr2 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk2 START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr2 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr2 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f14k22.lkr0000644000175000017500000000161711156521271012604 00000000000000// File: 18f14k22.lkr // Sample linker script for the PIC18F14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f64j11_e.lkr0000644000175000017500000000143011156521271013103 00000000000000// File: 18f64j11_e.lkr // Sample linker script for the PIC18F64J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c756.lkr0000644000175000017500000000462311156521271012356 00000000000000// Sample linker command file for 17C756 // $Id: 17c756.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED SHAREBANK NAME=sfrnobnk START=0x400 END=0x40F PROTECTED SHAREBANK NAME=sfrnobnk START=0x500 END=0x50F PROTECTED SHAREBANK NAME=sfrnobnk START=0x600 END=0x60F PROTECTED SHAREBANK NAME=sfrnobnk START=0x700 END=0x70F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED DATABANK NAME=sfr4 START=0x410 END=0x417 PROTECTED DATABANK NAME=sfr5 START=0x510 END=0x517 PROTECTED DATABANK NAME=sfr6 START=0x610 END=0x617 PROTECTED DATABANK NAME=sfr7 START=0x710 END=0x717 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=sfrprod START=0x418 END=0x419 PROTECTED SHAREBANK NAME=sfrprod START=0x518 END=0x519 PROTECTED SHAREBANK NAME=sfrprod START=0x618 END=0x619 PROTECTED SHAREBANK NAME=sfrprod START=0x718 END=0x719 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F SHAREBANK NAME=registers START=0x41A END=0x41F SHAREBANK NAME=registers START=0x51A END=0x51F SHAREBANK NAME=registers START=0x61A END=0x61F SHAREBANK NAME=registers START=0x71A END=0x71F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF DATABANK NAME=gpr2 START=0x220 END=0x2FF DATABANK NAME=gpr3 START=0x320 END=0x3FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18f86j15.lkr0000644000175000017500000000271711156521271012620 00000000000000// File: 18f86j15.lkr // Sample linker script for the PIC18F86J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j65i.lkr0000644000175000017500000000315711156521271012773 00000000000000// File: 18f66j65i.lkr // Sample ICD2 linker script for the PIC18F66J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8493_e.lkr0000644000175000017500000000157111156521271012753 00000000000000// File: 18f8493_e.lkr // Sample linker script for the PIC18F8493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j16i_e.lkr0000644000175000017500000000316111156521271013270 00000000000000// File: 18f86j16i_e.lkr // Sample ICD2 linker script for the PIC18F86J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4458.lkr0000644000175000017500000000235011156521271012440 00000000000000// File: 18f4458.lkr // Sample linker script for the PIC18F4458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4455i_e.lkr0000644000175000017500000000252411156521271013115 00000000000000// File: 18f4455i_e.lkr // Sample ICD2 linker script for the PIC18F4455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f609i.lkr0000644000175000017500000000161511156521271012520 00000000000000// Sample ICD2 linker command file for 12F609 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f85j10i.lkr0000644000175000017500000000212111156521271012750 00000000000000// File: 18f85j10i.lkr // Sample ICD2 linker script for the PIC18F85J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f45j11.lkr0000644000175000017500000000277711156521271012615 00000000000000// File: 18f45j11_g.lkr // Generic linker script for the PIC18F45J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25j10.lkr0000644000175000017500000000142611156521271012600 00000000000000// File: 18f25j10.lkr // Sample linker script for the PIC18F25J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2450.lkr0000644000175000017500000000147511156521271012435 00000000000000// File: 18f2450.lkr // Sample linker script for the PIC18F2450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf25j50.lkr0000644000175000017500000000300111156521271012747 00000000000000// File: 18lf25j50_g.lkr // Generic linker script for the PIC18LF25J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26j50.lkr0000644000175000017500000000277711156521271012617 00000000000000// File: 18f26j50_g.lkr // Generic linker script for the PIC18F26J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j50.lkr0000644000175000017500000000303311156521271012605 00000000000000// File: 18f66j50.lkr // Sample linker script for the PIC18F66J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c74a.lkr0000644000175000017500000000127011156521271012422 00000000000000// Sample linker command file for 16C74A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f1937.lkr0000644000175000017500000001443211156521271012441 00000000000000// File: 16f1937_g.lkr // Generic linker script for the PIC16F1937 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x1A0 END=0x1EF DATABANK NAME=gpr4 START=0x220 END=0x26F DATABANK NAME=gpr5 START=0x2A0 END=0x2EF DATABANK NAME=gpr6 START=0x320 END=0x32F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=PROG2 ROM=page2 // ROM code space - page2 SECTION NAME=PROG3 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2220.lkr0000644000175000017500000000147711156521271012432 00000000000000// File: 18f2220.lkr // Sample linker script for the PIC18F2220 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4680i_e.lkr0000644000175000017500000000342111156521271013112 00000000000000// File: 18f4680i_e.lkr // Sample ICD2 linker script for the PIC18F4680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4420_e.lkr0000644000175000017500000000166511156521271012741 00000000000000// File: 18f4420_e.lkr // Sample linker script for the PIC18F4420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8490.lkr0000644000175000017500000000156711156521271012451 00000000000000// File: 18f8490.lkr // Sample linker script for the PIC18F8490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f506.lkr0000644000175000017500000000214411156521271012345 00000000000000// Sample linker command file for 16f506 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x0C PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x2C PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x4C PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x6C PROTECTED SHAREBANK NAME=gprnobnk START=0x0D END=0x0F SHAREBANK NAME=gprnobnk START=0x2D END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x4D END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x6D END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8627i.lkr0000644000175000017500000000342011156521271012612 00000000000000// File: 18f8627i.lkr // Sample ICD2 linker script for the PIC18F8627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/10f204i.lkr0000644000175000017500000000113611156313115012477 00000000000000// Sample ICD2 linker command file for 10F204 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 10F204.lkr but named 10F204i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFF CODEPAGE NAME=.idlocs START=0x100 END=0x103 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x10 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6493i.lkr0000644000175000017500000000203211156521271012607 00000000000000// File: 18f6493i.lkr // Sample ICD2 linker script for the PIC18F6493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4525i.lkr0000644000175000017500000000341711156521271012611 00000000000000// File: 18f4525i.lkr // Sample ICD2 linker script for the PIC18F4525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4553.lkr0000644000175000017500000000235011156521271012434 00000000000000// File: 18f4553.lkr // Sample linker script for the PIC18F4553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j50_e.lkr0000644000175000017500000000303511156521271013115 00000000000000// File: 18f86j50_e.lkr // Sample linker script for the PIC18F86J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j11i_e.lkr0000644000175000017500000000316111156521271013264 00000000000000// File: 18f87j11i_e.lkr // Sample ICD2 linker script for the PIC18F87J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j10.lkr0000644000175000017500000000177611156521271012616 00000000000000// File: 18f85j10.lkr // Sample linker script for the PIC18F85J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1230i_e.lkr0000644000175000017500000000174311156521271013103 00000000000000// File: 18f1230i_e.lkr // Sample ICD2 linker script for the PIC18F1230 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xE3F CODEPAGE NAME=debug START=0xE40 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xF3 DATABANK NAME=dbgspr START=0xF4 END=0xFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4620_e.lkr0000644000175000017500000000324711156521271012741 00000000000000// File: 18f4620_e.lkr // Sample linker script for the PIC18F4620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4450i_e.lkr0000644000175000017500000000165111156521271013110 00000000000000// File: 18f4450i_e.lkr // Sample ICD2 linker script for the PIC18F4450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c717.lkr0000644000175000017500000000174311156521271012352 00000000000000// Sample linker command file for 16C717 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f25j11.lkr0000644000175000017500000000277711156521271012613 00000000000000// File: 18f25j11_g.lkr // Generic linker script for the PIC18F25J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f777.lkr0000644000175000017500000000331111156521271012354 00000000000000// Sample linker command file for 16F767 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprs START=0x70 END=0x7F SHAREBANK NAME=gprs START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=PROG2 ROM=page2 // ROM code space SECTION NAME=PROG3 ROM=page3 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/18f4455_e.lkr0000644000175000017500000000226111156521271012742 00000000000000// File: 18f4455_e.lkr // Sample linker script for the PIC18F4455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f505i.lkr0000644000175000017500000000236711156521271012524 00000000000000// Sample linker command file for 16f505 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 16F505.lkr but named 16F505i.lkr LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x07 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x08 END=0x0F SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16lf723i.lkr0000644000175000017500000000303211156521271012670 00000000000000// Sample ICD2 linker command file for 16LF723 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x124 DATABANK NAME=gpr2dbg START=0x125 END=0x12F PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2525i_e.lkr0000644000175000017500000000351211156521271013107 00000000000000// File: 18f2525i_e.lkr // Sample ICD2 linker script for the PIC18F2525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6493.lkr0000644000175000017500000000156711156521271012452 00000000000000// File: 18f6493.lkr // Sample linker script for the PIC18F6493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6620i.lkr0000644000175000017500000000332511156521271012605 00000000000000// File: 18f6620i.lkr // Sample ICD2 linker script for the PIC18F6620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f23k20.lkr0000644000175000017500000000141211156521271012573 00000000000000// File: 18f23k20_g.lkr // Generic linker script for the PIC18F23K20 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f252i.lkr0000644000175000017500000000231111156521271012512 00000000000000// File: 18f252i.lkr // Sample ICD2 linker script for the PIC18F252 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2480.lkr0000644000175000017500000000214111156521271012427 00000000000000// File: 18f2480.lkr // Sample linker script for the PIC18F2480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c242.lkr0000644000175000017500000000135611156521271012345 00000000000000// File: 18c242.lkr // Sample linker script for the PIC18C242 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x300007 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4550_e.lkr0000644000175000017500000000226111156521271012736 00000000000000// File: 18f4550_e.lkr // Sample linker script for the PIC18F4550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr54b.lkr0000644000175000017500000000071511156521271012606 00000000000000// Sample linker command file for 16CR54B LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f870i.lkr0000644000175000017500000000322211156521271012520 00000000000000// Sample ICD2 linker command file for 16F870 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x20 END=0x6F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x16F PROTECTED SHAREBANK NAME=gprnobnk1 START=0xA0 END=0xB4 SHAREBANK NAME=dbgspr1 START=0xB5 END=0xBF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1A0 END=0x1B4 PROTECTED SHAREBANK NAME=dbgspr1 START=0x1B5 END=0x1BF PROTECTED SHAREBANK NAME=dbgspr2 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x71 END=0x7F SHAREBANK NAME=dbgspr2 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk2 START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr2 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr2 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6393.lkr0000644000175000017500000000156711156521271012451 00000000000000// File: 18f6393.lkr // Sample linker script for the PIC18F6393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17cr43.lkr0000644000175000017500000000254411156521271012445 00000000000000// Sample linker command file for 17CR43 // $Id: 17cr43.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/16f871.lkr0000644000175000017500000000230311156521271012347 00000000000000// Sample linker command file for 16F871 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x20 END=0x6F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x16F PROTECTED SHAREBANK NAME=gprnobnk1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk1 START=0x1A0 END=0x1BF PROTECTED SHAREBANK NAME=gprnobnk2 START=0x70 END=0x7F SHAREBANK NAME=gprnobnk2 START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk2 START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk2 START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c73a.lkr0000644000175000017500000000127011156521271012421 00000000000000// Sample linker command file for 16C73A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f1936.lkr0000644000175000017500000001443211156521271012440 00000000000000// File: 16f1936_g.lkr // Generic linker script for the PIC16F1936 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x1A0 END=0x1EF DATABANK NAME=gpr4 START=0x220 END=0x26F DATABANK NAME=gpr5 START=0x2A0 END=0x2EF DATABANK NAME=gpr6 START=0x320 END=0x32F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=PROG2 ROM=page2 // ROM code space - page2 SECTION NAME=PROG3 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f818i.lkr0000644000175000017500000000361011156521271012523 00000000000000// Sample ICD2 linker command file for the PIC16F818 LIBPATH . CODEPAGE NAME=page START=0x0000 END=0x02FF CODEPAGE NAME=debug START=0x0300 END=0x03FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk0 START=0x20 END=0x3F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x13F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1A0 END=0x1BF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x40 END=0x64 SHAREBANK NAME=dbgspr1 START=0x65 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x71 END=0x7F SHAREBANK NAME=gprnobnk1 START=0xC0 END=0xE4 PROTECTED SHAREBANK NAME=dbgspr1 START=0xE5 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk2 START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x140 END=0x164 PROTECTED SHAREBANK NAME=dbgspr1 START=0x165 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1C0 END=0x1E4 PROTECTED SHAREBANK NAME=dbgspr1 START=0x1E5 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk2 START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4610.lkr0000644000175000017500000000303411156521271012426 00000000000000// File: 18f4610.lkr // Sample linker script for the PIC18F4610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr63.lkr0000644000175000017500000000127011156521271012441 00000000000000// Sample linker command file for 16CR63 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j10i_e.lkr0000644000175000017500000000212311156521271013257 00000000000000// File: 18f86j10i_e.lkr // Sample ICD2 linker script for the PIC18F86J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2523_e.lkr0000644000175000017500000000214311156521271012733 00000000000000// File: 18f2523_e.lkr // Sample linker script for the PIC18F2523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c54b.lkr0000644000175000017500000000071411156521271012423 00000000000000// Sample linker command file for 16C54B LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4321i_e.lkr0000644000175000017500000000203611156521271013103 00000000000000// File: 18f4321i_e.lkr // Sample ICD2 linker script for the PIC18F4321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2320i.lkr0000644000175000017500000000174311156521271012600 00000000000000// File: 18f2320i.lkr // Sample ICD2 linker script for the PIC18F2320 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f83j11i_e.lkr0000644000175000017500000000155311156521271013263 00000000000000// File: 18f83j11i_e.lkr // Sample ICD2 linker script for the PIC18F83J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j50i.lkr0000644000175000017500000000315611156521271012764 00000000000000// File: 18f66j50i.lkr // Sample ICD2 linker script for the PIC18F66J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j11_e.lkr0000644000175000017500000000303511156521271013110 00000000000000// File: 18f66j11_e.lkr // Sample linker script for the PIC18F66J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12c672.lkr0000644000175000017500000000127211156521271012343 00000000000000// Sample linker command file for 12C672 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f63j90.lkr0000644000175000017500000000142611156521271012612 00000000000000// File: 18f63j90.lkr // Sample linker script for the PIC18F63J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j15_e.lkr0000644000175000017500000000200011156521271013104 00000000000000// File: 18f85j15_e.lkr // Sample linker script for the PIC18F85J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f96j60_e.lkr0000644000175000017500000000303511156521271013117 00000000000000// File: 18f96j60_e.lkr // Sample linker script for the PIC18F96J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4450_e.lkr0000644000175000017500000000140611156521271012735 00000000000000// File: 18f4450_e.lkr // Sample linker script for the PIC18F4450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16ce624.lkr0000644000175000017500000000120111156521271012501 00000000000000// Sample linker command file for 16CE624 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f917i.lkr0000644000175000017500000000370511156521271012530 00000000000000// Sample ICD2 linker command file for 16F917 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=gpr2dbg START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f65j11_e.lkr0000644000175000017500000000200011156521271013076 00000000000000// File: 18f65j11_e.lkr // Sample linker script for the PIC18F65J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f946i.lkr0000644000175000017500000000365711156521271012540 00000000000000// Sample ICD2 linker command file for 16F946 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=gpr2dbg START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x1A0 END=0x1EF SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c924.lkr0000644000175000017500000000204511156521271012346 00000000000000// Sample linker command file for 16C924 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4510i.lkr0000644000175000017500000000217311156521271012601 00000000000000// File: 18f4510i.lkr // Sample ICD2 linker script for the PIC18F4510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f248i.lkr0000644000175000017500000000215011156521271012520 00000000000000// File: 18f248i.lkr // Sample ICD2 linker script for the PIC18F248 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f689.lkr0000644000175000017500000000252011156521271012357 00000000000000// Sample linker command file for 16F689 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/12f509i.lkr0000644000175000017500000000163711156521271012523 00000000000000// Sample linker command file for 12F509 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 12F509.lkr but named 12F509i.lkr LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x06 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=gprnobnk START=0x07 END=0x0F SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f873ai.lkr0000644000175000017500000000254711156521271012675 00000000000000// Sample ICD2 linker command file for 16F873a LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7D SHAREBANK NAME=dbg0 START=0x7E END=0x7F PROTECTED SHAREBANK NAME=gpr0 START=0x120 END=0x17D PROTECTED SHAREBANK NAME=dbg0 START=0x17E END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xF3 SHAREBANK NAME=dbg1 START=0xF4 END=0xFF PROTECTED SHAREBANK NAME=gpr1 START=0x1A0 END=0x1F3 PROTECTED SHAREBANK NAME=dbg1 START=0x1F4 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2515.lkr0000644000175000017500000000303411156521271012430 00000000000000// File: 18f2515.lkr // Sample linker script for the PIC18F2515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j15i_e.lkr0000644000175000017500000000212311156521271013261 00000000000000// File: 18f65j15i_e.lkr // Sample ICD2 linker script for the PIC18F65J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1220.lkr0000644000175000017500000000140511156521271012420 00000000000000// File: 18f1220.lkr // Sample linker script for the PIC18F1220 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4515i_e.lkr0000644000175000017500000000337211156521271013114 00000000000000// File: 18f4515i_e.lkr // Sample ICD2 linker script for the PIC18F4515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f873.lkr0000644000175000017500000000205611156521271012356 00000000000000// Sample linker command file for 16F873 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7F SHAREBANK NAME=gpr0 START=0x120 END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xFF SHAREBANK NAME=gpr1 START=0x1A0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6628_e.lkr0000644000175000017500000000315711156521271012753 00000000000000// File: 18f6628_e.lkr // Sample linker script for the PIC18F6628 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f874a.lkr0000644000175000017500000000205411156521271012516 00000000000000// Sample linker command file for 16F873 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x7F SHAREBANK NAME=gpr0 START=0x120 END=0x17F PROTECTED SHAREBANK NAME=gpr1 START=0xA0 END=0xFF SHAREBANK NAME=gpr1 START=0x1A0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c73b.lkr0000644000175000017500000000127111156521271012423 00000000000000// Sample linker command file for 16C73B LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f13k50i_e.lkr0000644000175000017500000000162711156521271013262 00000000000000// File: 18f13k50i_e.lkr // Sample ICD2 linker script for the PIC18F13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f452i.lkr0000644000175000017500000000231111156521271012514 00000000000000// File: 18f452i.lkr // Sample ICD2 linker script for the PIC18F452 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c774.lkr0000644000175000017500000000212711156521271012352 00000000000000// Sample linker command file for 16C774 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10B PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18B PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8410.lkr0000644000175000017500000000156711156521271012441 00000000000000// File: 18f8410.lkr // Sample linker script for the PIC18F8410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f13k50i.lkr0000644000175000017500000000162511156521271012754 00000000000000// File: 18f13k50i.lkr // Sample ICD2 linker script for the PIC18F13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f727i.lkr0000644000175000017500000000346511156521271012532 00000000000000// Sample ICD2 linker command file for 16F727 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=gpr3dbg START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f59.lkr0000644000175000017500000000405111156521271012267 00000000000000// Sample linker command file for 16F59 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x9 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x29 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x49 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x69 PROTECTED SHAREBANK NAME=sfrs START=0x80 END=0x89 PROTECTED SHAREBANK NAME=sfrs START=0xA0 END=0xA9 PROTECTED SHAREBANK NAME=sfrs START=0xC0 END=0xC9 PROTECTED SHAREBANK NAME=sfrs START=0xE0 END=0xE9 PROTECTED SHAREBANK NAME=gprnobnk START=0xA END=0xF SHAREBANK NAME=gprnobnk START=0x2A END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x4A END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x6A END=0x6F PROTECTED SHAREBANK NAME=gprnobnk START=0x8A END=0x8F PROTECTED SHAREBANK NAME=gprnobnk START=0xAA END=0xAF PROTECTED SHAREBANK NAME=gprnobnk START=0xCA END=0xCF PROTECTED SHAREBANK NAME=gprnobnk START=0xEA END=0xEF PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F DATABANK NAME=gpr4 START=0x90 END=0x9F DATABANK NAME=gpr5 START=0xB0 END=0xBF DATABANK NAME=gpr6 START=0xD0 END=0xDF DATABANK NAME=gpr7 START=0xF0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f687.lkr0000644000175000017500000000225711156521271012364 00000000000000// Sample linker command file for 16F687 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/17c43.lkr0000644000175000017500000000254211156521271012261 00000000000000// Sample linker command file for 17C43 // $Id: 17c43.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/mcv28a.lkr0000644000175000017500000000250411156521271012616 00000000000000// Sample linker command file for MCV28A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x28 END=0x2F SHAREBANK NAME=gprnobnk START=0x48 END=0x4F SHAREBANK NAME=gprnobnk START=0x68 END=0x6F DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f627ai.lkr0000644000175000017500000000402411156521271012662 00000000000000// Sample ICD2 linker command file for 16F627A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10B PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x144 DATABANK NAME=dbg2 START=0x145 END=0x14F PROTECTED SHAREBANK NAME=dbgnobnk0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk0 START=0x71 END=0x7E SHAREBANK NAME=gprnobnk0 START=0xF1 END=0xFE PROTECTED SHAREBANK NAME=gprnobnk0 START=0x171 END=0x17E PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1F1 END=0x1FE PROTECTED SHAREBANK NAME=gprnobnk1 START=0x7F END=0x7F SHAREBANK NAME=gprnobnk1 START=0xFF END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x17F END=0x17F PROTECTED DATABANK NAME=testreg START=0x1FF END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=DEBUG ROM=debug // ICD debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=.icd_inst // ICD instruction SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f44j10_e.lkr0000644000175000017500000000152111156521271013101 00000000000000// File: 18f44j10_e.lkr // Sample linker script for the PIC18F44J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26k20_g.lkr0000644000175000017500000000501111156521271013103 00000000000000// File: 18f26k20_g.lkr // Generic linker script for the PIC18F26K20 processor #DEFINE _CODEEND _DEBUGCODESTART - 1 #DEFINE _CEND _CODEEND + _DEBUGCODELEN #DEFINE _DATAEND _DEBUGDATASTART - 1 #DEFINE _DEND _DATAEND + _DEBUGDATALEN LIBPATH . #IFDEF _CRUNTIME #IFDEF _EXTENDEDMODE FILES c018i_e.o FILES clib_e.lib FILES p18f26k20_e.lib #ELSE FILES c018i.o FILES clib.lib FILES p18f26k20.lib #FI #FI #IFDEF _DEBUGCODESTART CODEPAGE NAME=page START=0x0 END=_CODEEND CODEPAGE NAME=debug START=_DEBUGCODESTART END=_CEND PROTECTED #ELSE CODEPAGE NAME=page START=0x0 END=0xFFFF #FI CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED #IFDEF _EXTENDEDMODE DATABANK NAME=gpre START=0x0 END=0x5F #ELSE ACCESSBANK NAME=accessram START=0x0 END=0x5F #FI DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF #IFDEF _DEBUGDATASTART DATABANK NAME=gpr14 START=0xE00 END=_DATAEND DATABANK NAME=dbgspr START=_DEBUGDATASTART END=_DEND PROTECTED #ELSE //no debug DATABANK NAME=gpr14 START=0xE00 END=0xEFF #FI DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED #IFDEF _CRUNTIME SECTION NAME=CONFIG ROM=config #IFDEF _DEBUGDATASTART STACK SIZE=0x100 RAM=gpr13 #ELSE STACK SIZE=0x100 RAM=gpr14 #FI #FI gputils-0.13.7/lkr/16c773.lkr0000644000175000017500000000212711156521271012351 00000000000000// Sample linker command file for 16C773 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10B PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18B PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f66j60i_e.lkr0000644000175000017500000000316011156521271013264 00000000000000// File: 18f66j60i_e.lkr // Sample ICD2 linker script for the PIC18F66J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6490i.lkr0000644000175000017500000000203211156521271012604 00000000000000// File: 18f6490i.lkr // Sample ICD2 linker script for the PIC18F6490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j50.lkr0000644000175000017500000000303311156521271012607 00000000000000// File: 18f86j50.lkr // Sample linker script for the PIC18F86J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f83j11i.lkr0000644000175000017500000000155111156521271012755 00000000000000// File: 18f83j11i.lkr // Sample ICD2 linker script for the PIC18F83J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j10i.lkr0000644000175000017500000000304211156521271012753 00000000000000// File: 18f67j10i.lkr // Sample ICD2 linker script for the PIC18F67J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6390i_e.lkr0000644000175000017500000000203411156521271013111 00000000000000// File: 18f6390i_e.lkr // Sample ICD2 linker script for the PIC18F6390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/Makefile.sh0000755000175000017500000000117211156521271013060 00000000000000#!/bin/sh # generate Makefile.am from the directory contents MAKE_FILE=Makefile.am cat > $MAKE_FILE <<\_ACEOF ## This file was automatically generated by Makefile.sh pkgdatadir = @GPUTILS_LKR_PATH@ LKR_FILES =\ _ACEOF # count the number of items in the list let count=0 for x in *.lkr do let count=count+1 done # output the file list let number=0 for x in *.lkr do let number=number+1 if [ $number -eq $count ]; then echo " $x" >> $MAKE_FILE else echo " $x \\" >> $MAKE_FILE fi done cat >> $MAKE_FILE <<\_ACEOF pkgdata_DATA = $(LKR_FILES) EXTRA_DIST = $(LKR_FILES) Makefile.sh _ACEOF gputils-0.13.7/lkr/mcv18a.lkr0000644000175000017500000000071411156521271012616 00000000000000// Sample linker command file for MCV18A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x6 PROTECTED DATABANK NAME=gprs START=0x7 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6490_e.lkr0000644000175000017500000000157111156521271012746 00000000000000// File: 18f6490_e.lkr // Sample linker script for the PIC18F6490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2620.lkr0000644000175000017500000000315411156521271012430 00000000000000// File: 18f2620.lkr // Sample linker script for the PIC18F2620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f628ai.lkr0000644000175000017500000000402511156521271012664 00000000000000// Sample ICD2 linker command file for 16F628A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10B PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x144 DATABANK NAME=dbg2 START=0x145 END=0x14F PROTECTED SHAREBANK NAME=dbgnobnk0 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk0 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk0 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk0 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk0 START=0x71 END=0x7E SHAREBANK NAME=gprnobnk0 START=0xF1 END=0xFE PROTECTED SHAREBANK NAME=gprnobnk0 START=0x171 END=0x17E PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1F1 END=0x1FE PROTECTED SHAREBANK NAME=gprnobnk1 START=0x7F END=0x7F SHAREBANK NAME=gprnobnk1 START=0xFF END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x17F END=0x17F PROTECTED DATABANK NAME=testreg START=0x1FF END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=DEBUG ROM=debug // ICD2 debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=.icd_inst // ICD instruction SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6622i_e.lkr0000644000175000017500000000342111156521271013110 00000000000000// File: 18f6622i_e.lkr // Sample ICD2 linker script for the PIC18F6622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12ce674.lkr0000644000175000017500000000127311156521271012513 00000000000000// Sample linker command file for 12CE674 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f819.lkr0000644000175000017500000000244411156521271012357 00000000000000// Sample linker command file for 16F819.lkr LIBPATH . CODEPAGE NAME=page START=0x0000 END=0x07FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0xA0 END=0xEF DATABANK NAME=gpr1 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk0 START=0x20 END=0x6F SHAREBANK NAME=gprnobnk0 START=0x1A0 END=0x1EF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x70 END=0x7F SHAREBANK NAME=gprnobnk1 START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/Makefile.am0000644000175000017500000003646611156521271013056 00000000000000## This file was automatically generated by Makefile.sh pkgdatadir = @GPUTILS_LKR_PATH@ LKR_FILES =\ 10f200i.lkr \ 10f200.lkr \ 10f202i.lkr \ 10f202.lkr \ 10f204i.lkr \ 10f204.lkr \ 10f206i.lkr \ 10f206.lkr \ 10f220i.lkr \ 10f220.lkr \ 10f222i.lkr \ 10f222.lkr \ 12c508a.lkr \ 12c508.lkr \ 12c509a.lkr \ 12c509.lkr \ 12c671.lkr \ 12c672.lkr \ 12ce518.lkr \ 12ce519.lkr \ 12ce673.lkr \ 12ce674.lkr \ 12cr509a.lkr \ 12f508i.lkr \ 12f508.lkr \ 12f509i.lkr \ 12f509.lkr \ 12f510i.lkr \ 12f510.lkr \ 12f519.lkr \ 12f609i.lkr \ 12f609.lkr \ 12f615i.lkr \ 12f615.lkr \ 12f629i.lkr \ 12f629.lkr \ 12f635i.lkr \ 12f635.lkr \ 12f675i.lkr \ 12f675.lkr \ 12f683i.lkr \ 12f683.lkr \ 12hv609i.lkr \ 12hv609.lkr \ 12hv615i.lkr \ 12hv615.lkr \ 14000.lkr \ 16c432.lkr \ 16c433.lkr \ 16c505.lkr \ 16c52.lkr \ 16c54a.lkr \ 16c54b.lkr \ 16c54c.lkr \ 16c54.lkr \ 16c554.lkr \ 16c557.lkr \ 16c558.lkr \ 16c55a.lkr \ 16c55.lkr \ 16c56a.lkr \ 16c56.lkr \ 16c57c.lkr \ 16c57.lkr \ 16c58a.lkr \ 16c58b.lkr \ 16c61.lkr \ 16c620a.lkr \ 16c620.lkr \ 16c621a.lkr \ 16c621.lkr \ 16c622a.lkr \ 16c622.lkr \ 16c62a.lkr \ 16c62b.lkr \ 16c62.lkr \ 16c63a.lkr \ 16c63.lkr \ 16c642.lkr \ 16c64a.lkr \ 16c64.lkr \ 16c65a.lkr \ 16c65b.lkr \ 16c65.lkr \ 16c662.lkr \ 16c66.lkr \ 16c67.lkr \ 16c710.lkr \ 16c711.lkr \ 16c712.lkr \ 16c715.lkr \ 16c716.lkr \ 16c717.lkr \ 16c71.lkr \ 16c72a.lkr \ 16c72.lkr \ 16c73a.lkr \ 16c73b.lkr \ 16c73.lkr \ 16c745.lkr \ 16c74a.lkr \ 16c74b.lkr \ 16c74.lkr \ 16c765.lkr \ 16c76.lkr \ 16c770.lkr \ 16c771.lkr \ 16c773.lkr \ 16c774.lkr \ 16c77.lkr \ 16c781.lkr \ 16c782.lkr \ 16c84.lkr \ 16c923.lkr \ 16c924.lkr \ 16c925.lkr \ 16c926.lkr \ 16ce623.lkr \ 16ce624.lkr \ 16ce625.lkr \ 16cr54a.lkr \ 16cr54b.lkr \ 16cr54c.lkr \ 16cr54.lkr \ 16cr56a.lkr \ 16cr57a.lkr \ 16cr57b.lkr \ 16cr57c.lkr \ 16cr58a.lkr \ 16cr58b.lkr \ 16cr620a.lkr \ 16cr62.lkr \ 16cr63.lkr \ 16cr64.lkr \ 16cr65.lkr \ 16cr72.lkr \ 16cr83.lkr \ 16cr84.lkr \ 16f1933.lkr \ 16f1934.lkr \ 16f1936.lkr \ 16f1937.lkr \ 16f505i.lkr \ 16f505.lkr \ 16f506i.lkr \ 16f506.lkr \ 16f526.lkr \ 16f54.lkr \ 16f57.lkr \ 16f59.lkr \ 16f610i.lkr \ 16f610.lkr \ 16f616i.lkr \ 16f616.lkr \ 16f627ai.lkr \ 16f627a.lkr \ 16f627.lkr \ 16f628ai.lkr \ 16f628a.lkr \ 16f628.lkr \ 16f630i.lkr \ 16f630.lkr \ 16f631i.lkr \ 16f631.lkr \ 16f636i.lkr \ 16f636.lkr \ 16f639i.lkr \ 16f639.lkr \ 16f648ai.lkr \ 16f648a.lkr \ 16f676i.lkr \ 16f676.lkr \ 16f677i.lkr \ 16f677.lkr \ 16f684i.lkr \ 16f684.lkr \ 16f685i.lkr \ 16f685.lkr \ 16f687i.lkr \ 16f687.lkr \ 16f688i.lkr \ 16f688.lkr \ 16f689i.lkr \ 16f689.lkr \ 16f690i.lkr \ 16f690.lkr \ 16f716i.lkr \ 16f716.lkr \ 16f722i.lkr \ 16f722.lkr \ 16f723i.lkr \ 16f723.lkr \ 16f724i.lkr \ 16f724.lkr \ 16f726i.lkr \ 16f726.lkr \ 16f727i.lkr \ 16f727.lkr \ 16f72.lkr \ 16f737i.lkr \ 16f737.lkr \ 16f73.lkr \ 16f747i.lkr \ 16f747.lkr \ 16f74.lkr \ 16f767i.lkr \ 16f767.lkr \ 16f76.lkr \ 16f777i.lkr \ 16f777.lkr \ 16f77.lkr \ 16f785i.lkr \ 16f785.lkr \ 16f818i.lkr \ 16f818.lkr \ 16f819i.lkr \ 16f819.lkr \ 16f83.lkr \ 16f84a.lkr \ 16f84.lkr \ 16f870i.lkr \ 16f870.lkr \ 16f871i.lkr \ 16f871.lkr \ 16f872i.lkr \ 16f872.lkr \ 16f873ai.lkr \ 16f873a.lkr \ 16f873i.lkr \ 16f873.lkr \ 16f874ai.lkr \ 16f874a.lkr \ 16f874i.lkr \ 16f874.lkr \ 16f876ai.lkr \ 16f876a.lkr \ 16f876i.lkr \ 16f876.lkr \ 16f877ai.lkr \ 16f877a.lkr \ 16f877i.lkr \ 16f877.lkr \ 16f87i.lkr \ 16f87.lkr \ 16f882i.lkr \ 16f882.lkr \ 16f883i.lkr \ 16f883.lkr \ 16f884i.lkr \ 16f884.lkr \ 16f886i.lkr \ 16f886.lkr \ 16f887i.lkr \ 16f887.lkr \ 16f88i.lkr \ 16f88.lkr \ 16f913i.lkr \ 16f913.lkr \ 16f914i.lkr \ 16f914.lkr \ 16f916i.lkr \ 16f916.lkr \ 16f917i.lkr \ 16f917.lkr \ 16f946i.lkr \ 16f946.lkr \ 16hv540.lkr \ 16hv610i.lkr \ 16hv610.lkr \ 16hv616i.lkr \ 16hv616.lkr \ 16hv785i.lkr \ 16hv785.lkr \ 16lf1933.lkr \ 16lf1934.lkr \ 16lf1936.lkr \ 16lf1937.lkr \ 16lf722i.lkr \ 16lf722.lkr \ 16lf723i.lkr \ 16lf723.lkr \ 16lf724i.lkr \ 16lf724.lkr \ 16lf726i.lkr \ 16lf726.lkr \ 16lf727i.lkr \ 16lf727.lkr \ 17c42a.lkr \ 17c42.lkr \ 17c43.lkr \ 17c44.lkr \ 17c752.lkr \ 17c756a.lkr \ 17c756.lkr \ 17c762.lkr \ 17c766.lkr \ 17cr42.lkr \ 17cr43.lkr \ 18c242.lkr \ 18c252.lkr \ 18c442.lkr \ 18c452.lkr \ 18c601i.lkr \ 18c601.lkr \ 18c658.lkr \ 18c801i.lkr \ 18c801.lkr \ 18c858.lkr \ 18f1220i.lkr \ 18f1220.lkr \ 18f1230_e.lkr \ 18f1230i_e.lkr \ 18f1230i.lkr \ 18f1230.lkr \ 18f1320i.lkr \ 18f1320.lkr \ 18f1330_e.lkr \ 18f1330i_e.lkr \ 18f1330i.lkr \ 18f1330.lkr \ 18f13k22_e.lkr \ 18f13k22i_e.lkr \ 18f13k22i.lkr \ 18f13k22.lkr \ 18f13k50_e.lkr \ 18f13k50i_e.lkr \ 18f13k50i.lkr \ 18f13k50.lkr \ 18f14k22_e.lkr \ 18f14k22i_e.lkr \ 18f14k22i.lkr \ 18f14k22.lkr \ 18f14k50_e.lkr \ 18f14k50i_e.lkr \ 18f14k50i.lkr \ 18f14k50.lkr \ 18f2220i.lkr \ 18f2220.lkr \ 18f2221_e.lkr \ 18f2221i_e.lkr \ 18f2221i.lkr \ 18f2221.lkr \ 18f2320i.lkr \ 18f2320.lkr \ 18f2321_e.lkr \ 18f2321i_e.lkr \ 18f2321i.lkr \ 18f2321.lkr \ 18f2331i.lkr \ 18f2331.lkr \ 18f23k20.lkr \ 18f2410_e.lkr \ 18f2410i_e.lkr \ 18f2410i.lkr \ 18f2410.lkr \ 18f2420_e.lkr \ 18f2420i_e.lkr \ 18f2420i.lkr \ 18f2420.lkr \ 18f2423_e.lkr \ 18f2423i_e.lkr \ 18f2423i.lkr \ 18f2423.lkr \ 18f242i.lkr \ 18f242.lkr \ 18f2431i.lkr \ 18f2431.lkr \ 18f2439i.lkr \ 18f2439.lkr \ 18f2450_e.lkr \ 18f2450i_e.lkr \ 18f2450i.lkr \ 18f2450.lkr \ 18f2455_e.lkr \ 18f2455i_e.lkr \ 18f2455i.lkr \ 18f2455.lkr \ 18f2458_e.lkr \ 18f2458i_e.lkr \ 18f2458i.lkr \ 18f2458.lkr \ 18f2480_e.lkr \ 18f2480i_e.lkr \ 18f2480i.lkr \ 18f2480.lkr \ 18f248i.lkr \ 18f248.lkr \ 18f24j10_e.lkr \ 18f24j10i_e.lkr \ 18f24j10i.lkr \ 18f24j10.lkr \ 18f24j11.lkr \ 18f24j50.lkr \ 18f24k20_e.lkr \ 18f24k20_g.lkr \ 18f24k20i_e.lkr \ 18f24k20i.lkr \ 18f24k20.lkr \ 18f2510_e.lkr \ 18f2510i_e.lkr \ 18f2510i.lkr \ 18f2510.lkr \ 18f2515_e.lkr \ 18f2515i_e.lkr \ 18f2515i.lkr \ 18f2515.lkr \ 18f2520_e.lkr \ 18f2520i_e.lkr \ 18f2520i.lkr \ 18f2520.lkr \ 18f2523_e.lkr \ 18f2523i_e.lkr \ 18f2523i.lkr \ 18f2523.lkr \ 18f2525_e.lkr \ 18f2525i_e.lkr \ 18f2525i.lkr \ 18f2525.lkr \ 18f252i.lkr \ 18f252.lkr \ 18f2539i.lkr \ 18f2539.lkr \ 18f2550_e.lkr \ 18f2550i_e.lkr \ 18f2550i.lkr \ 18f2550.lkr \ 18f2553_e.lkr \ 18f2553i_e.lkr \ 18f2553i.lkr \ 18f2553.lkr \ 18f2580_e.lkr \ 18f2580i_e.lkr \ 18f2580i.lkr \ 18f2580.lkr \ 18f2585_e.lkr \ 18f2585i_e.lkr \ 18f2585i.lkr \ 18f2585.lkr \ 18f258i.lkr \ 18f258.lkr \ 18f25j10_e.lkr \ 18f25j10i_e.lkr \ 18f25j10i.lkr \ 18f25j10.lkr \ 18f25j11.lkr \ 18f25j50.lkr \ 18f25k20_e.lkr \ 18f25k20i_e.lkr \ 18f25k20i.lkr \ 18f25k20.lkr \ 18f2610_e.lkr \ 18f2610i_e.lkr \ 18f2610i.lkr \ 18f2610.lkr \ 18f2620_e.lkr \ 18f2620i_e.lkr \ 18f2620i.lkr \ 18f2620.lkr \ 18f2680_e.lkr \ 18f2680i_e.lkr \ 18f2680i.lkr \ 18f2680.lkr \ 18f2682_e.lkr \ 18f2682i_e.lkr \ 18f2682i.lkr \ 18f2682.lkr \ 18f2685_e.lkr \ 18f2685i_e.lkr \ 18f2685i.lkr \ 18f2685.lkr \ 18f26j11.lkr \ 18f26j50.lkr \ 18f26k20_e.lkr \ 18f26k20_g.lkr \ 18f26k20i_e.lkr \ 18f26k20i.lkr \ 18f26k20.lkr \ 18f4220i.lkr \ 18f4220.lkr \ 18f4221_e.lkr \ 18f4221i_e.lkr \ 18f4221i.lkr \ 18f4221.lkr \ 18f4320i.lkr \ 18f4320.lkr \ 18f4321_e.lkr \ 18f4321i_e.lkr \ 18f4321i.lkr \ 18f4321.lkr \ 18f4331i.lkr \ 18f4331.lkr \ 18f43k20.lkr \ 18f4410_e.lkr \ 18f4410i_e.lkr \ 18f4410i.lkr \ 18f4410.lkr \ 18f4420_e.lkr \ 18f4420i_e.lkr \ 18f4420i.lkr \ 18f4420.lkr \ 18f4423_e.lkr \ 18f4423i_e.lkr \ 18f4423i.lkr \ 18f4423.lkr \ 18f442i.lkr \ 18f442.lkr \ 18f4431i.lkr \ 18f4431.lkr \ 18f4439i.lkr \ 18f4439.lkr \ 18f4450_e.lkr \ 18f4450i_e.lkr \ 18f4450i.lkr \ 18f4450.lkr \ 18f4455_e.lkr \ 18f4455i_e.lkr \ 18f4455i.lkr \ 18f4455.lkr \ 18f4458_e.lkr \ 18f4458i_e.lkr \ 18f4458i.lkr \ 18f4458.lkr \ 18f4480_e.lkr \ 18f4480i_e.lkr \ 18f4480i.lkr \ 18f4480.lkr \ 18f448i.lkr \ 18f448.lkr \ 18f44j10_e.lkr \ 18f44j10i_e.lkr \ 18f44j10i.lkr \ 18f44j10.lkr \ 18f44j11.lkr \ 18f44j50.lkr \ 18f44k20_e.lkr \ 18f44k20_g.lkr \ 18f44k20i_e.lkr \ 18f44k20i.lkr \ 18f44k20.lkr \ 18f4510_e.lkr \ 18f4510i_e.lkr \ 18f4510i.lkr \ 18f4510.lkr \ 18f4515_e.lkr \ 18f4515i_e.lkr \ 18f4515i.lkr \ 18f4515.lkr \ 18f4520_e.lkr \ 18f4520i_e.lkr \ 18f4520i.lkr \ 18f4520.lkr \ 18f4523_e.lkr \ 18f4523i_e.lkr \ 18f4523i.lkr \ 18f4523.lkr \ 18f4525_e.lkr \ 18f4525i_e.lkr \ 18f4525i.lkr \ 18f4525.lkr \ 18f452i.lkr \ 18f452.lkr \ 18f4539i.lkr \ 18f4539.lkr \ 18f4550_e.lkr \ 18f4550i_e.lkr \ 18f4550i.lkr \ 18f4550.lkr \ 18f4553_e.lkr \ 18f4553i_e.lkr \ 18f4553i.lkr \ 18f4553.lkr \ 18f4580_e.lkr \ 18f4580i_e.lkr \ 18f4580i.lkr \ 18f4580.lkr \ 18f4585_e.lkr \ 18f4585i_e.lkr \ 18f4585i.lkr \ 18f4585.lkr \ 18f458i.lkr \ 18f458.lkr \ 18f45j10_e.lkr \ 18f45j10i_e.lkr \ 18f45j10i.lkr \ 18f45j10.lkr \ 18f45j11.lkr \ 18f45j50.lkr \ 18f45k20_e.lkr \ 18f45k20i_e.lkr \ 18f45k20i.lkr \ 18f45k20.lkr \ 18f4610_e.lkr \ 18f4610i_e.lkr \ 18f4610i.lkr \ 18f4610.lkr \ 18f4620_e.lkr \ 18f4620i_e.lkr \ 18f4620i.lkr \ 18f4620.lkr \ 18f4680_e.lkr \ 18f4680i_e.lkr \ 18f4680i.lkr \ 18f4680.lkr \ 18f4682_e.lkr \ 18f4682i_e.lkr \ 18f4682i.lkr \ 18f4682.lkr \ 18f4685_e.lkr \ 18f4685i_e.lkr \ 18f4685i.lkr \ 18f4685.lkr \ 18f46j11.lkr \ 18f46j50.lkr \ 18f46k20_e.lkr \ 18f46k20_g.lkr \ 18f46k20i_e.lkr \ 18f46k20i.lkr \ 18f46k20.lkr \ 18f6310_e.lkr \ 18f6310i_e.lkr \ 18f6310i.lkr \ 18f6310.lkr \ 18f6390_e.lkr \ 18f6390i_e.lkr \ 18f6390i.lkr \ 18f6390.lkr \ 18f6393_e.lkr \ 18f6393i_e.lkr \ 18f6393i.lkr \ 18f6393.lkr \ 18f63j11_e.lkr \ 18f63j11i_e.lkr \ 18f63j11i.lkr \ 18f63j11.lkr \ 18f63j90_e.lkr \ 18f63j90i_e.lkr \ 18f63j90i.lkr \ 18f63j90.lkr \ 18f6410_e.lkr \ 18f6410i_e.lkr \ 18f6410i.lkr \ 18f6410.lkr \ 18f6490_e.lkr \ 18f6490i_e.lkr \ 18f6490i.lkr \ 18f6490.lkr \ 18f6493_e.lkr \ 18f6493i_e.lkr \ 18f6493i.lkr \ 18f6493.lkr \ 18f64j11_e.lkr \ 18f64j11i_e.lkr \ 18f64j11i.lkr \ 18f64j11.lkr \ 18f64j90_e.lkr \ 18f64j90i_e.lkr \ 18f64j90i.lkr \ 18f64j90.lkr \ 18f6520i.lkr \ 18f6520.lkr \ 18f6525i.lkr \ 18f6525.lkr \ 18f6527_e.lkr \ 18f6527i_e.lkr \ 18f6527i.lkr \ 18f6527.lkr \ 18f6585i.lkr \ 18f6585.lkr \ 18f65j10_e.lkr \ 18f65j10i_e.lkr \ 18f65j10i.lkr \ 18f65j10.lkr \ 18f65j11_e.lkr \ 18f65j11i_e.lkr \ 18f65j11i.lkr \ 18f65j11.lkr \ 18f65j15_e.lkr \ 18f65j15i_e.lkr \ 18f65j15i.lkr \ 18f65j15.lkr \ 18f65j50_e.lkr \ 18f65j50i_e.lkr \ 18f65j50i.lkr \ 18f65j50.lkr \ 18f65j90_e.lkr \ 18f65j90i_e.lkr \ 18f65j90i.lkr \ 18f65j90.lkr \ 18f6620i.lkr \ 18f6620.lkr \ 18f6621i.lkr \ 18f6621.lkr \ 18f6622_e.lkr \ 18f6622i_e.lkr \ 18f6622i.lkr \ 18f6622.lkr \ 18f6627_e.lkr \ 18f6627i_e.lkr \ 18f6627i.lkr \ 18f6627.lkr \ 18f6628_e.lkr \ 18f6628i_e.lkr \ 18f6628i.lkr \ 18f6628.lkr \ 18f6680i.lkr \ 18f6680.lkr \ 18f66j10_e.lkr \ 18f66j10i_e.lkr \ 18f66j10i.lkr \ 18f66j10.lkr \ 18f66j11_e.lkr \ 18f66j11i_e.lkr \ 18f66j11i.lkr \ 18f66j11.lkr \ 18f66j15_e.lkr \ 18f66j15i_e.lkr \ 18f66j15i.lkr \ 18f66j15.lkr \ 18f66j16_e.lkr \ 18f66j16i_e.lkr \ 18f66j16i.lkr \ 18f66j16.lkr \ 18f66j50_e.lkr \ 18f66j50i_e.lkr \ 18f66j50i.lkr \ 18f66j50.lkr \ 18f66j55_e.lkr \ 18f66j55i_e.lkr \ 18f66j55i.lkr \ 18f66j55.lkr \ 18f66j60_e.lkr \ 18f66j60i_e.lkr \ 18f66j60i.lkr \ 18f66j60.lkr \ 18f66j65_e.lkr \ 18f66j65i_e.lkr \ 18f66j65i.lkr \ 18f66j65.lkr \ 18f66j90.lkr \ 18f6720i.lkr \ 18f6720.lkr \ 18f6722_e.lkr \ 18f6722i_e.lkr \ 18f6722i.lkr \ 18f6722.lkr \ 18f6723_e.lkr \ 18f6723i_e.lkr \ 18f6723i.lkr \ 18f6723.lkr \ 18f67j10_e.lkr \ 18f67j10i_e.lkr \ 18f67j10i.lkr \ 18f67j10.lkr \ 18f67j11_e.lkr \ 18f67j11i_e.lkr \ 18f67j11i.lkr \ 18f67j11.lkr \ 18f67j50_e.lkr \ 18f67j50i_e.lkr \ 18f67j50i.lkr \ 18f67j50.lkr \ 18f67j60_e.lkr \ 18f67j60i_e.lkr \ 18f67j60i.lkr \ 18f67j60.lkr \ 18f67j90.lkr \ 18f8310_e.lkr \ 18f8310i_e.lkr \ 18f8310i.lkr \ 18f8310.lkr \ 18f8390_e.lkr \ 18f8390i_e.lkr \ 18f8390i.lkr \ 18f8390.lkr \ 18f8393_e.lkr \ 18f8393i_e.lkr \ 18f8393i.lkr \ 18f8393.lkr \ 18f83j11_e.lkr \ 18f83j11i_e.lkr \ 18f83j11i.lkr \ 18f83j11.lkr \ 18f83j90_e.lkr \ 18f83j90i_e.lkr \ 18f83j90i.lkr \ 18f83j90.lkr \ 18f8410_e.lkr \ 18f8410i_e.lkr \ 18f8410i.lkr \ 18f8410.lkr \ 18f8490_e.lkr \ 18f8490i_e.lkr \ 18f8490i.lkr \ 18f8490.lkr \ 18f8493_e.lkr \ 18f8493i_e.lkr \ 18f8493i.lkr \ 18f8493.lkr \ 18f84j11_e.lkr \ 18f84j11i_e.lkr \ 18f84j11i.lkr \ 18f84j11.lkr \ 18f84j90_e.lkr \ 18f84j90i_e.lkr \ 18f84j90i.lkr \ 18f84j90.lkr \ 18f8520i.lkr \ 18f8520.lkr \ 18f8525i.lkr \ 18f8525.lkr \ 18f8527_e.lkr \ 18f8527i_e.lkr \ 18f8527i.lkr \ 18f8527.lkr \ 18f8585i.lkr \ 18f8585.lkr \ 18f85j10_e.lkr \ 18f85j10i_e.lkr \ 18f85j10i.lkr \ 18f85j10.lkr \ 18f85j11_e.lkr \ 18f85j11i_e.lkr \ 18f85j11i.lkr \ 18f85j11.lkr \ 18f85j15_e.lkr \ 18f85j15i_e.lkr \ 18f85j15i.lkr \ 18f85j15.lkr \ 18f85j50_e.lkr \ 18f85j50i_e.lkr \ 18f85j50i.lkr \ 18f85j50.lkr \ 18f85j90_e.lkr \ 18f85j90i_e.lkr \ 18f85j90i.lkr \ 18f85j90.lkr \ 18f8620i.lkr \ 18f8620.lkr \ 18f8621i.lkr \ 18f8621.lkr \ 18f8622_e.lkr \ 18f8622i_e.lkr \ 18f8622i.lkr \ 18f8622.lkr \ 18f8627_e.lkr \ 18f8627i_e.lkr \ 18f8627i.lkr \ 18f8627.lkr \ 18f8628_e.lkr \ 18f8628i_e.lkr \ 18f8628i.lkr \ 18f8628.lkr \ 18f8680i.lkr \ 18f8680.lkr \ 18f86j10_e.lkr \ 18f86j10i_e.lkr \ 18f86j10i.lkr \ 18f86j10.lkr \ 18f86j11_e.lkr \ 18f86j11i_e.lkr \ 18f86j11i.lkr \ 18f86j11.lkr \ 18f86j15_e.lkr \ 18f86j15i_e.lkr \ 18f86j15i.lkr \ 18f86j15.lkr \ 18f86j16_e.lkr \ 18f86j16i_e.lkr \ 18f86j16i.lkr \ 18f86j16.lkr \ 18f86j50_e.lkr \ 18f86j50i_e.lkr \ 18f86j50i.lkr \ 18f86j50.lkr \ 18f86j55_e.lkr \ 18f86j55i_e.lkr \ 18f86j55i.lkr \ 18f86j55.lkr \ 18f86j60_e.lkr \ 18f86j60i_e.lkr \ 18f86j60i.lkr \ 18f86j60.lkr \ 18f86j65_e.lkr \ 18f86j65i_e.lkr \ 18f86j65i.lkr \ 18f86j65.lkr \ 18f86j90.lkr \ 18f8720i.lkr \ 18f8720.lkr \ 18f8722_e.lkr \ 18f8722i_e.lkr \ 18f8722i.lkr \ 18f8722.lkr \ 18f8723_e.lkr \ 18f8723i_e.lkr \ 18f8723i.lkr \ 18f8723.lkr \ 18f87j10_e.lkr \ 18f87j10i_e.lkr \ 18f87j10i.lkr \ 18f87j10.lkr \ 18f87j11_e.lkr \ 18f87j11i_e.lkr \ 18f87j11i.lkr \ 18f87j11.lkr \ 18f87j50_e.lkr \ 18f87j50i_e.lkr \ 18f87j50i.lkr \ 18f87j50.lkr \ 18f87j60_e.lkr \ 18f87j60i_e.lkr \ 18f87j60i.lkr \ 18f87j60.lkr \ 18f87j90.lkr \ 18f96j60_e.lkr \ 18f96j60i_e.lkr \ 18f96j60i.lkr \ 18f96j60.lkr \ 18f96j65_e.lkr \ 18f96j65i_e.lkr \ 18f96j65i.lkr \ 18f96j65.lkr \ 18f97j60_e.lkr \ 18f97j60i_e.lkr \ 18f97j60i.lkr \ 18f97j60.lkr \ 18lf13k22_e.lkr \ 18lf13k22i_e.lkr \ 18lf13k22i.lkr \ 18lf13k22.lkr \ 18lf13k50_e.lkr \ 18lf13k50i_e.lkr \ 18lf13k50i.lkr \ 18lf13k50.lkr \ 18lf14k22_e.lkr \ 18lf14k22i_e.lkr \ 18lf14k22i.lkr \ 18lf14k22.lkr \ 18lf14k50_e.lkr \ 18lf14k50i_e.lkr \ 18lf14k50i.lkr \ 18lf14k50.lkr \ 18lf24j11.lkr \ 18lf24j50.lkr \ 18lf25j11.lkr \ 18lf25j50.lkr \ 18lf26j11.lkr \ 18lf26j50.lkr \ 18lf44j11.lkr \ 18lf44j50.lkr \ 18lf45j11.lkr \ 18lf45j50.lkr \ 18lf46j11.lkr \ 18lf46j50.lkr \ hcs1365.lkr \ hcs1370.lkr \ mcv08a.lkr \ mcv14a.lkr \ mcv18a.lkr \ mcv28a.lkr \ ps500.lkr \ ps810.lkr \ rf509af.lkr \ rf509ag.lkr \ rf675fi.lkr \ rf675f.lkr \ rf675hi.lkr \ rf675h.lkr \ rf675ki.lkr \ rf675k.lkr pkgdata_DATA = $(LKR_FILES) EXTRA_DIST = $(LKR_FILES) Makefile.sh gputils-0.13.7/lkr/10f202.lkr0000644000175000017500000000070611156313115012326 00000000000000// Sample linker command file for 10F202 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x08 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f84j11.lkr0000644000175000017500000000142611156521271012606 00000000000000// File: 18f84j11.lkr // Sample linker script for the PIC18F84J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c72a.lkr0000644000175000017500000000107411156521271012422 00000000000000// Sample linker command file for 16C72A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8723i.lkr0000644000175000017500000000342011156521271012607 00000000000000// File: 18f8723i.lkr // Sample ICD2 linker script for the PIC18F8723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f883i.lkr0000644000175000017500000000311511156521271012525 00000000000000// Sample ICD2 linker command file for 16F883 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbgspr START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2458.lkr0000644000175000017500000000235011156521271012436 00000000000000// File: 18f2458.lkr // Sample linker script for the PIC18F2458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f14k22_e.lkr0000644000175000017500000000162111156521271013103 00000000000000// File: 18f14k22_e.lkr // Sample linker script for the PIC18F14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c57.lkr0000644000175000017500000000255511156521271012271 00000000000000// Sample linker command file for 16C57 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x28 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c62b.lkr0000644000175000017500000000107411156521271012422 00000000000000// Sample linker command file for 16C62B LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f67j11i.lkr0000644000175000017500000000315711156521271012763 00000000000000// File: 18f67j11i.lkr // Sample ICD2 linker script for the PIC18F67J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j10i_e.lkr0000644000175000017500000000304411156521271013263 00000000000000// File: 18f87j10i_e.lkr // Sample ICD2 linker script for the PIC18F87J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16hv610i.lkr0000644000175000017500000000161511156521271012704 00000000000000// Sample ICD2 linker command file for 16HV610 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8723i_e.lkr0000644000175000017500000000342211156521271013115 00000000000000// File: 18f8723i_e.lkr // Sample ICD2 linker script for the PIC18F8723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j15.lkr0000644000175000017500000000271711156521271012616 00000000000000// File: 18f66j15.lkr // Sample linker script for the PIC18F66J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/hcs1365.lkr0000644000175000017500000000244511156521271012616 00000000000000// Sample linker command file for HCS1365 // $Id: hcs1365.lkr,v 1.4 2006/02/04 00:06:46 nairnj Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0x7FF END=0x7FF PROTECTED SHAREBANK NAME=sfr_shr START=0x0 END=0x4 PROTECTED SHAREBANK NAME=sfr_shr START=0x20 END=0x24 PROTECTED SHAREBANK NAME=sfr_shr START=0x40 END=0x44 PROTECTED SHAREBANK NAME=sfr_shr START=0x60 END=0x64 PROTECTED DATABANK NAME=sfr_bnk0 START=0x5 END=0x7 PROTECTED DATABANK NAME=sfr_bnk1 START=0x25 END=0x27 PROTECTED DATABANK NAME=sfr_bnk2 START=0x45 END=0x47 PROTECTED DATABANK NAME=sfr_bnk3 START=0x65 END=0x67 PROTECTED SHAREBANK NAME=gpr_shr START=0x8 END=0xF SHAREBANK NAME=gpr_shr START=0x28 END=0x2F SHAREBANK NAME=gpr_shr START=0x48 END=0x4F SHAREBANK NAME=gpr_shr START=0x68 END=0x6F DATABANK NAME=gpr_bnk0 START=0x10 END=0x1F DATABANK NAME=gpr_bnk1 START=0x30 END=0x3F DATABANK NAME=gpr_bnk2 START=0x50 END=0x5F DATABANK NAME=gpr_bnk3 START=0x70 END=0x7F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16c63a.lkr0000644000175000017500000000127011156521271012420 00000000000000// Sample linker command file for 16C63A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f13k22i.lkr0000644000175000017500000000153311156521271012751 00000000000000// File: 18f13k22i.lkr // Sample ICD2 linker script for the PIC18F13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k22_e.lkr0000644000175000017500000000153111156521271013256 00000000000000// File: 18lf13k22_e.lkr // Sample linker script for the PIC18LF13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf14k50_e.lkr0000644000175000017500000000171511156521271013264 00000000000000// File: 18lf14k50_e.lkr // Sample linker script for the PIC18LF14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j10i_e.lkr0000644000175000017500000000212311156521271013255 00000000000000// File: 18f66j10i_e.lkr // Sample ICD2 linker script for the PIC18F66J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16lf1934.lkr0000644000175000017500000001331411156521271012610 00000000000000// File: 16lf1934_g.lkr // Generic linker script for the PIC16LF1934 processor LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x8000 END=0x8003 PROTECTED CODEPAGE NAME=.devid START=0x8006 END=0x8006 PROTECTED CODEPAGE NAME=.config START=0x8007 END=0x8008 PROTECTED CODEPAGE NAME=eedata START=0xF000 END=0xF0FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=sfr4 START=0x200 END=0x21F PROTECTED DATABANK NAME=sfr5 START=0x280 END=0x29F PROTECTED DATABANK NAME=sfr6 START=0x300 END=0x31F PROTECTED DATABANK NAME=sfr7 START=0x380 END=0x39F PROTECTED DATABANK NAME=sfr8 START=0x400 END=0x41F PROTECTED DATABANK NAME=sfr9 START=0x480 END=0x49F PROTECTED DATABANK NAME=sfr10 START=0x500 END=0x51F PROTECTED DATABANK NAME=sfr11 START=0x580 END=0x59F PROTECTED DATABANK NAME=sfr12 START=0x600 END=0x61F PROTECTED DATABANK NAME=sfr13 START=0x680 END=0x69F PROTECTED DATABANK NAME=sfr14 START=0x700 END=0x71F PROTECTED DATABANK NAME=sfr15 START=0x780 END=0x7EF PROTECTED DATABANK NAME=sfr16 START=0x800 END=0x81F PROTECTED DATABANK NAME=sfr17 START=0x880 END=0x89F PROTECTED DATABANK NAME=sfr18 START=0x900 END=0x91F PROTECTED DATABANK NAME=sfr19 START=0x980 END=0x99F PROTECTED DATABANK NAME=sfr20 START=0xA00 END=0xA1F PROTECTED DATABANK NAME=sfr21 START=0xA80 END=0xA9F PROTECTED DATABANK NAME=sfr22 START=0xB00 END=0xB1F PROTECTED DATABANK NAME=sfr23 START=0xB80 END=0xB9F PROTECTED DATABANK NAME=sfr24 START=0xC00 END=0xC1F PROTECTED DATABANK NAME=sfr25 START=0xC80 END=0xC9F PROTECTED DATABANK NAME=sfr26 START=0xD00 END=0xD1F PROTECTED DATABANK NAME=sfr27 START=0xD80 END=0xD9F PROTECTED DATABANK NAME=sfr28 START=0xE00 END=0xE1F PROTECTED DATABANK NAME=sfr29 START=0xE80 END=0xE9F PROTECTED DATABANK NAME=sfr30 START=0xF00 END=0xF1F PROTECTED DATABANK NAME=sfr31 START=0xF80 END=0xFEF PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobank START=0x70 END=0x7F SHAREBANK NAME=gprnobank START=0xF0 END=0xFF SHAREBANK NAME=gprnobank START=0x170 END=0x17F SHAREBANK NAME=gprnobank START=0x1F0 END=0x1FF SHAREBANK NAME=gprnobank START=0x270 END=0x27F SHAREBANK NAME=gprnobank START=0x2F0 END=0x2FF SHAREBANK NAME=gprnobank START=0x370 END=0x37F SHAREBANK NAME=gprnobank START=0x3F0 END=0x3FF SHAREBANK NAME=gprnobank START=0x470 END=0x47F SHAREBANK NAME=gprnobank START=0x4F0 END=0x4FF SHAREBANK NAME=gprnobank START=0x570 END=0x57F SHAREBANK NAME=gprnobank START=0x5F0 END=0x5FF SHAREBANK NAME=gprnobank START=0x670 END=0x67F SHAREBANK NAME=gprnobank START=0x6F0 END=0x6FF SHAREBANK NAME=gprnobank START=0x770 END=0x77F SHAREBANK NAME=gprnobank START=0x7F0 END=0x7FF SHAREBANK NAME=gprnobank START=0x870 END=0x87F SHAREBANK NAME=gprnobank START=0x8F0 END=0x8FF SHAREBANK NAME=gprnobank START=0x970 END=0x97F SHAREBANK NAME=gprnobank START=0x9F0 END=0x9FF SHAREBANK NAME=gprnobank START=0xA70 END=0xA7F SHAREBANK NAME=gprnobank START=0xAF0 END=0xAFF SHAREBANK NAME=gprnobank START=0xB70 END=0xB7F SHAREBANK NAME=gprnobank START=0xBF0 END=0xBFF SHAREBANK NAME=gprnobank START=0xC70 END=0xC7F SHAREBANK NAME=gprnobank START=0xCF0 END=0xCFF SHAREBANK NAME=gprnobank START=0xD70 END=0xD7F SHAREBANK NAME=gprnobank START=0xDF0 END=0xDFF SHAREBANK NAME=gprnobank START=0xE70 END=0xE7F SHAREBANK NAME=gprnobank START=0xEF0 END=0xEFF SHAREBANK NAME=gprnobank START=0xF70 END=0xF7F SHAREBANK NAME=gprnobank START=0xFF0 END=0xFFF SECTION NAME=PROG0 ROM=page0 // ROM code space - page0 SECTION NAME=PROG1 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f877a.lkr0000644000175000017500000000276411156521271012531 00000000000000// Sample linker command file for 16F877a and 876a LIBPATH . CODEPAGE NAME=page0 START=0x0000 END=0x07FF CODEPAGE NAME=page1 START=0x0800 END=0x0FFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2620i.lkr0000644000175000017500000000341711156521271012603 00000000000000// File: 18f2620i.lkr // Sample ICD2 linker script for the PIC18F2620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f14k50i_e.lkr0000644000175000017500000000172111156521271013256 00000000000000// File: 18f14k50i_e.lkr // Sample ICD2 linker script for the PIC18F14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24k20i.lkr0000644000175000017500000000203711156521271012751 00000000000000// File: 18f24k20i.lkr // Sample ICD2 linker script for the PIC18F24K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12ce518.lkr0000644000175000017500000000070611156521271012510 00000000000000// Sample linker command file for 12CE518 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gprs START=0x07 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f83j90_e.lkr0000644000175000017500000000143011156521271013113 00000000000000// File: 18f83j90_e.lkr // Sample linker script for the PIC18F83J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4553_e.lkr0000644000175000017500000000226111156521271012741 00000000000000// File: 18f4553_e.lkr // Sample linker script for the PIC18F4553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j50.lkr0000644000175000017500000000303411156521271012607 00000000000000// File: 18f67j50.lkr // Sample linker script for the PIC18F67J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f726.lkr0000644000175000017500000000256311156521271012356 00000000000000// Sample linker command file for 16F726 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2423_e.lkr0000644000175000017500000000166511156521271012742 00000000000000// File: 18f2423_e.lkr // Sample linker script for the PIC18F2423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2553.lkr0000644000175000017500000000235011156521271012432 00000000000000// File: 18f2553.lkr // Sample linker script for the PIC18F2553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j11.lkr0000644000175000017500000000303411156521271012604 00000000000000// File: 18f67j11.lkr // Sample linker script for the PIC18F67J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2455i_e.lkr0000644000175000017500000000252411156521271013113 00000000000000// File: 18f2455i_e.lkr // Sample ICD2 linker script for the PIC18F2455 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k22i_e.lkr0000644000175000017500000000153711156521271013435 00000000000000// File: 18lf13k22i_e.lkr // Sample ICD2 linker script for the PIC18LF13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j90.lkr0000644000175000017500000000275511156521271012624 00000000000000// File: 18f67j90_g.lkr // Generic linker script for the PIC18F67J90 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF53 DATABANK NAME=sfr15 START=0xF54 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2480_e.lkr0000644000175000017500000000205211156521271012734 00000000000000// File: 18f2480_e.lkr // Sample linker script for the PIC18F2480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f870.lkr0000644000175000017500000000230611156521271012351 00000000000000// Sample linker command file for 16F870 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x20 END=0x6F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x16F PROTECTED SHAREBANK NAME=gprnobnk1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk1 START=0x1A0 END=0x1BF PROTECTED SHAREBANK NAME=gprnobnk2 START=0x70 END=0x7F SHAREBANK NAME=gprnobnk2 START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk2 START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk2 START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f65j10i.lkr0000644000175000017500000000212111156521271012746 00000000000000// File: 18f65j10i.lkr // Sample ICD2 linker script for the PIC18F65J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4220i.lkr0000644000175000017500000000174211156521271012600 00000000000000// File: 18f4220i.lkr // Sample ICD2 linker script for the PIC18F4220 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xDBF CODEPAGE NAME=debug START=0xDC0 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f639.lkr0000644000175000017500000000236011156521271012354 00000000000000// Sample linker command file for 16F639 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x0 END=0x0B PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x100 END=0x10B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x80 END=0x8B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x180 END=0x18B PROTECTED DATABANK NAME=sfr0 START=0x0C END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x8C END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x10C END=0x11F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18lf14k22.lkr0000644000175000017500000000162111156521271012753 00000000000000// File: 18lf14k22.lkr // Sample linker script for the PIC18LF14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f630.lkr0000644000175000017500000000226311156521271012345 00000000000000// Sample linker command file for 16F630 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FE CODEPAGE NAME=oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0 START=0x20 END=0x5F SHAREBANK NAME=gpr0 START=0xA0 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=oscval // Oscillator value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f876.lkr0000644000175000017500000000275011156521271012362 00000000000000// Sample linker command file for 16F876 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/12f508i.lkr0000644000175000017500000000113111156521271012507 00000000000000// Sample linker command file for 12F508 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 12F508.lkr but named 12F508i.lkr LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gprs START=0x07 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8520.lkr0000644000175000017500000000223411156521271012433 00000000000000// File: 18f8520.lkr // Sample linker script for the PIC18F8520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j10_e.lkr0000644000175000017500000000200011156521271013100 00000000000000// File: 18f86j10_e.lkr // Sample linker script for the PIC18F86J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f916i.lkr0000644000175000017500000000370511156521271012527 00000000000000// Sample ICD2 linker command file for 16F916 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=gpr2dbg START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f6393i.lkr0000644000175000017500000000203211156521271012606 00000000000000// File: 18f6393i.lkr // Sample ICD2 linker script for the PIC18F6393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f44j50.lkr0000644000175000017500000000277711156521271012617 00000000000000// File: 18f44j50_g.lkr // Generic linker script for the PIC18F44J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6620.lkr0000644000175000017500000000306211156521271012432 00000000000000// File: 18f6620.lkr // Sample linker script for the PIC18F6620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12hv615.lkr0000644000175000017500000000123111156521271012526 00000000000000// Sample linker command file for 12HV615 // Based on 12F615 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2221_e.lkr0000644000175000017500000000157211156521271012733 00000000000000// File: 18f2221_e.lkr // Sample linker script for the PIC18F2221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16hv616.lkr0000644000175000017500000000131311156521271012534 00000000000000// Sample linker command file for 16HV616 // Based on 16F616 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f684.lkr0000644000175000017500000000244411156521271012357 00000000000000// Sample linker command file for 16F684 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=mfg_code START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=icd_inst // ICD instruction SECTION NAME=MFG_CODE ROM=mfg_code // Manufacturing code SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=CALIBR ROM=.config // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16lf722.lkr0000644000175000017500000000165111156521271012523 00000000000000// Sample linker command file for 16LF722 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4680_e.lkr0000644000175000017500000000315611156521271012746 00000000000000// File: 18f4680_e.lkr // Sample linker script for the PIC18F4680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f609.lkr0000644000175000017500000000120511156521271012342 00000000000000// Sample linker command file for 12F609 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2431i.lkr0000644000175000017500000000203511156521271012576 00000000000000// File: 18f2431i.lkr // Sample ICD2 linker script for the PIC18F2431 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f616.lkr0000644000175000017500000000126711156521271012354 00000000000000// Sample linker command file for 16F616 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f24j10i.lkr0000644000175000017500000000155111156521271012747 00000000000000// File: 18f24j10i.lkr // Sample ICD2 linker script for the PIC18F24J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr84.lkr0000644000175000017500000000120111156521271012436 00000000000000// Sample linker command file for 16CR84 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x4F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f83j11.lkr0000644000175000017500000000142611156521271012605 00000000000000// File: 18f83j11.lkr // Sample linker script for the PIC18F83J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16ce623.lkr0000644000175000017500000000117711156521271012514 00000000000000// Sample linker command file for 16CE623 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gprs START=0x20 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16lf726.lkr0000644000175000017500000000256411156521271012533 00000000000000// Sample linker command file for 16LF726 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f24j50.lkr0000644000175000017500000000277711156521271012615 00000000000000// File: 18f24j50_g.lkr // Generic linker script for the PIC18F24J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k22.lkr0000644000175000017500000000152711156521271012757 00000000000000// File: 18lf13k22.lkr // Sample linker script for the PIC18LF13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4458_e.lkr0000644000175000017500000000226111156521271012745 00000000000000// File: 18f4458_e.lkr // Sample linker script for the PIC18F4458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j15i.lkr0000644000175000017500000000304211156521271012757 00000000000000// File: 18f66j15i.lkr // Sample ICD2 linker script for the PIC18F66J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j65i_e.lkr0000644000175000017500000000316111156521271013272 00000000000000// File: 18f66j65i_e.lkr // Sample ICD2 linker script for the PIC18F66J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f628a.lkr0000644000175000017500000000272411156521271012517 00000000000000// Sample linker command file for 16F628A LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10B PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x14F SHAREBANK NAME=gprnobnk0 START=0x70 END=0x7E SHAREBANK NAME=gprnobnk0 START=0xF0 END=0xFE PROTECTED SHAREBANK NAME=gprnobnk0 START=0x170 END=0x17E PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1F0 END=0x1FE PROTECTED SHAREBANK NAME=gprnobnk1 START=0x7F END=0x7F SHAREBANK NAME=gprnobnk1 START=0xFF END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x17F END=0x17F PROTECTED DATABANK NAME=testreg START=0x1FF END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c662.lkr0000644000175000017500000000145111156521271012345 00000000000000// Sample linker command file for 16C662 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j10.lkr0000644000175000017500000000177611156521271012617 00000000000000// File: 18f86j10.lkr // Sample linker script for the PIC18F86J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6410i.lkr0000644000175000017500000000203211156521271012574 00000000000000// File: 18f6410i.lkr // Sample ICD2 linker script for the PIC18F6410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j55.lkr0000644000175000017500000000303411156521271012613 00000000000000// File: 18f66j55.lkr // Sample linker script for the PIC18F66J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f631.lkr0000644000175000017500000000217611156521271012351 00000000000000// Sample linker command file for 16F677 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/12f519.lkr0000644000175000017500000000167011156521271012350 00000000000000// Sample linker command file for 12F519 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=flashmem START=0x400 END=0x43F PROTECTED CODEPAGE NAME=.idlocs START=0x440 END=0x443 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x06 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=gprnobnk START=0x07 END=0x0F SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=FLASHDATA ROM=flashmem // Writable Flash Data Memory SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6410i_e.lkr0000644000175000017500000000203411156521271013102 00000000000000// File: 18f6410i_e.lkr // Sample ICD2 linker script for the PIC18F6410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4523i.lkr0000644000175000017500000000231311156521271012601 00000000000000// File: 18f4523i.lkr // Sample ICD2 linker script for the PIC18F4523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1320i.lkr0000644000175000017500000000165111156521271012575 00000000000000// File: 18f1320i.lkr // Sample ICD2 linker script for the PIC18F1320 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1E3F CODEPAGE NAME=debug START=0x1E40 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xF3 DATABANK NAME=dbgspr START=0xF4 END=0xFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2439i.lkr0000644000175000017500000000172011156521271012606 00000000000000// File: 18f2439i.lkr // Sample ICD2 linker script for the PIC18F2439 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2DBF CODEPAGE NAME=debug START=0x2DC0 END=0x2FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x27F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2520i_e.lkr0000644000175000017500000000240611156521271013103 00000000000000// File: 18f2520i_e.lkr // Sample ICD2 linker script for the PIC18F2520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f66j55i_e.lkr0000644000175000017500000000316111156521271013271 00000000000000// File: 18f66j55i_e.lkr // Sample ICD2 linker script for the PIC18F66J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f883.lkr0000644000175000017500000000231411156521271012354 00000000000000// Sample linker command file for 16F883 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16c55.lkr0000644000175000017500000000071311156521271012261 00000000000000// Sample linker command file for 16C55 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED DATABANK NAME=sfrs START=0x0 END=0x7 PROTECTED DATABANK NAME=gprs START=0x8 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f636i.lkr0000644000175000017500000000317311156521271012525 00000000000000// Sample ICD2 linker command file for 16F636 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x0 END=0x0B PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x100 END=0x10B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x80 END=0x8B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x180 END=0x18B PROTECTED DATABANK NAME=sfr0 START=0x0C END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x8C END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x10C END=0x11F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=gpr1 START=0xA0 END=0xBF DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f8393i_e.lkr0000644000175000017500000000203411156521271013116 00000000000000// File: 18f8393i_e.lkr // Sample ICD2 linker script for the PIC18F8393 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2423i.lkr0000644000175000017500000000203511156521271012577 00000000000000// File: 18f2423i.lkr // Sample ICD2 linker script for the PIC18F2423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4221i_e.lkr0000644000175000017500000000203511156521271013101 00000000000000// File: 18f4221i_e.lkr // Sample ICD2 linker script for the PIC18F4221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xDBF CODEPAGE NAME=debug START=0xDC0 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j50i_e.lkr0000644000175000017500000000316011156521271013265 00000000000000// File: 18f86j50i_e.lkr // Sample ICD2 linker script for the PIC18F86J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2510i.lkr0000644000175000017500000000217311156521271012577 00000000000000// File: 18f2510i.lkr // Sample ICD2 linker script for the PIC18F2510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf13k50_e.lkr0000644000175000017500000000162311156521271013261 00000000000000// File: 18lf13k50_e.lkr // Sample linker script for the PIC18LF13K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4525_e.lkr0000644000175000017500000000324711156521271012745 00000000000000// File: 18f4525_e.lkr // Sample linker script for the PIC18F4525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j10i.lkr0000644000175000017500000000304211156521271012755 00000000000000// File: 18f87j10i.lkr // Sample ICD2 linker script for the PIC18F87J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16lf727.lkr0000644000175000017500000000256411156521271012534 00000000000000// Sample linker command file for 16LF727 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6722i_e.lkr0000644000175000017500000000342211156521271013112 00000000000000// File: 18f6722i_e.lkr // Sample ICD2 linker script for the PIC18F6722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2321i.lkr0000644000175000017500000000174311156521271012601 00000000000000// File: 18f2321i.lkr // Sample ICD2 linker script for the PIC18F2321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j11.lkr0000644000175000017500000000177611156521271012615 00000000000000// File: 18f65j11.lkr // Sample linker script for the PIC18F65J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j11i_e.lkr0000644000175000017500000000316111156521271013262 00000000000000// File: 18f67j11i_e.lkr // Sample ICD2 linker script for the PIC18F67J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c766.lkr0000644000175000017500000000520611156521271012355 00000000000000// Sample linker command file for 17C766 // $Id: 17c766.lkr,v 1.5 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED SHAREBANK NAME=sfrnobnk START=0x400 END=0x40F PROTECTED SHAREBANK NAME=sfrnobnk START=0x500 END=0x50F PROTECTED SHAREBANK NAME=sfrnobnk START=0x600 END=0x60F PROTECTED SHAREBANK NAME=sfrnobnk START=0x700 END=0x70F PROTECTED SHAREBANK NAME=sfrnobnk START=0x800 END=0x80F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED DATABANK NAME=sfr4 START=0x410 END=0x417 PROTECTED DATABANK NAME=sfr5 START=0x510 END=0x517 PROTECTED DATABANK NAME=sfr6 START=0x610 END=0x617 PROTECTED DATABANK NAME=sfr7 START=0x710 END=0x717 PROTECTED DATABANK NAME=sfr8 START=0x810 END=0x817 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=sfrprod START=0x418 END=0x419 PROTECTED SHAREBANK NAME=sfrprod START=0x518 END=0x519 PROTECTED SHAREBANK NAME=sfrprod START=0x618 END=0x619 PROTECTED SHAREBANK NAME=sfrprod START=0x718 END=0x719 PROTECTED SHAREBANK NAME=sfrprod START=0x818 END=0x819 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F SHAREBANK NAME=registers START=0x41A END=0x41F SHAREBANK NAME=registers START=0x51A END=0x51F SHAREBANK NAME=registers START=0x61A END=0x61F SHAREBANK NAME=registers START=0x71A END=0x71F SHAREBANK NAME=registers START=0x81A END=0x81F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF DATABANK NAME=gpr2 START=0x220 END=0x2FF DATABANK NAME=gpr3 START=0x320 END=0x3FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18f44k20_g.lkr0000644000175000017500000000335611156521271013115 00000000000000// File: 18f44k20_g.lkr // Generic linker script for the PIC18F44K20 processor #DEFINE _CODEEND _DEBUGCODESTART - 1 #DEFINE _CEND _CODEEND + _DEBUGCODELEN #DEFINE _DATAEND _DEBUGDATASTART - 1 #DEFINE _DEND _DATAEND + _DEBUGDATALEN LIBPATH . #IFDEF _CRUNTIME #IFDEF _EXTENDEDMODE FILES c018i_e.o FILES clib_e.lib FILES p18f44k20_e.lib #ELSE FILES c018i.o FILES clib.lib FILES p18f44k20.lib #FI #FI #IFDEF _DEBUGCODESTART CODEPAGE NAME=page START=0x0 END=_CODEEND CODEPAGE NAME=debug START=_DEBUGCODESTART END=_CEND PROTECTED #ELSE CODEPAGE NAME=page START=0x0 END=0x3FFF #FI CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED #IFDEF _EXTENDEDMODE DATABANK NAME=gpre START=0x0 END=0x5F #ELSE ACCESSBANK NAME=accessram START=0x0 END=0x5F #FI DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF #IFDEF _DEBUGDATASTART DATABANK NAME=gpr2 START=0x200 END=_DATAEND DATABANK NAME=dbgspr START=_DEBUGDATASTART END=_DEND PROTECTED #ELSE //no debug DATABANK NAME=gpr2 START=0x200 END=0x2FF #FI ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED #IFDEF _CRUNTIME SECTION NAME=CONFIG ROM=config #IFDEF _DEBUGDATASTART STACK SIZE=0x100 RAM=gpr1 #ELSE STACK SIZE=0x100 RAM=gpr2 #FI #FI gputils-0.13.7/lkr/16f887.lkr0000644000175000017500000000275011156521271012364 00000000000000// Sample linker command file for 16F887 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f458.lkr0000644000175000017500000000216311156521271012356 00000000000000// File: 18f458.lkr // Sample linker script for the PIC18F458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f610.lkr0000644000175000017500000000120411156521271012335 00000000000000// Sample linker command file for 16F610 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x6F SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f97j60i.lkr0000644000175000017500000000315711156521271012772 00000000000000// File: 18f97j60i.lkr // Sample ICD2 linker script for the PIC18F97J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16lf726i.lkr0000644000175000017500000000346611156521271012706 00000000000000// Sample ICD2 linker command file for 16LF726 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=gpr3dbg START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j11i_e.lkr0000644000175000017500000000316011156521271013262 00000000000000// File: 18f86j11i_e.lkr // Sample ICD2 linker script for the PIC18F86J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f64j90i_e.lkr0000644000175000017500000000155311156521271013271 00000000000000// File: 18f64j90i_e.lkr // Sample ICD2 linker script for the PIC18F64J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j10i.lkr0000644000175000017500000000212111156521271012751 00000000000000// File: 18f86j10i.lkr // Sample ICD2 linker script for the PIC18F86J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6585i.lkr0000644000175000017500000000351011156521271012613 00000000000000// File: 18f6585i.lkr // Sample ICD2 linker script for the PIC18F6585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26j11.lkr0000644000175000017500000000277711156521271012614 00000000000000// File: 18f26j11_g.lkr // Generic linker script for the PIC18F26J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6627i.lkr0000644000175000017500000000342011156521271012610 00000000000000// File: 18f6627i.lkr // Sample ICD2 linker script for the PIC18F6627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17D7F CODEPAGE NAME=debug START=0x17D80 END=0x17FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f882.lkr0000755000175000017500000000204611156521271012360 00000000000000// Sample linker command file for 16F882 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18D PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f86j60i_e.lkr0000644000175000017500000000316011156521271013266 00000000000000// File: 18f86j60i_e.lkr // Sample ICD2 linker script for the PIC18F86J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f648ai.lkr0000644000175000017500000000420411156521271012665 00000000000000// Sample ICD2 linker command file for 16F648A LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icd_inst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.oscval START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=.test START=0x2009 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbg2 START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space SECTION NAME=PROG2 ROM=page1 // ROM code space SECTION NAME=DEBUG ROM=debug // ICD debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=ICD_INST ROM=.icd_inst // ICD instruction SECTION NAME=DEVID ROM=.devid // device id SECTION NAME=OSCVAL ROM=.oscval // Oscillator value SECTION NAME=TEST ROM=.test // Test program memory SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f86j15_e.lkr0000644000175000017500000000272111156521271013117 00000000000000// File: 18f86j15_e.lkr // Sample linker script for the PIC18F86J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f83j90i.lkr0000644000175000017500000000155111156521271012764 00000000000000// File: 18f83j90i.lkr // Sample ICD2 linker script for the PIC18F83J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18c252.lkr0000644000175000017500000000172611156521271012347 00000000000000// File: 18c252.lkr // Sample linker script for the PIC18C252 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x300007 PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/Makefile.in0000644000175000017500000006115611156521271013061 00000000000000# Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ top_builddir = .. am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd INSTALL = @INSTALL@ install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = lkr DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = SOURCES = DIST_SOURCES = am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; am__vpath_adj = case $$p in \ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ *) f=$$p;; \ esac; am__strip_dir = `echo $$p | sed -e 's|^.*/||'`; am__installdirs = "$(DESTDIR)$(pkgdatadir)" pkgdataDATA_INSTALL = $(INSTALL_DATA) DATA = $(pkgdata_DATA) DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) pkgdatadir = @GPUTILS_LKR_PATH@ ACLOCAL = @ACLOCAL@ AMDEP_FALSE = @AMDEP_FALSE@ AMDEP_TRUE = @AMDEP_TRUE@ AMTAR = @AMTAR@ AM_CFLAGS = @AM_CFLAGS@ AM_LDFLAGS = @AM_LDFLAGS@ AR = @AR@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPP = @CPP@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EGREP = @EGREP@ EXEEXT = @EXEEXT@ GPUTILS_HEADER_PATH = @GPUTILS_HEADER_PATH@ GPUTILS_LIB_PATH = @GPUTILS_LIB_PATH@ GPUTILS_LKR_PATH = @GPUTILS_LKR_PATH@ GREP = @GREP@ IBERTYOBJS = @IBERTYOBJS@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LDFLAGS = @LDFLAGS@ LEX = @LEX@ LEXLIB = @LEXLIB@ LEX_OUTPUT_ROOT = @LEX_OUTPUT_ROOT@ LIBGPUTILS = @LIBGPUTILS@ LIBIBERTY = @LIBIBERTY@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAINTAINER_MODE_FALSE = @MAINTAINER_MODE_FALSE@ MAINTAINER_MODE_TRUE = @MAINTAINER_MODE_TRUE@ MAKEINFO = @MAKEINFO@ MAKE_SUBDIRS = @MAKE_SUBDIRS@ OBJEXT = @OBJEXT@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ RANLIB = @RANLIB@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ YACC = @YACC@ YFLAGS = @YFLAGS@ ac_ct_CC = @ac_ct_CC@ am__fastdepCC_FALSE = @am__fastdepCC_FALSE@ am__fastdepCC_TRUE = @am__fastdepCC_TRUE@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ LKR_FILES = \ 10f200i.lkr \ 10f200.lkr \ 10f202i.lkr \ 10f202.lkr \ 10f204i.lkr \ 10f204.lkr \ 10f206i.lkr \ 10f206.lkr \ 10f220i.lkr \ 10f220.lkr \ 10f222i.lkr \ 10f222.lkr \ 12c508a.lkr \ 12c508.lkr \ 12c509a.lkr \ 12c509.lkr \ 12c671.lkr \ 12c672.lkr \ 12ce518.lkr \ 12ce519.lkr \ 12ce673.lkr \ 12ce674.lkr \ 12cr509a.lkr \ 12f508i.lkr \ 12f508.lkr \ 12f509i.lkr \ 12f509.lkr \ 12f510i.lkr \ 12f510.lkr \ 12f519.lkr \ 12f609i.lkr \ 12f609.lkr \ 12f615i.lkr \ 12f615.lkr \ 12f629i.lkr \ 12f629.lkr \ 12f635i.lkr \ 12f635.lkr \ 12f675i.lkr \ 12f675.lkr \ 12f683i.lkr \ 12f683.lkr \ 12hv609i.lkr \ 12hv609.lkr \ 12hv615i.lkr \ 12hv615.lkr \ 14000.lkr \ 16c432.lkr \ 16c433.lkr \ 16c505.lkr \ 16c52.lkr \ 16c54a.lkr \ 16c54b.lkr \ 16c54c.lkr \ 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\ 18f2321i.lkr \ 18f2321.lkr \ 18f2331i.lkr \ 18f2331.lkr \ 18f23k20.lkr \ 18f2410_e.lkr \ 18f2410i_e.lkr \ 18f2410i.lkr \ 18f2410.lkr \ 18f2420_e.lkr \ 18f2420i_e.lkr \ 18f2420i.lkr \ 18f2420.lkr \ 18f2423_e.lkr \ 18f2423i_e.lkr \ 18f2423i.lkr \ 18f2423.lkr \ 18f242i.lkr \ 18f242.lkr \ 18f2431i.lkr \ 18f2431.lkr \ 18f2439i.lkr \ 18f2439.lkr \ 18f2450_e.lkr \ 18f2450i_e.lkr \ 18f2450i.lkr \ 18f2450.lkr \ 18f2455_e.lkr \ 18f2455i_e.lkr \ 18f2455i.lkr \ 18f2455.lkr \ 18f2458_e.lkr \ 18f2458i_e.lkr \ 18f2458i.lkr \ 18f2458.lkr \ 18f2480_e.lkr \ 18f2480i_e.lkr \ 18f2480i.lkr \ 18f2480.lkr \ 18f248i.lkr \ 18f248.lkr \ 18f24j10_e.lkr \ 18f24j10i_e.lkr \ 18f24j10i.lkr \ 18f24j10.lkr \ 18f24j11.lkr \ 18f24j50.lkr \ 18f24k20_e.lkr \ 18f24k20_g.lkr \ 18f24k20i_e.lkr \ 18f24k20i.lkr \ 18f24k20.lkr \ 18f2510_e.lkr \ 18f2510i_e.lkr \ 18f2510i.lkr \ 18f2510.lkr \ 18f2515_e.lkr \ 18f2515i_e.lkr \ 18f2515i.lkr \ 18f2515.lkr \ 18f2520_e.lkr \ 18f2520i_e.lkr \ 18f2520i.lkr \ 18f2520.lkr \ 18f2523_e.lkr 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18f4682i_e.lkr \ 18f4682i.lkr \ 18f4682.lkr \ 18f4685_e.lkr \ 18f4685i_e.lkr \ 18f4685i.lkr \ 18f4685.lkr \ 18f46j11.lkr \ 18f46j50.lkr \ 18f46k20_e.lkr \ 18f46k20_g.lkr \ 18f46k20i_e.lkr \ 18f46k20i.lkr \ 18f46k20.lkr \ 18f6310_e.lkr \ 18f6310i_e.lkr \ 18f6310i.lkr \ 18f6310.lkr \ 18f6390_e.lkr \ 18f6390i_e.lkr \ 18f6390i.lkr \ 18f6390.lkr \ 18f6393_e.lkr \ 18f6393i_e.lkr \ 18f6393i.lkr \ 18f6393.lkr \ 18f63j11_e.lkr \ 18f63j11i_e.lkr \ 18f63j11i.lkr \ 18f63j11.lkr \ 18f63j90_e.lkr \ 18f63j90i_e.lkr \ 18f63j90i.lkr \ 18f63j90.lkr \ 18f6410_e.lkr \ 18f6410i_e.lkr \ 18f6410i.lkr \ 18f6410.lkr \ 18f6490_e.lkr \ 18f6490i_e.lkr \ 18f6490i.lkr \ 18f6490.lkr \ 18f6493_e.lkr \ 18f6493i_e.lkr \ 18f6493i.lkr \ 18f6493.lkr \ 18f64j11_e.lkr \ 18f64j11i_e.lkr \ 18f64j11i.lkr \ 18f64j11.lkr \ 18f64j90_e.lkr \ 18f64j90i_e.lkr \ 18f64j90i.lkr \ 18f64j90.lkr \ 18f6520i.lkr \ 18f6520.lkr \ 18f6525i.lkr \ 18f6525.lkr \ 18f6527_e.lkr \ 18f6527i_e.lkr \ 18f6527i.lkr \ 18f6527.lkr \ 18f6585i.lkr \ 18f6585.lkr \ 18f65j10_e.lkr \ 18f65j10i_e.lkr \ 18f65j10i.lkr \ 18f65j10.lkr \ 18f65j11_e.lkr \ 18f65j11i_e.lkr \ 18f65j11i.lkr \ 18f65j11.lkr \ 18f65j15_e.lkr \ 18f65j15i_e.lkr \ 18f65j15i.lkr \ 18f65j15.lkr \ 18f65j50_e.lkr \ 18f65j50i_e.lkr \ 18f65j50i.lkr \ 18f65j50.lkr \ 18f65j90_e.lkr \ 18f65j90i_e.lkr \ 18f65j90i.lkr \ 18f65j90.lkr \ 18f6620i.lkr \ 18f6620.lkr \ 18f6621i.lkr \ 18f6621.lkr \ 18f6622_e.lkr \ 18f6622i_e.lkr \ 18f6622i.lkr \ 18f6622.lkr \ 18f6627_e.lkr \ 18f6627i_e.lkr \ 18f6627i.lkr \ 18f6627.lkr \ 18f6628_e.lkr \ 18f6628i_e.lkr \ 18f6628i.lkr \ 18f6628.lkr \ 18f6680i.lkr \ 18f6680.lkr \ 18f66j10_e.lkr \ 18f66j10i_e.lkr \ 18f66j10i.lkr \ 18f66j10.lkr \ 18f66j11_e.lkr \ 18f66j11i_e.lkr \ 18f66j11i.lkr \ 18f66j11.lkr \ 18f66j15_e.lkr \ 18f66j15i_e.lkr \ 18f66j15i.lkr \ 18f66j15.lkr \ 18f66j16_e.lkr \ 18f66j16i_e.lkr \ 18f66j16i.lkr \ 18f66j16.lkr \ 18f66j50_e.lkr \ 18f66j50i_e.lkr \ 18f66j50i.lkr \ 18f66j50.lkr \ 18f66j55_e.lkr \ 18f66j55i_e.lkr \ 18f66j55i.lkr \ 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18f86j10_e.lkr \ 18f86j10i_e.lkr \ 18f86j10i.lkr \ 18f86j10.lkr \ 18f86j11_e.lkr \ 18f86j11i_e.lkr \ 18f86j11i.lkr \ 18f86j11.lkr \ 18f86j15_e.lkr \ 18f86j15i_e.lkr \ 18f86j15i.lkr \ 18f86j15.lkr \ 18f86j16_e.lkr \ 18f86j16i_e.lkr \ 18f86j16i.lkr \ 18f86j16.lkr \ 18f86j50_e.lkr \ 18f86j50i_e.lkr \ 18f86j50i.lkr \ 18f86j50.lkr \ 18f86j55_e.lkr \ 18f86j55i_e.lkr \ 18f86j55i.lkr \ 18f86j55.lkr \ 18f86j60_e.lkr \ 18f86j60i_e.lkr \ 18f86j60i.lkr \ 18f86j60.lkr \ 18f86j65_e.lkr \ 18f86j65i_e.lkr \ 18f86j65i.lkr \ 18f86j65.lkr \ 18f86j90.lkr \ 18f8720i.lkr \ 18f8720.lkr \ 18f8722_e.lkr \ 18f8722i_e.lkr \ 18f8722i.lkr \ 18f8722.lkr \ 18f8723_e.lkr \ 18f8723i_e.lkr \ 18f8723i.lkr \ 18f8723.lkr \ 18f87j10_e.lkr \ 18f87j10i_e.lkr \ 18f87j10i.lkr \ 18f87j10.lkr \ 18f87j11_e.lkr \ 18f87j11i_e.lkr \ 18f87j11i.lkr \ 18f87j11.lkr \ 18f87j50_e.lkr \ 18f87j50i_e.lkr \ 18f87j50i.lkr \ 18f87j50.lkr \ 18f87j60_e.lkr \ 18f87j60i_e.lkr \ 18f87j60i.lkr \ 18f87j60.lkr \ 18f87j90.lkr \ 18f96j60_e.lkr \ 18f96j60i_e.lkr \ 18f96j60i.lkr \ 18f96j60.lkr \ 18f96j65_e.lkr \ 18f96j65i_e.lkr \ 18f96j65i.lkr \ 18f96j65.lkr \ 18f97j60_e.lkr \ 18f97j60i_e.lkr \ 18f97j60i.lkr \ 18f97j60.lkr \ 18lf13k22_e.lkr \ 18lf13k22i_e.lkr \ 18lf13k22i.lkr \ 18lf13k22.lkr \ 18lf13k50_e.lkr \ 18lf13k50i_e.lkr \ 18lf13k50i.lkr \ 18lf13k50.lkr \ 18lf14k22_e.lkr \ 18lf14k22i_e.lkr \ 18lf14k22i.lkr \ 18lf14k22.lkr \ 18lf14k50_e.lkr \ 18lf14k50i_e.lkr \ 18lf14k50i.lkr \ 18lf14k50.lkr \ 18lf24j11.lkr \ 18lf24j50.lkr \ 18lf25j11.lkr \ 18lf25j50.lkr \ 18lf26j11.lkr \ 18lf26j50.lkr \ 18lf44j11.lkr \ 18lf44j50.lkr \ 18lf45j11.lkr \ 18lf45j50.lkr \ 18lf46j11.lkr \ 18lf46j50.lkr \ hcs1365.lkr \ hcs1370.lkr \ mcv08a.lkr \ mcv14a.lkr \ mcv18a.lkr \ mcv28a.lkr \ ps500.lkr \ ps810.lkr \ rf509af.lkr \ rf509ag.lkr \ rf675fi.lkr \ rf675f.lkr \ rf675hi.lkr \ rf675h.lkr \ rf675ki.lkr \ rf675k.lkr pkgdata_DATA = $(LKR_FILES) EXTRA_DIST = $(LKR_FILES) Makefile.sh all: all-am .SUFFIXES: $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \ && exit 0; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu lkr/Makefile'; \ cd $(top_srcdir) && \ $(AUTOMAKE) --gnu lkr/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh uninstall-info-am: install-pkgdataDATA: $(pkgdata_DATA) @$(NORMAL_INSTALL) test -z "$(pkgdatadir)" || $(mkdir_p) "$(DESTDIR)$(pkgdatadir)" @list='$(pkgdata_DATA)'; for p in $$list; do \ if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ f=$(am__strip_dir) \ echo " $(pkgdataDATA_INSTALL) '$$d$$p' '$(DESTDIR)$(pkgdatadir)/$$f'"; \ $(pkgdataDATA_INSTALL) "$$d$$p" "$(DESTDIR)$(pkgdatadir)/$$f"; \ done uninstall-pkgdataDATA: @$(NORMAL_UNINSTALL) @list='$(pkgdata_DATA)'; for p in $$list; do \ f=$(am__strip_dir) \ echo " rm -f '$(DESTDIR)$(pkgdatadir)/$$f'"; \ rm -f "$(DESTDIR)$(pkgdatadir)/$$f"; \ done tags: TAGS TAGS: ctags: CTAGS CTAGS: distdir: $(DISTFILES) @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \ list='$(DISTFILES)'; for file in $$list; do \ case $$file in \ $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \ $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \ esac; \ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ if test "$$dir" != "$$file" && test "$$dir" != "."; then \ dir="/$$dir"; \ $(mkdir_p) "$(distdir)$$dir"; \ else \ dir=''; \ fi; \ if test -d $$d/$$file; then \ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ fi; \ cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ else \ test -f $(distdir)/$$file \ || cp -p $$d/$$file $(distdir)/$$file \ || exit 1; \ fi; \ done check-am: all-am check: check-am all-am: Makefile $(DATA) installdirs: for dir in "$(DESTDIR)$(pkgdatadir)"; do \ test -z "$$dir" || $(mkdir_p) "$$dir"; \ done install: install-am install-exec: install-exec-am install-data: install-data-am uninstall: uninstall-am install-am: all-am @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am installcheck: installcheck-am install-strip: $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ `test -z '$(STRIP)' || \ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install mostlyclean-generic: clean-generic: distclean-generic: -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) maintainer-clean-generic: @echo "This command is intended for maintainers to use" @echo "it deletes files that may require special tools to rebuild." clean: clean-am clean-am: clean-generic mostlyclean-am distclean: distclean-am -rm -f Makefile distclean-am: clean-am distclean-generic dvi: dvi-am dvi-am: html: html-am info: info-am info-am: install-data-am: install-pkgdataDATA install-exec-am: install-info: install-info-am install-man: installcheck-am: maintainer-clean: maintainer-clean-am -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-am mostlyclean-am: mostlyclean-generic pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: uninstall-info-am uninstall-pkgdataDATA .PHONY: all all-am check check-am clean clean-generic distclean \ distclean-generic distdir dvi dvi-am html html-am info info-am \ install install-am install-data install-data-am install-exec \ install-exec-am install-info install-info-am install-man \ install-pkgdataDATA install-strip installcheck installcheck-am \ installdirs maintainer-clean maintainer-clean-generic \ mostlyclean mostlyclean-generic pdf pdf-am ps ps-am uninstall \ uninstall-am uninstall-info-am uninstall-pkgdataDATA # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: gputils-0.13.7/lkr/18f6490i_e.lkr0000644000175000017500000000203411156521271013112 00000000000000// File: 18f6490i_e.lkr // Sample ICD2 linker script for the PIC18F6490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6627.lkr0000644000175000017500000000315511156521271012444 00000000000000// File: 18f6627.lkr // Sample linker script for the PIC18F6627 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/10f206.lkr0000644000175000017500000000070611156313115012332 00000000000000// Sample linker command file for 10F206 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x200 END=0x203 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x07 PROTECTED DATABANK NAME=gprs START=0x08 END=0x1F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8722_e.lkr0000644000175000017500000000315711156521271012750 00000000000000// File: 18f8722_e.lkr // Sample linker script for the PIC18F8722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f45k20i.lkr0000644000175000017500000000231511156521271012753 00000000000000// File: 18f45k20i.lkr // Sample ICD2 linker script for the PIC18F45K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8525i.lkr0000644000175000017500000000332511156521271012613 00000000000000// File: 18f8525i.lkr // Sample ICD2 linker script for the PIC18F8525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2580i.lkr0000644000175000017500000000266211156521271012611 00000000000000// File: 18f2580i.lkr // Sample ICD2 linker script for the PIC18F2580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8490_e.lkr0000644000175000017500000000157111156521271012750 00000000000000// File: 18f8490_e.lkr // Sample linker script for the PIC18F8490 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j15i.lkr0000644000175000017500000000212111156521271012753 00000000000000// File: 18f65j15i.lkr // Sample ICD2 linker script for the PIC18F65J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/12f509.lkr0000644000175000017500000000141411156521271012343 00000000000000// Sample linker command file for 12F509 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x06 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x26 PROTECTED SHAREBANK NAME=gprnobnk START=0x07 END=0x0F SHAREBANK NAME=gprnobnk START=0x27 END=0x2F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f248.lkr0000644000175000017500000000170511156521271012354 00000000000000// File: 18f248.lkr // Sample linker script for the PIC18F248 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=bankedsfr START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f96j60i_e.lkr0000644000175000017500000000316011156521271013267 00000000000000// File: 18f96j60i_e.lkr // Sample ICD2 linker script for the PIC18F96J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6722i.lkr0000644000175000017500000000342011156521271012604 00000000000000// File: 18f6722i.lkr // Sample ICD2 linker script for the PIC18F6722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FD7F CODEPAGE NAME=debug START=0x1FD80 END=0x1FFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j11_e.lkr0000644000175000017500000000200011156521271013100 00000000000000// File: 18f85j11_e.lkr // Sample linker script for the PIC18F85J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f46k20i.lkr0000644000175000017500000000342111156521271012753 00000000000000// File: 18f46k20i.lkr // Sample ICD2 linker script for the PIC18F46K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f690i.lkr0000644000175000017500000000332411156521271012523 00000000000000// Sample ICD2 linker command file for 16F690 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x164 DATABANK NAME=dbgspr START=0x165 END=0x16F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2539.lkr0000644000175000017500000000205011156521271012433 00000000000000// File: 18f2539.lkr // Sample linker script for the PIC18F2539 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x57F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2553i_e.lkr0000644000175000017500000000252411156521271013112 00000000000000// File: 18f2553i_e.lkr // Sample ICD2 linker script for the PIC18F2553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f14k50i.lkr0000644000175000017500000000171711156521271012757 00000000000000// File: 18f14k50i.lkr // Sample ICD2 linker script for the PIC18F14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4480i.lkr0000644000175000017500000000240411156521271012604 00000000000000// File: 18f4480i.lkr // Sample ICD2 linker script for the PIC18F4480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25k20i_e.lkr0000644000175000017500000000231711156521271013257 00000000000000// File: 18f25k20i_e.lkr // Sample ICD2 linker script for the PIC18F25K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16lf727i.lkr0000644000175000017500000000346611156521271012707 00000000000000// Sample ICD2 linker command file for 16LF727 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1E4 DATABANK NAME=gpr3dbg START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8723.lkr0000644000175000017500000000315511156521271012443 00000000000000// File: 18f8723.lkr // Sample linker script for the PIC18F8723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c73.lkr0000644000175000017500000000126711156521271012266 00000000000000// Sample linker command file for 16C73 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f65j90i_e.lkr0000644000175000017500000000212311156521271013264 00000000000000// File: 18f65j90i_e.lkr // Sample ICD2 linker script for the PIC18F65J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4410.lkr0000644000175000017500000000145211156521271012426 00000000000000// File: 18f4410.lkr // Sample linker script for the PIC18F4410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f64j90i.lkr0000644000175000017500000000155111156521271012763 00000000000000// File: 18f64j90i.lkr // Sample ICD2 linker script for the PIC18F64J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f46k20.lkr0000644000175000017500000000315611156521271012607 00000000000000// File: 18f46k20.lkr // Sample linker script for the PIC18F46K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f76.lkr0000644000175000017500000000256211156521271012273 00000000000000// Sample linker command file for 16F76 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f86j60.lkr0000644000175000017500000000303311156521271012610 00000000000000// File: 18f86j60.lkr // Sample linker script for the PIC18F86J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2550_e.lkr0000644000175000017500000000226111156521271012734 00000000000000// File: 18f2550_e.lkr // Sample linker script for the PIC18F2550 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2450_e.lkr0000644000175000017500000000140611156521271012733 00000000000000// File: 18f2450_e.lkr // Sample linker script for the PIC18F2450 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8723_e.lkr0000644000175000017500000000315711156521271012751 00000000000000// File: 18f8723_e.lkr // Sample linker script for the PIC18F8723 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f14k22i_e.lkr0000644000175000017500000000162711156521271013262 00000000000000// File: 18f14k22i_e.lkr // Sample ICD2 linker script for the PIC18F14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4321.lkr0000644000175000017500000000150011156521271012421 00000000000000// File: 18f4321.lkr // Sample linker script for the PIC18F4321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4553i.lkr0000644000175000017500000000261311156521271012607 00000000000000// File: 18f4553i.lkr // Sample ICD2 linker script for the PIC18F4553 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j90i.lkr0000644000175000017500000000212111156521271012760 00000000000000// File: 18f85j90i.lkr // Sample ICD2 linker script for the PIC18F85J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f777i.lkr0000644000175000017500000000412511156521271012531 00000000000000// Sample ICD2 linker command file for 16F777 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1EFF CODEPAGE NAME=debug START=0x1F00 END=0x1FFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x164 DATABANK NAME=dbgspr2 START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=dbgspr START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprs START=0x71 END=0x7F SHAREBANK NAME=gprs START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=PROG2 ROM=page2 // ROM code space SECTION NAME=PROG3 ROM=page3 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/18f67j60i.lkr0000644000175000017500000000315711156521271012767 00000000000000// File: 18f67j60i.lkr // Sample ICD2 linker script for the PIC18F67J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2515i.lkr0000644000175000017500000000327711156521271012612 00000000000000// File: 18f2515i.lkr // Sample ICD2 linker script for the PIC18F2515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2610i_e.lkr0000644000175000017500000000337211156521271013106 00000000000000// File: 18f2610i_e.lkr // Sample ICD2 linker script for the PIC18F2610 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2682.lkr0000644000175000017500000000324611156521271012442 00000000000000// File: 18f2682.lkr // Sample linker script for the PIC18F2682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2420.lkr0000644000175000017500000000157211156521271012430 00000000000000// File: 18f2420.lkr // Sample linker script for the PIC18F2420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f819i.lkr0000644000175000017500000000353611156521271012533 00000000000000// Sample ICD2 linker command file for the PIC16F819 LIBPATH . CODEPAGE NAME=page START=0x0000 END=0x06FF CODEPAGE NAME=debug START=0x0700 END=0x07FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0xA0 END=0xE4 DATABANK NAME=dbgspr START=0xE5 END=0xEF PROTECTED DATABANK NAME=gpr1 START=0x120 END=0x164 DATABANK NAME=dbgspr2 START=0x165 END=0x16F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x20 END=0x64 SHAREBANK NAME=dbgspr0 START=0x65 END=0x6F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1A0 END=0x1E4 PROTECTED SHAREBANK NAME=dbgspr0 START=0x1E5 END=0x1EF PROTECTED SHAREBANK NAME=dbgspr1 START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnk1 START=0x71 END=0x7F SHAREBANK NAME=dbgspr1 START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk1 START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=dbgspr1 START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnk1 START=0x171 END=0x17F PROTECTED SHAREBANK NAME=dbgspr1 START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f64j11.lkr0000644000175000017500000000142611156521271012604 00000000000000// File: 18f64j11.lkr // Sample linker script for the PIC18F64J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6527_e.lkr0000644000175000017500000000315611156521271012750 00000000000000// File: 18f6527_e.lkr // Sample linker script for the PIC18F6527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4539i.lkr0000644000175000017500000000217611156521271012617 00000000000000// File: 18f4539i.lkr // Sample ICD2 linker script for the PIC18F4539 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5DBF CODEPAGE NAME=debug START=0x5DC0 END=0x5FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x57F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f26k20i.lkr0000644000175000017500000000342111156521271012751 00000000000000// File: 18f26k20i.lkr // Sample ICD2 linker script for the PIC18F26K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j65i_e.lkr0000644000175000017500000000316111156521271013274 00000000000000// File: 18f86j65i_e.lkr // Sample ICD2 linker script for the PIC18F86J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr57b.lkr0000644000175000017500000000255711156521271012617 00000000000000// Sample linker command file for 16CR57B LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=page2 START=0x400 END=0x5FF CODEPAGE NAME=page3 START=0x600 END=0x7FF CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x800 END=0x803 PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x7 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x27 PROTECTED SHAREBANK NAME=sfrs START=0x40 END=0x47 PROTECTED SHAREBANK NAME=sfrs START=0x60 END=0x67 PROTECTED SHAREBANK NAME=gprnobnk START=0x8 END=0xF SHAREBANK NAME=gprnobnk START=0x29 END=0x2F PROTECTED SHAREBANK NAME=gprnobnk START=0x48 END=0x4F PROTECTED SHAREBANK NAME=gprnobnk START=0x68 END=0x6F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F DATABANK NAME=gpr2 START=0x50 END=0x5F DATABANK NAME=gpr3 START=0x70 END=0x7F SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2520.lkr0000644000175000017500000000205011156521271012421 00000000000000// File: 18f2520.lkr // Sample linker script for the PIC18F2520 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c84.lkr0000644000175000017500000000120011156521271012253 00000000000000// Sample linker command file for 16C84 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x2F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f24k20_g.lkr0000644000175000017500000000335611156521271013113 00000000000000// File: 18f24k20_g.lkr // Generic linker script for the PIC18F24K20 processor #DEFINE _CODEEND _DEBUGCODESTART - 1 #DEFINE _CEND _CODEEND + _DEBUGCODELEN #DEFINE _DATAEND _DEBUGDATASTART - 1 #DEFINE _DEND _DATAEND + _DEBUGDATALEN LIBPATH . #IFDEF _CRUNTIME #IFDEF _EXTENDEDMODE FILES c018i_e.o FILES clib_e.lib FILES p18f24k20_e.lib #ELSE FILES c018i.o FILES clib.lib FILES p18f24k20.lib #FI #FI #IFDEF _DEBUGCODESTART CODEPAGE NAME=page START=0x0 END=_CODEEND CODEPAGE NAME=debug START=_DEBUGCODESTART END=_CEND PROTECTED #ELSE CODEPAGE NAME=page START=0x0 END=0x3FFF #FI CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED #IFDEF _EXTENDEDMODE DATABANK NAME=gpre START=0x0 END=0x5F #ELSE ACCESSBANK NAME=accessram START=0x0 END=0x5F #FI DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF #IFDEF _DEBUGDATASTART DATABANK NAME=gpr2 START=0x200 END=_DATAEND DATABANK NAME=dbgspr START=_DEBUGDATASTART END=_DEND PROTECTED #ELSE //no debug DATABANK NAME=gpr2 START=0x200 END=0x2FF #FI ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED #IFDEF _CRUNTIME SECTION NAME=CONFIG ROM=config #IFDEF _DEBUGDATASTART STACK SIZE=0x100 RAM=gpr1 #ELSE STACK SIZE=0x100 RAM=gpr2 #FI #FI gputils-0.13.7/lkr/18f2510.lkr0000644000175000017500000000173011156521271012424 00000000000000// File: 18f2510.lkr // Sample linker script for the PIC18F2510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24j10i_e.lkr0000644000175000017500000000164411156521271013256 00000000000000// File: 18f24j10i_e.lkr // Sample ICD2 linker script for the PIC18F24J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25k20.lkr0000644000175000017500000000205211156521271012576 00000000000000// File: 18f25k20.lkr // Sample linker script for the PIC18F25K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/rf675fi.lkr0000644000175000017500000000237211156313115012705 00000000000000// Sample ICD2 linker command file for rfPIC12F675F LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x53 SHAREBANK NAME=dbgspr START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xD3 SHAREBANK NAME=dbgspr START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/16f785.lkr0000644000175000017500000000221711156521271012357 00000000000000// Sample linker command file for 16F785 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gpr2 START=0x70 END=0x7F SHAREBANK NAME=gpr2 START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gpr2 START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gpr2 START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2682_e.lkr0000644000175000017500000000315711156521271012747 00000000000000// File: 18f2682_e.lkr // Sample linker script for the PIC18F2682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f716.lkr0000644000175000017500000000125511156521271012352 00000000000000// Sample linker command file for 16f716 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f4682_e.lkr0000644000175000017500000000315711156521271012751 00000000000000// File: 18f4682_e.lkr // Sample linker script for the PIC18F4682 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x13FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2620i_e.lkr0000644000175000017500000000351211156521271013103 00000000000000// File: 18f2620i_e.lkr // Sample ICD2 linker script for the PIC18F2620 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6410.lkr0000644000175000017500000000156711156521271012437 00000000000000// File: 18f6410.lkr // Sample linker script for the PIC18F6410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f84j11_e.lkr0000644000175000017500000000143011156521271013105 00000000000000// File: 18f84j11_e.lkr // Sample linker script for the PIC18F84J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f677i.lkr0000644000175000017500000000306311156521271012530 00000000000000// Sample ICD2 linker command file for 16F677 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.calib START=0x2008 END=0x2008 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=gpr1 START=0xA0 END=0xBF DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=CALIBR ROM=.calib // Calibration bits location SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f44j10i_e.lkr0000644000175000017500000000164411156521271013260 00000000000000// File: 18f44j10i_e.lkr // Sample ICD2 linker script for the PIC18F44J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f616i.lkr0000644000175000017500000000166311156521271012525 00000000000000// Sample ICD2 linker command file for 16F616 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xB4 DATABANK NAME=dbgspr START=0xB5 END=0xBF PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f13k22i_e.lkr0000644000175000017500000000153511156521271013257 00000000000000// File: 18f13k22i_e.lkr // Sample ICD2 linker script for the PIC18F13K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16hv616i.lkr0000644000175000017500000000166311156521271012715 00000000000000// Sample ICD2 linker command file for 16F616 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xB4 DATABANK NAME=dbgspr START=0xB5 END=0xBF PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2420i_e.lkr0000644000175000017500000000213011156521271013074 00000000000000// File: 18f2420i_e.lkr // Sample ICD2 linker script for the PIC18F2420 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f767.lkr0000644000175000017500000000331111156521271012353 00000000000000// Sample linker command file for 16F767 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprs START=0x70 END=0x7F SHAREBANK NAME=gprs START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=PROG2 ROM=page2 // ROM code space SECTION NAME=PROG3 ROM=page3 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/18f87j11i.lkr0000644000175000017500000000315711156521271012765 00000000000000// File: 18f87j11i.lkr // Sample ICD2 linker script for the PIC18F87J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f442.lkr0000644000175000017500000000157011156521271012350 00000000000000// File: 18f442.lkr // Sample linker script for the PIC18F442 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8390.lkr0000644000175000017500000000156711156521271012450 00000000000000// File: 18f8390.lkr // Sample linker script for the PIC18F8390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2523i.lkr0000644000175000017500000000231311156521271012577 00000000000000// File: 18f2523i.lkr // Sample ICD2 linker script for the PIC18F2523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7DBF CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5F3 DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6621.lkr0000644000175000017500000000306211156521271012433 00000000000000// File: 18f6621.lkr // Sample linker script for the PIC18F6621 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j50_e.lkr0000644000175000017500000000303511156521271013112 00000000000000// File: 18f65j50_e.lkr // Sample linker script for the PIC18F65J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j50i_e.lkr0000644000175000017500000000316111156521271013265 00000000000000// File: 18f67j50i_e.lkr // Sample ICD2 linker script for the PIC18F67J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f639i.lkr0000644000175000017500000000317311156521271012530 00000000000000// Sample ICD2 linker command file for 16F639 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x6FF CODEPAGE NAME=debug START=0x700 END=0x7FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x0 END=0x0B PROTECTED SHAREBANK NAME=sfrnobnk0 START=0x100 END=0x10B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x80 END=0x8B PROTECTED SHAREBANK NAME=sfrnobnk1 START=0x180 END=0x18B PROTECTED DATABANK NAME=sfr0 START=0x0C END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x8C END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x10C END=0x11F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x64 DATABANK NAME=gpr1 START=0xA0 END=0xBF DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgnobnk START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgnobnk START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f96j65i_e.lkr0000644000175000017500000000316111156521271013275 00000000000000// File: 18f96j65i_e.lkr // Sample ICD2 linker script for the PIC18F96J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2685_e.lkr0000644000175000017500000000315711156521271012752 00000000000000// File: 18f2685_e.lkr // Sample linker script for the PIC18F2685 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j50i_e.lkr0000644000175000017500000000316111156521271013267 00000000000000// File: 18f87j50i_e.lkr // Sample ICD2 linker script for the PIC18F87J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4480.lkr0000644000175000017500000000214111156521271012431 00000000000000// File: 18f4480.lkr // Sample linker script for the PIC18F4480 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f83j90.lkr0000644000175000017500000000142611156521271012614 00000000000000// File: 18f83j90.lkr // Sample linker script for the PIC18F83J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF7 CODEPAGE NAME=config START=0x1FF8 END=0x1FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6622_e.lkr0000644000175000017500000000315611156521271012744 00000000000000// File: 18f6622_e.lkr // Sample linker script for the PIC18F6622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr65.lkr0000644000175000017500000000127011156521271012443 00000000000000// Sample linker command file for 16CR65 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xFF SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f8722.lkr0000644000175000017500000000315511156521271012442 00000000000000// File: 18f8722.lkr // Sample linker script for the PIC18F8722 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f64j11i_e.lkr0000644000175000017500000000155311156521271013262 00000000000000// File: 18f64j11i_e.lkr // Sample ICD2 linker script for the PIC18F64J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3F3 DATABANK NAME=dbgspr START=0x3F4 END=0x3FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c752.lkr0000644000175000017500000000454111156521271012351 00000000000000// Sample linker command file for 17C752 // $Id: 17c752.lkr,v 1.4 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED SHAREBANK NAME=sfrnobnk START=0x400 END=0x40F PROTECTED SHAREBANK NAME=sfrnobnk START=0x500 END=0x50F PROTECTED SHAREBANK NAME=sfrnobnk START=0x600 END=0x60F PROTECTED SHAREBANK NAME=sfrnobnk START=0x700 END=0x70F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED DATABANK NAME=sfr4 START=0x410 END=0x417 PROTECTED DATABANK NAME=sfr5 START=0x510 END=0x517 PROTECTED DATABANK NAME=sfr6 START=0x610 END=0x617 PROTECTED DATABANK NAME=sfr7 START=0x710 END=0x717 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=sfrprod START=0x418 END=0x419 PROTECTED SHAREBANK NAME=sfrprod START=0x518 END=0x519 PROTECTED SHAREBANK NAME=sfrprod START=0x618 END=0x619 PROTECTED SHAREBANK NAME=sfrprod START=0x718 END=0x719 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F SHAREBANK NAME=registers START=0x41A END=0x41F SHAREBANK NAME=registers START=0x51A END=0x51F SHAREBANK NAME=registers START=0x61A END=0x61F SHAREBANK NAME=registers START=0x71A END=0x71F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF DATABANK NAME=gpr2 START=0x220 END=0x2FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/16c66.lkr0000644000175000017500000000256211156521271012267 00000000000000// Sample linker command file for 16C66 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f67j11_e.lkr0000644000175000017500000000303611156521271013112 00000000000000// File: 18f67j11_e.lkr // Sample linker script for the PIC18F67J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/rf675hi.lkr0000644000175000017500000000237111156313115012706 00000000000000// Sample ICD2 linker command file for rfPIC12F675H LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FE PROTECTED CODEPAGE NAME=.oscval START=0x3FF END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.icdinst START=0x2004 END=0x2004 PROTECTED CODEPAGE NAME=.mfgcode START=0x2005 END=0x2005 PROTECTED CODEPAGE NAME=.devid START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=.reserve START=0x2008 END=0x200F PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0nobnk START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1nobnk START=0x80 END=0x9F PROTECTED SHAREBANK NAME=gpr0nobnk START=0x20 END=0x53 SHAREBANK NAME=dbgspr START=0x54 END=0x5F PROTECTED SHAREBANK NAME=gpr0nobnk START=0xA0 END=0xD3 SHAREBANK NAME=dbgspr START=0xD4 END=0xDF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=OSCVAL ROM=.oscval // Oscillator Cal Value SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f66j55i.lkr0000644000175000017500000000315711156521271012772 00000000000000// File: 18f66j55i.lkr // Sample ICD2 linker script for the PIC18F66J55 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c926.lkr0000644000175000017500000000256311156521271012355 00000000000000// Sample linker command file for 16C926 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x16F DATABANK NAME=gpr3 START=0x1A0 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f6680i.lkr0000644000175000017500000000351011156521271012607 00000000000000// File: 18f6680i.lkr // Sample ICD2 linker script for the PIC18F6680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2221i_e.lkr0000644000175000017500000000203511156521271013077 00000000000000// File: 18f2221i_e.lkr // Sample ICD2 linker script for the PIC18F2221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xDBF CODEPAGE NAME=debug START=0xDC0 END=0xFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/12c509.lkr0000644000175000017500000000076511156521271012350 00000000000000// Sample linker command file for 12C509 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED DATABANK NAME=sfrs START=0x0 END=0x06 PROTECTED DATABANK NAME=gpr0 START=0x07 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f737i.lkr0000644000175000017500000000355311156521271012531 00000000000000// Sample ICD2 linker command file for 16F737 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.test_vect START=0x2004 END=0x2005 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=.test START=0x200A END=0x203F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x164 DATABANK NAME=dbgspr2 START=0x165 END=0x16F PROTECTED DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=dbgspr START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgspr START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=dbgspr START=0x170 END=0x170 PROTECTED SHAREBANK NAME=dbgspr START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprs START=0x71 END=0x7F SHAREBANK NAME=gprs START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprs START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprs START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=TEST_VECT ROM=.test_vect // Test vector SECTION NAME=DEVICEID ROM=.device_id // Device ID SECTION NAME=TEST ROM=.test // Test gputils-0.13.7/lkr/16f724i.lkr0000644000175000017500000000303111156521271012514 00000000000000// Sample ICD2 linker command file for 16F724 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xEFF CODEPAGE NAME=debug START=0xF00 END=0xFFF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2008 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x120 END=0x124 DATABANK NAME=gpr2dbg START=0x125 END=0x12F PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x70 END=0x70 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x170 END=0x170 PROTECTED SHAREBANK NAME=gprnobnkdbg START=0x1F0 END=0x1F0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x171 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F1 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=DEBUG ROM=debug // debug exec SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/16f818.lkr0000644000175000017500000000250011156521271012347 00000000000000// Sample linker command file for 16F818.lkr LIBPATH . CODEPAGE NAME=page START=0x0000 END=0x03FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.device_id START=0x2006 END=0x2006 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2009 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x217F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x11F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x19F PROTECTED DATABANK NAME=gpr0 START=0xA0 END=0xBF SHAREBANK NAME=gprnobnk0 START=0x20 END=0x3F SHAREBANK NAME=gprnobnk0 START=0x120 END=0x13F PROTECTED SHAREBANK NAME=gprnobnk0 START=0x1A0 END=0x1BF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x40 END=0x7F SHAREBANK NAME=gprnobnk1 START=0xC0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk1 START=0x140 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk1 START=0x1C0 END=0x1FF PROTECTED SECTION NAME=PROG ROM=page // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEVICEID ROM=.device_id // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f4680i.lkr0000644000175000017500000000351011156521271012605 00000000000000// File: 18f4680i.lkr // Sample ICD2 linker script for the PIC18F4680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f85j15i.lkr0000644000175000017500000000212111156521271012755 00000000000000// File: 18f85j15i.lkr // Sample ICD2 linker script for the PIC18F85J15 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFF7 CODEPAGE NAME=config START=0xBFF8 END=0xBFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7F3 DATABANK NAME=dbgspr START=0x7F4 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f610i.lkr0000644000175000017500000000161411156521271012513 00000000000000// Sample ICD2 linker command file for 16F610 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x2FF CODEPAGE NAME=debug START=0x300 END=0x3FF PROTECTED CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x00 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x40 END=0x64 DATABANK NAME=dbgspr START=0x65 END=0x6F PROTECTED SHAREBANK NAME=dbgnobnk START=0x70 END=0x70 PROTECTED SHAREBANK NAME=dbgnobnk START=0xF0 END=0xF0 PROTECTED SHAREBANK NAME=gprnobnk START=0x71 END=0x7F SHAREBANK NAME=gprnobnk START=0xF1 END=0xFF PROTECTED SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f2680i.lkr0000644000175000017500000000351011156521271012603 00000000000000// File: 18f2680i.lkr // Sample ICD2 linker script for the PIC18F2680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f877.lkr0000644000175000017500000000275011156521271012363 00000000000000// Sample linker command file for 16F877 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=page1 START=0x800 END=0xFFF CODEPAGE NAME=page2 START=0x1000 END=0x17FF CODEPAGE NAME=page3 START=0x1800 END=0x1FFF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x21FF PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x6F DATABANK NAME=gpr1 START=0xA0 END=0xEF DATABANK NAME=gpr2 START=0x110 END=0x16F DATABANK NAME=gpr3 START=0x190 END=0x1EF SHAREBANK NAME=gprnobnk START=0x70 END=0x7F SHAREBANK NAME=gprnobnk START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=gprnobnk START=0x170 END=0x17F PROTECTED SHAREBANK NAME=gprnobnk START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=PROG2 ROM=page1 // ROM code space - page1 SECTION NAME=PROG3 ROM=page2 // ROM code space - page2 SECTION NAME=PROG4 ROM=page3 // ROM code space - page3 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f2523.lkr0000644000175000017500000000205011156521271012424 00000000000000// File: 18f2523.lkr // Sample linker script for the PIC18F2523 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8390i_e.lkr0000644000175000017500000000203411156521271013113 00000000000000// File: 18f8390i_e.lkr // Sample ICD2 linker script for the PIC18F8390 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j50i.lkr0000644000175000017500000000315711156521271012766 00000000000000// File: 18f67j50i.lkr // Sample ICD2 linker script for the PIC18F67J50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF3F DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4510_e.lkr0000644000175000017500000000202311156521271012726 00000000000000// File: 18f4510_e.lkr // Sample linker script for the PIC18F4510 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4221_e.lkr0000644000175000017500000000157211156521271012735 00000000000000// File: 18f4221_e.lkr // Sample linker script for the PIC18F4221 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2515_e.lkr0000644000175000017500000000312711156521271012737 00000000000000// File: 18f2515_e.lkr // Sample linker script for the PIC18F2515 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4525i_e.lkr0000644000175000017500000000351211156521271013111 00000000000000// File: 18f4525i_e.lkr // Sample ICD2 linker script for the PIC18F4525 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF7F ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf24j11.lkr0000644000175000017500000000300111156521271012743 00000000000000// File: 18lf24j11_g.lkr // Generic linker script for the PIC18LF24J11 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FF7 CODEPAGE NAME=config START=0x3FF8 END=0x3FFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f46j50.lkr0000644000175000017500000000277711156521271012621 00000000000000// File: 18f46j50_g.lkr // Generic linker script for the PIC18F46J50 processor LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFF PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEBF DATABANK NAME=sfr14 START=0xEC0 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4321_e.lkr0000644000175000017500000000157311156521271012737 00000000000000// File: 18f4321_e.lkr // Sample linker script for the PIC18F4321 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F ACCESSBANK NAME=accessram START=0x60 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j11.lkr0000644000175000017500000000303311156521271012604 00000000000000// File: 18f86j11.lkr // Sample linker script for the PIC18F86J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16c558.lkr0000644000175000017500000000107411156521271012352 00000000000000// Sample linker command file for 16C558 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/12f510i.lkr0000644000175000017500000000163711156521271012513 00000000000000// Sample linker command file for 12F510 // No additional resource constraints were required by the ICD2 for this // device so this file is a duplicate of 12F510.lkr but named 12F510i.lkr LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x1FF CODEPAGE NAME=page1 START=0x200 END=0x3FF CODEPAGE NAME=.idlocs START=0x400 END=0x403 PROTECTED CODEPAGE NAME=.config START=0xFFF END=0xFFF PROTECTED SHAREBANK NAME=sfrs START=0x0 END=0x09 PROTECTED SHAREBANK NAME=sfrs START=0x20 END=0x29 PROTECTED SHAREBANK NAME=gprnobnk START=0x0A END=0x0F SHAREBANK NAME=gprnobnk START=0x2A END=0x2F PROTECTED DATABANK NAME=gpr0 START=0x10 END=0x1F DATABANK NAME=gpr1 START=0x30 END=0x3F SECTION NAME=PROG0 ROM=page0 // ROM code space SECTION NAME=PROG1 ROM=page1 // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f46k20i_e.lkr0000644000175000017500000000342311156521271013261 00000000000000// File: 18f46k20i_e.lkr // Sample ICD2 linker script for the PIC18F46K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8493.lkr0000644000175000017500000000156711156521271012454 00000000000000// File: 18f8493.lkr // Sample linker script for the PIC18F8493 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8410_e.lkr0000644000175000017500000000157111156521271012740 00000000000000// File: 18f8410_e.lkr // Sample linker script for the PIC18F8410 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2423.lkr0000644000175000017500000000157211156521271012433 00000000000000// File: 18f2423.lkr // Sample linker script for the PIC18F2423 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f442i.lkr0000644000175000017500000000203311156521271012514 00000000000000// File: 18f442i.lkr // Sample ICD2 linker script for the PIC18F442 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3DBF CODEPAGE NAME=debug START=0x3DC0 END=0x3FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2F3 DATABANK NAME=dbgspr START=0x2F4 END=0x2FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j16.lkr0000644000175000017500000000303411156521271012612 00000000000000// File: 18f86j16.lkr // Sample linker script for the PIC18F86J16 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF59 DATABANK NAME=sfr15 START=0xF5A END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2585.lkr0000644000175000017500000000324511156521271012443 00000000000000// File: 18f2585.lkr // Sample linker script for the PIC18F2585 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f87j10.lkr0000644000175000017500000000271711156521271012614 00000000000000// File: 18f87j10.lkr // Sample linker script for the PIC18F87J10 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEFF DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f24k20.lkr0000644000175000017500000000157411156521271012605 00000000000000// File: 18f24k20.lkr // Sample linker script for the PIC18F24K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6310.lkr0000644000175000017500000000156711156521271012436 00000000000000// File: 18f6310.lkr // Sample linker script for the PIC18F6310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18lf14k22i.lkr0000644000175000017500000000162711156521271013132 00000000000000// File: 18lf14k22i.lkr // Sample ICD2 linker script for the PIC18LF14K22 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8622i.lkr0000644000175000017500000000341711156521271012613 00000000000000// File: 18f8622i.lkr // Sample ICD2 linker script for the PIC18F8622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8680i.lkr0000644000175000017500000000351011156521271012611 00000000000000// File: 18f8680i.lkr // Sample ICD2 linker script for the PIC18F8680 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCF3 DATABANK NAME=dbgspr START=0xCF4 END=0xCFF PROTECTED DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8310_e.lkr0000644000175000017500000000157111156521271012737 00000000000000// File: 18f8310_e.lkr // Sample linker script for the PIC18F8310 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f8527i.lkr0000644000175000017500000000341711156521271012617 00000000000000// File: 18f8527i.lkr // Sample ICD2 linker script for the PIC18F8527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f25k20_e.lkr0000644000175000017500000000205411156521271013104 00000000000000// File: 18f25k20_e.lkr // Sample linker script for the PIC18F25K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr83.lkr0000644000175000017500000000120111156521271012435 00000000000000// Sample linker command file for 16CR83 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0xB PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x8B PROTECTED DATABANK NAME=gprs START=0xC END=0x2F SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18f85j11.lkr0000644000175000017500000000177611156521271012617 00000000000000// File: 18f85j11.lkr // Sample linker script for the PIC18F85J11 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4320i.lkr0000644000175000017500000000174311156521271012602 00000000000000// File: 18f4320i.lkr // Sample ICD2 linker script for the PIC18F4320 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1DBF CODEPAGE NAME=debug START=0x1DC0 END=0x1FFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1F3 DATABANK NAME=dbgspr START=0x1F4 END=0x1FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/16cr62.lkr0000644000175000017500000000107411156521271012442 00000000000000// Sample linker command file for 16CR62 LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=gpr0 START=0x20 END=0x7F DATABANK NAME=gpr1 START=0xA0 END=0xBF SECTION NAME=PROG ROM=page // ROM code space SECTION NAME=IDLOCS ROM=.idlocs // ID locations gputils-0.13.7/lkr/18f44k20.lkr0000644000175000017500000000157411156521271012607 00000000000000// File: 18f44k20.lkr // Sample linker script for the PIC18F44K20 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j60i.lkr0000644000175000017500000000315611156521271012767 00000000000000// File: 18f86j60i.lkr // Sample ICD2 linker script for the PIC18F86J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF7 CODEPAGE NAME=config START=0xFFF8 END=0xFFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f65j90_e.lkr0000644000175000017500000000200011156521271013105 00000000000000// File: 18f65j90_e.lkr // Sample linker script for the PIC18F65J90 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FF7 CODEPAGE NAME=config START=0x7FF8 END=0x7FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/16f872.lkr0000644000175000017500000000224511156521271012355 00000000000000// Sample linker command file for 16F872 LIBPATH . CODEPAGE NAME=page0 START=0x0 END=0x7FF CODEPAGE NAME=.idlocs START=0x2000 END=0x2003 PROTECTED CODEPAGE NAME=.config START=0x2007 END=0x2007 PROTECTED CODEPAGE NAME=eedata START=0x2100 END=0x213F PROTECTED DATABANK NAME=sfr0 START=0x0 END=0x1F PROTECTED DATABANK NAME=sfr1 START=0x80 END=0x9F PROTECTED DATABANK NAME=sfr2 START=0x100 END=0x10F PROTECTED DATABANK NAME=sfr3 START=0x180 END=0x18F PROTECTED SHAREBANK NAME=share0 START=0x20 END=0x6F SHAREBANK NAME=share0 START=0x120 END=0x16F PROTECTED SHAREBANK NAME=share1 START=0xA0 END=0xBF SHAREBANK NAME=share1 START=0x1A0 END=0x1BF PROTECTED SHAREBANK NAME=share2 START=0x70 END=0x7F SHAREBANK NAME=share2 START=0xF0 END=0xFF PROTECTED SHAREBANK NAME=share2 START=0x170 END=0x17F PROTECTED SHAREBANK NAME=share2 START=0x1F0 END=0x1FF PROTECTED SECTION NAME=PROG1 ROM=page0 // ROM code space - page0 SECTION NAME=IDLOCS ROM=.idlocs // ID locations SECTION NAME=DEEPROM ROM=eedata // Data EEPROM gputils-0.13.7/lkr/18lf14k50i.lkr0000644000175000017500000000172111156521271013126 00000000000000// File: 18lf14k50i.lkr // Sample ICD2 linker script for the PIC18LF14K50 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x3FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=sfr15 START=0xF40 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f2458_e.lkr0000644000175000017500000000226111156521271012743 00000000000000// File: 18f2458_e.lkr // Sample linker script for the PIC18F2458 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x5FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED DATABANK NAME=gpr0 START=0x0 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=usb4 START=0x400 END=0x4FF PROTECTED DATABANK NAME=usb5 START=0x500 END=0x5FF PROTECTED DATABANK NAME=usb6 START=0x600 END=0x6FF PROTECTED DATABANK NAME=usb7 START=0x700 END=0x7FF PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f1230.lkr0000644000175000017500000000140511156521271012421 00000000000000// File: 18f1230.lkr // Sample linker script for the PIC18F1230 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF0007F PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x7F DATABANK NAME=gpr0 START=0x80 END=0xFF ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f86j65_e.lkr0000644000175000017500000000303611156521271013124 00000000000000// File: 18f86j65_e.lkr // Sample linker script for the PIC18F86J65 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x17FF7 CODEPAGE NAME=config START=0x17FF8 END=0x17FFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f67j60i_e.lkr0000644000175000017500000000316111156521271013266 00000000000000// File: 18f67j60i_e.lkr // Sample ICD2 linker script for the PIC18F67J60 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF7 CODEPAGE NAME=config START=0x1FFF8 END=0x1FFFD PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDF3 DATABANK NAME=dbgspr START=0xDF4 END=0xDFF PROTECTED DATABANK NAME=gpr14 START=0xE00 END=0xE7F DATABANK NAME=sfr14 START=0xE80 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f6622i.lkr0000644000175000017500000000341711156521271012611 00000000000000// File: 18f6622i.lkr // Sample ICD2 linker script for the PIC18F6622 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xFD7F CODEPAGE NAME=debug START=0xFD80 END=0xFFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/17c762.lkr0000644000175000017500000000512411156521271012350 00000000000000// Sample linker command file for 17C762 // $Id: 17c762.lkr,v 1.5 2008/03/20 17:19:03 curtiss Exp $ LIBPATH . CODEPAGE NAME=page START=0x0 END=0x1FFF CODEPAGE NAME=config START=0xFE00 END=0xFE0F PROTECTED SHAREBANK NAME=sfrnobnk START=0x0 END=0xF PROTECTED SHAREBANK NAME=sfrnobnk START=0x100 END=0x10F PROTECTED SHAREBANK NAME=sfrnobnk START=0x200 END=0x20F PROTECTED SHAREBANK NAME=sfrnobnk START=0x300 END=0x30F PROTECTED SHAREBANK NAME=sfrnobnk START=0x400 END=0x40F PROTECTED SHAREBANK NAME=sfrnobnk START=0x500 END=0x50F PROTECTED SHAREBANK NAME=sfrnobnk START=0x600 END=0x60F PROTECTED SHAREBANK NAME=sfrnobnk START=0x700 END=0x70F PROTECTED SHAREBANK NAME=sfrnobnk START=0x800 END=0x80F PROTECTED DATABANK NAME=sfr0 START=0x10 END=0x17 PROTECTED DATABANK NAME=sfr1 START=0x110 END=0x117 PROTECTED DATABANK NAME=sfr2 START=0x210 END=0x217 PROTECTED DATABANK NAME=sfr3 START=0x310 END=0x317 PROTECTED DATABANK NAME=sfr4 START=0x410 END=0x417 PROTECTED DATABANK NAME=sfr5 START=0x510 END=0x517 PROTECTED DATABANK NAME=sfr6 START=0x610 END=0x617 PROTECTED DATABANK NAME=sfr7 START=0x710 END=0x717 PROTECTED DATABANK NAME=sfr8 START=0x810 END=0x817 PROTECTED SHAREBANK NAME=sfrprod START=0x18 END=0x19 PROTECTED SHAREBANK NAME=sfrprod START=0x118 END=0x119 PROTECTED SHAREBANK NAME=sfrprod START=0x218 END=0x219 PROTECTED SHAREBANK NAME=sfrprod START=0x318 END=0x319 PROTECTED SHAREBANK NAME=sfrprod START=0x418 END=0x419 PROTECTED SHAREBANK NAME=sfrprod START=0x518 END=0x519 PROTECTED SHAREBANK NAME=sfrprod START=0x618 END=0x619 PROTECTED SHAREBANK NAME=sfrprod START=0x718 END=0x719 PROTECTED SHAREBANK NAME=sfrprod START=0x818 END=0x819 PROTECTED SHAREBANK NAME=registers START=0x1A END=0x1F SHAREBANK NAME=registers START=0x11A END=0x11F SHAREBANK NAME=registers START=0x21A END=0x21F SHAREBANK NAME=registers START=0x31A END=0x31F SHAREBANK NAME=registers START=0x41A END=0x41F SHAREBANK NAME=registers START=0x51A END=0x51F SHAREBANK NAME=registers START=0x61A END=0x61F SHAREBANK NAME=registers START=0x71A END=0x71F SHAREBANK NAME=registers START=0x81A END=0x81F DATABANK NAME=gpr0 START=0x20 END=0xFF DATABANK NAME=gpr1 START=0x120 END=0x1FF DATABANK NAME=gpr2 START=0x220 END=0x2FF // The stack directive below is for use with MPLAB-C17 // STACK SIZE=0x20 gputils-0.13.7/lkr/18f6527i_e.lkr0000644000175000017500000000342111156521271013114 00000000000000// File: 18f6527i_e.lkr // Sample ICD2 linker script for the PIC18F6527 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0xBD7F CODEPAGE NAME=debug START=0xBD80 END=0xBFFF PROTECTED CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF003FF PROTECTED DATABANK NAME=gpre START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=gpr6 START=0x600 END=0x6FF DATABANK NAME=gpr7 START=0x700 END=0x7FF DATABANK NAME=gpr8 START=0x800 END=0x8FF DATABANK NAME=gpr9 START=0x900 END=0x9FF DATABANK NAME=gpr10 START=0xA00 END=0xAFF DATABANK NAME=gpr11 START=0xB00 END=0xBFF DATABANK NAME=gpr12 START=0xC00 END=0xCFF DATABANK NAME=gpr13 START=0xD00 END=0xDFF DATABANK NAME=gpr14 START=0xE00 END=0xEF3 DATABANK NAME=dbgspr START=0xEF4 END=0xEFF PROTECTED DATABANK NAME=gpr15 START=0xF00 END=0xF5F ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/lkr/18f4580.lkr0000644000175000017500000000241711156521271012440 00000000000000// File: 18f4580.lkr // Sample linker script for the PIC18F4580 processor // Not intended for use with MPLAB C18. For C18 projects, // use the linker scripts provided with that product. LIBPATH . CODEPAGE NAME=page START=0x0 END=0x7FFF CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED ACCESSBANK NAME=accessram START=0x0 END=0x5F DATABANK NAME=gpr0 START=0x60 END=0xFF DATABANK NAME=gpr1 START=0x100 END=0x1FF DATABANK NAME=gpr2 START=0x200 END=0x2FF DATABANK NAME=gpr3 START=0x300 END=0x3FF DATABANK NAME=gpr4 START=0x400 END=0x4FF DATABANK NAME=gpr5 START=0x500 END=0x5FF DATABANK NAME=sfr13 START=0xD00 END=0xDFF PROTECTED DATABANK NAME=sfr14 START=0xE00 END=0xEFF PROTECTED DATABANK NAME=sfr15 START=0xF00 END=0xF5F PROTECTED ACCESSBANK NAME=accesssfr START=0xF60 END=0xFFF PROTECTED gputils-0.13.7/doc/0000777000175000017500000000000011156521351011043 500000000000000gputils-0.13.7/doc/gputils.lyx0000644000175000017500000063567111156521302013222 00000000000000#LyX 1.5.1 created this file. For more info see http://www.lyx.org/ \lyxformat 276 \begin_document \begin_header \textclass book \language english \inputencoding default \font_roman times \font_sans default \font_typewriter default \font_default_family default \font_sc false \font_osf false \font_sf_scale 100 \font_tt_scale 100 \graphics default \paperfontsize 10 \spacing single \papersize letterpaper \use_geometry true \use_amsmath 1 \use_esint 0 \cite_engine basic \use_bibtopic false \paperorientation portrait \leftmargin 34mm \rightmargin 34mm \secnumdepth 2 \tocdepth 2 \paragraph_separation indent \defskip medskip \quotes_language english \papercolumns 1 \papersides 1 \paperpagestyle default \tracking_changes false \output_changes false \author "" \end_header \begin_body \begin_layout Title gputils 0.13.7 \end_layout \begin_layout Author James Bowman, Craig Franklin, and David Barnett \end_layout \begin_layout Date November 20, 2007 \end_layout \begin_layout Standard \begin_inset LatexCommand tableofcontents \end_inset \end_layout \begin_layout Chapter Introduction \end_layout \begin_layout Standard gputils is a collection of tools for Microchip ( \shape smallcaps TM \shape default ) PIC microcontrollers. It includes gpasm, gplink, and gplib. Each tool is intended to be an open source replacement for a corresponding Microchip (TM) tool. This manual covers the basics of running the tools. For more details on a microcontroller, consult the manual for the specific PICmicro product that you are using. \end_layout \begin_layout Standard This document is part of gputils. \end_layout \begin_layout Standard gputils is free software; you can redistribute it and/or modify it under the terms of the \begin_inset LatexCommand index name "GNU" \end_inset GNU General Public \begin_inset LatexCommand index name "License" \end_inset License as published by the Free Software Foundation; either version 2, or (at your option) any later version. \end_layout \begin_layout Standard gputils is distributed in the hope that it will be useful, but WITHOUT ANY \begin_inset LatexCommand index name "NO WARRANTY" \end_inset WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. \end_layout \begin_layout Standard You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. \end_layout \begin_layout Section Tool Flows \end_layout \begin_layout Standard gputils can be used in two different ways: absolute asm mode and relocatable asm mode. \end_layout \begin_layout Subsection Absolute Asm Mode \end_layout \begin_layout Standard In absolute asm mode, an assembly language source file is directly converted into a hex file by gpasm. This method is absolute because the final addresses are hard coded into the source file. \end_layout \begin_layout Subsection Relocatable Asm Mode \end_layout \begin_layout Standard In relocatable asm mode, the microcontroller assembly source code is divided into separate modules. Each module is assembled into an object using gpasm. That object can be placed \begin_inset Quotes eld \end_inset anywhere \begin_inset Quotes erd \end_inset in microcontroller's memory. Then gplink is used to resolve symbols references, assign final address, and to patch the machine code with the final addresses. The output from gplink is an absolute executable object. \end_layout \begin_layout Subsection Which Tool Flow is best? \end_layout \begin_layout Standard Absolute mode is simple to understand and to use. It only requires one tool, gpasm. Most of the examples on Microchip's website use absolute mode. So why use relocatable mode? \end_layout \begin_layout Itemize Code can be written without regard to addresses. This makes it easier to write and reuse. \end_layout \begin_layout Itemize The objects can be archived to create a library, which also simplifies reuse. \end_layout \begin_layout Itemize Recompiling a project can be faster, because you only compile the portions that have changed. \end_layout \begin_layout Itemize Files can have local name spaces. The user chooses what symbols are global. \end_layout \begin_layout Standard Most develpment tools use relocatable objects for these reasons. The few that don't are generally microcontroller tools. Their applications are so small that absolute mode isn't impractical. For PICs, relocatable mode has one big disadvantage. The bank and page control is a challenge. \end_layout \begin_layout Section Supported processors \end_layout \begin_layout Standard gputils currently supports all processors supported by MPLAB 8.20 (except eeprom16 and related devices). This includes the following processors: \newline \end_layout \begin_layout LyX-Code eeprom8 gen hcs1365 hcs1370 mcv08a mcv14a \newline mcv18a mcv28a p10f200 p10f202 p10f204 p10f206 \newline p10f220 p10f222 p12c508 p12c508a p12f508 p12c509 \newline p12c509a p12cr509a p12f509 p12f510 p12ce518 p12ce519 \newline p12f519 p12f609 p12hv609 p12f615 p12hv615 p12f629 \newline p12f635 p12c671 p12c672 p12ce673 p12ce674 p12f675 \newline p12f683 p14000 p16cxx p16f1933 p16lf1933 p16f1934 \newline p16lf1934 p16f1936 p16lf1936 p16f1937 p16lf1937 p16c432 \newline p16c433 p16c5x p16c505 p16f505 p16f506 p16c52 \newline p16f526 p16c54 p16c54a p16c54b p16c54c p16cr54 \newline p16cr54a p16cr54b p16cr54c p16f54 p16hv540 p16c55 \newline p16c55a p16c554 p16c557 p16c558 p16c56 p16c56a \newline p16cr56a p16c57 p16c57c p16cr57a p16cr57b p16cr57c \newline p16f57 p16c58a p16c58b p16cr58a p16cr58b p16f59 \newline p16c61 p16f610 p16hv610 p16f616 p16hv616 p16c62 \newline p16c62a p16c62b p16cr62 p16c620 p16c620a p16cr620a \newline p16c621 p16c621a p16c622 p16c622a p16ce623 p16ce624 \newline p16ce625 p16f627 p16f627a p16f628 p16f628a p16c63 \newline p16c63a p16cr63 p16f630 p16f631 p16f636 p16f639 \newline p16c64 p16c64a p16cr64 p16c642 p16f648a p16c65 \newline p16c65a p16c65b p16cr65 p16c66 p16c662 p16c67 \newline p16f676 p16f677 p16f684 p16f685 p16f687 p16f688 \newline p16f689 p16f690 p16c71 p16c710 p16c711 p16c712 \newline p16c715 p16c716 p16f716 p16c717 p16c72 p16c72a \newline p16cr72 p16f72 p16f722 p16lf722 p16f723 p16lf723 \newline p16f724 p16lf724 p16f726 p16lf726 p16f727 p16lf727 \newline p16c73 p16c73a p16c73b p16f73 p16f737 p16c74 \newline p16c74a p16c74b p16f74 p16c745 p16f747 p16c76 \newline p16f76 p16c765 p16f767 p16c77 p16f77 p16c770 \newline p16c771 p16c773 p16c774 p16f777 p16c781 p16c782 \newline p16f785 p16hv785 p16f818 p16f819 p16cr83 p16f83 \newline p16c84 p16cr84 p16f84 p16f84a p16f87 p16f870 \newline p16f871 p16f872 p16f873 p16f873a p16f874 p16f874a \newline p16f876 p16f876a p16f877 p16f877a p16f88 p16f882 \newline p16f883 p16f884 p16f886 p16f887 p16f913 p16f914 \newline p16f916 p16f917 p16c923 p16c924 p16c925 p16c926 \newline p16f946 p17cxx p17c42 p17c42a p17cr42 p17c43 \newline p17cr43 p17c44 p17c752 p17c756 p17c756a p17c762 \newline p17c766 p18cxx p18f1220 p18f1230 p18f1320 p18f13k22 \newline p18lf13k22 p18f1330 p18f13k50 p18lf13k50 p18f14k22 p18lf14k22 \newline p18f14k50 p18lf14k50 p18f2220 p18f2221 p18f2320 p18f23k20 \newline p18f2321 p18f2331 p18f2410 p18f24j10 p18f24j11 p18lf24j11 \newline p18c242 p18f242 p18f2420 p18f24k20 p18f2423 p18f2431 \newline p18f2439 p18f2450 p18f24j50 p18lf24j50 p18f2455 p18f2458 \newline p18f248 p18f2480 p18f2510 p18f25j10 p18f25j11 p18lf25j11 \newline p18f2515 p18c252 p18f252 p18f2520 p18f25k20 p18f2523 \newline p18f2525 p18f2539 p18f2550 p18f25j50 p18lf25j50 p18f2553 \newline p18f258 p18f2580 p18f2585 p18f2610 p18f26j11 p18lf26j11 \newline p18f2620 p18f26k20 p18f26j50 p18lf26j50 p18f2680 p18f2681 \newline p18f2682 p18f2685 p18f4220 p18f4221 p18f4320 p18f43k20 \newline p18f4321 p18f4331 p18f4410 p18f44j10 p18f44j11 p18lf44j11 \newline p18c442 p18f442 p18f4420 p18f44k20 p18f4423 p18f4431 \newline p18f4439 p18f4450 p18f44j50 p18lf44j50 p18f4455 p18f4458 \newline p18f448 p18f4480 p18f4510 p18f45j10 p18f45j11 p18lf45j11 \newline p18f4515 p18c452 p18f452 p18f4520 p18f45k20 p18f4523 \newline p18f4525 p18f4539 p18f4550 p18f45j50 p18lf45j50 p18f4553 \newline p18f458 p18f4580 p18f4585 p18f4610 p18f46j11 p18lf46j11 \newline p18f4620 p18f46k20 p18f46j50 p18lf46j50 p18f4680 p18f4681 \newline p18f4682 p18f4685 p18c601 p18f6310 p18f63j11 p18f6390 \newline p18f63j90 p18f6393 p18f6410 p18f64j11 p18f64j15 p18f6490 \newline p18f64j90 p18f6493 p18f65j10 p18f65j11 p18f65j15 p18f6520 \newline p18f6525 p18f6527 p18f65j50 p18c658 p18f6585 p18f65j90 \newline p18f66j10 p18f66j11 p18f66j15 p18f66j16 p18f6620 p18f6621 \newline p18f6622 p18f6627 p18f6628 p18f66j50 p18f66j55 p18f66j60 \newline p18f66j65 p18f6680 p18f66j90 p18f67j10 p18f67j11 p18f6720 \newline p18f6722 p18f6723 p18f67j50 p18f67j60 p18f67j90 p18c801 \newline p18f8310 p18f83j11 p18f8390 p18f83j90 p18f8393 p18f8410 \newline p18f84j11 p18f84j15 p18f8490 p18f84j90 p18f8493 p18f85j10 \newline p18f85j11 p18f85j15 p18f8520 p18f8525 p18f8527 p18f85j50 \newline p18c858 p18f8585 p18f85j90 p18f86j10 p18f86j11 p18f86j15 \newline p18f86j16 p18f8620 p18f8621 p18f8622 p18f8627 p18f8628 \newline p18f86j50 p18f86j55 p18f86j60 p18f86j65 p18f8680 p18f86j90 \newline p18f87j10 p18f87j11 p18f8720 p18f8722 p18f8723 p18f87j50 \newline p18f87j60 p18f87j90 p18f96j60 p18f96j65 p18f97j60 ps500 \newline ps810 rf509af rf509ag rf675f rf675h rf675k \newline sx18 sx20 sx28 sx48 sx52 \newline \end_layout \begin_layout Chapter gpasm \end_layout \begin_layout Section Running gpasm \begin_inset LatexCommand index name "gpasm options" \end_inset \end_layout \begin_layout Standard The general syntax for running gpasm is \end_layout \begin_layout LyX-Code gpasm [options] asm-file \end_layout \begin_layout Standard Where options can be one of: \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard \align center \begin_inset Tabular \begin_inset Text \begin_layout Standard Option \end_layout \end_inset \begin_inset Text \begin_layout Standard Meaning \end_layout \end_inset \begin_inset Text \begin_layout Standard a \end_layout \end_inset \begin_inset Text \begin_layout Standard Produce \begin_inset LatexCommand index name "hex file" \end_inset hex file in one of four formats: inhx8m, inhx8s, inhx16, inhx32 (the default). \end_layout \end_inset \begin_inset Text \begin_layout Standard c \end_layout \end_inset \begin_inset Text \begin_layout Standard Output a relocatable object in the older version of the Microchip COFF format \end_layout \end_inset \begin_inset Text \begin_layout Standard C \end_layout \end_inset \begin_inset Text \begin_layout Standard Output a relocatable object in the new Microchip COFF format \end_layout \end_inset \begin_inset Text \begin_layout Standard d \end_layout \end_inset \begin_inset Text \begin_layout Standard Output debug messages \end_layout \end_inset \begin_inset Text \begin_layout Standard D symbol[=value] \end_layout \end_inset \begin_inset Text \begin_layout Standard Equivalent to \begin_inset Quotes eld \end_inset #define \begin_inset Quotes erd \end_inset \end_layout \end_inset \begin_inset Text \begin_layout Standard e [ON|OFF] \end_layout \end_inset \begin_inset Text \begin_layout Standard Expand macros in listing file \end_layout \end_inset \begin_inset Text \begin_layout Standard g \end_layout \end_inset \begin_inset Text \begin_layout Standard Use debug directives for COFF \end_layout \end_inset \begin_inset Text \begin_layout Standard h \end_layout \end_inset \begin_inset Text \begin_layout Standard Display the help message \end_layout \end_inset \begin_inset Text \begin_layout Standard i \end_layout \end_inset \begin_inset Text \begin_layout Standard \begin_inset LatexCommand index name "case" \end_inset Ignore case in source code. By default gpasms to treats \begin_inset Quotes eld \end_inset fooYa \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset FOOYA \begin_inset Quotes erd \end_inset as being different. \end_layout \end_inset \begin_inset Text \begin_layout Standard I \end_layout \end_inset \begin_inset Text \begin_layout Standard Specify an include directory \end_layout \end_inset \begin_inset Text \begin_layout Standard l \end_layout \end_inset \begin_inset Text \begin_layout Standard List the supported processors \end_layout \end_inset \begin_inset Text \begin_layout Standard L \end_layout \end_inset \begin_inset Text \begin_layout Standard Ignore nolist directives \end_layout \end_inset \begin_inset Text \begin_layout Standard m \end_layout \end_inset \begin_inset Text \begin_layout Standard Memory dump \end_layout \end_inset \begin_inset Text \begin_layout Standard M \end_layout \end_inset \begin_inset Text \begin_layout Standard Output a dependency file \end_layout \end_inset \begin_inset Text \begin_layout Standard n \end_layout \end_inset \begin_inset Text \begin_layout Standard Use DOS style newlines (CRLF) in hex file. This option is disabled on win32 systems. \end_layout \end_inset \begin_inset Text \begin_layout Standard o \end_layout \end_inset \begin_inset Text \begin_layout Standard Alternate name of hex output file \end_layout \end_inset \begin_inset Text \begin_layout Standard p \end_layout \end_inset \begin_inset Text \begin_layout Standard Select target processor \end_layout \end_inset \begin_inset Text \begin_layout Standard q \end_layout \end_inset \begin_inset Text \begin_layout Standard Quiet \end_layout \end_inset \begin_inset Text \begin_layout Standard r \end_layout \end_inset \begin_inset Text \begin_layout Standard Set the \begin_inset LatexCommand index name "radix" \end_inset radix, i.e. the number base that gpasm uses when interpreting numbers. can be one of \begin_inset Quotes eld \end_inset oct \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset dec \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset hex \begin_inset Quotes erd \end_inset for bases eight, ten, and sixteen respectively. Default is \begin_inset Quotes eld \end_inset hex \begin_inset Quotes erd \end_inset . \end_layout \end_inset \begin_inset Text \begin_layout Standard u \end_layout \end_inset \begin_inset Text \begin_layout Standard Use absolute paths \end_layout \end_inset \begin_inset Text \begin_layout Standard v \end_layout \end_inset \begin_inset Text \begin_layout Standard Print gpasm version information and exit \end_layout \end_inset \begin_inset Text \begin_layout Standard w [ 0 | 1 | 2 ] \end_layout \end_inset \begin_inset Text \begin_layout Standard Set the message level \end_layout \end_inset \begin_inset Text \begin_layout Standard y \end_layout \end_inset \begin_inset Text \begin_layout Standard Enable 18xx extended mode \end_layout \end_inset \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard Unless otherwise specified, gpasm removes the \begin_inset Quotes eld \end_inset .asm \begin_inset Quotes erd \end_inset suffix from its input file, replacing it with \begin_inset Quotes eld \end_inset .lst \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset .hex \begin_inset Quotes erd \end_inset for the list and hex output files respectively. On most modern operating systems case is significant in filenames. For this reason you should ensure that filenames are named consistently, and that the \begin_inset Quotes eld \end_inset .asm \begin_inset Quotes erd \end_inset suffix on any source file is in lower case. \end_layout \begin_layout Standard gpasm always produces a \begin_inset Quotes eld \end_inset .lst \begin_inset Quotes erd \end_inset file. If it runs without errors, it also produces a \begin_inset Quotes eld \end_inset .hex \begin_inset Quotes erd \end_inset file or a \begin_inset Quotes eld \end_inset .o \begin_inset Quotes erd \end_inset file. \end_layout \begin_layout Subsection Using gpasm with \begin_inset Quotes eld \end_inset make \begin_inset Quotes erd \end_inset \begin_inset LatexCommand index name "make" \end_inset \end_layout \begin_layout Standard On most operating systems, you can build a project using the make utility. To use gpasm with make, you might have a \begin_inset Quotes eld \end_inset makefile \begin_inset Quotes erd \end_inset like this: \end_layout \begin_layout LyX-Code tree.hex: tree.asm treedef.inc \newline gpasm tree.asm \end_layout \begin_layout Standard This will rebuild \begin_inset Quotes eld \end_inset tree.hex \begin_inset Quotes erd \end_inset whenever either of the \begin_inset Quotes eld \end_inset tree.asm \begin_inset Quotes erd \end_inset or \begin_inset Quotes eld \end_inset treedef.inc \begin_inset Quotes erd \end_inset files change. A more comprehensive example of using gpasm with makefiles is included as example1 in the gpasm source distribution. \end_layout \begin_layout Subsection Dealing with errors \begin_inset LatexCommand index name "error file" \end_inset \end_layout \begin_layout Standard gpasm doesn't specifically create an error file. This can be a problem if you want to keep a record of errors, or if your assembly produces so many errors that they scroll off the screen. To deal with this if your shell is \begin_inset LatexCommand index name "sh" \end_inset \begin_inset Quotes eld \end_inset sh \begin_inset Quotes erd \end_inset , \begin_inset LatexCommand index name "bash" \end_inset \begin_inset Quotes eld \end_inset bash \begin_inset Quotes erd \end_inset or \begin_inset LatexCommand index name "ksh" \end_inset \begin_inset Quotes eld \end_inset ksh \begin_inset Quotes erd \end_inset , you can do something like: \end_layout \begin_layout LyX-Code gpasm tree.asm 2>&1 | tee tree.err \end_layout \begin_layout Standard This redirects standard error to standard output ( \begin_inset Quotes eld \end_inset 2>&1 \begin_inset Quotes erd \end_inset ), then pipes this output into \begin_inset Quotes eld \end_inset \begin_inset LatexCommand index name "tee" \end_inset tee \begin_inset Quotes erd \end_inset , which copies it input to \begin_inset Quotes eld \end_inset tree.err \begin_inset Quotes erd \end_inset , and then displays it. \end_layout \begin_layout Section Syntax \end_layout \begin_layout Subsection File structure \end_layout \begin_layout Standard gpasm source files consist of a series of lines. Lines can contain a \begin_inset LatexCommand index name "labels" \end_inset label (starting in column 1) or an operation (starting in any column after 1), both, or neither. \begin_inset LatexCommand index name "comments" \end_inset Comments follow a \begin_inset Quotes eld \end_inset ; \begin_inset Quotes erd \end_inset character, and are treated as a newline. Labels may be any series of the letters A-z, digits 0-9, and the underscore ( \begin_inset Quotes eld \end_inset _ \begin_inset Quotes erd \end_inset ); they may not begin with a digit. Labels may be followed by a colon ( \begin_inset Quotes eld \end_inset : \begin_inset Quotes erd \end_inset ). \end_layout \begin_layout Standard An operation is a single identifier (the same rules as for a label above) followed by a space, and a comma-separated list of parameters. For example, the following are all legal source lines: \end_layout \begin_layout LyX-Code ; Blank line \newline loop sleep ; Label and operation \newline incf 6,1 ; Operation with 2 parameters \newline goto loop ; Operation with 1 parameter \end_layout \begin_layout Subsection Expressions \end_layout \begin_layout Standard gpasm supports a full set of \begin_inset LatexCommand index name "operators" \end_inset operators, based on the C operator set. The operators in the following table are arranged in groups of equal precedence , but the groups are arranged in order of increasing precedence. When gpasm encounters operators of equal precedence, it always evaluates from left to right. \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard \align center \begin_inset Tabular \begin_inset Text \begin_layout Standard Operator \end_layout \end_inset \begin_inset Text \begin_layout Standard Description \end_layout \end_inset \begin_inset Text \begin_layout Standard = \end_layout \end_inset \begin_inset Text \begin_layout Standard assignment \end_layout \end_inset \begin_inset Text \begin_layout Standard || \end_layout \end_inset \begin_inset Text \begin_layout Standard logical or \end_layout \end_inset \begin_inset Text \begin_layout Standard && \end_layout \end_inset \begin_inset Text \begin_layout Standard logical and \end_layout \end_inset \begin_inset Text \begin_layout Standard & \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise and \end_layout \end_inset \begin_inset Text \begin_layout Standard | \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise or \end_layout \end_inset \begin_inset Text \begin_layout Standard ^ \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise exclusive-or \end_layout \end_inset \begin_inset Text \begin_layout Standard < \end_layout \end_inset \begin_inset Text \begin_layout Standard less than \end_layout \end_inset \begin_inset Text \begin_layout Standard > \end_layout \end_inset \begin_inset Text \begin_layout Standard greater than \end_layout \end_inset \begin_inset Text \begin_layout Standard == \end_layout \end_inset \begin_inset Text \begin_layout Standard equals \end_layout \end_inset \begin_inset Text \begin_layout Standard != \end_layout \end_inset \begin_inset Text \begin_layout Standard not equals \end_layout \end_inset \begin_inset Text \begin_layout Standard >= \end_layout \end_inset \begin_inset Text \begin_layout Standard greater than or equal \end_layout \end_inset \begin_inset Text \begin_layout Standard <= \end_layout \end_inset \begin_inset Text \begin_layout Standard less than or equal \end_layout \end_inset \begin_inset Text \begin_layout Standard << \end_layout \end_inset \begin_inset Text \begin_layout Standard left shift \end_layout \end_inset \begin_inset Text \begin_layout Standard >> \end_layout \end_inset \begin_inset Text \begin_layout Standard right shift \end_layout \end_inset \begin_inset Text \begin_layout Standard + \end_layout \end_inset \begin_inset Text \begin_layout Standard addition \end_layout \end_inset \begin_inset Text \begin_layout Standard - \end_layout \end_inset \begin_inset Text \begin_layout Standard subtraction \end_layout \end_inset \begin_inset Text \begin_layout Standard * \end_layout \end_inset \begin_inset Text \begin_layout Standard multiplication \end_layout \end_inset \begin_inset Text \begin_layout Standard / \end_layout \end_inset \begin_inset Text \begin_layout Standard division \end_layout \end_inset \begin_inset Text \begin_layout Standard % \end_layout \end_inset \begin_inset Text \begin_layout Standard modulo \end_layout \end_inset \begin_inset Text \begin_layout Standard UPPER \end_layout \end_inset \begin_inset Text \begin_layout Standard upper byte \end_layout \end_inset \begin_inset Text \begin_layout Standard HIGH \end_layout \end_inset \begin_inset Text \begin_layout Standard high byte \end_layout \end_inset \begin_inset Text \begin_layout Standard LOW \end_layout \end_inset \begin_inset Text \begin_layout Standard low byte \end_layout \end_inset \begin_inset Text \begin_layout Standard - \end_layout \end_inset \begin_inset Text \begin_layout Standard negation \end_layout \end_inset \begin_inset Text \begin_layout Standard ! \end_layout \end_inset \begin_inset Text \begin_layout Standard logical not \end_layout \end_inset \begin_inset Text \begin_layout Standard ~ \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise no \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard \align left Any symbol appearing in column 1 may be assigned a value using the assignment operator (=) in the previous table. Additionally, any value previously assigned may be modified using one of the operators in the table below. Each of these operators evaluates the current value of the symbol and then assigns a new value based on the operator. \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard \align center \begin_inset Tabular \begin_inset Text \begin_layout Standard Operator \end_layout \end_inset \begin_inset Text \begin_layout Standard Description \end_layout \end_inset \begin_inset Text \begin_layout Standard = \end_layout \end_inset \begin_inset Text \begin_layout Standard assignment \end_layout \end_inset \begin_inset Text \begin_layout Standard ++ \end_layout \end_inset \begin_inset Text \begin_layout Standard increment by 1 \end_layout \end_inset \begin_inset Text \begin_layout Standard -- \end_layout \end_inset \begin_inset Text \begin_layout Standard decrement by 1 \end_layout \end_inset \begin_inset Text \begin_layout Standard += \end_layout \end_inset \begin_inset Text \begin_layout Standard increment \end_layout \end_inset \begin_inset Text \begin_layout Standard -= \end_layout \end_inset \begin_inset Text \begin_layout Standard decrement \end_layout \end_inset \begin_inset Text \begin_layout Standard *= \end_layout \end_inset \begin_inset Text \begin_layout Standard multiply \end_layout \end_inset \begin_inset Text \begin_layout Standard /= \end_layout \end_inset \begin_inset Text \begin_layout Standard divide \end_layout \end_inset \begin_inset Text \begin_layout Standard %= \end_layout \end_inset \begin_inset Text \begin_layout Standard modulo \end_layout \end_inset \begin_inset Text \begin_layout Standard <<= \end_layout \end_inset \begin_inset Text \begin_layout Standard left shift \end_layout \end_inset \begin_inset Text \begin_layout Standard >>= \end_layout \end_inset \begin_inset Text \begin_layout Standard right shift \end_layout \end_inset \begin_inset Text \begin_layout Standard &= \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise and \end_layout \end_inset \begin_inset Text \begin_layout Standard |= \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise or \end_layout \end_inset \begin_inset Text \begin_layout Standard ^= \end_layout \end_inset \begin_inset Text \begin_layout Standard bitwise exclusive-or \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Subsection Numbers \begin_inset LatexCommand index name "radix" \end_inset \end_layout \begin_layout Standard \begin_inset LatexCommand label name "sec:numbers" \end_inset gpasm gives you several ways of specifying numbers. You can use a syntax that uses an initial character to indicate the number's base. The following table summarizes the alternatives. Note the C-style option for specifying hexadecimal numbers. \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard \align center \begin_inset Tabular \begin_inset Text \begin_layout Standard base \end_layout \end_inset \begin_inset Text \begin_layout Standard general syntax \end_layout \end_inset \begin_inset Text \begin_layout Standard 21 decimal written as \end_layout \end_inset \begin_inset Text \begin_layout Standard binary \end_layout \end_inset \begin_inset Text \begin_layout Standard B'[01]*' \end_layout \end_inset \begin_inset Text \begin_layout Standard B'10101' \end_layout \end_inset \begin_inset Text \begin_layout Standard octal \end_layout \end_inset \begin_inset Text \begin_layout Standard O'[0-7]*' \end_layout \end_inset \begin_inset Text \begin_layout Standard O'25' \end_layout \end_inset \begin_inset Text \begin_layout Standard decimal \end_layout \end_inset \begin_inset Text \begin_layout Standard D'[0-9]*' \end_layout \end_inset \begin_inset Text \begin_layout Standard D'21' \end_layout \end_inset \begin_inset Text \begin_layout Standard hex \end_layout \end_inset \begin_inset Text \begin_layout Standard H'[0-F]*' \end_layout \end_inset \begin_inset Text \begin_layout Standard H'15' \end_layout \end_inset \begin_inset Text \begin_layout Standard hex \end_layout \end_inset \begin_inset Text \begin_layout Standard 0x[0-F]* \end_layout \end_inset \begin_inset Text \begin_layout Standard 0x15 \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard When you write a number without a specifying prefix such as \begin_inset Quotes eld \end_inset 45 \begin_inset Quotes erd \end_inset , gpasm uses the current radix (base) to interpret the number. You can change this radix with the RADIX directive, or with the \begin_inset Quotes eld \end_inset -r \begin_inset Quotes erd \end_inset option on gpasm's command-line. The default radix is hexadecimal. \end_layout \begin_layout Standard If you do not start hexadecimal numbers with a digit, gpasm will attempt to interpret what you've written as an identifier. For example, instead of writing C2, write either 0C2, 0xC2 or H'C2'. \end_layout \begin_layout Standard Case is not significant when interpreting numbers: 0ca, 0CA, h'CA' and H'ca' are all equivalent. \end_layout \begin_layout Standard Several legacy mpasm number formats are also supported. These formats have various shortcomings, but are still supported. The table below summarizes them. \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard \align center \begin_inset Tabular \begin_inset Text \begin_layout Standard base \end_layout \end_inset \begin_inset Text \begin_layout Standard general syntax \end_layout \end_inset \begin_inset Text \begin_layout Standard 21 decimal written as \end_layout \end_inset \begin_inset Text \begin_layout Standard binary \end_layout \end_inset \begin_inset Text \begin_layout Standard [01]*b \end_layout \end_inset \begin_inset Text \begin_layout Standard 10101b \end_layout \end_inset \begin_inset Text \begin_layout Standard octal \end_layout \end_inset \begin_inset Text \begin_layout Standard q'[0-7]*' \end_layout \end_inset \begin_inset Text \begin_layout Standard q'25' \end_layout \end_inset \begin_inset Text \begin_layout Standard octal \end_layout \end_inset \begin_inset Text \begin_layout Standard [0-7]*o \end_layout \end_inset \begin_inset Text \begin_layout Standard 25o \end_layout \end_inset \begin_inset Text \begin_layout Standard octal \end_layout \end_inset \begin_inset Text \begin_layout Standard [0-7]*q \end_layout \end_inset \begin_inset Text \begin_layout Standard 25q \end_layout \end_inset \begin_inset Text \begin_layout Standard decimal \end_layout \end_inset \begin_inset Text \begin_layout Standard 0-9]*d \end_layout \end_inset \begin_inset Text \begin_layout Standard 21d \end_layout \end_inset \begin_inset Text \begin_layout Standard decimal \end_layout \end_inset \begin_inset Text \begin_layout Standard .[0-9]* \end_layout \end_inset \begin_inset Text \begin_layout Standard .21 \end_layout \end_inset \begin_inset Text \begin_layout Standard hex \end_layout \end_inset \begin_inset Text \begin_layout Standard [0-F]*h \end_layout \end_inset \begin_inset Text \begin_layout Standard 15h \end_layout \end_inset \end_inset \end_layout \begin_layout Standard \begin_inset VSpace 0.3cm \end_inset \end_layout \begin_layout Standard You can write the \begin_inset LatexCommand index name "ASCII" \end_inset ASCII code for a \begin_inset LatexCommand index name "character" \end_inset character X using 'X', or A'X'. \end_layout \begin_layout Subsection Preprocessor \end_layout \begin_layout Standard \begin_inset LatexCommand index name "include" \end_inset A line such as: \end_layout \begin_layout LyX-Code include foo.inc \end_layout \begin_layout Standard will make gpasm fetch source lines from the file \begin_inset Quotes eld \end_inset foo.inc \begin_inset Quotes erd \end_inset until the end of the file, and then return to the original source file at the line following the include. \end_layout \begin_layout Standard Lines beginning with a \begin_inset Quotes eld \end_inset # \begin_inset Quotes erd \end_inset are preprocessor directives, and are treated differently by gpasm. They may contain a \begin_inset Quotes eld \end_inset #define \begin_inset Quotes erd \end_inset , or a \begin_inset Quotes eld \end_inset #undefine \begin_inset Quotes erd \end_inset directive. \end_layout \begin_layout Standard Once gpasm has processed a line such as: \end_layout \begin_layout LyX-Code #define X Y \end_layout \begin_layout Standard every subsequent occurrence of X is replaced with Y, until the end of file or a line \end_layout \begin_layout LyX-Code #undefine X \end_layout \begin_layout Standard appears. \end_layout \begin_layout Standard The preprocessor will replace an occurance of #v(expression) in a symbol with the value of \begin_inset Quotes eld \end_inset expression \begin_inset Quotes erd \end_inset in decimal. In the following expression: \end_layout \begin_layout LyX-Code number equ 5 \newline label_#v( (number +1) * 5 )_suffix equ 0x10 \end_layout \begin_layout Standard gpasm will place the symbol \begin_inset Quotes eld \end_inset label_30_suffix \begin_inset Quotes erd \end_inset with a value of 0x10 in the symbol table. \end_layout \begin_layout Standard The preprocessor in gpasm is only \shape italic like \shape default the C preprocessor; its syntax is rather different from that of the C preproces sor. gpasm uses a simple internal preprocessor to implement \begin_inset Quotes eld \end_inset include \begin_inset Quotes erd \end_inset , \begin_inset Quotes eld \end_inset #define \begin_inset Quotes erd \end_inset and \begin_inset Quotes eld \end_inset #undefine \begin_inset Quotes erd \end_inset . \end_layout \begin_layout Subsection Processor header files \end_layout \begin_layout Standard gputils distributes the Microchip processor header files. These files contain processor specific data that is helpful in developing PIC applications. The location of these files is reported in the gpasm help message. Use the INCLUDE directive to utilize the appropriate file in your source code. Only the name of the file is required. gpasm will search the default path automatically. \end_layout \begin_layout Section Directives \end_layout \begin_layout Subsection Code generation \end_layout \begin_layout Standard In absolute mode, use the ORG directive to set the PIC memory location where gpasm will start assembling code. If you don't specify an address with ORG, gpasm assumes 0x0000. In relocatable mode, use the CODE directive. \end_layout \begin_layout Subsection Configuration \end_layout \begin_layout Standard You can choose the fuse settings for your PIC implementation using the __CONFIG directive, so that the hex file set the fuses explicitly. Naturally you should make sure that these settings match your PIC hardware design. \end_layout \begin_layout Standard The __MAXRAM and __BADRAM directives specify which RAM locations are legal. These directives are mostly used in processor-specific configuration files. \end_layout \begin_layout Subsection Conditional assembly \end_layout \begin_layout Standard The IF, IFNDEF, IFDEF, ELSE and ENDIF directives enable you to assemble certain sections of code only if a condition is met. In themselves, they do not cause gpasm to emit any PIC code. The example in section \begin_inset LatexCommand ref reference "sec:macros" \end_inset for demonstrates conditional assembly. \end_layout \begin_layout Subsection Macros \end_layout \begin_layout Standard \begin_inset LatexCommand label name "sec:macros" \end_inset gpasm supports a simple macro scheme; you can define and use macros like this: \end_layout \begin_layout LyX-Code any macro parm \newline movlw parm \newline endm \newline ... \newline any 33 \end_layout \begin_layout Standard A more useful example of some macros in use is: \end_layout \begin_layout LyX-Code ; Shift reg left \newline slf macro reg \newline clrc \newline rlf reg,f \newline endm \newline \end_layout \begin_layout LyX-Code ; Scale W by \begin_inset Quotes eld \end_inset factor \begin_inset Quotes erd \end_inset . Result in \begin_inset Quotes eld \end_inset reg \begin_inset Quotes erd \end_inset , W unchanged. \end_layout \begin_layout LyX-Code scale macro reg, factor \newline if (factor == 1) \newline movwf reg ; 1 X is easy \newline else \newline scale reg, (factor / 2) ; W * (factor / 2) \newline slf reg,f ; double reg \newline if ((factor & 1) == 1) ; if lo-bit set .. \newline addwf reg,f ; .. add W to reg \newline endif \newline endif \newline endm \end_layout \begin_layout Standard This recursive macro generates code to multiply W by a constant \begin_inset Quotes eld \end_inset factor \begin_inset Quotes erd \end_inset , and stores the result in \begin_inset Quotes eld \end_inset reg \begin_inset Quotes erd \end_inset . So writing: \end_layout \begin_layout LyX-Code scale tmp,D'10' \end_layout \begin_layout Standard is the same as writing: \end_layout \begin_layout LyX-Code movwf tmp ; tmp = W \newline clrc \newline rlf tmp,f ; tmp = 2 * W \newline clrc \newline rlf tmp,f ; tmp = 4 * W \newline addwf tmp,f ; tmp = (4 * W) + W = 5 * W \newline clrc \newline rlf tmp,f ; tmp = 10 * W \end_layout \begin_layout Subsection $ \end_layout \begin_layout Standard $ expands to the address of the instruction currently being assembled. If it's used in a context other than an instruction, such as a conditional, it expands to the address the next instruction would occupy, since the assembler's idea of current address is incremented after an instruction is assembled. $ may be manipulated just like any other number: \end_layout \begin_layout LyX-Code $ \newline $ + 1 \newline $ - 2 \end_layout \begin_layout Standard and can be used as a shortcut for writing loops without labels. \end_layout \begin_layout LyX-Code LOOP: BTFSS flag,0x00 \newline GOTO LOOP \newline \newline BTFSS flag,0x00 \newline GOTO $ - 1 \end_layout \begin_layout Subsection Suggestions for structuring your code \end_layout \begin_layout Standard \begin_inset LatexCommand label name "sec:structuring" \end_inset Nested IF operations can quickly become confusing. Indentation is one way of making code clearer. Another way is to add braces on IF, ELSE and ENDIF, like this: \end_layout \begin_layout LyX-Code IF (this) ; { \newline ... \newline ELSE ; }{ \newline ... \newline ENDIF ; } \end_layout \begin_layout Standard After you've done this, you can use your text editor's show-matching-brace to check matching parts of the IF structure. In vi this command is \begin_inset Quotes eld \end_inset % \begin_inset Quotes erd \end_inset , in emacs it's M-C-f and M-C-b. \end_layout \begin_layout Subsection Directive summary \begin_inset LatexCommand label name "sec:directivesummary" \end_inset \end_layout \begin_layout Subsection* __BADRAM \begin_inset LatexCommand index name "\\_\\_BADRAM" \end_inset \end_layout \begin_layout LyX-Code __BADRAM [, ]* \end_layout \begin_layout Standard Instructs gpasm that it should generate an error if there is any use of the given RAM locations. Specify a range of addresses with -. See any processor-specific header file for an example. \end_layout \begin_layout Standard See also: __MAXRAM \end_layout \begin_layout Subsection* __BADROM \begin_inset LatexCommand index name "\\_\\_BADROM" \end_inset \end_layout \begin_layout LyX-Code __BADROM [, ]* \end_layout \begin_layout Standard Instructs gpasm that it should generate an error if there is any use of the given ROM locations. Specify a range of addresses with -. See any processor-specific header file for an example. \end_layout \begin_layout Standard See also: __MAXROM \end_layout \begin_layout Subsection* __CONFIG \begin_inset LatexCommand index name "\\_\\_CONFIG" \end_inset \end_layout \begin_layout LyX-Code __CONFIG \end_layout \begin_layout Standard Sets the PIC processor's configuration fuses. \end_layout \begin_layout Standard See also: CONFIG, __FUSES \end_layout \begin_layout Subsection* __FUSES \begin_inset LatexCommand index name "\\_\\_FUSES" \end_inset \end_layout \begin_layout LyX-Code __FUSES \end_layout \begin_layout Standard Alias for __CONFIG. Sets the PIC processor's configuration fuses. \end_layout \begin_layout Standard See also: CONFIG \end_layout \begin_layout Subsection* __IDLOCS \begin_inset LatexCommand index name "\\_\\_IDLOCS" \end_inset \end_layout \begin_layout LyX-Code __IDLOCS or __IDLOCS , \end_layout \begin_layout Standard Sets the PIC processor's identification locations. For 12 and 14 bit processors, the four id locations are set to the hexadecimal value of expression. For 18cxx devices idlocation expression1 is set to the hexadecimal value of expression2. \end_layout \begin_layout Subsection* __MAXRAM \begin_inset LatexCommand index name "\\_\\_MAXRAM" \end_inset \end_layout \begin_layout LyX-Code __MAXRAM \end_layout \begin_layout Standard Instructs gpasm that an attempt to use any RAM location above the one specified should be treated as an error. See any processor specific header file for an example. \end_layout \begin_layout Standard See also: __BADRAM \end_layout \begin_layout Subsection* __MAXROM \begin_inset LatexCommand index name "\\_\\_MAXROM" \end_inset \end_layout \begin_layout LyX-Code __MAXROM \end_layout \begin_layout Standard Instructs gpasm that an attempt to use any ROM location above the one specified should be treated as an error. See any processor specific header file for an example. \end_layout \begin_layout Standard See also: __BADROM \end_layout \begin_layout Subsection* BANKISEL \begin_inset LatexCommand index name "BANKISEL" \end_inset \end_layout \begin_layout LyX-Code BANKISEL

e0 %type

e1 %type

parameter_list %type

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See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA # 02111-1307, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. if test $# -eq 0; then echo 1>&2 "Try \`$0 --help' for more information" exit 1 fi run=: # In the cases where this matters, `missing' is being run in the # srcdir already. if test -f configure.ac; then configure_ac=configure.ac else configure_ac=configure.in fi msg="missing on your system" case "$1" in --run) # Try to run requested program, and just exit if it succeeds. run= shift "$@" && exit 0 # Exit code 63 means version mismatch. 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You should only need it if you modified a dependency of a manual page. You may need the \`Help2man' package in order for those modifications to take effect. You can get \`Help2man' from any GNU archive site." file=`echo "$*" | sed -n 's/.*-o \([^ ]*\).*/\1/p'` if test -z "$file"; then file=`echo "$*" | sed -n 's/.*--output=\([^ ]*\).*/\1/p'` fi if [ -f "$file" ]; then touch $file else test -z "$file" || exec >$file echo ".ab help2man is required to generate this page" exit 1 fi ;; makeinfo) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified a \`.texi' or \`.texinfo' file, or any other file indirectly affecting the aspect of the manual. The spurious call might also be the consequence of using a buggy \`make' (AIX, DU, IRIX). You might want to install the \`Texinfo' package or the \`GNU make' package. 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AC_PREREQ(2.59) AC_INIT([gputils],[0.13.7], []) AC_CONFIG_SRCDIR([config.h.in]) AC_CONFIG_HEADER([config.h]) AM_INIT_AUTOMAKE AM_MAINTAINER_MODE # Determine the host and build type. The target is always a PIC. AC_CANONICAL_BUILD AC_CANONICAL_HOST # Defaults GPUTILS_HEADER_PATH="\$(datadir)/gputils/header" GPUTILS_LKR_PATH="\$(datadir)/gputils/lkr" GPUTILS_LIB_PATH="\$(datadir)/gputils/lib" LIBGPUTILS=libgputils/libgputils.a LIBIBERTY=libiberty/libiberty.a MAKE_SUBDIRS="libgputils libiberty gpasm gplink gputils header lkr doc man" # Check for additional parameters AC_ARG_ENABLE(debug, [ --enable-debug enable gputils debug features], [enable_gputils_debug=yes]) AC_ARG_ENABLE(path, [ --disable-path disable adding default search paths], [], [enable_gputils_path=yes]) # Checks for programs. AC_PROG_CC AC_PROG_YACC AM_PROG_LEX set `$LEX -V` if test "${3}" != "2.5.4"; then AC_MSG_WARN(gputils supports flex version 2.5.4) fi AC_PROG_INSTALL # append the host alias to the tools for cross compiling AC_CHECK_TOOL(RANLIB, ranlib, :) AC_CHECK_TOOL(AR, ar, :) # Checks for header files. AC_HEADER_STDC AC_CHECK_HEADERS([libintl.h malloc.h stdlib.h string.h strings.h unistd.h windows.h]) AC_CHECK_DECLS([asprintf, basename, getopt, vasprintf]) # Checks for typedefs, structures, and compiler characteristics. AC_C_CONST AC_TYPE_SIZE_T AC_STRUCT_TM # Checks for library functions. AC_CHECK_FUNCS([strcasecmp stricmp]) # Check for functions to compile into libiberty (getopt is always compiled). IBERTYOBJS= AC_CHECK_FUNC(bzero, , [IBERTYOBJS="$IBERTYOBJS bzero.o"]) AC_CHECK_FUNC(vsnprintf, , [IBERTYOBJS="$IBERTYOBJS vasprintf.o vsnprintf.o"]) AC_CHECK_FUNC(snprintf, , [IBERTYOBJS="$IBERTYOBJS snprintf.o"]) AM_CFLAGS= AM_LDFLAGS= # Options for the system on which the package will run case "${host}" in *cygwin* ) if test "x$GCC" = "xyes"; then AM_CFLAGS="-Wall -pedantic" AM_LDFLAGS="-Wl,-warn-common -Wl,-warn-once" fi ;; *linux* ) if test "x$GCC" = "xyes"; then AM_CFLAGS="-Wall -pedantic" AM_LDFLAGS="-Wl,-warn-common -Wl,-warn-once" fi ;; *sun* ) # sunos cc needs the -xCC flag for // comments if test "x$GCC" != "xyes"; then AM_CFLAGS="-xCC" fi ;; *mingw* ) ;; *-pc-os2_emx | *-pc-os2-emx ) EXEEXT=".exe" if test "x$GCC" = "xyes"; then AM_CFLAGS="-Zcrtdll" fi ;; esac # Host filesystem options case "${host}" in *mingw* | *-pc-os2_emx | *-pc-os2-emx | *djgpp* ) AC_DEFINE(HAVE_DOS_BASED_FILE_SYSTEM, 1, [Define if your host uses a DOS based file system. ]) ;; esac # Process the options if test x$enable_gputils_debug = xyes; then AC_DEFINE(GPUTILS_DEBUG, 1, [Define if you want to enable GPUTILS debug features. ]) fi if test x$enable_gputils_path = xyes; then AC_DEFINE(USE_DEFAULT_PATHS, 1, [Define if you want to add default search paths. ]) fi # Substitute configuration variables AC_SUBST(AM_CFLAGS) AC_SUBST(AM_LDFLAGS) AC_SUBST(GPUTILS_HEADER_PATH) AC_SUBST(GPUTILS_LKR_PATH) AC_SUBST(GPUTILS_LIB_PATH) AC_SUBST(IBERTYOBJS) AC_SUBST(LIBGPUTILS) AC_SUBST(LIBIBERTY) AC_SUBST(MAKE_SUBDIRS) # Generate Makefiles AC_CONFIG_FILES([Makefile doc/Makefile gpasm/Makefile gplink/Makefile gputils/Makefile header/Makefile libgputils/Makefile libiberty/Makefile lkr/Makefile man/Makefile man/fr/Makefile gputils.spec]) AC_OUTPUT AC_MSG_RESULT([ gputils-$PACKAGE_VERSION is now configured for $canonical_host_type Build: $build Host: $host Source directory: $srcdir Installation prefix: $prefix C compiler: $CC $CFLAGS ]) gputils-0.13.7/gputils.spec0000644000175000017500000000246711156521352012567 00000000000000Name: gputils Version: 0.13.7 Release: 1 Summary: Development utilities for Microchip (TM) PIC (TM) microcontrollers License: GPL Group: Development/Languages Source: http://prdownloads.sourceforge.net/gputils/gputils-0.13.7.tar.gz Packager: Craig Franklin Vendor: Craig Franklin Distribution: Red Hat Linux URL: http://gputils.sourceforge.net Buildroot: %{_tmppath}/%{name}-%{version}-root %description This is a collection of development tools for Microchip (TM) PIC (TM) microcontrollers. This is ALPHA software: there may be serious bugs in it, and it's nowhere near complete. gputils currently only implements a subset of the features available with Microchip's tools. See the documentation for an up-to-date list of what gputils can do. %prep %setup %build ./configure --prefix=/usr --mandir=/usr/share/man make %install make DESTDIR="$RPM_BUILD_ROOT" install %clean [ ${RPM_BUILD_ROOT} != "/" ] && rm -rf ${RPM_BUILD_ROOT} %files %defattr(-, root, root) %{_bindir}/gpasm %{_bindir}/gpdasm %{_bindir}/gplib %{_bindir}/gplink %{_bindir}/gpstrip %{_bindir}/gpvc %{_bindir}/gpvo %{_mandir}/man1 %{_mandir}/fr/man1 %{_datadir}/gputils/header %{_datadir}/gputils/lkr %doc AUTHORS COPYING ChangeLog NEWS README %doc doc/gputils.pdf doc/gputils.ps gputils-0.13.7/config.sub0000755000175000017500000007511311156313233012202 00000000000000#! /bin/sh # Configuration validation subroutine script. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. timestamp='2004-08-29' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software # can handle that machine. It does not imply ALL GNU software can. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, # Boston, MA 02111-1307, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # Configuration subroutine to validate and canonicalize a configuration type. # Supply the specified configuration type as an argument. # If it is invalid, we print an error message on stderr and exit with code 1. # Otherwise, we print the canonical config type on stdout and succeed. # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases # that are meaningful with *any* GNU software. # Each package is responsible for reporting which valid configurations # it does not support. The user should be able to distinguish # a failure to support a valid configuration from a meaningless # configuration. # The goal of this file is to map all the various variations of a given # machine specification into a single specification in the form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM # or in some cases, the newer four-part form: # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS $0 [OPTION] ALIAS Canonicalize a configuration name. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.sub ($timestamp) Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit 0 ;; --version | -v ) echo "$version" ; exit 0 ;; --help | --h* | -h ) echo "$usage"; exit 0 ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" exit 1 ;; *local*) # First pass through any local machine types. echo $1 exit 0;; * ) break ;; esac done case $# in 0) echo "$me: missing argument$help" >&2 exit 1;; 1) ;; *) echo "$me: too many arguments$help" >&2 exit 1;; esac # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | linux-dietlibc | linux-uclibc* | uclinux-uclibc* | uclinux-gnu* | \ kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | storm-chaos* | os2-emx* | rtmk-nova*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; *) basic_machine=`echo $1 | sed 's/-[^-]*$//'` if [ $basic_machine != $1 ] then os=`echo $1 | sed 's/.*-/-/'` else os=; fi ;; esac ### Let's recognize common machines as not being operating systems so ### that things like config.sub decstation-3100 work. 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m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown os=-none ;; m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) ;; # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word "unknown" tends to confuse beginning users. i*86 | x86_64) basic_machine=$basic_machine-pc ;; # Object if more than one company name word. *-*-*) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; # Recognize the basic CPU types with company name. 580-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* \ | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ | clipper-* | craynv-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ | f30[01]-* | f700-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* | iq2000-* \ | m32r-* | m32rle-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | mcore-* \ | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ | mips16-* \ | mips64-* | mips64el-* \ | mips64vr-* | mips64vrel-* \ | mips64orion-* | mips64orionel-* \ | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* \ | mips64vr5000-* | mips64vr5000el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ | mipsisa64-* | mipsisa64el-* \ | mipsisa64r2-* | mipsisa64r2el-* \ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ | mmix-* \ | msp430-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ | sh-* | sh[1234]-* | sh[23]e-* | sh[34]eb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc86x-* | sparclet-* | sparclite-* \ | sparcv8-* | sparcv9-* | sparcv9b-* | strongarm-* | sv1-* | sx?-* \ | tahoe-* | thumb-* \ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ | tron-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xps100-* | xscale-* | xstormy16-* \ | xtensa-* \ | ymp-* \ | z8k-*) ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; abacus) basic_machine=abacus-unknown ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amd64) basic_machine=x86_64-pc ;; amd64-*) basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; c90) basic_machine=c90-cray os=-unicos ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | j90) basic_machine=j90-cray os=-unicos ;; craynv) basic_machine=craynv-cray os=-unicosmp ;; cr16c) basic_machine=cr16c-unknown os=-elf ;; crds | unos) basic_machine=m68k-crds ;; crisv32 | crisv32-* | etraxfs*) basic_machine=crisv32-axis ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; crx) basic_machine=crx-unknown os=-elf ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; decsystem10* | dec10*) basic_machine=pdp10-dec os=-tops10 ;; decsystem20* | dec20*) basic_machine=pdp10-dec os=-tops20 ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. Should this be sysv3.2? i*86v32) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv32 ;; i*86v4*) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv4 ;; i*86v) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv ;; i*86sol2) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-solaris2 ;; i386mach) basic_machine=i386-mach os=-mach ;; i386-vsta | vsta) basic_machine=i386-unknown os=-vsta ;; iris | iris4d) basic_machine=mips-sgi case $os in -irix*) ;; *) os=-irix4 ;; esac ;; isi68 | isi) basic_machine=m68k-isi os=-sysv ;; m88k-omron*) basic_machine=m88k-omron ;; magnum | m3230) basic_machine=mips-mips os=-sysv ;; merlin) basic_machine=ns32k-utek os=-sysv ;; mingw32) basic_machine=i386-pc os=-mingw32 ;; miniframe) basic_machine=m68000-convergent ;; *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) basic_machine=m68k-atari os=-mint ;; mips3*-*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` ;; mips3*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown ;; monitor) basic_machine=m68k-rom68k os=-coff ;; morphos) basic_machine=powerpc-unknown os=-morphos ;; msdos) basic_machine=i386-pc os=-msdos ;; mvs) basic_machine=i370-ibm os=-mvs ;; ncr3000) basic_machine=i486-ncr os=-sysv4 ;; netbsd386) basic_machine=i386-unknown os=-netbsd ;; netwinder) basic_machine=armv4l-rebel os=-linux ;; news | news700 | news800 | news900) basic_machine=m68k-sony os=-newsos ;; news1000) basic_machine=m68030-sony os=-newsos ;; news-3600 | risc-news) basic_machine=mips-sony os=-newsos ;; necv70) basic_machine=v70-nec os=-sysv ;; next | m*-next ) basic_machine=m68k-next case $os in -nextstep* ) ;; -ns2*) os=-nextstep2 ;; *) os=-nextstep3 ;; esac ;; nh3000) basic_machine=m68k-harris os=-cxux ;; nh[45]000) basic_machine=m88k-harris os=-cxux ;; nindy960) basic_machine=i960-intel os=-nindy ;; mon960) basic_machine=i960-intel os=-mon960 ;; nonstopux) basic_machine=mips-compaq os=-nonstopux ;; np1) basic_machine=np1-gould ;; nsr-tandem) basic_machine=nsr-tandem ;; op50n-* | op60c-*) basic_machine=hppa1.1-oki os=-proelf ;; or32 | or32-*) basic_machine=or32-unknown os=-coff ;; os400) basic_machine=powerpc-ibm os=-os400 ;; OSE68000 | ose68000) basic_machine=m68000-ericsson os=-ose ;; os68k) basic_machine=m68k-none os=-os68k ;; pa-hitachi) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; paragon) basic_machine=i860-intel os=-osf ;; pbd) basic_machine=sparc-tti ;; pbb) basic_machine=m68k-tti ;; pc532 | pc532-*) basic_machine=ns32k-pc532 ;; pentium | p5 | k5 | k6 | nexgen | viac3) basic_machine=i586-pc ;; pentiumpro | p6 | 6x86 | athlon | athlon_*) basic_machine=i686-pc ;; pentiumii | pentium2 | pentiumiii | pentium3) basic_machine=i686-pc ;; pentium4) basic_machine=i786-pc ;; pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumpro-* | p6-* | 6x86-* | athlon-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium4-*) basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pn) basic_machine=pn-gould ;; power) basic_machine=power-ibm ;; ppc) basic_machine=powerpc-unknown ;; ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; s390 | s390-*) basic_machine=s390-ibm ;; s390x | s390x-*) basic_machine=s390x-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sb1) basic_machine=mipsisa64sb1-unknown ;; sb1el) basic_machine=mipsisa64sb1el-unknown ;; sei) basic_machine=mips-sei os=-seiux ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sh64) basic_machine=sh64-unknown ;; sparclite-wrs | simso-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; sv1) basic_machine=sv1-cray os=-unicos ;; symmetry) basic_machine=i386-sequent os=-dynix ;; t3e) basic_machine=alphaev5-cray os=-unicos ;; t90) basic_machine=t90-cray os=-unicos ;; tic54x | c54x*) basic_machine=tic54x-unknown os=-coff ;; tic55x | c55x*) basic_machine=tic55x-unknown os=-coff ;; tic6x | c6x*) basic_machine=tic6x-unknown os=-coff ;; tx39) basic_machine=mipstx39-unknown ;; tx39el) basic_machine=mipstx39el-unknown ;; toad1) basic_machine=pdp10-xkl os=-tops20 ;; tower | tower-32) basic_machine=m68k-ncr ;; tpf) basic_machine=s390x-ibm os=-tpf ;; udi29k) basic_machine=a29k-amd os=-udi ;; ultra3) basic_machine=a29k-nyu os=-sym1 ;; v810 | necv810) basic_machine=v810-nec os=-none ;; vaxv) basic_machine=vax-dec os=-sysv ;; vms) basic_machine=vax-dec os=-vms ;; vpp*|vx|vx-*) basic_machine=f301-fujitsu ;; vxworks960) basic_machine=i960-wrs os=-vxworks ;; vxworks68) basic_machine=m68k-wrs os=-vxworks ;; vxworks29k) basic_machine=a29k-wrs os=-vxworks ;; w65*) basic_machine=w65-wdc os=-none ;; w89k-*) basic_machine=hppa1.1-winbond os=-proelf ;; xps | xps100) basic_machine=xps100-honeywell ;; ymp) basic_machine=ymp-cray os=-unicos ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. It is in # some cases the only manufacturer, in others, it is the most popular. w89k) basic_machine=hppa1.1-winbond ;; op50n) basic_machine=hppa1.1-oki ;; op60c) basic_machine=hppa1.1-oki ;; romp) basic_machine=romp-ibm ;; mmix) basic_machine=mmix-knuth ;; rs6000) basic_machine=rs6000-ibm ;; vax) basic_machine=vax-dec ;; pdp10) # there are many clones, so DEC is not a safe bet basic_machine=pdp10-unknown ;; pdp11) basic_machine=pdp11-dec ;; we32k) basic_machine=we32k-att ;; sh3 | sh4 | sh[34]eb | sh[1234]le | sh[23]ele) basic_machine=sh-unknown ;; sh64) basic_machine=sh64-unknown ;; sparc | sparcv8 | sparcv9 | sparcv9b) basic_machine=sparc-sun ;; cydra) basic_machine=cydra-cydrome ;; orion) basic_machine=orion-highlevel ;; orion105) basic_machine=clipper-highlevel ;; mac | mpw | mac-mpw) basic_machine=m68k-apple ;; pmac | pmac-mpw) basic_machine=powerpc-apple ;; *-unknown) # Make sure to match an already-canonicalized machine name. ;; *) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; esac # Here we canonicalize certain aliases for manufacturers. case $basic_machine in *-digital*) basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` ;; *-commodore*) basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` ;; *) ;; esac # Decode manufacturer-specific aliases for certain operating systems. if [ x"$os" != x"" ] then case $os in # First match some system type aliases # that might get confused with valid system types. # -solaris* is a basic system type, with this one exception. -solaris1 | -solaris1.*) os=`echo $os | sed -e 's|solaris1|sunos4|'` ;; -solaris) os=-solaris2 ;; -svr4*) os=-sysv4 ;; -unixware*) os=-sysv4.2uw ;; -gnu/linux*) os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` ;; # First accept the basic system types. # The portable systems comes first. # Each alternative MUST END IN A *, to match a version number. # -sysv* is not here because it comes later, after sysvr4. -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ | -aos* \ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* | -openbsd* \ | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | -chorusos* | -chorusrdb* \ | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ | -mingw32* | -linux-gnu* | -linux-uclibc* | -uxpv* | -beos* | -mpeix* | -udk* \ | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) case $basic_machine in x86-* | i*86-*) ;; *) os=-nto$os ;; esac ;; -nto-qnx*) ;; -nto*) os=`echo $os | sed -e 's|nto|nto-qnx|'` ;; -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ | -windows* | -osx | -abug | -netware* | -os9* | -beos* \ | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) ;; -mac*) os=`echo $os | sed -e 's|mac|macos|'` ;; -linux-dietlibc) os=-linux-dietlibc ;; -linux*) os=`echo $os | sed -e 's|linux|linux-gnu|'` ;; -sunos5*) os=`echo $os | sed -e 's|sunos5|solaris2|'` ;; -sunos6*) os=`echo $os | sed -e 's|sunos6|solaris3|'` ;; -opened*) os=-openedition ;; -os400*) os=-os400 ;; -wince*) os=-wince ;; -osfrose*) os=-osfrose ;; -osf*) os=-osf ;; -utek*) os=-bsd ;; -dynix*) os=-bsd ;; -acis*) os=-aos ;; -atheos*) os=-atheos ;; -syllable*) os=-syllable ;; -386bsd) os=-bsd ;; -ctix* | -uts*) os=-sysv ;; -nova*) os=-rtmk-nova ;; -ns2 ) os=-nextstep2 ;; -nsk*) os=-nsk ;; # Preserve the version number of sinix5. -sinix5.*) os=`echo $os | sed -e 's|sinix|sysv|'` ;; -sinix*) os=-sysv4 ;; -tpf*) os=-tpf ;; -triton*) os=-sysv3 ;; -oss*) os=-sysv3 ;; -svr4) os=-sysv4 ;; -svr3) os=-sysv3 ;; -sysvr4) os=-sysv4 ;; # This must come after -sysvr4. -sysv*) ;; -ose*) os=-ose ;; -es1800*) os=-ose ;; -xenix) os=-xenix ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) os=-mint ;; -aros*) os=-aros ;; -kaos*) os=-kaos ;; -none) ;; *) # Get rid of the `-' at the beginning of $os. os=`echo $os | sed 's/[^-]*-//'` echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 exit 1 ;; esac else # Here we handle the default operating systems that come with various machines. # The value should be what the vendor currently ships out the door with their # machine or put another way, the most popular os provided with the machine. # Note that if you're going to try to match "-MANUFACTURER" here (say, # "-sun"), then you have to tell the case statement up towards the top # that MANUFACTURER isn't an operating system. Otherwise, code above # will signal an error saying that MANUFACTURER isn't an operating # system, and we'll never get to this point. case $basic_machine in *-acorn) os=-riscix1.2 ;; arm*-rebel) os=-linux ;; arm*-semi) os=-aout ;; c4x-* | tic4x-*) os=-coff ;; # This must come before the *-dec entry. pdp10-*) os=-tops20 ;; pdp11-*) os=-none ;; *-dec | vax-*) os=-ultrix4.2 ;; m68*-apollo) os=-domain ;; i386-sun) os=-sunos4.0.2 ;; m68000-sun) os=-sunos3 # This also exists in the configure program, but was not the # default. # os=-sunos4 ;; m68*-cisco) os=-aout ;; mips*-cisco) os=-elf ;; mips*-*) os=-elf ;; or32-*) os=-coff ;; *-tti) # must be before sparc entry or we get the wrong os. os=-sysv3 ;; sparc-* | *-sun) os=-sunos4.1.1 ;; *-be) os=-beos ;; *-ibm) os=-aix ;; *-knuth) os=-mmixware ;; *-wec) os=-proelf ;; *-winbond) os=-proelf ;; *-oki) os=-proelf ;; *-hp) os=-hpux ;; *-hitachi) os=-hiux ;; i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) os=-sysv ;; *-cbm) os=-amigaos ;; *-dg) os=-dgux ;; *-dolphin) os=-sysv3 ;; m68k-ccur) os=-rtu ;; m88k-omron*) os=-luna ;; *-next ) os=-nextstep ;; *-sequent) os=-ptx ;; *-crds) os=-unos ;; *-ns) os=-genix ;; i370-*) os=-mvs ;; *-next) os=-nextstep3 ;; *-gould) os=-sysv ;; *-highlevel) os=-bsd ;; *-encore) os=-bsd ;; *-sgi) os=-irix ;; *-siemens) os=-sysv4 ;; *-masscomp) os=-rtu ;; f30[01]-fujitsu | f700-fujitsu) os=-uxpv ;; *-rom68k) os=-coff ;; *-*bug) os=-coff ;; *-apple) os=-macos ;; *-atari*) os=-mint ;; *) os=-none ;; esac fi # Here we handle the case where we know the os, and the CPU type, but not the # manufacturer. We pick the logical manufacturer. vendor=unknown case $basic_machine in *-unknown) case $os in -riscix*) vendor=acorn ;; -sunos*) vendor=sun ;; -aix*) vendor=ibm ;; -beos*) vendor=be ;; -hpux*) vendor=hp ;; -mpeix*) vendor=hp ;; -hiux*) vendor=hitachi ;; -unos*) vendor=crds ;; -dgux*) vendor=dg ;; -luna*) vendor=omron ;; -genix*) vendor=ns ;; -mvs* | -opened*) vendor=ibm ;; -os400*) vendor=ibm ;; -ptx*) vendor=sequent ;; -tpf*) vendor=ibm ;; -vxsim* | -vxworks* | -windiss*) vendor=wrs ;; -aux*) vendor=apple ;; -hms*) vendor=hitachi ;; -mpw* | -macos*) vendor=apple ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) vendor=atari ;; -vos*) vendor=stratus ;; esac basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` ;; esac echo $basic_machine$os exit 0 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: gputils-0.13.7/include/0000777000175000017500000000000011156521334011722 500000000000000gputils-0.13.7/include/ansidecl.h0000644000175000017500000002445411156313063013600 00000000000000/* ANSI and traditional C compatability macros Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU C Library. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* ANSI and traditional C compatibility macros ANSI C is assumed if __STDC__ is #defined. Macro ANSI C definition Traditional C definition ----- ---- - ---------- ----------- - ---------- ANSI_PROTOTYPES 1 not defined PTR `void *' `char *' PTRCONST `void *const' `char *' LONG_DOUBLE `long double' `double' const not defined `' volatile not defined `' signed not defined `' VA_START(ap, var) va_start(ap, var) va_start(ap) Note that it is safe to write "void foo();" indicating a function with no return value, in all K+R compilers we have been able to test. For declaring functions with prototypes, we also provide these: PARAMS ((prototype)) -- for functions which take a fixed number of arguments. Use this when declaring the function. When defining the function, write a K+R style argument list. For example: char *strcpy PARAMS ((char *dest, char *source)); ... char * strcpy (dest, source) char *dest; char *source; { ... } VPARAMS ((prototype, ...)) -- for functions which take a variable number of arguments. Use PARAMS to declare the function, VPARAMS to define it. For example: int printf PARAMS ((const char *format, ...)); ... int printf VPARAMS ((const char *format, ...)) { ... } For writing functions which take variable numbers of arguments, we also provide the VA_OPEN, VA_CLOSE, and VA_FIXEDARG macros. These hide the differences between K+R and C89 more thoroughly than the simple VA_START() macro mentioned above. VA_OPEN and VA_CLOSE are used *instead of* va_start and va_end. Immediately after VA_OPEN, put a sequence of VA_FIXEDARG calls corresponding to the list of fixed arguments. Then use va_arg normally to get the variable arguments, or pass your va_list object around. You do not declare the va_list yourself; VA_OPEN does it for you. Here is a complete example: int printf VPARAMS ((const char *format, ...)) { int result; VA_OPEN (ap, format); VA_FIXEDARG (ap, const char *, format); result = vfprintf (stdout, format, ap); VA_CLOSE (ap); return result; } You can declare variables either before or after the VA_OPEN, VA_FIXEDARG sequence. Also, VA_OPEN and VA_CLOSE are the beginning and end of a block. They must appear at the same nesting level, and any variables declared after VA_OPEN go out of scope at VA_CLOSE. Unfortunately, with a K+R compiler, that includes the argument list. You can have multiple instances of VA_OPEN/VA_CLOSE pairs in a single function in case you need to traverse the argument list more than once. For ease of writing code which uses GCC extensions but needs to be portable to other compilers, we provide the GCC_VERSION macro that simplifies testing __GNUC__ and __GNUC_MINOR__ together, and various wrappers around __attribute__. Also, __extension__ will be #defined to nothing if it doesn't work. See below. This header also defines a lot of obsolete macros: CONST, VOLATILE, SIGNED, PROTO, EXFUN, DEFUN, DEFUN_VOID, AND, DOTS, NOARGS. Don't use them. */ #ifndef _ANSIDECL_H #define _ANSIDECL_H 1 /* Every source file includes this file, so they will all get the switch for lint. */ /* LINTLIBRARY */ /* Using MACRO(x,y) in cpp #if conditionals does not work with some older preprocessors. Thus we can't define something like this: #define HAVE_GCC_VERSION(MAJOR, MINOR) \ (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) and then test "#if HAVE_GCC_VERSION(2,7)". So instead we use the macro below and test it against specific values. */ /* This macro simplifies testing whether we are using gcc, and if it is of a particular minimum version. (Both major & minor numbers are significant.) This macro will evaluate to 0 if we are not using gcc at all. */ #ifndef GCC_VERSION #define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) #endif /* GCC_VERSION */ #if defined (__STDC__) || defined (_AIX) || (defined (__mips) && defined (_SYSTYPE_SVR4)) || defined(_WIN32) || (defined(__alpha) && defined(__cplusplus)) /* All known AIX compilers implement these things (but don't always define __STDC__). The RISC/OS MIPS compiler defines these things in SVR4 mode, but does not define __STDC__. */ /* eraxxon@alumni.rice.edu: The Compaq C++ compiler, unlike many other C++ compilers, does not define __STDC__, though it acts as if this was so. (Verified versions: 5.7, 6.2, 6.3, 6.5) */ #define ANSI_PROTOTYPES 1 #define PTR void * #define PTRCONST void *const #define LONG_DOUBLE long double #define PARAMS(ARGS) ARGS #define VPARAMS(ARGS) ARGS #define VA_START(VA_LIST, VAR) va_start(VA_LIST, VAR) /* variadic function helper macros */ /* "struct Qdmy" swallows the semicolon after VA_OPEN/VA_FIXEDARG's use without inhibiting further decls and without declaring an actual variable. */ #define VA_OPEN(AP, VAR) { va_list AP; va_start(AP, VAR); { struct Qdmy #define VA_CLOSE(AP) } va_end(AP); } #define VA_FIXEDARG(AP, T, N) struct Qdmy #undef const #undef volatile #undef signed /* inline requires special treatment; it's in C99, and GCC >=2.7 supports it too, but it's not in C89. */ #undef inline #if __STDC_VERSION__ > 199901L /* it's a keyword */ #else # if GCC_VERSION >= 2007 # define inline __inline__ /* __inline__ prevents -pedantic warnings */ # else # define inline /* nothing */ # endif #endif /* These are obsolete. Do not use. */ #ifndef IN_GCC #define CONST const #define VOLATILE volatile #define SIGNED signed #define PROTO(type, name, arglist) type name arglist #define EXFUN(name, proto) name proto #define DEFUN(name, arglist, args) name(args) #define DEFUN_VOID(name) name(void) #define AND , #define DOTS , ... #define NOARGS void #endif /* ! IN_GCC */ #else /* Not ANSI C. */ #undef ANSI_PROTOTYPES #define PTR char * #define PTRCONST PTR #define LONG_DOUBLE double #define PARAMS(args) () #define VPARAMS(args) (va_alist) va_dcl #define VA_START(va_list, var) va_start(va_list) #define VA_OPEN(AP, VAR) { va_list AP; va_start(AP); { struct Qdmy #define VA_CLOSE(AP) } va_end(AP); } #define VA_FIXEDARG(AP, TYPE, NAME) TYPE NAME = va_arg(AP, TYPE) /* some systems define these in header files for non-ansi mode */ #undef const #undef volatile #undef signed #undef inline #define const #define volatile #define signed #define inline #ifndef IN_GCC #define CONST #define VOLATILE #define SIGNED #define PROTO(type, name, arglist) type name () #define EXFUN(name, proto) name() #define DEFUN(name, arglist, args) name arglist args; #define DEFUN_VOID(name) name() #define AND ; #define DOTS #define NOARGS #endif /* ! IN_GCC */ #endif /* ANSI C. */ /* Define macros for some gcc attributes. This permits us to use the macros freely, and know that they will come into play for the version of gcc in which they are supported. */ #if (GCC_VERSION < 2007) # define __attribute__(x) #endif /* Attribute __malloc__ on functions was valid as of gcc 2.96. */ #ifndef ATTRIBUTE_MALLOC # if (GCC_VERSION >= 2096) # define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) # else # define ATTRIBUTE_MALLOC # endif /* GNUC >= 2.96 */ #endif /* ATTRIBUTE_MALLOC */ /* Attributes on labels were valid as of gcc 2.93. */ #ifndef ATTRIBUTE_UNUSED_LABEL # if (GCC_VERSION >= 2093) # define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED # else # define ATTRIBUTE_UNUSED_LABEL # endif /* GNUC >= 2.93 */ #endif /* ATTRIBUTE_UNUSED_LABEL */ #ifndef ATTRIBUTE_UNUSED #define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) #endif /* ATTRIBUTE_UNUSED */ #ifndef ATTRIBUTE_NORETURN #define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) #endif /* ATTRIBUTE_NORETURN */ /* Attribute `nonnull' was valid as of gcc 3.3. */ #ifndef ATTRIBUTE_NONNULL # if (GCC_VERSION >= 3003) # define ATTRIBUTE_NONNULL(m) __attribute__ ((__nonnull__ (m))) # else # define ATTRIBUTE_NONNULL(m) # endif /* GNUC >= 3.3 */ #endif /* ATTRIBUTE_NONNULL */ /* Use ATTRIBUTE_PRINTF when the format specifier must not be NULL. This was the case for the `printf' format attribute by itself before GCC 3.3, but as of 3.3 we need to add the `nonnull' attribute to retain this behavior. */ #ifndef ATTRIBUTE_PRINTF #define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) ATTRIBUTE_NONNULL(m) #define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) #define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) #define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) #define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) #define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) #endif /* ATTRIBUTE_PRINTF */ /* Use ATTRIBUTE_NULL_PRINTF when the format specifier may be NULL. A NULL format specifier was allowed as of gcc 3.3. */ #ifndef ATTRIBUTE_NULL_PRINTF # if (GCC_VERSION >= 3003) # define ATTRIBUTE_NULL_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) # else # define ATTRIBUTE_NULL_PRINTF(m, n) # endif /* GNUC >= 3.3 */ # define ATTRIBUTE_NULL_PRINTF_1 ATTRIBUTE_NULL_PRINTF(1, 2) # define ATTRIBUTE_NULL_PRINTF_2 ATTRIBUTE_NULL_PRINTF(2, 3) # define ATTRIBUTE_NULL_PRINTF_3 ATTRIBUTE_NULL_PRINTF(3, 4) # define ATTRIBUTE_NULL_PRINTF_4 ATTRIBUTE_NULL_PRINTF(4, 5) # define ATTRIBUTE_NULL_PRINTF_5 ATTRIBUTE_NULL_PRINTF(5, 6) #endif /* ATTRIBUTE_NULL_PRINTF */ /* We use __extension__ in some places to suppress -pedantic warnings about GCC extensions. This feature didn't work properly before gcc 2.8. */ #if GCC_VERSION < 2008 #define __extension__ #endif #endif /* ansidecl.h */ gputils-0.13.7/include/libiberty.h0000644000175000017500000002654411156313063014005 00000000000000/* Function declarations for libiberty. Copyright 2001, 2002 Free Software Foundation, Inc. Note - certain prototypes declared in this header file are for functions whoes implementation copyright does not belong to the FSF. Those prototypes are present in this file for reference purposes only and their presence in this file should not construed as an indication of ownership by the FSF of the implementation of those functions in any way or form whatsoever. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. Written by Cygnus Support, 1994. The libiberty library provides a number of functions which are missing on some operating systems. We do not declare those here, to avoid conflicts with the system header files on operating systems that do support those functions. In this file we only declare those functions which are specific to libiberty. */ #ifndef LIBIBERTY_H #define LIBIBERTY_H #ifdef __cplusplus extern "C" { #endif #include "ansidecl.h" #ifdef ANSI_PROTOTYPES /* Get a definition for size_t. */ #include /* Get a definition for va_list. */ #include #endif /* Build an argument vector from a string. Allocates memory using malloc. Use freeargv to free the vector. */ extern char **buildargv PARAMS ((const char *)) ATTRIBUTE_MALLOC; /* Free a vector returned by buildargv. */ extern void freeargv PARAMS ((char **)); /* Duplicate an argument vector. Allocates memory using malloc. Use freeargv to free the vector. */ extern char **dupargv PARAMS ((char **)) ATTRIBUTE_MALLOC; /* Return the last component of a path name. Note that we can't use a prototype here because the parameter is declared inconsistently across different systems, sometimes as "char *" and sometimes as "const char *" */ /* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is undefined, we haven't run the autoconf check so provide the declaration without arguments. If it is 0, we checked and failed to find the declaration so provide a fully prototyped one. If it is 1, we found it so don't provide any declaration at all. */ #if !HAVE_DECL_BASENAME #if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined(__NetBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || defined (HAVE_DECL_BASENAME) extern char *basename PARAMS ((const char *)); #else extern char *basename (); #endif #endif /* A well-defined basename () that is always compiled in. */ extern const char *lbasename PARAMS ((const char *)); /* A well-defined realpath () that is always compiled in. */ extern char *lrealpath PARAMS ((const char *)); /* Concatenate an arbitrary number of strings. You must pass NULL as the last argument of this function, to terminate the list of strings. Allocates memory using xmalloc. */ extern char *concat PARAMS ((const char *, ...)) ATTRIBUTE_MALLOC; /* Concatenate an arbitrary number of strings. You must pass NULL as the last argument of this function, to terminate the list of strings. Allocates memory using xmalloc. The first argument is not one of the strings to be concatenated, but if not NULL is a pointer to be freed after the new string is created, similar to the way xrealloc works. */ extern char *reconcat PARAMS ((char *, const char *, ...)) ATTRIBUTE_MALLOC; /* Determine the length of concatenating an arbitrary number of strings. You must pass NULL as the last argument of this function, to terminate the list of strings. */ extern unsigned long concat_length PARAMS ((const char *, ...)); /* Concatenate an arbitrary number of strings into a SUPPLIED area of memory. You must pass NULL as the last argument of this function, to terminate the list of strings. The supplied memory is assumed to be large enough. */ extern char *concat_copy PARAMS ((char *, const char *, ...)); /* Concatenate an arbitrary number of strings into a GLOBAL area of memory. You must pass NULL as the last argument of this function, to terminate the list of strings. The supplied memory is assumed to be large enough. */ extern char *concat_copy2 PARAMS ((const char *, ...)); /* This is the global area used by concat_copy2. */ extern char *libiberty_concat_ptr; /* Concatenate an arbitrary number of strings. You must pass NULL as the last argument of this function, to terminate the list of strings. Allocates memory using alloca. The arguments are evaluated twice! */ #define ACONCAT(ACONCAT_PARAMS) \ (libiberty_concat_ptr = alloca (concat_length ACONCAT_PARAMS + 1), \ concat_copy2 ACONCAT_PARAMS) /* Check whether two file descriptors refer to the same file. */ extern int fdmatch PARAMS ((int fd1, int fd2)); /* Get the working directory. The result is cached, so don't call chdir() between calls to getpwd(). */ extern char * getpwd PARAMS ((void)); /* Get the amount of time the process has run, in microseconds. */ extern long get_run_time PARAMS ((void)); /* Generate a relocated path to some installation directory. Allocates return value using malloc. */ extern char *make_relative_prefix PARAMS ((const char *, const char *, const char *)); /* Choose a temporary directory to use for scratch files. */ extern char *choose_temp_base PARAMS ((void)) ATTRIBUTE_MALLOC; /* Return a temporary file name or NULL if unable to create one. */ extern char *make_temp_file PARAMS ((const char *)) ATTRIBUTE_MALLOC; /* Allocate memory filled with spaces. Allocates using malloc. */ extern const char *spaces PARAMS ((int count)); /* Return the maximum error number for which strerror will return a string. */ extern int errno_max PARAMS ((void)); /* Return the name of an errno value (e.g., strerrno (EINVAL) returns "EINVAL"). */ extern const char *strerrno PARAMS ((int)); /* Given the name of an errno value, return the value. */ extern int strtoerrno PARAMS ((const char *)); /* ANSI's strerror(), but more robust. */ extern char *xstrerror PARAMS ((int)); /* Return the maximum signal number for which strsignal will return a string. */ extern int signo_max PARAMS ((void)); /* Return a signal message string for a signal number (e.g., strsignal (SIGHUP) returns something like "Hangup"). */ /* This is commented out as it can conflict with one in system headers. We still document its existence though. */ /*extern const char *strsignal PARAMS ((int));*/ /* Return the name of a signal number (e.g., strsigno (SIGHUP) returns "SIGHUP"). */ extern const char *strsigno PARAMS ((int)); /* Given the name of a signal, return its number. */ extern int strtosigno PARAMS ((const char *)); /* Register a function to be run by xexit. Returns 0 on success. */ extern int xatexit PARAMS ((void (*fn) (void))); /* Exit, calling all the functions registered with xatexit. */ extern void xexit PARAMS ((int status)) ATTRIBUTE_NORETURN; /* Set the program name used by xmalloc. */ extern void xmalloc_set_program_name PARAMS ((const char *)); /* Report an allocation failure. */ extern void xmalloc_failed PARAMS ((size_t)) ATTRIBUTE_NORETURN; /* Allocate memory without fail. If malloc fails, this will print a message to stderr (using the name set by xmalloc_set_program_name, if any) and then call xexit. */ extern PTR xmalloc PARAMS ((size_t)) ATTRIBUTE_MALLOC; /* Reallocate memory without fail. This works like xmalloc. Note, realloc type functions are not suitable for attribute malloc since they may return the same address across multiple calls. */ extern PTR xrealloc PARAMS ((PTR, size_t)); /* Allocate memory without fail and set it to zero. This works like xmalloc. */ extern PTR xcalloc PARAMS ((size_t, size_t)) ATTRIBUTE_MALLOC; /* Copy a string into a memory buffer without fail. */ extern char *xstrdup PARAMS ((const char *)) ATTRIBUTE_MALLOC; /* Copy an existing memory buffer to a new memory buffer without fail. */ extern PTR xmemdup PARAMS ((const PTR, size_t, size_t)) ATTRIBUTE_MALLOC; /* Physical memory routines. Return values are in BYTES. */ extern double physmem_total PARAMS ((void)); extern double physmem_available PARAMS ((void)); /* hex character manipulation routines */ #define _hex_array_size 256 #define _hex_bad 99 extern const unsigned char _hex_value[_hex_array_size]; extern void hex_init PARAMS ((void)); #define hex_p(c) (hex_value (c) != _hex_bad) /* If you change this, note well: Some code relies on side effects in the argument being performed exactly once. */ #define hex_value(c) ((unsigned int) _hex_value[(unsigned char) (c)]) /* Definitions used by the pexecute routine. */ #define PEXECUTE_FIRST 1 #define PEXECUTE_LAST 2 #define PEXECUTE_ONE (PEXECUTE_FIRST + PEXECUTE_LAST) #define PEXECUTE_SEARCH 4 #define PEXECUTE_VERBOSE 8 /* Execute a program. */ extern int pexecute PARAMS ((const char *, char * const *, const char *, const char *, char **, char **, int)); /* Wait for pexecute to finish. */ extern int pwait PARAMS ((int, int *, int)); #if !HAVE_DECL_ASPRINTF /* Like sprintf but provides a pointer to malloc'd storage, which must be freed by the caller. */ extern int asprintf PARAMS ((char **, const char *, ...)) ATTRIBUTE_PRINTF_2; #endif #if !HAVE_DECL_VASPRINTF /* Like vsprintf but provides a pointer to malloc'd storage, which must be freed by the caller. */ extern int vasprintf PARAMS ((char **, const char *, va_list)) ATTRIBUTE_PRINTF(2,0); #endif #define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) /* Drastically simplified alloca configurator. If we're using GCC, we use __builtin_alloca; otherwise we use the C alloca. The C alloca is always available. You can override GCC by defining USE_C_ALLOCA yourself. The canonical autoconf macro C_ALLOCA is also set/unset as it is often used to indicate whether code needs to call alloca(0). */ extern PTR C_alloca PARAMS ((size_t)) ATTRIBUTE_MALLOC; #undef alloca #if GCC_VERSION >= 2000 && !defined USE_C_ALLOCA # define alloca(x) __builtin_alloca(x) # undef C_ALLOCA # define ASTRDUP(X) \ (__extension__ ({ const char *const libiberty_optr = (X); \ const unsigned long libiberty_len = strlen (libiberty_optr) + 1; \ char *const libiberty_nptr = alloca (libiberty_len); \ (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len); })) #else # define alloca(x) C_alloca(x) # undef USE_C_ALLOCA # define USE_C_ALLOCA 1 # undef C_ALLOCA # define C_ALLOCA 1 extern const char *libiberty_optr; extern char *libiberty_nptr; extern unsigned long libiberty_len; # define ASTRDUP(X) \ (libiberty_optr = (X), \ libiberty_len = strlen (libiberty_optr) + 1, \ libiberty_nptr = alloca (libiberty_len), \ (char *) memcpy (libiberty_nptr, libiberty_optr, libiberty_len)) #endif #ifdef __cplusplus } #endif #endif /* ! defined (LIBIBERTY_H) */ gputils-0.13.7/include/stdhdr.h0000644000175000017500000000332411156313063013277 00000000000000/* standard defines and includes Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __STDHDR_H__ #define __STDHDR_H__ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #include #ifdef HAVE_STDLIB_H #include #endif #ifndef EXIT_SUCCESS #define EXIT_SUCCESS 0 #define EXIT_FAILURE 1 #endif #ifdef HAVE_UNISTD_H #include #endif #include "getopt.h" #ifndef HAVE_STDLIB_H #ifdef HAVE_MALLOC_H #include #endif #endif #ifndef HAVE_STRCASECMP #ifdef HAVE_STRICMP #define strcasecmp stricmp #endif #endif #if defined(HAVE_STRING_H) #include #elif defined(HAVE_STRINGS_H) #include #endif #include #include #include #ifdef HAVE_DOS_BASED_FILE_SYSTEM #define UNIX_PATH_CHAR '/' #define PATH_CHAR '\\' #define COPY_CHAR "\\" #else #define PATH_CHAR '/' #define COPY_CHAR "/" #endif #define GPUTILS_COPYRIGHT_STRING "Copyright (c) 1998-2005 gputils project" #endif gputils-0.13.7/include/getopt.h0000644000175000017500000001173511156313063013316 00000000000000/* Declarations for getopt. Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000 Free Software Foundation, Inc. NOTE: The canonical source of this file is maintained with the GNU C Library. Bugs can be reported to bug-glibc@gnu.org. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _GETOPT_H #define _GETOPT_H 1 #ifdef __cplusplus extern "C" { #endif /* For communication from `getopt' to the caller. When `getopt' finds an option that takes an argument, the argument value is returned here. Also, when `ordering' is RETURN_IN_ORDER, each non-option ARGV-element is returned here. */ extern char *optarg; /* Index in ARGV of the next element to be scanned. This is used for communication to and from the caller and for communication between successive calls to `getopt'. On entry to `getopt', zero means this is the first call; initialize. When `getopt' returns -1, this is the index of the first of the non-option elements that the caller should itself scan. Otherwise, `optind' communicates from one call to the next how much of ARGV has been scanned so far. */ extern int optind; /* Callers store zero here to inhibit the error message `getopt' prints for unrecognized options. */ extern int opterr; /* Set to an option character which was unrecognized. */ extern int optopt; /* Describe the long-named options requested by the application. The LONG_OPTIONS argument to getopt_long or getopt_long_only is a vector of `struct option' terminated by an element containing a name which is zero. The field `has_arg' is: no_argument (or 0) if the option does not take an argument, required_argument (or 1) if the option requires an argument, optional_argument (or 2) if the option takes an optional argument. If the field `flag' is not NULL, it points to a variable that is set to the value given in the field `val' when the option is found, but left unchanged if the option is not found. To have a long-named option do something other than set an `int' to a compiled-in constant, such as set a value from `optarg', set the option's `flag' field to zero and its `val' field to a nonzero value (the equivalent single-letter option character, if there is one). For long options that have a zero `flag' field, `getopt' returns the contents of the `val' field. */ struct option { #if defined (__STDC__) && __STDC__ const char *name; #else char *name; #endif /* has_arg can't be an enum because some compilers complain about type mismatches in all the code that assumes it is an int. */ int has_arg; int *flag; int val; }; /* Names for the values of the `has_arg' field of `struct option'. */ #define no_argument 0 #define required_argument 1 #define optional_argument 2 #if defined (__STDC__) && __STDC__ /* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is undefined, we haven't run the autoconf check so provide the declaration without arguments. If it is 0, we checked and failed to find the declaration so provide a fully prototyped one. If it is 1, we found it so don't provide any declaration at all. */ #if defined (__GNU_LIBRARY__) || (defined (HAVE_DECL_GETOPT) && !HAVE_DECL_GETOPT) /* Many other libraries have conflicting prototypes for getopt, with differences in the consts, in stdlib.h. To avoid compilation errors, only prototype getopt for the GNU C library. */ extern int getopt (int argc, char *const *argv, const char *shortopts); #else /* not __GNU_LIBRARY__ */ # if !defined (HAVE_DECL_GETOPT) && !defined (__cplusplus) extern int getopt (); # endif #endif /* __GNU_LIBRARY__ */ extern int getopt_long (int argc, char *const *argv, const char *shortopts, const struct option *longopts, int *longind); extern int getopt_long_only (int argc, char *const *argv, const char *shortopts, const struct option *longopts, int *longind); /* Internal only. Users should not call this directly. */ extern int _getopt_internal (int argc, char *const *argv, const char *shortopts, const struct option *longopts, int *longind, int long_only); #else /* not __STDC__ */ extern int getopt (); extern int getopt_long (); extern int getopt_long_only (); extern int _getopt_internal (); #endif /* __STDC__ */ #ifdef __cplusplus } #endif #endif /* getopt.h */ gputils-0.13.7/INSTALL0000644000175000017500000002202411156313233011241 00000000000000Copyright 1994, 1995, 1996, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. This file is free documentation; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. Basic Installation ================== These are generic installation instructions. The `configure' shell script attempts to guess correct values for various system-dependent variables used during compilation. It uses those values to create a `Makefile' in each directory of the package. It may also create one or more `.h' files containing system-dependent definitions. Finally, it creates a shell script `config.status' that you can run in the future to recreate the current configuration, and a file `config.log' containing compiler output (useful mainly for debugging `configure'). It can also use an optional file (typically called `config.cache' and enabled with `--cache-file=config.cache' or simply `-C') that saves the results of its tests to speed up reconfiguring. (Caching is disabled by default to prevent problems with accidental use of stale cache files.) If you need to do unusual things to compile the package, please try to figure out how `configure' could check whether to do them, and mail diffs or instructions to the address given in the `README' so they can be considered for the next release. If you are using the cache, and at some point `config.cache' contains results you don't want to keep, you may remove or edit it. The file `configure.ac' (or `configure.in') is used to create `configure' by a program called `autoconf'. You only need `configure.ac' if you want to change it or regenerate `configure' using a newer version of `autoconf'. The simplest way to compile this package is: 1. `cd' to the directory containing the package's source code and type `./configure' to configure the package for your system. If you're using `csh' on an old version of System V, you might need to type `sh ./configure' instead to prevent `csh' from trying to execute `configure' itself. Running `configure' takes awhile. While running, it prints some messages telling which features it is checking for. 2. Type `make' to compile the package. 3. Optionally, type `make check' to run any self-tests that come with the package. 4. Type `make install' to install the programs and any data files and documentation. 5. You can remove the program binaries and object files from the source code directory by typing `make clean'. To also remove the files that `configure' created (so you can compile the package for a different kind of computer), type `make distclean'. There is also a `make maintainer-clean' target, but that is intended mainly for the package's developers. If you use it, you may have to get all sorts of other programs in order to regenerate files that came with the distribution. Compilers and Options ===================== Some systems require unusual options for compilation or linking that the `configure' script does not know about. Run `./configure --help' for details on some of the pertinent environment variables. You can give `configure' initial values for configuration parameters by setting variables in the command line or in the environment. Here is an example: ./configure CC=c89 CFLAGS=-O2 LIBS=-lposix *Note Defining Variables::, for more details. Compiling For Multiple Architectures ==================================== You can compile the package for more than one kind of computer at the same time, by placing the object files for each architecture in their own directory. To do this, you must use a version of `make' that supports the `VPATH' variable, such as GNU `make'. `cd' to the directory where you want the object files and executables to go and run the `configure' script. `configure' automatically checks for the source code in the directory that `configure' is in and in `..'. If you have to use a `make' that does not support the `VPATH' variable, you have to compile the package for one architecture at a time in the source code directory. After you have installed the package for one architecture, use `make distclean' before reconfiguring for another architecture. Installation Names ================== By default, `make install' will install the package's files in `/usr/local/bin', `/usr/local/man', etc. You can specify an installation prefix other than `/usr/local' by giving `configure' the option `--prefix=PATH'. You can specify separate installation prefixes for architecture-specific files and architecture-independent files. If you give `configure' the option `--exec-prefix=PATH', the package will use PATH as the prefix for installing programs and libraries. Documentation and other data files will still use the regular prefix. In addition, if you use an unusual directory layout you can give options like `--bindir=PATH' to specify different values for particular kinds of files. Run `configure --help' for a list of the directories you can set and what kinds of files go in them. If the package supports it, you can cause programs to be installed with an extra prefix or suffix on their names by giving `configure' the option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. Optional Features ================= Some packages pay attention to `--enable-FEATURE' options to `configure', where FEATURE indicates an optional part of the package. They may also pay attention to `--with-PACKAGE' options, where PACKAGE is something like `gnu-as' or `x' (for the X Window System). The `README' should mention any `--enable-' and `--with-' options that the package recognizes. For packages that use the X Window System, `configure' can usually find the X include and library files automatically, but if it doesn't, you can use the `configure' options `--x-includes=DIR' and `--x-libraries=DIR' to specify their locations. Specifying the System Type ========================== There may be some features `configure' cannot figure out automatically, but needs to determine by the type of machine the package will run on. Usually, assuming the package is built to be run on the _same_ architectures, `configure' can figure that out, but if it prints a message saying it cannot guess the machine type, give it the `--build=TYPE' option. TYPE can either be a short name for the system type, such as `sun4', or a canonical name which has the form: CPU-COMPANY-SYSTEM where SYSTEM can have one of these forms: OS KERNEL-OS See the file `config.sub' for the possible values of each field. If `config.sub' isn't included in this package, then this package doesn't need to know the machine type. If you are _building_ compiler tools for cross-compiling, you should use the `--target=TYPE' option to select the type of system they will produce code for. If you want to _use_ a cross compiler, that generates code for a platform different from the build platform, you should specify the "host" platform (i.e., that on which the generated programs will eventually be run) with `--host=TYPE'. Sharing Defaults ================ If you want to set default values for `configure' scripts to share, you can create a site shell script called `config.site' that gives default values for variables like `CC', `cache_file', and `prefix'. `configure' looks for `PREFIX/share/config.site' if it exists, then `PREFIX/etc/config.site' if it exists. Or, you can set the `CONFIG_SITE' environment variable to the location of the site script. A warning: not all `configure' scripts look for a site script. Defining Variables ================== Variables not defined in a site shell script can be set in the environment passed to `configure'. However, some packages may run configure again during the build, and the customized values of these variables may be lost. In order to avoid this problem, you should set them in the `configure' command line, using `VAR=value'. For example: ./configure CC=/usr/local2/bin/gcc will cause the specified gcc to be used as the C compiler (unless it is overridden in the site shell script). `configure' Invocation ====================== `configure' recognizes the following options to control how it operates. `--help' `-h' Print a summary of the options to `configure', and exit. `--version' `-V' Print the version of Autoconf used to generate the `configure' script, and exit. `--cache-file=FILE' Enable the cache: use and save the results of the tests in FILE, traditionally `config.cache'. FILE defaults to `/dev/null' to disable caching. `--config-cache' `-C' Alias for `--cache-file=config.cache'. `--quiet' `--silent' `-q' Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). `--srcdir=DIR' Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. `configure' also accepts some other, not widely useful, options. Run `configure --help' for more details. gputils-0.13.7/header/0000777000175000017500000000000011156521340011524 500000000000000gputils-0.13.7/header/p18f2585.inc0000644000175000017500000041126211156521302013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2585 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2585 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2585 ; 2. LIST directive in the source file ; LIST P=PIC18F2585 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2585 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXBODBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXB0DBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB4'-H'0FB7' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c773.inc0000644000175000017500000003364511156313161013160 00000000000000 LIST ; P16C773.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C773 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C773 ; 2. LIST directive in the source file ; LIST P=PIC16C773 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 08/07/98 Initial Release ;1.01 25Jan99 Fixed LVVx bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C773 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' REFCON EQU H'009B' LVDCON EQU H'009C' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- LVDIF EQU H'0007' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- LVDIE EQU H'0007' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- REFCON Bits -------------------------------------------------------- VRHEN EQU H'0007' VRLEN EQU H'0006' VRHOEN EQU H'0005' VRLOEN EQU H'0004' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09' __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A', H'9D' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CCF' _CP_75 EQU H'1DDF' _CP_50 EQU H'2EEF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c558.inc0000644000175000017500000001075211156313161013153 00000000000000 LIST ; P16C558.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C558 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C558 ; 2. LIST directive in the source file ; LIST P=PIC16C558 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/22/96 Initial Creation ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C558 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PCON EQU H'008E' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'07'-H'09', H'0C'-H'1F' __BADRAM H'87'-H'89', H'8C'-H'8D', H'8F'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f2331.inc0000644000175000017500000011415411156521301013225 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2331 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2331 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2331 ; 2. LIST directive in the source file ; LIST P=PIC18F2331 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2331 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- DFLTCON EQU H'0F60' CAP3CON EQU H'0F61' CAP2CON EQU H'0F62' CAP1CON EQU H'0F63' CAP3BUFL EQU H'0F64' MAXCNTL EQU H'0F64' CAP3BUFH EQU H'0F65' MAXCNTH EQU H'0F65' CAP2BUFL EQU H'0F66' POSCNTL EQU H'0F66' CAP2BUFH EQU H'0F67' POSCNTH EQU H'0F67' CAP1BUFL EQU H'0F68' VELRL EQU H'0F68' CAP1BUFH EQU H'0F69' VELRH EQU H'0F69' OVDCONS EQU H'0F6A' OVDCOND EQU H'0F6B' FLTCONFIG EQU H'0F6C' DTCON EQU H'0F6D' PWMCON1 EQU H'0F6E' PWMCON0 EQU H'0F6F' SEVTCMPH EQU H'0F70' SEVTCMPL EQU H'0F71' PDC2H EQU H'0F74' PDC2L EQU H'0F75' PDC1H EQU H'0F76' PDC1L EQU H'0F77' PDC0H EQU H'0F78' PDC0L EQU H'0F79' PTPERH EQU H'0F7A' PTPERL EQU H'0F7B' PTMRH EQU H'0F7C' PTMRL EQU H'0F7D' PTCON1 EQU H'0F7E' PTCON0 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' TMR5L EQU H'0F87' TMR5H EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' PR5L EQU H'0F90' PR5H EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' ADCHS EQU H'0F99' ADCON3 EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' BAUDCON EQU H'0FAA' BAUDCTL EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' QEICON EQU H'0FB6' T5CON EQU H'0FB7' ANSEL0 EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- DFLTCON Bits ----------------------------------------------------- FLTCK0 EQU H'0000' FLTCK1 EQU H'0001' FLTCK2 EQU H'0002' FLT1EN EQU H'0003' FLT2EN EQU H'0004' FLT3EN EQU H'0005' FLT4EN EQU H'0006' ;----- CAP3CON Bits ----------------------------------------------------- CAP3M0 EQU H'0000' CAP3M1 EQU H'0001' CAP3M2 EQU H'0002' CAP3M3 EQU H'0003' CAP3TMR EQU H'0005' CAP3REN EQU H'0006' ;----- CAP2CON Bits ----------------------------------------------------- CAP2M0 EQU H'0000' CAP2M1 EQU H'0001' CAP2M2 EQU H'0002' CAP2M3 EQU H'0003' CAP2TMR EQU H'0005' CAP2REN EQU H'0006' ;----- CAP1CON Bits ----------------------------------------------------- CAP1M0 EQU H'0000' CAP1M1 EQU H'0001' CAP1M2 EQU H'0002' CAP1M3 EQU H'0003' CAP1TMR EQU H'0005' CAP1REN EQU H'0006' ;----- OVDCONS Bits ----------------------------------------------------- POUT0 EQU H'0000' POUT1 EQU H'0001' POUT2 EQU H'0002' POUT3 EQU H'0003' POUT4 EQU H'0004' POUT5 EQU H'0005' POUT6 EQU H'0006' POUT7 EQU H'0007' ;----- OVDCOND Bits ----------------------------------------------------- POVD0 EQU H'0000' POVD1 EQU H'0001' POVD2 EQU H'0002' POVD3 EQU H'0003' POVD4 EQU H'0004' POVD5 EQU H'0005' POVD6 EQU H'0006' POVD7 EQU H'0007' ;----- FLTCONFIG Bits ----------------------------------------------------- FLTAEN EQU H'0000' FLTAMOD EQU H'0001' FLTAS EQU H'0002' FLTCON EQU H'0003' FLTBEN EQU H'0004' FLTBMOD EQU H'0005' FLTBS EQU H'0006' ;----- DTCON Bits ----------------------------------------------------- DT0 EQU H'0000' DT1 EQU H'0001' DT2 EQU H'0002' DT3 EQU H'0003' DT4 EQU H'0004' DT5 EQU H'0005' DTPS0 EQU H'0006' DTPS1 EQU H'0007' DTA0 EQU H'0000' DTA1 EQU H'0001' DTA2 EQU H'0002' DTA3 EQU H'0003' DTA4 EQU H'0004' DTA5 EQU H'0005' DTAPS0 EQU H'0006' DTAPS1 EQU H'0007' ;----- PWMCON1 Bits ----------------------------------------------------- OSYNC EQU H'0000' UDIS EQU H'0001' SEVTDIR EQU H'0003' SEVOPS0 EQU H'0004' SEVOPS1 EQU H'0005' SEVOPS2 EQU H'0006' SEVOPS3 EQU H'0007' ;----- PWMCON0 Bits ----------------------------------------------------- PMOD0 EQU H'0000' PMOD1 EQU H'0001' PMOD2 EQU H'0002' PMOD3 EQU H'0003' PWMEN0 EQU H'0004' PWMEN1 EQU H'0005' PWMEN2 EQU H'0006' ;----- PTCON1 Bits ----------------------------------------------------- PTDIR EQU H'0006' PTEN EQU H'0007' ;----- PTCON0 Bits ----------------------------------------------------- PTMOD0 EQU H'0000' PTMOD1 EQU H'0001' PTCKPS0 EQU H'0002' PTCKPS1 EQU H'0003' PTOPS0 EQU H'0004' PTOPS1 EQU H'0005' PTOPS2 EQU H'0006' PTOPS3 EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' INT0 EQU H'0003' INT1 EQU H'0004' INT2 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' T0CKI EQU H'0003' SDA EQU H'0004' SCK EQU H'0005' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' NOT_FLTA EQU H'0001' NOT_FLTB EQU H'0002' T5CKI EQU H'0003' SDI EQU H'0004' SCL EQU H'0005' NOT_SS EQU H'0006' SDO EQU H'0007' FLTA EQU H'0001' FLTB EQU H'0002' SS EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- ADCHS Bits ----------------------------------------------------- GASEL0 EQU H'0000' GASEL1 EQU H'0001' GCSEL0 EQU H'0002' GCSEL1 EQU H'0003' GBSEL0 EQU H'0004' GBSEL1 EQU H'0005' GDSEL0 EQU H'0006' GDSEL1 EQU H'0007' SASEL0 EQU H'0000' SASEL1 EQU H'0001' SCSEL0 EQU H'0002' SCSEL1 EQU H'0003' SBSEL0 EQU H'0004' SBSEL1 EQU H'0005' SDSEL0 EQU H'0006' SDSEL1 EQU H'0007' ;----- ADCON3 Bits ----------------------------------------------------- SSRC0 EQU H'0000' SSRC1 EQU H'0001' SSRC2 EQU H'0002' SSRC3 EQU H'0003' SSRC4 EQU H'0004' ADRS0 EQU H'0006' ADRS1 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TBIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TBIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LVDIE EQU H'0002' EEIE EQU H'0004' OSFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LVDIF EQU H'0002' EEIF EQU H'0004' OSFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' LVDIP EQU H'0002' EEIP EQU H'0004' OSFIP EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR5IE EQU H'0000' IC1IE EQU H'0001' IC2QEIE EQU H'0002' IC3DRIE EQU H'0003' PTIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- TMR5IF EQU H'0000' IC1IF EQU H'0001' IC2QEIF EQU H'0002' IC3DRIF EQU H'0003' PTIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- TMR5IP EQU H'0000' IC1IP EQU H'0001' IC2QEIP EQU H'0002' IC3DRIP EQU H'0003' PTIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- QEICON Bits ----------------------------------------------------- PDEC0 EQU H'0000' PDEC1 EQU H'0001' QEIM0 EQU H'0002' QEIM1 EQU H'0003' QEIM2 EQU H'0004' UP_DOWN EQU H'0005' ; ERROR is a reserved word ; ERROR EQU H'0006' VELM EQU H'0007' UP EQU H'0005' DOWN EQU H'0005' NOT_DOWN EQU H'0005' NOT_VELM EQU H'0007' ;----- T5CON Bits ----------------------------------------------------- TMR5ON EQU H'0000' TMR5CS EQU H'0001' T5SYNC EQU H'0002' T5PS0 EQU H'0003' T5PS1 EQU H'0004' T5MOD EQU H'0005' RESEN EQU H'0006' T5SEN EQU H'0007' NOT_T5SYNC EQU H'0002' NOT_RESEN EQU H'0006' ;----- ANSEL0 Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ACQT3 EQU H'0006' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- ADPNT0 EQU H'0000' ADPNT1 EQU H'0001' BFOVFL EQU H'0002' BFEMT EQU H'0003' FIFOEN EQU H'0004' VCFG0 EQU H'0006' VCFG1 EQU H'0007' FFOVFL EQU H'0002' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' ACMOD0 EQU H'0002' ACMOD1 EQU H'0003' ACSCH EQU H'0004' ACONV EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDT0 EQU H'0001' WDT1 EQU H'0002' WDT2 EQU H'0003' WDT3 EQU H'0004' WDT4 EQU H'0005' WDT5 EQU H'0006' WDT6 EQU H'0007' WDTW EQU H'0007' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F5F' __BADRAM H'0F83'-H'0F86' __BADRAM H'0F8C'-H'0F8F' __BADRAM H'0F95'-H'0F98' __BADRAM H'0F9C' __BADRAM H'0FB1'-H'0FB5' __BADRAM H'0FB9' __BADRAM H'0FC5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC2 External RC, RA6 is CLKOUT ; OSC = EC EC, RA6 is CLKOUT ; OSC = ECIO EC, RA6 is I/O ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO External RC, RA6 is I/O ; OSC = IRCIO Internal RC, RA6 & RA7 are I/O ; OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O ; OSC = RC1 External RC, RA6 is CLKOUT ; OSC = RC External RC, RA6 is CLKOUT ; ; Fail-Safe Clock Monitor Enable: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal/External Switch-Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRTEN = ON Enabled ; PWRTEN = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDTEN = OFF Disabled ; WDTEN = ON Enabled ; ; Watchdog Timer Enable Window: ; WINEN = ON Enabled ; WINEN = OFF Disabled ; ; Watchdog Postscaler: ; WDPS = 1 1:1 ; WDPS = 2 1:2 ; WDPS = 4 1:4 ; WDPS = 8 1:8 ; WDPS = 16 1:16 ; WDPS = 32 1:32 ; WDPS = 64 1:64 ; WDPS = 128 1:128 ; WDPS = 256 1:256 ; WDPS = 512 1:512 ; WDPS = 1024 1:1024 ; WDPS = 2048 1:2048 ; WDPS = 4096 1:4096 ; WDPS = 8192 1:8192 ; WDPS = 16384 1:16384 ; WDPS = 32768 1:32768 ; ; Timer1 Oscillator MUX: ; T1OSCMX = OFF Active ; T1OSCMX = ON Inactive ; ; High-Side Transistors Polarity: ; HPOL = LOW Active low ; HPOL = HIGH Active high ; ; Low-Side Transistors Polarity: ; LPOL = LOW Active low ; LPOL = HIGH Active high ; ; PWM output pins Reset state control: ; PWMPIN = ON Enabled ; PWMPIN = OFF Disabled ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC2_1H EQU H'F3' ; External RC, RA6 is CLKOUT _OSC_EC_1H EQU H'F4' ; EC, RA6 is CLKOUT _OSC_ECIO_1H EQU H'F5' ; EC, RA6 is I/O _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; External RC, RA6 is I/O _OSC_IRCIO_1H EQU H'F8' ; Internal RC, RA6 & RA7 are I/O _OSC_IRC_1H EQU H'F9' ; Internal RC, RA6 is CLKOUT, RA7 is I/O _OSC_RC1_1H EQU H'FB' ; External RC, RA6 is CLKOUT _OSC_RC_1H EQU H'FF' ; External RC, RA6 is CLKOUT _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; Enabled _PWRTEN_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'FD' ; Disabled _BOREN_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; Disabled _WDTEN_ON_2H EQU H'FF' ; Enabled _WINEN_ON_2H EQU H'DF' ; Enabled _WINEN_OFF_2H EQU H'FF' ; Disabled _WDPS_1_2H EQU H'E1' ; 1:1 _WDPS_2_2H EQU H'E3' ; 1:2 _WDPS_4_2H EQU H'E5' ; 1:4 _WDPS_8_2H EQU H'E7' ; 1:8 _WDPS_16_2H EQU H'E9' ; 1:16 _WDPS_32_2H EQU H'EB' ; 1:32 _WDPS_64_2H EQU H'ED' ; 1:64 _WDPS_128_2H EQU H'EF' ; 1:128 _WDPS_256_2H EQU H'F1' ; 1:256 _WDPS_512_2H EQU H'F3' ; 1:512 _WDPS_1024_2H EQU H'F5' ; 1:1024 _WDPS_2048_2H EQU H'F7' ; 1:2048 _WDPS_4096_2H EQU H'F9' ; 1:4096 _WDPS_8192_2H EQU H'FB' ; 1:8192 _WDPS_16384_2H EQU H'FD' ; 1:16384 _WDPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _T1OSCMX_OFF_3L EQU H'DF' ; Active _T1OSCMX_ON_3L EQU H'FF' ; Inactive _HPOL_LOW_3L EQU H'EF' ; Active low _HPOL_HIGH_3L EQU H'FF' ; Active high _LPOL_LOW_3L EQU H'F7' ; Active low _LPOL_HIGH_3L EQU H'FF' ; Active high _PWMPIN_ON_3L EQU H'FB' ; Enabled _PWMPIN_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16ce624.inc0000644000175000017500000001423511156313161013312 00000000000000 LIST ; P16CE624.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CE624 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CE624 ; 2. LIST directive in the source file ; LIST P=PIC16CE624 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Initial Release ;1.01 02 Apr 1998 Fix incorrect BADRAM and MAXRAM information ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CE624 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' EEINTF EQU H'0090' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EEINTF Bits ---------------------------------------------------------- EESDA EQU H'0001' EESCL EQU H'0002' EEVDD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'07'-H'09', H'0D'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E' __BADRAM H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_50 EQU H'15DF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f627a.inc0000644000175000017500000002501511156313161013312 00000000000000 LIST ; P16F627A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F627A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F627A ; 2. LIST directive in the source file ; LIST P=PIC16F627A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR ;1.00 22 Aug 2002 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F627A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' CMIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits --------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' CMIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' NOT_BOD EQU H'0000' ;Backwards compatability to 16F62X ;----- TXSTA Bits ---------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' ;Backwards compatability to 16F62X _BODEN_OFF EQU H'3FBF' ;Backwards compatability to 16F62X _BOREN_ON EQU H'3FFF' _BOREN_OFF EQU H'3FBF' _CP_ON EQU H'1FFF' _CP_OFF EQU H'3FFF' _DATA_CP_ON EQU H'3EFF' _DATA_CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _RC_OSC_CLKOUT EQU H'3FFF' _RC_OSC_NOCLKOUT EQU H'3FFE' _ER_OSC_CLKOUT EQU H'3FFF' ;Backwards compatability to 16F62X _ER_OSC_NOCLKOUT EQU H'3FFE' ;Backwards compatability to 16F62X _INTOSC_OSC_CLKOUT EQU H'3FFD' _INTOSC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' ;Backwards compatability to 16F62X _INTRC_OSC_NOCLKOUT EQU H'3FFC' ;Backwards compatability to 16F62X _EXTCLK_OSC EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' LIST gputils-0.13.7/header/p18f6527.inc0000644000175000017500000017000411156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6527 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6527 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6527 ; 2. LIST directive in the source file ; LIST P=PIC18F6527 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6527 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f65j15.inc0000644000175000017500000013047111156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F65J15 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F65J15 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F65J15 ; 2. LIST directive in the source file ; LIST P=PIC18F65J15 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F65J15 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f1933.inc0000644000175000017500000011641711156521301013236 00000000000000 LIST ;========================================================================== ; MPASM PIC16F1933 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16F1933 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16F1933 ; 2. LIST directive in the source file ; LIST P=PIC16F1933 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F1933 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'000F' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'008F' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'010F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E'-H'0190' __BADRAM H'0197'-H'0198' __BADRAM H'01A0'-H'01EF' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'0220'-H'026F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'02A0'-H'02EF' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0320'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079A'-H'079F' __BADRAM H'07A2' __BADRAM H'07A5' __BADRAM H'07A8' __BADRAM H'07AB'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _nPWRTE_OFF EQU H'FFDF' ; PWRT enabled _nPWRTE_ON EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _nDEBUG_ON EQU H'EFFF' ; Background debugger is enabled _nDEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p16c745.inc0000644000175000017500000003306711156313161013155 00000000000000 LIST ; P16C745.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C745 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C745 ; 2. LIST directive in the source file ; LIST P=PIC16C745 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 28 Sep 99 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C745 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' UIR EQU H'0190' UIE EQU H'0191' UEIR EQU H'0192' UEIE EQU H'0193' USTAT EQU H'0194' UCTRL EQU H'0195' UADDR EQU H'0196' USWSTAT EQU H'0197' UEP0 EQU H'0198' UEP1 EQU H'0199' UEP2 EQU H'019A' BD0OST EQU H'01A0' BD0OBC EQU H'01A1' BD0OAL EQU H'01A2' BD0IST EQU H'01A4' BD0IBC EQU H'01A5' BD0IAL EQU H'01A6' BD1OST EQU H'01A8' BD1OBC EQU H'01A9' BD1OAL EQU H'01AA' BD1IST EQU H'01AC' BD1IBC EQU H'01AD' BD1IAL EQU H'01AE' BD2OST EQU H'01B0' BD2OBC EQU H'01B1' BD2OAL EQU H'01B2' BD2IST EQU H'01B4' BD2IBC EQU H'01B5' BD2IAL EQU H'01B6' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' USBIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' USBIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- UIR/UIE Bits ----------------------------------------------------- STALL EQU H'0005' UIDLE EQU H'0004' TOK_DNE EQU H'0003' ACTIVITY EQU H'0002' UERR EQU H'0001' USB_RST EQU H'0000' ;----- UEIR/UEIE Bits ----------------------------------------------------- BTS_ERR EQU H'0007' OWN_ERR EQU H'0006' WRT_ERR EQU H'0005' BTO_ERR EQU H'0004' DFN8 EQU H'0003' CRC16 EQU H'0002' CRC5 EQU H'0001' PID_ERR EQU H'0000' ;----- USTAT Bits --------------------------------------------------------- ENDP1 EQU H'0004' ENDP0 EQU H'0003' IN EQU H'0002' ;----- UCTRL Bits --------------------------------------------------------- SE0 EQU H'0005' PKT_DIS EQU H'0004' DEV_ATT EQU H'0003' RESUME EQU H'0002' SUSPND EQU H'0001' ;----- UEPn Bits --------------------------------------------------------- EP_CTL_DIS EQU H'0003' EP_OUT_EN EQU H'0002' EP_IN_EN EQU H'0001' EP_STALL EQU H'0000' ;----- Buffer descriptor Bits --------------------------------------------- UOWN EQU H'0007' OWN EQU H'0007' DATA01 EQU H'0006' DTS EQU H'0003' BSTALL EQU H'0002' PID3 EQU H'0005' PID2 EQU H'0004' PID1 EQU H'0003' PID0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'8', H'9', H'13', H'14', H'88', H'89', H'8F'-H'91' __BADRAM H'93'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F' __BADRAM H'1E0'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _HS_OSC EQU H'3FFC' _EC_OSC EQU H'3FFD' _H4_OSC EQU H'3FFE' _E4_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f23k20.inc0000644000175000017500000012477311156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F23K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F23K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F23K20 ; 2. LIST directive in the source file ; LIST P=PIC18F23K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F23K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' P1C EQU H'0001' P1B EQU H'0002' P1D EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f1220.inc0000644000175000017500000007342411156521301013225 00000000000000 LIST ; P18F1220.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4320 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F1220 ; 2. LIST directive in the source file ; LIST P=PIC18F1220 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 03 June 2002 Initial release GK ;0.11 09/26/02 Include both names SWDTE and SWDTEN pas ;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD ; Changed _MCLRE_()_3H description from RE3 to RA5 ;0.22 23Jan2003 Added RCIO, ECIO, INTIO1, INTIO2 OSC modes BD ; Commented out RCIO6, ECIO6, INTIO7, INTIO67 ; Maintains compatability to 18F4320 ;0.23 29Jan2003 Changed from BAUDCTL:W4E to WUE BD ;0.24 04Feb2003 Changed ECCPAS EQU from H'0FB8' to H'0FB6' BD ;0.25 1 Oct 2003 Bit names changed BD ; LVVn to LVDLn IVRST to IRVST ; FSCMEN to FSCM ; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1, ; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0, ; Removed redundant bit names ; RCIO6 use RCIO INTIO7 use INTIO1 ; ECIO6 use ECIO INTIO67 use INTIO2 ; BKBUG use DEBUG SWDTE use SWDTEN ; T0IE use TMR0IE INT0E use INT0IE ; T0IF use TMR0IF INT0F use INT0IE ; BGST use IRVST T1INSYNC use T1SYNC ; TXD8 use TX9D T3INSYNC use T3SYNC ; TX8_9 use TX9 NOT_TX8 use TX9 ; RC9 use RX9 NOT_RC8 use RX9 ; RC8_9 use RX9 RCD8 use RX9D ; INT2P use INT2IP INT1P use INT1IP ; INT2E use INT2IE INT1E use INT1IE ; INT2F use INT2IF INT1F use INT1IF ; FLTS use IOFS STKOVF use STKFUL ; Added equates for PIC16 Compatability ; ADRES, INTF, INTE, CCPnX, CCPnY ; General clean-up (removed some comments) ;======================================================================= ; ; Verify Processor ; ;======================================================================= IFNDEF __18F1220 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define ADRES ADRESH ; PIC16 SFR substitution #define INTE INT0IE ; PIC16 bit substitution #define INTF INT0IF ; PIC16 bit substitution #define CCP1X DC1B1 ; PIC16 bit substitution #define CCP1Y DC1B0 ; PIC16 bit substitution #define SCS SCS0 ; PIC18 bit substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' ; reserved EQU H'0FC9' ; reserved EQU H'0FC8' ; reserved EQU H'0FC7' ; reserved EQU H'0FC6' ; reserved EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' ; reserved EQU H'0FBC' ; reserved EQU H'0FBB' ; reserved EQU H'0FBA' ; reserved EQU H'0FB9' ; reserved EQU H'0FB8' PWM1CON EQU H'0FB7' ECCPAS EQU H'0FB6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' SPBRGH EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' BAUDCTL EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' ; reserved EQU H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ; reserved EQU H'0F9C' OSCTUNE EQU H'0F9B' ; reserved EQU H'0F9A' ; reserved EQU H'0F99' ; reserved EQU H'0F98' ; reserved EQU H'0F97' ; reserved EQU H'0F96' ; reserved EQU H'0F95' ; reserved EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ; reserved EQU H'0F91' ; reserved EQU H'0F90' ; reserved EQU H'0F8F' ; reserved EQU H'0F8E' ; reserved EQU H'0F8D' ; reserved EQU H'0F8C' ; reserved EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved EQU H'0F88' ; reserved EQU H'0F87' ; reserved EQU H'0F86' ; reserved EQU H'0F85' ; reserved EQU H'0F84' ; reserved EQU H'0F83' ; reserved EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' SP4 EQU H'0004' SP3 EQU H'0003' SP2 EQU H'0002' SP1 EQU H'0001' SP0 EQU H'0000' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' INT0IE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- VCFG1 EQU H'0007' VCFG0 EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- PCFG6 EQU H'0006' PCFG5 EQU H'0005' PCFG4 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ---------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON bits ---------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits ----------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------ CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------ SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------ RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- OSCFIP EQU H'0007' EEIP EQU H'0004' LVDIP EQU H'0002' TMR3IP EQU H'0001' ;----- PIR2 Bits ------------------------------------------------------- OSCFIF EQU H'0007' EEIF EQU H'0004' LVDIF EQU H'0002' TMR3IF EQU H'0001' ;----- PIE2 Bits ------------------------------------------------------- OSCFIE EQU H'0007' EEIE EQU H'0004' LVDIE EQU H'0002' TMR3IE EQU H'0001' ;----- IPR1 Bits ------------------------------------------------------- ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- OSCTUNE Bits ---------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 LVDIN EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 RA7 EQU 7 OSC1 EQU 7 CLKI EQU 7 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 AN4 EQU 0 RB1 EQU 1 INT1 EQU 1 AN5 EQU 1 TX EQU 1 CK EQU 1 RB2 EQU 2 INT2 EQU 2 P1B EQU 2 RB3 EQU 3 CCP1 EQU 3 P1A EQU 3 RB4 EQU 4 KBI0 EQU 4 AN6 EQU 4 RX EQU 4 RB5 EQU 5 KBI1 EQU 5 PGM EQU 5 RB6 EQU 6 KBI2 EQU 6 PGC EQU 6 T1OSO EQU 6 T1CKI EQU 6 T13CKI EQU 6 P1C EQU 6 RB7 EQU 7 KBI3 EQU 7 T1OSI EQU 7 PGD EQU 7 P1D EQU 7 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'100'-H'F7F' __BADRAM H'F82'-H'F88',H'F8B'-H'F91',H'F94'-H'F9A',H'F9C' __BADRAM H'FA3'-H'FA5',H'FB4'-H'FB5',H'FB8'-H'FBC' __BADRAM H'FC5'-H'FC9',H'FD4' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = EC External Clock on OSC1, OSC2 as FOSC/4 ; OSC = ECIO External Clock on OSC1, OSC2 as RA6 ; OSC = HSPLL HS + PLL ; OSC = RCIO External RC on OSC1, OSC2 as RA6 ; OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6 ; OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4 ; OSC = RC External RC on OSC1, OSC2 as FOSC/4 ; ; Fail-Safe Clock Monitor: ; FSCM = OFF Fail-Safe Clock Monitor disabled ; FSCM = ON Fail-Safe Clock Monitor enabled ; ; Internal External Switch Over mode: ; IESO = OFF Internal External Switch Over mode disabled ; IESO = ON Internal External Switch Over mode enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; Stack Full/Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To embed the Configuration Bits in your source code, paste the ; following lines into your source code in the following format, ; and change the configuration value to the desired setting (such ; as WDT_OFF to WDT_ON). ; These lines are commented out - each __CONFIG line should have the ; preceding semicolon (;) removed when pasted into your source code. ; __CONFIG _CONFIG1H, _IESO_ON_1H & _FSCM_OFF_1H & _RC_OSC_1H ; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_27_2L ; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H ; __CONFIG _CONFIG3H, _MCLRE_ON_3H ; __CONFIG _CONFIG4L, _DEBUG_OFF_4L & _LVP_ON_4L & _STVR_ON_4L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 1H Options _IESO_ON_1H EQU H'FF' ; Internal External Oscillator Switch Over mode enabled _IESO_OFF_1H EQU H'7F' ; Internal External Oscillator Switch Over mode disabled _FSCM_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _FSCM_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as FOSC/4 _RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6 _LP_OSC_1H EQU H'F0' ; LP Oscillator _XT_OSC_1H EQU H'F1' ; XT Oscillator _HS_OSC_1H EQU H'F2' ; HS Oscillator _HSPLL_OSC_1H EQU H'F6' ; HS + PLL _EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as FOSC/4 _ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6 _INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4 _INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options _BORV_27_2L EQU H'FB' ; BOR Voltage - 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _PWRT_OFF_2L EQU H'FF' ; Power-up Timer disabled _PWRT_ON_2L EQU H'FE' ; Power-up Timer enabled ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled _WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio _WDTPS_16K_2H EQU H'FD' ; 1:16,384 _WDTPS_8K_2H EQU H'FB' ; 1: 8,192 _WDTPS_4K_2H EQU H'F9' ; 1: 4,096 _WDTPS_2K_2H EQU H'F7' ; 1: 2,048 _WDTPS_1K_2H EQU H'F5' ; 1: 1,024 _WDTPS_512_2H EQU H'F3' ; 1: 512 _WDTPS_256_2H EQU H'F1' ; 1: 256 _WDTPS_128_2H EQU H'EF' ; 1: 128 _WDTPS_64_2H EQU H'ED' ; 1: 64 _WDTPS_32_2H EQU H'EB' ; 1: 32 _WDTPS_16_2H EQU H'E9' ; 1: 16 _WDTPS_8_2H EQU H'E7' ; 1: 8 _WDTPS_4_2H EQU H'E5' ; 1: 4 _WDTPS_2_2H EQU H'E3' ; 1: 2 _WDTPS_1_2H EQU H'E1' ; 1: 1 ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'FF' ; MCLR enabled, RA5 input disabled _MCLRE_OFF_3H EQU H'7F' ; MCLR disabled, RA5 input enabled ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; BacKground deBUGger enabled _DEBUG_OFF_4L EQU H'FF' ; BacKground deBUGger disabled _LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled _LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP0_ON_5L EQU H'FE' ; Block 0 protected _CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable _CP1_ON_5L EQU H'FD' ; Block 1 protected _CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'BF' ; Boot Block protected _CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'7F' ; Data EE memory protected _CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT0_ON_6L EQU H'FE' ; Block 0 write protected _WRT0_OFF_6L EQU H'FF' ; Block 0 writable _WRT1_ON_6L EQU H'FD' ; Block 1 write protected _WRT1_OFF_6L EQU H'FF' ; Block 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'DF' ; Config registers write protected _WRTC_OFF_6H EQU H'FF' ; Config registers writable _WRTB_ON_6H EQU H'BF' ; Boot block write protected _WRTB_OFF_6H EQU H'FF' ; Boot block writable _WRTD_ON_6H EQU H'7F' ; Data EE write protected _WRTD_OFF_6H EQU H'FF' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR0_ON_7L EQU H'FE' ; Block 0 protected _EBTR0_OFF_7L EQU H'FF' ; Block 0 readable _EBTR1_ON_7L EQU H'FD' ; Block 1 protected _EBTR1_OFF_7L EQU H'FF' ; Block 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'BF' ; Boot block read protected _EBTRB_OFF_7H EQU H'FF' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p18f252.inc0000644000175000017500000007124711156313161013155 00000000000000 LIST ; P18F252.INC Standard Header File, Version 1.4 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F252 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F252 ; 2. LIST directive in the source file ; LIST P=PIC18F252 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;1.0 03/23/01 Modified C252 for F252 tr ;1.1 08/01/01 Added EECON1 bits, corrected code protect config bit inserts ;1.2 09/17/01 Corrected MAXRAM,BADRAM tr ;1.3 10/23/01 Corrected CONFIG bits/registers tr/pas ;1.4 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F252 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' ;RESERVED_0F96 EQU H'0F96' ;RESERVED_0F95 EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' ;RESERVED_0F8D EQU H'0F8D' ;RESERVED_0F8C EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' ;RESERVED_0F84 EQU H'0F84' ;RESERVED_0F83 EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR2 Bits ---------------------------------------------------------- EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'600'-H'F7F' __BADRAM H'F85'-H'F88' __BADRAM H'F8E'-H'F91' __BADRAM H'F97'-H'F9C' __BADRAM H'FA3'-H'FA5' __BADRAM H'FAA' __BADRAM H'FB4'-H'FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p18f2550.inc0000644000175000017500000014350711156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2550 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2550 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2550 ; 2. LIST directive in the source file ; LIST P=PIC18F2550 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2550 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f946.inc0000644000175000017500000011021111156521301013143 00000000000000 LIST ; P16F946.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F946 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F946 ; 2. LIST directive in the source file ; LIST P=PIC16F946 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 02/25/05 Initial Release ;1.01 10/05/05 Correct names of bits in ANSEL, Add EEADRH and EEADRL bit ; definitions ;1.02 10/31/05 Remove EECON2 from badram. ;1.03 02/26/07 Added Alias of EEADR and EEDATA ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F946 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' WPU EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' CMCON1 EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON0 EQU H'009C' VRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LCDCON EQU H'0107' LCDPS EQU H'0108' LVDCON EQU H'0109' EEDATL EQU H'010C' EEDATA EQU H'010C' EEADRL EQU H'010D' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' LCDDATA0 EQU H'0110' LCDDATA1 EQU H'0111' LCDDATA2 EQU H'0112' LCDDATA3 EQU H'0113' LCDDATA4 EQU H'0114' LCDDATA5 EQU H'0115' LCDDATA6 EQU H'0116' LCDDATA7 EQU H'0117' LCDDATA8 EQU H'0118' LCDDATA9 EQU H'0119' LCDDATA10 EQU H'011A' LCDDATA11 EQU H'011B' LCDSE0 EQU H'011C' LCDSE1 EQU H'011D' LCDSE2 EQU H'011E' TRISF EQU H'0185' TRISG EQU H'0187' PORTF EQU H'0188' PORTG EQU H'0189' EECON1 EQU H'018C' EECON2 EQU H'018D' LCDDATA12 EQU H'0190' LCDDATA13 EQU H'0191' LCDDATA14 EQU H'0192' LCDDATA15 EQU H'0193' LCDDATA16 EQU H'0194' LCDDATA17 EQU H'0195' LCDDATA18 EQU H'0196' LCDDATA19 EQU H'0197' LCDDATA20 EQU H'0198' LCDDATA21 EQU H'0199' LCDDATA22 EQU H'019A' LCDDATA23 EQU H'019B' LCDSE3 EQU H'019C' LCDSE4 EQU H'019D' LCDSE5 EQU H'019E' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' LCDIF EQU H'0004' LVDIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0006' VCFG0 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' LCDIE EQU H'0004' LVDIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' AN7 EQU H'0007' ; Backward compatibility only ANS6 EQU H'0006' AN6 EQU H'0006' ; Backward compatibility only ANS5 EQU H'0005' AN5 EQU H'0005' ; Backward compatibility only ANS4 EQU H'0004' AN4 EQU H'0004' ; Backward compatibility only ANS3 EQU H'0003' AN3 EQU H'0003' ; Backward compatibility only ANS2 EQU H'0002' AN2 EQU H'0002' ; Backward compatibility only ANS1 EQU H'0001' AN1 EQU H'0001' ; Backward compatibility only ANS0 EQU H'0000' AN0 EQU H'0000' ; Backward compatibility only ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' WPU6 EQU H'0006' WPU5 EQU H'0005' WPU4 EQU H'0004' WPU3 EQU H'0003' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' IOC6 EQU H'0006' IOC5 EQU H'0005' IOC4 EQU H'0004' ;----- CMCON1 Bits -------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON0 Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- VRCON Bits -------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' VLCDEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- WFT EQU H'0007' BIASMD EQU H'0006' LCDA EQU H'0005' WA EQU H'0004' LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- LCDDATA0 Bits ------------------------------------------------------- SEG7COM0 EQU H'0007' SEG6COM0 EQU H'0006' SEG5COM0 EQU H'0005' SEG4COM0 EQU H'0004' SEG3COM0 EQU H'0003' SEG2COM0 EQU H'0002' SEG1COM0 EQU H'0001' SEG0COM0 EQU H'0000' S7C0 EQU H'0007' S6C0 EQU H'0006' S5C0 EQU H'0005' S4C0 EQU H'0004' S3C0 EQU H'0003' S2C0 EQU H'0002' S1C0 EQU H'0001' S0C0 EQU H'0000' ;----- LCDDATA1 Bits ------------------------------------------------------- SEG15COM0 EQU H'0007' SEG14COM0 EQU H'0006' SEG13COM0 EQU H'0005' SEG12COM0 EQU H'0004' SEG11COM0 EQU H'0003' SEG10COM0 EQU H'0002' SEG9COM0 EQU H'0001' SEG8COM0 EQU H'0000' S15C0 EQU H'0007' S14C0 EQU H'0006' S13C0 EQU H'0005' S12C0 EQU H'0004' S11C0 EQU H'0003' S10C0 EQU H'0002' S9C0 EQU H'0001' S8C0 EQU H'0000' ;----- LCDDATA2 Bits ------------------------------------------------------- SEG23COM0 EQU H'0007' SEG22COM0 EQU H'0006' SEG21COM0 EQU H'0005' SEG20COM0 EQU H'0004' SEG19COM0 EQU H'0003' SEG18COM0 EQU H'0002' SEG17COM0 EQU H'0001' SEG16COM0 EQU H'0000' S23C0 EQU H'0007' S22C0 EQU H'0006' S21C0 EQU H'0005' S20C0 EQU H'0004' S19C0 EQU H'0003' S18C0 EQU H'0002' S17C0 EQU H'0001' S16C0 EQU H'0000' ;----- LCDDATA3 Bits ------------------------------------------------------- SEG7COM1 EQU H'0007' SEG6COM1 EQU H'0006' SEG5COM1 EQU H'0005' SEG4COM1 EQU H'0004' SEG3COM1 EQU H'0003' SEG2COM1 EQU H'0002' SEG1COM1 EQU H'0001' SEG0COM1 EQU H'0000' S7C1 EQU H'0007' S6C1 EQU H'0006' S5C1 EQU H'0005' S4C1 EQU H'0004' S3C1 EQU H'0003' S2C1 EQU H'0002' S1C1 EQU H'0001' S0C1 EQU H'0000' ;----- LCDDATA4 Bits ------------------------------------------------------- SEG15COM1 EQU H'0007' SEG14COM1 EQU H'0006' SEG13COM1 EQU H'0005' SEG12COM1 EQU H'0004' SEG11COM1 EQU H'0003' SEG10COM1 EQU H'0002' SEG9COM1 EQU H'0001' SEG8COM1 EQU H'0000' S15C1 EQU H'0007' S14C1 EQU H'0006' S13C1 EQU H'0005' S12C1 EQU H'0004' S11C1 EQU H'0003' S10C1 EQU H'0002' S9C1 EQU H'0001' S8C1 EQU H'0000' ;----- LCDDATA5 Bits ------------------------------------------------------- SEG23COM1 EQU H'0007' SEG22COM1 EQU H'0006' SEG21COM1 EQU H'0005' SEG20COM1 EQU H'0004' SEG19COM1 EQU H'0003' SEG18COM1 EQU H'0002' SEG17COM1 EQU H'0001' SEG16COM1 EQU H'0000' S23C1 EQU H'0007' S22C1 EQU H'0006' S21C1 EQU H'0005' S20C1 EQU H'0004' S19C1 EQU H'0003' S18C1 EQU H'0002' S17C1 EQU H'0001' S16C1 EQU H'0000' ;----- LCDDATA6 Bits ------------------------------------------------------- SEG7COM2 EQU H'0007' SEG6COM2 EQU H'0006' SEG5COM2 EQU H'0005' SEG4COM2 EQU H'0004' SEG3COM2 EQU H'0003' SEG2COM2 EQU H'0002' SEG1COM2 EQU H'0001' SEG0COM2 EQU H'0000' S7C2 EQU H'0007' S6C2 EQU H'0006' S5C2 EQU H'0005' S4C2 EQU H'0004' S3C2 EQU H'0003' S2C2 EQU H'0002' S1C2 EQU H'0001' S0C2 EQU H'0000' ;----- LCDDATA7 Bits ------------------------------------------------------- SEG15COM2 EQU H'0007' SEG14COM2 EQU H'0006' SEG13COM2 EQU H'0005' SEG12COM2 EQU H'0004' SEG11COM2 EQU H'0003' SEG10COM2 EQU H'0002' SEG9COM2 EQU H'0001' SEG8COM2 EQU H'0000' S15C2 EQU H'0007' S14C2 EQU H'0006' S13C2 EQU H'0005' S12C2 EQU H'0004' S11C2 EQU H'0003' S10C2 EQU H'0002' S9C2 EQU H'0001' S8C2 EQU H'0000' ;----- LCDDATA8 Bits ------------------------------------------------------- SEG23COM2 EQU H'0007' SEG22COM2 EQU H'0006' SEG21COM2 EQU H'0005' SEG20COM2 EQU H'0004' SEG19COM2 EQU H'0003' SEG18COM2 EQU H'0002' SEG17COM2 EQU H'0001' SEG16COM2 EQU H'0000' S23C2 EQU H'0007' S22C2 EQU H'0006' S21C2 EQU H'0005' S20C2 EQU H'0004' S19C2 EQU H'0003' S18C2 EQU H'0002' S17C2 EQU H'0001' S16C2 EQU H'0000' ;----- LCDDATA9 Bits ------------------------------------------------------- SEG7COM3 EQU H'0007' SEG6COM3 EQU H'0006' SEG5COM3 EQU H'0005' SEG4COM3 EQU H'0004' SEG3COM3 EQU H'0003' SEG2COM3 EQU H'0002' SEG1COM3 EQU H'0001' SEG0COM3 EQU H'0000' S7C3 EQU H'0007' S6C3 EQU H'0006' S5C3 EQU H'0005' S4C3 EQU H'0004' S3C3 EQU H'0003' S2C3 EQU H'0002' S1C3 EQU H'0001' S0C3 EQU H'0000' ;----- LCDDATA10 Bits ------------------------------------------------------- SEG15COM3 EQU H'0007' SEG14COM3 EQU H'0006' SEG13COM3 EQU H'0005' SEG12COM3 EQU H'0004' SEG11COM3 EQU H'0003' SEG10COM3 EQU H'0002' SEG9COM3 EQU H'0001' SEG8COM3 EQU H'0000' S15C3 EQU H'0007' S14C3 EQU H'0006' S13C3 EQU H'0005' S12C3 EQU H'0004' S11C3 EQU H'0003' S10C3 EQU H'0002' S9C3 EQU H'0001' S8C3 EQU H'0000' ;----- LCDDATA11 Bits ------------------------------------------------------- SEG23COM3 EQU H'0007' SEG22COM3 EQU H'0006' SEG21COM3 EQU H'0005' SEG20COM3 EQU H'0004' SEG19COM3 EQU H'0003' SEG18COM3 EQU H'0002' SEG17COM3 EQU H'0001' SEG16COM3 EQU H'0000' S23C3 EQU H'0007' S22C3 EQU H'0006' S21C3 EQU H'0005' S20C3 EQU H'0004' S19C3 EQU H'0003' S18C3 EQU H'0002' S17C3 EQU H'0001' S16C3 EQU H'0000' ;----- LCDDATA12 Bits ------------------------------------------------------- SEG31COM0 EQU H'0007' SEG30COM0 EQU H'0006' SEG29COM0 EQU H'0005' SEG28COM0 EQU H'0004' SEG27COM0 EQU H'0003' SEG26COM0 EQU H'0002' SEG25COM0 EQU H'0001' SEG24COM0 EQU H'0000' S31C0 EQU H'0007' S30C0 EQU H'0006' S29C0 EQU H'0005' S28C0 EQU H'0004' S27C0 EQU H'0003' S26C0 EQU H'0002' S25C0 EQU H'0001' S24C0 EQU H'0000' ;----- LCDDATA13 Bits ------------------------------------------------------- SEG39COM0 EQU H'0007' SEG38COM0 EQU H'0006' SEG37COM0 EQU H'0005' SEG36COM0 EQU H'0004' SEG35COM0 EQU H'0003' SEG34COM0 EQU H'0002' SEG33COM0 EQU H'0001' SEG32COM0 EQU H'0000' S39C0 EQU H'0007' S38C0 EQU H'0006' S37C0 EQU H'0005' S36C0 EQU H'0004' S35C0 EQU H'0003' S34C0 EQU H'0002' S33C0 EQU H'0001' S32C0 EQU H'0000' ;----- LCDDATA14 Bits ------------------------------------------------------- SEG41COM0 EQU H'0001' SEG40COM0 EQU H'0000' S41C0 EQU H'0001' S40C0 EQU H'0000' ;----- LCDDATA15 Bits ------------------------------------------------------- SEG31COM1 EQU H'0007' SEG30COM1 EQU H'0006' SEG29COM1 EQU H'0005' SEG28COM1 EQU H'0004' SEG27COM1 EQU H'0003' SEG26COM1 EQU H'0002' SEG25COM1 EQU H'0001' SEG24COM1 EQU H'0000' S31C1 EQU H'0007' S30C1 EQU H'0006' S29C1 EQU H'0005' S28C1 EQU H'0004' S27C1 EQU H'0003' S26C1 EQU H'0002' S25C1 EQU H'0001' S24C1 EQU H'0000' ;----- LCDDATA16 Bits ------------------------------------------------------- SEG39COM1 EQU H'0007' SEG38COM1 EQU H'0006' SEG37COM1 EQU H'0005' SEG36COM1 EQU H'0004' SEG35COM1 EQU H'0003' SEG34COM1 EQU H'0002' SEG33COM1 EQU H'0001' SEG32COM1 EQU H'0000' S39C1 EQU H'0007' S38C1 EQU H'0006' S37C1 EQU H'0005' S36C1 EQU H'0004' S35C1 EQU H'0003' S34C1 EQU H'0002' S33C1 EQU H'0001' S32C1 EQU H'0000' ;----- LCDDATA17 Bits ------------------------------------------------------- SEG41COM1 EQU H'0001' SEG40COM1 EQU H'0000' S41C1 EQU H'0001' S40C1 EQU H'0000' ;----- LCDDATA18 Bits ------------------------------------------------------- SEG31COM2 EQU H'0007' SEG30COM2 EQU H'0006' SEG29COM2 EQU H'0005' SEG28COM2 EQU H'0004' SEG27COM2 EQU H'0003' SEG26COM2 EQU H'0002' SEG25COM2 EQU H'0001' SEG24COM2 EQU H'0000' S31C2 EQU H'0007' S30C2 EQU H'0006' S29C2 EQU H'0005' S28C2 EQU H'0004' S27C2 EQU H'0003' S26C2 EQU H'0002' S25C2 EQU H'0001' S24C2 EQU H'0000' ;----- LCDDATA19 Bits ------------------------------------------------------- SEG39COM2 EQU H'0007' SEG38COM2 EQU H'0006' SEG37COM2 EQU H'0005' SEG36COM2 EQU H'0004' SEG35COM2 EQU H'0003' SEG34COM2 EQU H'0002' SEG33COM2 EQU H'0001' SEG32COM2 EQU H'0000' S39C2 EQU H'0007' S38C2 EQU H'0006' S37C2 EQU H'0005' S36C2 EQU H'0004' S35C2 EQU H'0003' S34C2 EQU H'0002' S33C2 EQU H'0001' S32C2 EQU H'0000' ;----- LCDDATA20 Bits ------------------------------------------------------- SEG41COM2 EQU H'0001' SEG40COM2 EQU H'0000' S41C2 EQU H'0001' S40C2 EQU H'0000' ;----- LCDDATA21 Bits ------------------------------------------------------- SEG31COM3 EQU H'0007' SEG30COM3 EQU H'0006' SEG29COM3 EQU H'0005' SEG28COM3 EQU H'0004' SEG27COM3 EQU H'0003' SEG26COM3 EQU H'0002' SEG25COM3 EQU H'0001' SEG24COM3 EQU H'0000' S31C3 EQU H'0007' S30C3 EQU H'0006' S29C3 EQU H'0005' S28C3 EQU H'0004' S27C3 EQU H'0003' S26C3 EQU H'0002' S25C3 EQU H'0001' S24C3 EQU H'0000' ;----- LCDDATA22 Bits ------------------------------------------------------- SEG39COM3 EQU H'0007' SEG38COM3 EQU H'0006' SEG37COM3 EQU H'0005' SEG36COM3 EQU H'0004' SEG35COM3 EQU H'0003' SEG34COM3 EQU H'0002' SEG33COM3 EQU H'0001' SEG32COM3 EQU H'0000' S39C3 EQU H'0007' S38C3 EQU H'0006' S37C3 EQU H'0005' S36C3 EQU H'0004' S35C3 EQU H'0003' S34C3 EQU H'0002' S33C3 EQU H'0001' S32C3 EQU H'0000' ;----- LCDDATA23 Bits ------------------------------------------------------- SEG41COM3 EQU H'0001' SEG40COM3 EQU H'0000' S41C3 EQU H'0001' S40C3 EQU H'0000' ;----- LCDSE0 Bits -------------------------------------------------------- SE7 EQU H'0007' SE6 EQU H'0006' SE5 EQU H'0005' SE4 EQU H'0004' SE3 EQU H'0003' SE2 EQU H'0002' SE1 EQU H'0001' SE0 EQU H'0000' SEGEN7 EQU H'0007' SEGEN6 EQU H'0006' SEGEN5 EQU H'0005' SEGEN4 EQU H'0004' SEGEN3 EQU H'0003' SEGEN2 EQU H'0002' SEGEN1 EQU H'0001' SEGEN0 EQU H'0000' ;----- LCDSE1 Bits -------------------------------------------------------- SE15 EQU H'0007' SE14 EQU H'0006' SE13 EQU H'0005' SE12 EQU H'0004' SE11 EQU H'0003' SE10 EQU H'0002' SE9 EQU H'0001' SE8 EQU H'0000' SEGEN15 EQU H'0007' SEGEN14 EQU H'0006' SEGEN13 EQU H'0005' SEGEN12 EQU H'0004' SEGEN11 EQU H'0003' SEGEN10 EQU H'0002' SEGEN9 EQU H'0001' SEGEN8 EQU H'0000' ;----- LCDSE2 Bits -------------------------------------------------------- SE23 EQU H'0007' SE22 EQU H'0006' SE21 EQU H'0005' SE20 EQU H'0004' SE19 EQU H'0003' SE18 EQU H'0002' SE17 EQU H'0001' SE16 EQU H'0000' SEGEN23 EQU H'0007' SEGEN22 EQU H'0006' SEGEN21 EQU H'0005' SEGEN20 EQU H'0004' SEGEN19 EQU H'0003' SEGEN18 EQU H'0002' SEGEN17 EQU H'0001' SEGEN16 EQU H'0000' ;----- LCDSE3 Bits -------------------------------------------------------- SE31 EQU H'0007' SE30 EQU H'0006' SE29 EQU H'0005' SE28 EQU H'0004' SE27 EQU H'0003' SE26 EQU H'0002' SE25 EQU H'0001' SE24 EQU H'0000' SEGEN31 EQU H'0007' SEGEN30 EQU H'0006' SEGEN29 EQU H'0005' SEGEN28 EQU H'0004' SEGEN27 EQU H'0003' SEGEN26 EQU H'0002' SEGEN25 EQU H'0001' SEGEN24 EQU H'0000' ;----- LCDSE4 Bits -------------------------------------------------------- SE39 EQU H'0007' SE38 EQU H'0006' SE37 EQU H'0005' SE36 EQU H'0004' SE35 EQU H'0003' SE34 EQU H'0002' SE33 EQU H'0001' SE32 EQU H'0000' SEGEN39 EQU H'0007' SEGEN38 EQU H'0006' SEGEN37 EQU H'0005' SEGEN36 EQU H'0004' SEGEN35 EQU H'0003' SEGEN34 EQU H'0002' SEGEN33 EQU H'0001' SEGEN32 EQU H'0000' ;----- LCDSE5 Bits -------------------------------------------------------- SE41 EQU H'0001' SE40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN40 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' EEWR EQU H'0001' RD EQU H'0000' EERD EQU H'0000' ;----- EEADRH Bits -------------------------------------------------------- EEADRH4 EQU H'0004' EEADRH3 EQU H'0003' EEADRH2 EQU H'0002' EEADRH1 EQU H'0001' EEADRH0 EQU H'0000' ;----- EEADRL Bits -------------------------------------------------------- EEADRL7 EQU H'0007' EEADRL6 EQU H'0006' EEADRL5 EQU H'0005' EEADRL4 EQU H'0004' EEADRL3 EQU H'0003' EEADRL2 EQU H'0002' EEADRL1 EQU H'0001' EEADRL0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'9A'-H'9B' __BADRAM H'11F' __BADRAM H'18E'-H'18F', H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG EQU H'2007' ;Configuration Byte 1 Options _DEBUG_ON EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16f884.inc0000644000175000017500000005605711156521302013166 00000000000000 LIST ; P16F884.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F884 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F884 ; 2. LIST directive in the source file ; LIST P=PIC16F884 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ; ;1.00 11/18/05 Original ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F884 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' MSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' VRCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' PWM1CON EQU H'009B' ECCPAS EQU H'009C' PSTRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' CM1CON0 EQU H'0107' CM2CON0 EQU H'0108' CM2CON1 EQU H'0109' EEDATA EQU H'010C' EEDAT EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' SRCON EQU H'0185' BAUDCTL EQU H'0187' ANSEL EQU H'0188' ANSELH EQU H'0189' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' BCLIF EQU H'0003' ULPWUIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GIV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' CCP1X EQU H'0005' ; Backward compatibility only DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' ; Backward compatibility only DC2B1 EQU H'0005' CCP2Y EQU H'0004' ; Backward compatibility only DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' BCLIE EQU H'0003' ULPWUIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- IOCB Bits ---------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' C1RSEL EQU H'0005' C2RSEL EQU H'0004' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' FVREN EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS13 EQU H'0005' ANS12 EQU H'0004' ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'110'-H'11F' __BADRAM H'18E'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word1 ------------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'2FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word2 ------------------------------------------------ _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _BOR21V EQU H'3EFF' _BOR40V EQU H'3FFF' LIST gputils-0.13.7/header/p16f785.inc0000644000175000017500000004273311156521301013161 00000000000000 LIST ; P16F785.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F785 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F785 ; 2. LIST directive in the source file ; LIST P=PIC16F785 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 03/26/04 Original ;1.10 07/12/04 Updated for changes to REFCON and VRCON ;1.20 08/26/04 Updated for changes from BOD to BOR ;1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON ;1.40 10/25/04 Added WPUA3 bit to WPUA register ; Deleted OVRLP bit from PWMCON1 register ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F785 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' WDTCON EQU H'0018' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' ANSEL0 EQU H'0091' PR2 EQU H'0092' ANSEL1 EQU H'0093' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' REFCON EQU H'0098' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' PWMCON1 EQU H'0110' PWMCON0 EQU H'0111' PWMCLK EQU H'0112' PWMPH1 EQU H'0113' PWMPH2 EQU H'0114' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' OPA1CON EQU H'011C' OPA2CON EQU H'011D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CCP1IF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' OSFIF EQU H'0002' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CCP1IE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' OSFIE EQU H'0002' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBODEN EQU H'0004' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits or ANSEL0 Bits ------------------------------------------ ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSEL1 Bits -------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA3 EQU H'0003' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- BGST EQU H'0005' VRBB EQU H'0004' VREN EQU H'0003' VROE EQU H'0002' CVROE EQU H'0001' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- PWMCON1 Bits -------------------------------------------------------- COMOD1 EQU H'0006' COMOD0 EQU H'0005' CMDLY4 EQU H'0004' CMDLY3 EQU H'0003' CMDLY2 EQU H'0002' CMDLY1 EQU H'0001' CMDLY0 EQU H'0000' ;----- PWMCON0 Bits -------------------------------------------------------- PRSEN EQU H'0007' PASEN EQU H'0006' BLANK2 EQU H'0005' BLANK1 EQU H'0004' SYNC1 EQU H'0003' SYNC0 EQU H'0002' PH2EN EQU H'0001' PH1EN EQU H'0000' ;----- PWMCLK Bits -------------------------------------------------------- PWMASE EQU H'0007' PWMP1 EQU H'0006' PWMP0 EQU H'0005' PER4 EQU H'0004' PER3 EQU H'0003' PER2 EQU H'0002' PER1 EQU H'0001' PER0 EQU H'0000' ;----- PWMPH1 Bits & PWMPH2 Bits ------------------------------------------ POL EQU H'0007' C2EN EQU H'0006' C1EN EQU H'0005' PH4 EQU H'0004' PH3 EQU H'0003' PH2 EQU H'0002' PH1 EQU H'0001' PH0 EQU H'0000' ;----- CM1CON0 Bits -------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1SP EQU H'0003' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits -------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2SP EQU H'0003' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits -------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- OPA1CON Bits & OPA2CON Bits ----------------------------------------- OPAON EQU H'0007' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D' __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF' __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F' __BADRAM H'188'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBOREN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16c554.inc0000644000175000017500000001063611156313161013150 00000000000000 LIST ; P16C554.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C554 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C554 ; 2. LIST directive in the source file ; LIST P=PIC16C554 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/22/96 Initial Creation ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C554 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PCON EQU H'008E' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'09F' __BADRAM H'07'-H'09', H'0C'-H'1F', H'70'-H'7F' __BADRAM H'87'-H'89', H'8C'-H'8D', H'8F'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'00CF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f8390.inc0000644000175000017500000017646211156521301013252 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8390 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8390 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8390 ; 2. LIST directive in the source file ; LIST P=PIC18F8390 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8390 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDSE4 EQU H'0F5E' LCDSE5 EQU H'0F5F' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG32 EQU H'0000' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F7D' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18lf45j50.inc0000644000175000017500000017424311156521301013565 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF45J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF45J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF45J50 ; 2. LIST directive in the source file ; LIST P=PIC18LF45J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF45J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c73a.inc0000644000175000017500000002752711156313161013234 00000000000000 LIST ; P16C73A.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C73A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C73A ; 2. LIST directive in the source file ; LIST P=PIC16C73A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.02 05/17/96 Updated BADRAM map ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C73A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f676.inc0000644000175000017500000002171711156521301013157 00000000000000 LIST ; P16F676.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F676 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F676 ; 2. LIST directive in the source file ; LIST P=PIC16F676 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 05/13/02 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F676 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' ANSEL EQU H'0091' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEDAT EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F' __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16c64.inc0000644000175000017500000002155411156313161013065 00000000000000 LIST ; P16C64.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C64 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C64 ; 2. LIST directive in the source file ; LIST P=PIC16C64 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 04/22/96 Added TRISE bits ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C64 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'0D', H'18'-H'1F', H'8D', H'8F'-H'91', H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3F8F' _CP_75 EQU H'3F9F' _CP_50 EQU H'3FAF' _CP_OFF EQU H'3FBF' _PWRTE_ON EQU H'3FBF' _PWRTE_OFF EQU H'3FB7' _WDT_ON EQU H'3FBF' _WDT_OFF EQU H'3FBB' _LP_OSC EQU H'3FBC' _XT_OSC EQU H'3FBD' _HS_OSC EQU H'3FBE' _RC_OSC EQU H'3FBF' LIST gputils-0.13.7/header/p12f509.inc0000644000175000017500000000750511156313161013150 00000000000000 LIST ; P12F509.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F509 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12F509 ; 2. LIST directive in the source file ; LIST P=12F509 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/09/03 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F509 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16hv610.inc0000644000175000017500000003130211156521301013322 00000000000000 LIST ; P16HV610.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; Based on P16F610.INC ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16HV610 microcontroller. These names are taken to ; match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16HV610 ; 2. LIST directive in the source file ; LIST P=PIC16HV610 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 07/10/06 Original ;1.01 12/04/06 Added WPU, BOR and IOC aliases ;1.02 01/15/07 Added TRISA & TRISC bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16HV610 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' VRCON EQU H'0019' CM1CON0 EQU H'001A' CM2CON0 EQU H'001B' CM2CON1 EQU H'001C' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' ANSEL EQU H'0091' WPUA EQU H'0095' WPU EQU H'0095' IOCA EQU H'0096' IOC EQU H'0096' SRCON0 EQU H'0099' SRCON1 EQU H'009A' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- PORTC Bits --------------------------------------------------------- RC5 EQU H'0005' RC4 EQU H'0004' RC3 EQU H'0003' RC2 EQU H'0002' RC1 EQU H'0001' RC0 EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- C2IF EQU H'0004' C1IF EQU H'0003' TMR1IF EQU H'0000' T1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' FVREN EQU H'0004' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1ACS EQU H'0004' C1HYS EQU H'0003' C2HYS EQU H'0002' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISC Bits -------------------------------------------------------- TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- C2IE EQU H'0004' C1IE EQU H'0003' TMR1IE EQU H'0000' T1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- WPU Bits --------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- SRCON0 Bits ------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' SRCLKEN EQU H'0000' ;----- SRCON1 Bits ------------------------------------------------------- SRCS1 EQU H'0007' SRCS0 EQU H'0006' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'11' -H'18', H'1D'-H'1F', H'20' -H'3F' __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'9B' -H'9F', H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOD_ON EQU H'3FFF' _BOR_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOR_NSLEEP EQU H'3EFF' _BOD_OFF EQU H'3CFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f65j10.inc0000644000175000017500000013047111156521301013402 00000000000000 LIST ;========================================================================== ; MPASM PIC18F65J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F65J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F65J10 ; 2. LIST directive in the source file ; LIST P=PIC18F65J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F65J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f67j10.inc0000644000175000017500000013043011156521301013377 00000000000000 LIST ;========================================================================== ; MPASM PIC18F67J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F67J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F67J10 ; 2. LIST directive in the source file ; LIST P=PIC18F67J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F67J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f4420.inc0000644000175000017500000012316611156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4420 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4420 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4420 ; 2. LIST directive in the source file ; LIST P=PIC18F4420 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4420 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCPAS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCPAS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p10f200.inc0000644000175000017500000001033111156313161013121 00000000000000 LIST ; P10F200.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC10f200 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P10F200 ; 2. LIST directive in the source file ; LIST P=10F200 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/14/04 Initial Release ;1.01 07/07/04 Add bad ram ;1.02 10/05/05 Add IntRC_OSC comment ;1.03 01/13/06 Added GPIO bit descriptions ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __10F200 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' FOSC4 EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' __BADRAM H'07'-H'0F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _IntRC_OSC EQU H'0FFF';IntRC_OSC is the only option. ;It is here for backwards compatibility ;only. LIST gputils-0.13.7/header/p18f4553.inc0000644000175000017500000015437611156521301013247 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4553 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4553 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4553 ; 2. LIST directive in the source file ; LIST P=PIC18F4553 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4553 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SPPDATA EQU H'0F62' SPPCFG EQU H'0F63' SPPEPS EQU H'0F64' SPPCON EQU H'0F65' UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SPPCFG Bits ----------------------------------------------------- WS0 EQU H'0000' WS1 EQU H'0001' WS2 EQU H'0002' WS3 EQU H'0003' CLK1EN EQU H'0004' CSEN EQU H'0005' CLKCFG0 EQU H'0006' CLKCFG1 EQU H'0007' ;----- SPPEPS Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' SPPBUSY EQU H'0004' WRSPP EQU H'0006' RDSPP EQU H'0007' ;----- SPPCON Bits ----------------------------------------------------- SPPEN EQU H'0000' SPPOWN EQU H'0001' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SPP0 EQU H'0000' SPP1 EQU H'0001' SPP2 EQU H'0002' SPP3 EQU H'0003' SPP4 EQU H'0004' SPP5 EQU H'0005' SPP6 EQU H'0006' SPP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RDPU EQU H'0007' CK1SPP EQU H'0000' CK2SPP EQU H'0001' OESPP EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SPPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SPPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SPPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPRT = OFF ICPORT disabled ; ICPRT = ON ICPORT enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _ICPRT_OFF_4L EQU H'DF' ; ICPORT disabled _ICPRT_ON_4L EQU H'FF' ; ICPORT enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f6622.inc0000644000175000017500000017220711156521301013237 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6622 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6622 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6622 ; 2. LIST directive in the source file ; LIST P=PIC18F6622 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6622 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f639.inc0000644000175000017500000002557411156521301013163 00000000000000 LIST ; P16F639.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F639 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F639 ; 2. LIST directive in the source file ; LIST P=PIC16F639 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/28/04 Original based on P16F636.INC ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F639 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ ;Bank 0 INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' WDTCON EQU H'0018' CMCON0 EQU H'0019' CMCON1 EQU H'001A' ;Bank 1 OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' LVDCON EQU H'0094' WPUDA EQU H'0095' IOCA EQU H'0096' WDA EQU H'0097' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ;Bank 2 CRCON EQU H'0110' CRDAT0 EQU H'0111' CRDAT1 EQU H'0112' CRDAT2 EQU H'0113' CRDAT3 EQU H'0114' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' LVDIF EQU H'0006' CRIF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' OSFIF EQU H'0002' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' LVDIE EQU H'0006' CRIE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' OSFIE EQU H'0002' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBODEN EQU H'0004' NOT_WUR EQU H'0003' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits ---------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CRCON Bits -------------------------------------------------------- GO EQU H'0007' ENC_DEC EQU H'0006' CRREG1 EQU H'0001' CRREG0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDA Bits ----------------------------------------------------------- WDA5 EQU H'0005' WDA4 EQU H'0004' WDA2 EQU H'0002' WDA1 EQU H'0001' WDA0 EQU H'0000' ;----- WPUDA Bits ----------------------------------------------------------- WPUDA5 EQU H'0005' WPUDA4 EQU H'0004' WPUDA2 EQU H'0002' WPUDA1 EQU H'0001' WPUDA0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F' __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF' __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186' __BADRAM H'188'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _WUREN_ON EQU H'2FFF' _WUREN_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18macro.inc0000644000175000017500000004721111156521301013567 00000000000000; $Id: P18MACRO.INC,v 1.1 2003/12/17 19:32:43 sealep Exp $ ;========================================================================== ; ; MACROS ; ;========================================================================== LIST StkSetPtrToOffset macro Ptr,Offset ; Set pointer Ptr to argument in stack frame at Offset. movlw LOW(Offset) addwf FSR1L,W,ACCESS movwf Ptr,ACCESS movlw HIGH(Offset&0xFFFF) addwfc FSR1H,W,ACCESS movwf Ptr+1 endm StkPushPtrToOffset macro Offset ; Push pointer onto stack to point to Offset location in stack. ; Offset defined before push. movlw LOW(Offset) addwf FSR1L,W,ACCESS movwf INDF1,ACCESS movlw HIGH(Offset&0xFFFF) addwfc FSR1H,W,ACCESS movwf PREINC1,ACCESS movf POSTINC1,F,ACCESS ; increment FSR1 endm StkAddStackPtr macro N ; Add N to FSR1 movlw LOW(N) addwf FSR1L,F,ACCESS movlw HIGH(N&0xFFFF) addwfc FSR1H,F,ACCESS endm Stk1PushFromFSR0 macro ; Get one byte from FSR0 and push on stack. FSR0, WREG unchanged. movff INDF0,POSTINC1 endm Stk2PushFromFSR0 macro ; Get two bytes from FSR0 and push on stack. FSR0, WREG unchanged. movff POSTINC0,POSTINC1 movff POSTDEC0,POSTINC1 endm Stk3PushFromFSR0 macro ; Get three bytes from FSR0 and push on stack. FSR0, WREG unchanged. movff POSTINC0,POSTINC1 movff POSTINC0,POSTINC1 movff POSTDEC0,POSTINC1 movf POSTDEC0,F,ACCESS endm Stk1PushFromFSR2 macro ; Get one byte from FSR2 and push on stack. FSR2, WREG unchanged. movff INDF2,POSTINC1 endm Stk2PushFromFSR2 macro ; Get two bytes from FSR2 and push on stack. FSR2, WREG unchanged. movff POSTINC2,POSTINC1 movff POSTDEC2,POSTINC1 endm Stk3PushFromFSR2 macro ; Get three bytes from FSR2 and push on stack. FSR2, WREG unchanged. movff POSTINC2,POSTINC1 movff POSTINC2,POSTINC1 movff POSTDEC2,POSTINC1 movf POSTDEC2,F,ACCESS endm Stk1PushFromReg macro Reg ; Get one byte from Reg and push on stack. WREG unchanged. movff Reg,POSTINC1 endm Stk2PushFromReg macro Reg ; Get two bytes from Reg and push on stack. WREG unchanged. movff Reg,POSTINC1 movff Reg+1,POSTINC1 endm Stk3PushFromReg macro Reg ; Get three bytes from Reg and push on stack. WREG unchanged. movff Reg,POSTINC1 movff Reg+1,POSTINC1 movff Reg+2,POSTINC1 endm Stk1PopToFSR0 macro ; Pop one byte from stack and put it at FSR0 without exposing stack. ; WREG changed, FSR0 unchanged. movlw 0xFF movff PLUSW1,INDF0 movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk2PopToFSR0 macro ; Pop two bytes from stack and put them at FSR0 without exposing stack. ; WREG changed, FSR0 unchanged. movlw 0xFE movff PLUSW1,POSTINC0 movlw 0xFF movff PLUSW1,POSTDEC0 movf POSTDEC1,F,ACCESS ; decrement FSR1 movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk3PopToFSR0 macro ; Pop three bytes from stack and put them at FSR0 without exposing stack. ; WREG changed, FSR0 unchanged. movlw 0xFD movff PLUSW1,POSTINC0 movlw 0xFE movff PLUSW1,POSTINC0 movlw 0xFF movff PLUSW1,POSTDEC0 movf POSTDEC0,F,ACCESS ; restore FSR0 movf POSTDEC1,F,ACCESS ; decrement FSR1 movf POSTDEC1,F,ACCESS ; decrement FSR1 movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk1PopToFSR2 macro ; Pop one byte from stack and put it at FSR2 without exposing stack. ; WREG changed, FSR2 unchanged. movlw 0xFF movff PLUSW1,INDF2 movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk2PopToFSR2 macro ; Pop two bytes from stack and put them at FSR2 without exposing stack. ; WREG changed, FSR2 unchanged. movlw 0xFE movff PLUSW1,POSTINC2 movlw 0xFF movff PLUSW1,POSTDEC2 movf POSTDEC1,F,ACCESS ; decrement FSR1 movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk3PopToFSR2 macro ; Pop three bytes from stack and put them at FSR2 without exposing stack. ; WREG changed, FSR2 unchanged. movlw 0xFD movff PLUSW1,POSTINC2 movlw 0xFE movff PLUSW1,POSTINC2 movlw 0xFF movff PLUSW1,POSTDEC2 movf POSTDEC2,F,ACCESS ; restore FSR2 movf POSTDEC1,F,ACCESS ; decrement FSR1 movf POSTDEC1,F,ACCESS ; decrement FSR1 movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk1PopToReg macro Reg ; Pop one byte from stack and put it at Reg without exposing stack. ; WREG changed. movlw 0xFF movff PLUSW1,Ptr movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk2PopToReg macro Reg ; Pop two bytes from stack and put them at Reg without exposing stack. ; WREG changed. movlw 0xFF movff PLUSW1,Reg+1 movf POSTDEC1,F,ACCESS ; decrement FSR1 movlw 0xFF movff PLUSW1,Reg movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk3PopToReg macro Reg ; Pop three bytes from stack and put them at Reg without exposing stack. ; WREG changed. movlw 0xFF movff PLUSW1,Reg+2 movf POSTDEC1,F,ACCESS ; decrement FSR1 movlw 0xFF movff PLUSW1,Reg+1 movf POSTDEC1,F,ACCESS ; decrement FSR1 movlw 0xFF movff PLUSW1,Reg movf POSTDEC1,F,ACCESS ; decrement FSR1 endm Stk1CpyToFSR0 macro Offset ; Copy one byte from stack frame at Offset to FSR0 ; WREG changed, FSR0 unchanged. movlw LOW(Offset) movff PLUSW1,INDF0 endm Stk2CpyToFSR0 macro Offset ; Copy two bytes from stack frame at Offset to FSR0 ; WREG changed, FSR0 unchanged. movlw LOW(Offset) movff PLUSW1,POSTINC0 movlw LOW(Offset+1) movff PLUSW1,POSTDEC0 endm Stk1CpyToFSR2 macro Offset ; Copy one byte from stack frame at Offset to FSR2 ; WREG changed, FSR2 unchanged. movlw LOW(Offset) movff PLUSW1,INDF2 endm Stk2CpyToFSR2 macro Offset ; Copy two bytes from stack frame at Offset to FSR2 ; WREG changed, FSR2 unchanged. movlw LOW(Offset) movff PLUSW1,POSTINC2 movlw LOW(Offset+1) movff PLUSW1,POSTDEC2 endm Stk4CpyToFSR2 macro Offset ; Copy four bytes from stack frame at Offset to FSR2 ; WREG changed, FSR2 unchanged. movlw LOW(Offset) movff PLUSW1,POSTINC2 movlw LOW(Offset+1) movff PLUSW1,POSTINC2 movlw LOW(Offset+2) movff PLUSW1,POSTINC2 movlw LOW(Offset+3) movff PLUSW1,POSTDEC2 movf POSTDEC2,F,ACCESS movf POSTDEC2,F,ACCESS endm Stk1CpyToReg macro Offset,Reg ; Copy one byte from stack frame at Offset to Reg movlw LOW(Offset) movff PLUSW1,Reg endm Stk2CpyToReg macro Offset,Reg ; Copy two bytes from stack frame at Offset to Reg movlw LOW(Offset) movff PLUSW1,Reg movlw LOW(Offset+1) movff PLUSW1,Reg+1 endm Stk3CpyToReg macro Offset,Reg ; Copy three bytes from stack frame at Offset to Reg movlw LOW(Offset) movff PLUSW1,Reg movlw LOW(Offset+1) movff PLUSW1,Reg+1 movlw LOW(Offset+2) movff PLUSW1,Reg+2 endm Stk1CpyFromFSR0 macro Offset ; Copy one byte from FSR0 to stack frame at Offset movlw LOW(Offset) movff INDF0,PLUSW1 endm Stk2CpyFromFSR0 macro Offset ; Copy two bytes from FSR0 to stack frame at Offset movlw Offset movff POSTINC0,PLUSW1 movlw Offset+1 movff POSTDEC0,PLUSW1 endm Stk3CpyFromFSR0 macro Offset ; Copy three bytes from FSR0 to stack frame at Offset movlw Offset movff POSTINC0,PLUSW1 movlw Offset+1 movff POSTDEC0,PLUSW1 movlw Offset+2 movff POSTDEC0,PLUSW1 endm Stk4CpyFromFSR0 macro Offset ; Copy four bytes from FSR0 to stack frame at Offset movlw Offset movff POSTINC0,PLUSW1 movlw Offset+1 movff POSTINC0,PLUSW1 movlw Offset+2 movff POSTINC0,PLUSW1 movlw Offset+3 movff POSTDEC0,PLUSW1 movf POSTDEC0,F,ACCESS movf POSTDEC0,F,ACCESS endm Stk1CpyFromFSR2 macro Offset ; Copy one byte from FSR2 to stack frame at Offset movlw LOW(Offset) movff INDF2,PLUSW1 endm Stk2CpyFromFSR2 macro Offset ; Copy two bytes from FSR2 to stack frame at Offset movlw Offset movff POSTINC2,PLUSW1 movlw Offset+1 movff POSTDEC2,PLUSW1 endm Stk4CpyFromFSR2 macro Offset ; Copy four bytes from FSR2 to stack frame at Offset movlw Offset movff POSTINC2,PLUSW1 movlw Offset+1 movff POSTINC2,PLUSW1 movlw Offset+2 movff POSTINC2,PLUSW1 movlw Offset+3 movff POSTDEC2,PLUSW1 movf POSTDEC2,F,ACCESS movf POSTDEC2,F,ACCESS endm Stk1CpyFromReg macro Reg,Offset ; Copy one byte from Reg to stack frame at Offset movlw LOW(Offset) movff Reg,PLUSW1 endm Stk2CpyFromReg macro Reg,Offset ; Copy two bytes from Reg to stack frame at Offset movlw Offset movff Reg,PLUSW1 movlw Offset+1 movff Reg+1,PLUSW1 endm Stk3CpyFromReg macro Reg,Offset ; Copy three bytes from Reg to stack frame at Offset movlw Offset movff Reg,PLUSW1 movlw Offset+1 movff Reg+1,PLUSW1 movlw Offset+2 movff Reg+2,PLUSW1 endm Stk1Inc macro Offset ; Increment byte in stack at Offset movlw Offset incf PLUSW1,F,ACCESS endm Stk2Inc macro Offset ; Increment 2 bytes in stack at Offset movlw Offset incf PLUSW1,F,ACCESS movlw Offset+1 btfsc STATUS,Z incf PLUSW1,F,ACCESS endm Stk3Inc macro Offset ; Increment 3 bytes in stack at Offset local jEnd movlw Offset incf PLUSW1,F,ACCESS bnz jEnd movlw Offset+1 incf PLUSW1,F,ACCESS bnz jEnd movlw Offset+2 incf PLUSW1,F,ACCESS jEnd: endm Stk1Dec macro Offset ; Decrement byte in stack at Offset movlw Offset decf PLUSW1,F,ACCESS endm Stk2Dec macro Offset ; Decrement 2 bytes in stack at Offset local jEnd movlw Offset decf PLUSW1,F,ACCESS bc jEnd movlw Offset+1 decf PLUSW1,F,ACCESS jEnd: endm Stk3Dec macro Offset ; Decrement 3 bytes in stack at Offset local jEnd movlw Offset decf PLUSW1,F,ACCESS bc jEnd movlw Offset+1 decf PLUSW1,F,ACCESS bc jEnd movlw Offset+2 decf PLUSW1,F,ACCESS jEnd: endm Stk1TestForZero macro Offset,jZero ; Test 1 byte at Offset. Branch if zero. Returns 0 in WREG if zero. movlw Offset movf PLUSW1,W,ACCESS bz jZero endm Stk2TestForZero macro Offset,jZero ; Test 2 bytes at Offset. Branch if zero. Returns 0 in WREG if zero. local jContinue movlw Offset movf PLUSW1,W,ACCESS bnz jContinue movlw Offset+1 movf PLUSW1,W,ACCESS bz jZero jContinue endm Stk3TestForZero macro Offset,jZero ; Test 3 bytes at Offset. Branch if zero. Returns 0 in WREG if zero. local jContinue movlw Offset movf PLUSW1,W,ACCESS bnz jContinue movlw Offset+1 movf PLUSW1,W,ACCESS bnz jContinue movlw Offset+2 movf PLUSW1,W,ACCESS bz jZero jContinue endm Stk1AddToFSR0 macro Offset ; Add 1 byte in stack at Offset to byte at FSR0. Pointer FSR0 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf INDF0,F,ACCESS endm Stk2AddToFSR0 macro Offset ; Add 2 bytes in stack at Offset to 2 bytes at FSR0. Pointer FSR0 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf POSTINC0,F,ACCESS movlw Offset+1 movf PLUSW1,W,ACCESS addwfc POSTDEC0,F,ACCESS endm Stk3AddToFSR0 macro Offset ; Add 3 bytes in stack at Offset to 3 bytes at FSR0. Pointer FSR0 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf POSTINC0,F,ACCESS movlw Offset+1 movf PLUSW1,W,ACCESS addwfc POSTINC0,F,ACCESS movlw Offset+2 movf PLUSW1,W,ACCESS addwfc POSTDEC0,F,ACCESS movf POSTDEC0,F,ACCESS endm Stk4AddToFSR0 macro Offset ; Add 4 bytes in stack at Offset to 4 bytes at FSR0. Pointer FSR0 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf POSTINC0,F,ACCESS movlw Offset+1 movf PLUSW1,W,ACCESS addwfc POSTINC0,F,ACCESS movlw Offset+2 movf PLUSW1,W,ACCESS addwfc POSTINC0,F,ACCESS movlw Offset+3 movf PLUSW1,W,ACCESS addwfc POSTDEC0,F,ACCESS movf POSTDEC0,F,ACCESS movf POSTDEC0,F,ACCESS endm Stk1AddToFSR2 macro Offset ; Add 1 byte in stack at Offset to byte at FSR2. Pointer FSR2 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf INDF2,F,ACCESS endm Stk2AddToFSR2 macro Offset ; Add 2 bytes in stack at Offset to 2 bytes at FSR2. Pointer FSR2 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf POSTINC2,F,ACCESS movlw Offset+1 movf PLUSW1,W,ACCESS addwfc POSTDEC2,F,ACCESS endm Stk3AddToFSR2 macro Offset ; Add 3 bytes in stack at Offset to 3 bytes at FSR2. Pointer FSR2 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf POSTINC2,F,ACCESS movlw Offset+1 movf PLUSW1,W,ACCESS addwfc POSTINC2,F,ACCESS movlw Offset+2 movf PLUSW1,W,ACCESS addwfc POSTDEC2,F,ACCESS movf POSTDEC2,F,ACCESS endm Stk4AddToFSR2 macro Offset ; Add 4 bytes in stack at Offset to 4 bytes at FSR2. Pointer FSR2 unchanged. movlw Offset movf PLUSW1,W,ACCESS addwf POSTINC2,F,ACCESS movlw Offset+1 movf PLUSW1,W,ACCESS addwfc POSTINC2,F,ACCESS movlw Offset+2 movf PLUSW1,W,ACCESS addwfc POSTINC2,F,ACCESS movlw Offset+3 movf PLUSW1,W,ACCESS addwfc POSTDEC2,F,ACCESS movf POSTDEC2,F,ACCESS movf POSTDEC2,F,ACCESS endm Stk1ShiftLeft macro Offset ; Shift left 1 byte in stack at Offset bcf STATUS,C movlw Offset rlcf PLUSW1,F,ACCESS endm Stk2ShiftLeft macro Offset ; Shift left 2 bytes in stack at Offset bcf STATUS,C movlw Offset rlcf PLUSW1,F,ACCESS movlw Offset+1 rlcf PLUSW1,F,ACCESS endm Stk4ShiftLeft macro Offset ; Shift left 4 bytes in stack at Offset bcf STATUS,C movlw Offset rlcf PLUSW1,F,ACCESS movlw Offset+1 rlcf PLUSW1,F,ACCESS movlw Offset+2 rlcf PLUSW1,F,ACCESS movlw Offset+3 rlcf PLUSW1,F,ACCESS endm Stk1Negate macro Offset ; Negate 1 byte in stack at Offset movlw Offset comf PLUSW1,F,ACCESS incf PLUSW1,F,ACCESS endm Stk2Negate macro Offset ; Negate 2 bytesin stack at Offset movlw Offset comf PLUSW1,F,ACCESS incf PLUSW1,F,ACCESS movlw Offset+1 btfsc STATUS,Z decf PLUSW1,F,ACCESS comf PLUSW1,F,ACCESS endm Stk4Negate macro Offset ; Negate 4 bytes in stack at Offset local jEnd movlw Offset comf PLUSW1,F,ACCESS movlw Offset+1 comf PLUSW1,F,ACCESS movlw Offset+2 comf PLUSW1,F,ACCESS movlw Offset+3 comf PLUSW1,F,ACCESS movlw Offset incf PLUSW1,F,ACCESS bnz jEnd movlw Offset+1 incf PLUSW1,F,ACCESS bnz jEnd movlw Offset+2 incf PLUSW1,F,ACCESS bnz jEnd movlw Offset+3 incf PLUSW1,F,ACCESS jEnd: endm Stk1NegateFSR2 macro ; Negate 1 byte at FSR2. FSR2 unchanged. comf INDF2,F,ACCESS incf INDF2,F,ACCESS endm Stk2NegateFSR2 macro ; Negate 2 bytes at FSR2. FSR2 unchanged. comf INDF2,F,ACCESS incf POSTINC2,F,ACCESS btfsc STATUS,Z decf INDF2,F,ACCESS comf POSTDEC2,F,ACCESS endm ;====== These branches are short ============== jmpWeqZ macro Label ; jmp if W == 0 movf WREG,F,ACCESS bz Label endm jmpWneZ macro Label ; jmp if W != 0 tstfsz WREG,ACCESS bra Label endm jmpFeqZ macro Reg,Acc,Label movf Reg,F,Acc bz Label endm jmpFneZ macro Reg,Acc,Label movf Reg,F,Acc bnz Label endm jmpFeqL macro Reg,Acc,bVal,Label movlw bVal subwf Reg,W,Acc bz Label endm jmpFneL macro Reg,Acc,bVal,Label movlw bVal subwf Reg,W,Acc bnz Label endm jmpFleL macro Reg,Acc,bVal,Label movlw bVal cpfsgt Reg,Acc bra Label endm jmpFgeL macro Reg,Acc,bVal,Label movlw bVal cpfslt Reg,Acc bra Label endm jmpFeqF macro Reg1,Acc1,Reg2,Acc2,Label movf Reg1,W,Acc1 subwf Reg2,W,Acc2 bz Label endm jmpFneF macro Reg1,Acc1,Reg2,Acc2,Label movf Reg1,W,Acc1 subwf Reg2,W,Acc2 bnz Label endm jmpClr macro Reg,Bit,Acc,Label btfss Reg,Bit,Acc bra Label endm jmpSet macro Reg,Bit,Acc,Label btfsc Reg,Bit,Acc bra Label endm gputils-0.13.7/header/p18f87j50.inc0000644000175000017500000020340511156521301013410 00000000000000 LIST ;========================================================================== ; MPASM PIC18F87J50 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F87J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F87J50 ; 2. LIST directive in the source file ; LIST P=PIC18F87J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F87J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f8680.inc0000644000175000017500000042256611156521301013253 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8680 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8680 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8680 ; 2. LIST directive in the source file ; LIST P=PIC18F8680 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8680 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' ECCP1DEL EQU H'0F79' BAUDCON EQU H'0F7E' SPBRGH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' TXRTR EQU H'0006' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDM EQU H'0003' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXRTRR0 EQU H'0003' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RTRR0 EQU H'0005' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE0 EQU H'0001' ICODE1 EQU H'0002' ICODE2 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' TX2EN EQU H'0006' TX2SRC EQU H'0007' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' NOT_FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CANTX1 EQU H'0000' CANTX2 EQU H'0001' CANRX EQU H'0002' P1D EQU H'0004' MCLR EQU H'0005' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E2E'-H'0E2F' __BADRAM H'0E3E'-H'0E3F' __BADRAM H'0E4E'-H'0E4F' __BADRAM H'0E5E'-H'0E5F' __BADRAM H'0E6E'-H'0E6F' __BADRAM H'0E7E'-H'0EFF' __BADRAM H'0F2E'-H'0F2F' __BADRAM H'0F3E'-H'0F3F' __BADRAM H'0F4E'-H'0F4F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F78' __BADRAM H'0F7A'-H'0F7D' __BADRAM H'0F9B' __BADRAM H'0FB7'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC RC oscillator with OSC2 configured as divide by 4 clock output ; OSC = EC EC oscillator with OSC2 configured as divide by 4 clock output ; OSC = ECIO EC oscillator with OSC2 configured as RA6 ; OSC = HSPLL HS oscillator with HW enabled 4x PLL ; OSC = RCIO RC oscillator with OSC2 configured as RA6 ; OSC = ECIOPLL EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL ; OSC = ECIOSWPLL EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL ; OSC = HSSWPLL HS oscillator with SW enabled 4x PLL ; ; Oscillator System Clock Switch Enable bit: ; OSCS = ON Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) ; OSCS = OFF Oscillator system clock switch option is disabled (main oscillator is source) ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bit: ; BOR = OFF Brown-out Reset disabled ; BOR = ON Brown-out Reset enabled ; ; Brown-out Reset Voltage bits: ; BORV = 45 VBOR set to 4.5V ; BORV = 42 VBOR set to 4.2V ; BORV = 27 VBOR set to 2.7V ; BORV = 20 VBOR set to 2.0V ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) ; WAIT = OFF Wait selections unavailable for table reads and table writes ; ; MCLR Enable bit: ; MCLRE = OFF RG5 input enabled, MCLR disabled ; MCLRE = ON MCLR pin enabled, RG5 input pin disabled ; ; CCP1 PWM outputs P1B, P1C mux bit: ; ECCPMX = PORTH P1B, P1C are multiplexed with RH7, RH6 ; ECCPMX = PORTE P1B, P1C are multiplexed with RE6, RE5 ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVR = OFF Stack full/underflow will not cause Reset ; STVR = ON Stack full/underflow will cause Reset ; ; Low-Voltage ICSP Enable bit: ; LVP = OFF Low-voltage ICSP disabled ; LVP = ON Low-voltage ICSP enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. ; DEBUG = OFF Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; RC oscillator with OSC2 configured as divide by 4 clock output _OSC_EC_1H EQU H'F4' ; EC oscillator with OSC2 configured as divide by 4 clock output _OSC_ECIO_1H EQU H'F5' ; EC oscillator with OSC2 configured as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator with HW enabled 4x PLL _OSC_RCIO_1H EQU H'F7' ; RC oscillator with OSC2 configured as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS oscillator with SW enabled 4x PLL _OSCS_ON_1H EQU H'DF' ; Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) _OSCS_OFF_1H EQU H'FF' ; Oscillator system clock switch option is disabled (main oscillator is source) ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BORV_45_2L EQU H'F3' ; VBOR set to 4.5V _BORV_42_2L EQU H'F7' ; VBOR set to 4.2V _BORV_27_2L EQU H'FB' ; VBOR set to 2.7V _BORV_20_2L EQU H'FF' ; VBOR set to 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) _WAIT_OFF_3L EQU H'FF' ; Wait selections unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input enabled, MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RG5 input pin disabled _ECCPMX_PORTH_3H EQU H'FD' ; P1B, P1C are multiplexed with RH7, RH6 _ECCPMX_PORTE_3H EQU H'FF' ; P1B, P1C are multiplexed with RE6, RE5 _CCP2MX_OFF_3H EQU H'FE' ; CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVR_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Low-voltage ICSP disabled _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4423.inc0000644000175000017500000012423411156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4423 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4423 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4423 ; 2. LIST directive in the source file ; LIST P=PIC18F4423 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4423 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' C1OUT_PORTA EQU H'0004' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' HLVDIN EQU H'0005' LVDIN EQU H'0005' C2OUT_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' P1A EQU H'0002' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTB CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTB_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f5x.inc0000644000175000017500000001004311156313161013162 00000000000000 LIST ; P16F5X.INC Standard Header File, Version 4.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the 16F5X microcontrollers. These names are taken to match ; the data sheets as closely as possible. The microcontrollers included ; in this file are: ; 16F59 ; 16F57 ; 16F54 ; There is one group of symbols that is valid for all microcontrollers. ; Each microcontroller in this family also has its own section of special ; symbols. Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16F54 ; C:\ MPASM MYFILE.ASM /P16F57 ; C:\ MPASM MYFILE.ASM /P16F59 ; 2. LIST directive in the source file ; LIST P=16F54 ; LIST P=16F57 ; LIST P=16F59 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/09/03 Initial release for the PIC16F54/F57 ;1.10 05/28/04 Update to add PIC16F59 ;========================================================================== ; ; Generic Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- PA2 EQU H'0007' PA1 EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; Processor-dependent Definitions ; ;========================================================================== IFDEF __16F54 __MAXRAM H'01F' ENDIF ;-------------------------------------------------------------------------- IFDEF __16F57 ; Register Files PORTC EQU H'0007' __MAXRAM H'07F' ENDIF ;-------------------------------------------------------------------------- IFDEF __16F59 ; Register Files PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' __MAXRAM H'0FF' ENDIF ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _HS_OSC EQU H'0FFE' _RC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f2580.inc0000644000175000017500000041360211156521301013233 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2580 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2580 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2580 ; 2. LIST directive in the source file ; LIST P=PIC18F2580 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2580 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREFA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0CFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FAA' __BADRAM H'0FB4'-H'0FB6' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'EF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'FF' ; 2K words (4K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c717.inc0000644000175000017500000003012511156313161013144 00000000000000 LIST ; P16C717.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C717 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C717 ; 2. LIST directive in the source file ; LIST P=PIC16C717 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 14Sep1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C717 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' P1DEL EQU H'0097' REFCON EQU H'009B' LVDCON EQU H'009C' ANSEL EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' PMDATL EQU H'010C' PMADRL EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- LVDIF EQU H'0007' BCLIF EQU H'0003' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- PWM1M1 EQU H'0007' PWM1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- LVDIE EQU H'0007' BCLIE EQU H'0003' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- VRHEN EQU H'0007' VRLEN EQU H'0006' VRHOEN EQU H'0005' VRLOEN EQU H'0004' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'18'-H'1D' __BADRAM H'87'-H'89' __BADRAM H'8F'-H'90', H'98'-H'9A' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CFF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _MCLRE_OFF EQU H'3FDF' _MCLRE_ON EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FFB' _HS_OSC EQU H'3FFA' _XT_OSC EQU H'3FF9' _LP_OSC EQU H'3FF8' LIST gputils-0.13.7/header/p18f2455.inc0000644000175000017500000014130411156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2455 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2455 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2455 ; 2. LIST directive in the source file ; LIST P=PIC18F2455 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2455 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f6585.inc0000644000175000017500000040742111156521301013246 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6585 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6585 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6585 ; 2. LIST directive in the source file ; LIST P=PIC18F6585 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6585 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' ECCP1DEL EQU H'0F79' BAUDCON EQU H'0F7E' SPBRGH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' TXRTR EQU H'0006' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDM EQU H'0003' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXRTRR0 EQU H'0003' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RTRR0 EQU H'0005' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE0 EQU H'0001' ICODE1 EQU H'0002' ICODE2 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' TX2EN EQU H'0006' TX2SRC EQU H'0007' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' NOT_FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' P1C EQU H'0005' P1B EQU H'0006' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CANTX1 EQU H'0000' CANTX2 EQU H'0001' CANRX EQU H'0002' P1D EQU H'0004' MCLR EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E2E'-H'0E2F' __BADRAM H'0E3E'-H'0E3F' __BADRAM H'0E4E'-H'0E4F' __BADRAM H'0E5E'-H'0E5F' __BADRAM H'0E6E'-H'0E6F' __BADRAM H'0E7E'-H'0EFF' __BADRAM H'0F2E'-H'0F2F' __BADRAM H'0F3E'-H'0F3F' __BADRAM H'0F4E'-H'0F4F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F78' __BADRAM H'0F7A'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9C' __BADRAM H'0FB7'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC RC oscillator with OSC2 configured as divide by 4 clock output ; OSC = EC EC oscillator with OSC2 configured as divide by 4 clock output ; OSC = ECIO EC oscillator with OSC2 configured as RA6 ; OSC = HSPLL HS oscillator with HW enabled 4x PLL ; OSC = RCIO RC oscillator with OSC2 configured as RA6 ; OSC = ECIOPLL EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL ; OSC = ECIOSWPLL EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL ; OSC = HSSWPLL HS oscillator with SW enabled 4x PLL ; ; Oscillator System Clock Switch Enable bit: ; OSCS = ON Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) ; OSCS = OFF Oscillator system clock switch option is disabled (main oscillator is source) ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bit: ; BOR = OFF Brown-out Reset disabled ; BOR = ON Brown-out Reset enabled ; ; Brown-out Reset Voltage bits: ; BORV = 45 VBOR set to 4.5V ; BORV = 42 VBOR set to 4.2V ; BORV = 27 VBOR set to 2.7V ; BORV = 20 VBOR set to 2.0V ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable bit: ; MCLRE = OFF RG5 input enabled, MCLR disabled ; MCLRE = ON MCLR pin enabled, RG5 input pin disabled ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RE7 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVR = OFF Stack full/underflow will not cause Reset ; STVR = ON Stack full/underflow will cause Reset ; ; Low-Voltage ICSP Enable bit: ; LVP = OFF Low-voltage ICSP disabled ; LVP = ON Low-voltage ICSP enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. ; DEBUG = OFF Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; RC oscillator with OSC2 configured as divide by 4 clock output _OSC_EC_1H EQU H'F4' ; EC oscillator with OSC2 configured as divide by 4 clock output _OSC_ECIO_1H EQU H'F5' ; EC oscillator with OSC2 configured as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator with HW enabled 4x PLL _OSC_RCIO_1H EQU H'F7' ; RC oscillator with OSC2 configured as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS oscillator with SW enabled 4x PLL _OSCS_ON_1H EQU H'DF' ; Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) _OSCS_OFF_1H EQU H'FF' ; Oscillator system clock switch option is disabled (main oscillator is source) ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BORV_45_2L EQU H'F3' ; VBOR set to 4.5V _BORV_42_2L EQU H'F7' ; VBOR set to 4.2V _BORV_27_2L EQU H'FB' ; VBOR set to 2.7V _BORV_20_2L EQU H'FF' ; VBOR set to 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input enabled, MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RG5 input pin disabled _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVR_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Low-voltage ICSP disabled _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18cxxx.inc0000644000175000017500000003013211156521301013452 00000000000000 LIST ; P18CXXX.INC Standard Header File, Microchip Technology, Inc. NOLIST ; This header file defines the list of processor specific header files. It is ; used to include the appropriate header file. ; Note that the processor must be selected before this file is included. The ; processor may be selected the following ways: ; Using the PIC18C452 as an example ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C452 ; 2. LIST directive in the source file ; LIST P=PIC18C452 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFDEF __18CXX INCLUDE ENDIF IFDEF __18C242 INCLUDE ENDIF IFDEF __18C252 INCLUDE ENDIF IFDEF __18C442 INCLUDE ENDIF IFDEF __18C452 INCLUDE ENDIF IFDEF __18C601 INCLUDE ENDIF IFDEF __18C658 INCLUDE ENDIF IFDEF __18C801 INCLUDE ENDIF IFDEF __18C858 INCLUDE ENDIF IFDEF __18F1220 INCLUDE ENDIF IFDEF __18F1230 INCLUDE ENDIF IFDEF __18F1320 INCLUDE ENDIF IFDEF __18F1330 INCLUDE ENDIF IFDEF __18F13K22 INCLUDE ENDIF IFDEF __18F13K50 INCLUDE ENDIF IFDEF __18F14K22 INCLUDE ENDIF IFDEF __18F14K50 INCLUDE ENDIF IFDEF __18F2220 INCLUDE ENDIF IFDEF __18F2221 INCLUDE ENDIF IFDEF __18F2320 INCLUDE ENDIF IFDEF __18F2321 INCLUDE ENDIF IFDEF __18F2331 INCLUDE ENDIF IFDEF __18F23K20 INCLUDE ENDIF IFDEF __18F2410 INCLUDE ENDIF IFDEF __18F242 INCLUDE ENDIF IFDEF __18F2420 INCLUDE ENDIF IFDEF __18F2423 INCLUDE ENDIF IFDEF __18F2431 INCLUDE ENDIF IFDEF __18F2439 INCLUDE ENDIF IFDEF __18F2450 INCLUDE ENDIF IFDEF __18F2455 INCLUDE ENDIF IFDEF __18F2458 INCLUDE ENDIF IFDEF __18F248 INCLUDE ENDIF IFDEF __18F2480 INCLUDE ENDIF IFDEF __18F24J10 INCLUDE ENDIF IFDEF __18F24J11 INCLUDE ENDIF IFDEF __18F24J50 INCLUDE ENDIF IFDEF __18F24K20 INCLUDE ENDIF IFDEF __18F2510 INCLUDE ENDIF IFDEF __18F2515 INCLUDE ENDIF IFDEF __18F252 INCLUDE ENDIF IFDEF __18F2520 INCLUDE ENDIF IFDEF __18F2523 INCLUDE ENDIF IFDEF __18F2525 INCLUDE ENDIF IFDEF __18F2539 INCLUDE ENDIF IFDEF __18F2550 INCLUDE ENDIF IFDEF __18F2553 INCLUDE ENDIF IFDEF __18F258 INCLUDE ENDIF IFDEF __18F2580 INCLUDE ENDIF IFDEF __18F2585 INCLUDE ENDIF IFDEF __18F25J10 INCLUDE ENDIF IFDEF __18F25J11 INCLUDE ENDIF IFDEF __18F25J50 INCLUDE ENDIF IFDEF __18F25K20 INCLUDE ENDIF IFDEF __18F2610 INCLUDE ENDIF IFDEF __18F2620 INCLUDE ENDIF IFDEF __18F2680 INCLUDE ENDIF IFDEF __18F2682 INCLUDE ENDIF IFDEF __18F2685 INCLUDE ENDIF IFDEF __18F26J11 INCLUDE ENDIF IFDEF __18F26J50 INCLUDE ENDIF IFDEF __18F26K20 INCLUDE ENDIF IFDEF __18F4220 INCLUDE ENDIF IFDEF __18F4221 INCLUDE ENDIF IFDEF __18F4320 INCLUDE ENDIF IFDEF __18F4321 INCLUDE ENDIF IFDEF __18F4331 INCLUDE ENDIF IFDEF __18F43K20 INCLUDE ENDIF IFDEF __18F4410 INCLUDE ENDIF IFDEF __18F442 INCLUDE ENDIF IFDEF __18F4420 INCLUDE ENDIF IFDEF __18F4423 INCLUDE ENDIF IFDEF __18F4431 INCLUDE ENDIF IFDEF __18F4439 INCLUDE ENDIF IFDEF __18F4450 INCLUDE ENDIF IFDEF __18F4455 INCLUDE ENDIF IFDEF __18F4458 INCLUDE ENDIF IFDEF __18F448 INCLUDE ENDIF IFDEF __18F4480 INCLUDE ENDIF IFDEF __18F44J10 INCLUDE ENDIF IFDEF __18F44J11 INCLUDE ENDIF IFDEF __18F44J50 INCLUDE ENDIF IFDEF __18F44K20 INCLUDE ENDIF IFDEF __18F4510 INCLUDE ENDIF IFDEF __18F4515 INCLUDE ENDIF IFDEF __18F452 INCLUDE ENDIF IFDEF __18F4520 INCLUDE ENDIF IFDEF __18F4523 INCLUDE ENDIF IFDEF __18F4525 INCLUDE ENDIF IFDEF __18F4539 INCLUDE ENDIF IFDEF __18F4550 INCLUDE ENDIF IFDEF __18F4553 INCLUDE ENDIF IFDEF __18F458 INCLUDE ENDIF IFDEF __18F4580 INCLUDE ENDIF IFDEF __18F4585 INCLUDE ENDIF IFDEF __18F45J10 INCLUDE ENDIF IFDEF __18F45J11 INCLUDE ENDIF IFDEF __18F45J50 INCLUDE ENDIF IFDEF __18F45K20 INCLUDE ENDIF IFDEF __18F4610 INCLUDE ENDIF IFDEF __18F4620 INCLUDE ENDIF IFDEF __18F4680 INCLUDE ENDIF IFDEF __18F4682 INCLUDE ENDIF IFDEF __18F4685 INCLUDE ENDIF IFDEF __18F46J11 INCLUDE ENDIF IFDEF __18F46J50 INCLUDE ENDIF IFDEF __18F46K20 INCLUDE ENDIF IFDEF __18F6310 INCLUDE ENDIF IFDEF __18F6390 INCLUDE ENDIF IFDEF __18F6393 INCLUDE ENDIF IFDEF __18F63J11 INCLUDE ENDIF IFDEF __18F63J90 INCLUDE ENDIF IFDEF __18F6410 INCLUDE ENDIF IFDEF __18F6490 INCLUDE ENDIF IFDEF __18F6493 INCLUDE ENDIF IFDEF __18F64J11 INCLUDE ENDIF IFDEF __18F64J90 INCLUDE ENDIF IFDEF __18F6520 INCLUDE ENDIF IFDEF __18F6525 INCLUDE ENDIF IFDEF __18F6527 INCLUDE ENDIF IFDEF __18F6585 INCLUDE ENDIF IFDEF __18F65J10 INCLUDE ENDIF IFDEF __18F65J11 INCLUDE ENDIF IFDEF __18F65J15 INCLUDE ENDIF IFDEF __18F65J50 INCLUDE ENDIF IFDEF __18F65J90 INCLUDE ENDIF IFDEF __18F6620 INCLUDE ENDIF IFDEF __18F6621 INCLUDE ENDIF IFDEF __18F6622 INCLUDE ENDIF IFDEF __18F6627 INCLUDE ENDIF IFDEF __18F6628 INCLUDE ENDIF IFDEF __18F6680 INCLUDE ENDIF IFDEF __18F66J10 INCLUDE ENDIF IFDEF __18F66J11 INCLUDE ENDIF IFDEF __18F66J15 INCLUDE ENDIF IFDEF __18F66J16 INCLUDE ENDIF IFDEF __18F66J50 INCLUDE ENDIF IFDEF __18F66J55 INCLUDE ENDIF IFDEF __18F66J60 INCLUDE ENDIF IFDEF __18F66J65 INCLUDE ENDIF IFDEF __18F66J90 INCLUDE ENDIF IFDEF __18F6720 INCLUDE ENDIF IFDEF __18F6722 INCLUDE ENDIF IFDEF __18F6723 INCLUDE ENDIF IFDEF __18F67J10 INCLUDE ENDIF IFDEF __18F67J11 INCLUDE ENDIF IFDEF __18F67J50 INCLUDE ENDIF IFDEF __18F67J60 INCLUDE ENDIF IFDEF __18F67J90 INCLUDE ENDIF IFDEF __18F8310 INCLUDE ENDIF IFDEF __18F8390 INCLUDE ENDIF IFDEF __18F8393 INCLUDE ENDIF IFDEF __18F83J11 INCLUDE ENDIF IFDEF __18F83J90 INCLUDE ENDIF IFDEF __18F8410 INCLUDE ENDIF IFDEF __18F8490 INCLUDE ENDIF IFDEF __18F8493 INCLUDE ENDIF IFDEF __18F84J11 INCLUDE ENDIF IFDEF __18F84J90 INCLUDE ENDIF IFDEF __18F8520 INCLUDE ENDIF IFDEF __18F8525 INCLUDE ENDIF IFDEF __18F8527 INCLUDE ENDIF IFDEF __18F8585 INCLUDE ENDIF IFDEF __18F85J10 INCLUDE ENDIF IFDEF __18F85J11 INCLUDE ENDIF IFDEF __18F85J15 INCLUDE ENDIF IFDEF __18F85J50 INCLUDE ENDIF IFDEF __18F85J90 INCLUDE ENDIF IFDEF __18F8620 INCLUDE ENDIF IFDEF __18F8621 INCLUDE ENDIF IFDEF __18F8622 INCLUDE ENDIF IFDEF __18F8627 INCLUDE ENDIF IFDEF __18F8628 INCLUDE ENDIF IFDEF __18F8680 INCLUDE ENDIF IFDEF __18F86J10 INCLUDE ENDIF IFDEF __18F86J11 INCLUDE ENDIF IFDEF __18F86J15 INCLUDE ENDIF IFDEF __18F86J16 INCLUDE ENDIF IFDEF __18F86J50 INCLUDE ENDIF IFDEF __18F86J55 INCLUDE ENDIF IFDEF __18F86J60 INCLUDE ENDIF IFDEF __18F86J65 INCLUDE ENDIF IFDEF __18F86J90 INCLUDE ENDIF IFDEF __18F8720 INCLUDE ENDIF IFDEF __18F8722 INCLUDE ENDIF IFDEF __18F8723 INCLUDE ENDIF IFDEF __18F87J10 INCLUDE ENDIF IFDEF __18F87J11 INCLUDE ENDIF IFDEF __18F87J50 INCLUDE ENDIF IFDEF __18F87J60 INCLUDE ENDIF IFDEF __18F87J90 INCLUDE ENDIF IFDEF __18F96J60 INCLUDE ENDIF IFDEF __18F96J65 INCLUDE ENDIF IFDEF __18F97J60 INCLUDE ENDIF IFDEF __18LF13K22 INCLUDE ENDIF IFDEF __18LF13K50 INCLUDE ENDIF IFDEF __18LF14K22 INCLUDE ENDIF IFDEF __18LF14K50 INCLUDE ENDIF IFDEF __18LF24J11 INCLUDE ENDIF IFDEF __18LF24J50 INCLUDE ENDIF IFDEF __18LF25J11 INCLUDE ENDIF IFDEF __18LF25J50 INCLUDE ENDIF IFDEF __18LF26J11 INCLUDE ENDIF IFDEF __18LF26J50 INCLUDE ENDIF IFDEF __18LF44J11 INCLUDE ENDIF IFDEF __18LF44J50 INCLUDE ENDIF IFDEF __18LF45J11 INCLUDE ENDIF IFDEF __18LF45J50 INCLUDE ENDIF IFDEF __18LF46J11 INCLUDE ENDIF IFDEF __18LF46J50 INCLUDE ENDIF gputils-0.13.7/header/p16c621a.inc0000644000175000017500000001355711156313161013311 00000000000000 LIST ; P16C621A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C621A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C621A ; 2. LIST directive in the source file ; LIST P=PIC16C621A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/28/97 Initial Release ;1.10 16/08/99 Added unbanked RAM at 70-7F ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C621A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'07'-H'09', H'0D'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' __BADRAM H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_50 EQU H'15DF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f25j11.inc0000644000175000017500000014260211156521301013376 00000000000000 LIST ;========================================================================== ; MPASM PIC18F25J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F25J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F25J11 ; 2. LIST directive in the source file ; LIST P=PIC18F25J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F25J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ULPWU EQU H'0000' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F65' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f877a.inc0000644000175000017500000003752511156313161013332 00000000000000 LIST ; P16F877A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F877A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F877A ; 2. LIST directive in the source file ; LIST P=PIC16F877A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 11/17/05 Added the ADCON1 bit ADCS2. ;1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. ;1.01 09/13/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE ;1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F877A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' __BADRAM H'105', H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _CPD_OFF EQU H'3FFF' _CPD_ON EQU H'3EFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _RC_OSC EQU H'3FFF' _HS_OSC EQU H'3FFE' _XT_OSC EQU H'3FFD' _LP_OSC EQU H'3FFC' LIST gputils-0.13.7/header/p18f46k20.inc0000644000175000017500000013735211156521302013411 00000000000000 LIST ;========================================================================== ; MPASM PIC18F46K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F46K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F46K20 ; 2. LIST directive in the source file ; LIST P=PIC18F46K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F46K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f66j15.inc0000644000175000017500000013043011156521301013403 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J15 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J15 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J15 ; 2. LIST directive in the source file ; LIST P=PIC18F66J15 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J15 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c620a.inc0000644000175000017500000001402011156313161013272 00000000000000 LIST ; P16C620A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C620A and PIC16CR620A microcontrollers. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C620A or ; C:\ MPASM MYFILE.ASM /PIC16CR620A ; 2. LIST directive in the source file ; LIST P=PIC16C620A or ; LIST P=PIC16CR620A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/28/97 Initial Release ;1.10 16/08/99 Added unbanked RAM at 70-7F ;1.20 06/12/02 Verification now includes the PIC16CR620A (pas) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C620A IFNDEF __16CR620A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'07'-H'09', H'0D'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' __BADRAM H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ON EQU H'00CF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f4450.inc0000644000175000017500000012175311156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4450 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4450 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4450 ; 2. LIST directive in the source file ; LIST P=PIC18F4450 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4450 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' RCV EQU H'0004' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' VMO EQU H'0002' VPO EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' NOT_UOE EQU H'0001' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' UOE EQU H'0001' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- LVDIE EQU H'0002' USBIE EQU H'0005' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- LVDIF EQU H'0002' USBIF EQU H'0005' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- LVDIP EQU H'0002' USBIP EQU H'0005' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'03FF' __BADRAM H'0500'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB1'-H'0FB7' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FC5'-H'0FC9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; 96 MHz PLL Prescaler: ; PLLDIV = 1 No divide (4 MHz input) ; PLLDIV = 2 Divide by 2 (8 MHz input) ; PLLDIV = 3 Divide by 3 (12 MHz input) ; PLLDIV = 4 Divide by 4 (16 MHz input) ; PLLDIV = 5 Divide by 5 (20 MHz input) ; PLLDIV = 6 Divide by 6 (24 MHz input) ; PLLDIV = 10 Divide by 10 (40 MHz input) ; PLLDIV = 12 Divide by 12 (48 MHz input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; Full-Speed USB Clock Source Selection: ; USBDIV = 1 Clock source from OSC1/OSC2 ; USBDIV = 2 Clock source from 96 MHz PLL/2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal/External Switch Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = SOFT Controlled by SBOREN ; BOR = ON_ACTIVE Enabled when the device is not in Sleep, SBOREN bit is disabled ; BOR = ON Enabled, SBOREN bit is disabled ; ; Brown-out Voltage: ; BORV = 46 4.6V ; BORV = 43 4.3V ; BORV = 28 2.8V ; BORV = 21 2.1V ; ; USB Voltage Regulator Enable: ; VREGEN = OFF Disabled ; VREGEN = ON Enabled ; ; Watchdog Timer: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; Low Power Timer1 Oscillator Enable: ; LPT1OSC = OFF Timer1 oscillator configured for high power ; LPT1OSC = ON Timer1 oscillator configured for low power ; ; PORTB A/D Enable: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input on Reset ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Boot Block Size Select Bit: ; BBSIZ = BB1K 1KW Boot Block Size ; BBSIZ = BB2K 2KW Boot Block Size ; ; Dedicated In-Circuit Debug/Programming Enable: ; ICPRT = OFF Disabled ; ICPRT = ON Enabled ; ; Extended Instruction Set Enable: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No divide (4 MHz input) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; Clock source from OSC1/OSC2 _USBDIV_2_1L EQU H'FF' ; Clock source from 96 MHz PLL/2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'F9' ; Disabled _BOR_SOFT_2L EQU H'FB' ; Controlled by SBOREN _BOR_ON_ACTIVE_2L EQU H'FD' ; Enabled when the device is not in Sleep, SBOREN bit is disabled _BOR_ON_2L EQU H'FF' ; Enabled, SBOREN bit is disabled _BORV_46_2L EQU H'E7' ; 4.6V _BORV_43_2L EQU H'EF' ; 4.3V _BORV_28_2L EQU H'F7' ; 2.8V _BORV_21_2L EQU H'FF' ; 2.1V _VREGEN_OFF_2L EQU H'DF' ; Disabled _VREGEN_ON_2L EQU H'FF' ; Enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 oscillator configured for high power _LPT1OSC_ON_3H EQU H'FF' ; Timer1 oscillator configured for low power _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input on Reset ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _BBSIZ_BB1K_4L EQU H'F7' ; 1KW Boot Block Size _BBSIZ_BB2K_4L EQU H'FF' ; 2KW Boot Block Size _ICPRT_OFF_4L EQU H'DF' ; Disabled _ICPRT_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Disabled _XINST_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/ps500.inc0000644000175000017500000005403311156313161013007 00000000000000 NOLIST ; Based on P18F1320.INC, and PS500 DOS - WK 10/7/03 LIST ; PS500.INC Standard Header File, Version 0.1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PS500 Fuel Gage. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PS500 ; 2. LIST directive in the source file ; LIST P=PS500 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 07 Oct 2003 Initial release WK ;0.20 14 Oct 2003 Fix for Unused bits reading '0' WK ;0.30 15 Oct 2003 Corrected 4L and 3H config bits WK ;0.40 31 Oct 2003 Corrected default of WRT23_ON to OFF WK ; Per DOS Rv.C added new SFR bits ; ; Verify Processor ; ;======================================================================= IFNDEF __PS500 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution ; #define DDRC TRISC ; PIC17Cxxx SFR substitution ; #define DDRD TRISD ; PIC17Cxxx SFR substitution ; #define DDRE TRISE ; PIC17Cxxx SFR substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved H'0FD4' OSCCON EQU H'0FD3' ; reserved H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' ; reserved H'0FBF' ; reserved H'0FBE' ; reserved H'0FBD' ; reserved H'0FBC' ; reserved H'0FBB' ; reserved H'0FBA' ; reserved H'0FB9' ; reserved H'0FB8' ; reserved H'0FB7' ; reserved H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ; reserved H'0FB0' ; reserved H'0FAF' ; reserved H'0FAE' ; reserved H'0FAD' ; reserved H'0FAC' ; reserved H'0FAB' ; reserved H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved H'0FB5' ; reserved H'0FB4' ; reserved H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' BGCAL EQU H'0F9C' OSCCAL EQU H'0F9B' REFCAL EQU H'0F9A' ; reserved H'0F99' ; reserved H'0F98' ; reserved H'0F97' ; reserved H'0F96' ; reserved H'0F95' ; reserved H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LEDB EQU H'0F91' LEDDC EQU H'0F90' ; reserved H'0F8F' ; reserved H'0F8E' ; reserved H'0F8D' ; reserved H'0F8C' ; reserved H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved H'0F88' ; reserved H'0F87' ; reserved H'0F86' ; reserved H'0F85' ; reserved H'0F84' ; reserved H'0F83' ; reserved H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' ;For backward compatibilty STKOVF EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0E EQU H'0004' INT0IE EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' ; For backward compatibility INT0F EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2P EQU H'0007' INT2IP EQU H'0007' INT1P EQU H'0006' INT1IP EQU H'0006' ; For backward compatibility INT2E EQU H'0004' INT2IE EQU H'0004' ; For compatibility INT1E EQU H'0003' INT1IE EQU H'0003' ; For backward compatibility INT2F EQU H'0001' INT2IF EQU H'0001' ; For compatibility INT1F EQU H'0000' INT1IF EQU H'0000' ; For backward compatibility ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' OSTS EQU H'0003' SCS0 EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' GPB EQU H'0006' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCOV EQU H'0007' SIZE2 EQU H'0006' SIZE1 EQU H'0005' SIZE0 EQU H'0004' BALC4 EQU H'0003' BALC3 EQU H'0002' BALC2 EQU H'0001' BALC1 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- C340 EQU H'0007' ADCS3 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CVRCON Bits ----------------------------------------------------- CWI4 EQU H'0007' CWI3 EQU H'0006' CWI2 EQU H'0005' CWI1 EQU H'0004' CWI0 EQU H'0003' CWV2 EQU H'0002' CWV1 EQU H'0001' CWV0 EQU H'0000' ;----- CMCON bits ------------------------------------------------------ CWTST EQU H'0007' CWVI EQU H'0004' CWCI EQU H'0003' CWDI EQU H'0002' CWIEN EQU H'0001' CWVEN EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' COMA EQU H'0005' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' TMR3IP EQU H'0001' ;----- PIR2 Bits ------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' TMR3IF EQU H'0001' ;----- PIE2 Bits ------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' TMR3IE EQU H'0001' ;----- IPR1 Bits ------------------------------------------------------- ADIP EQU H'0006' SSPIP EQU H'0003' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- BGCAL Bits ------------------------------------------------------- BGTC3 EQU H'0003' BGTC2 EQU H'0002' BGTC1 EQU H'0001' BGTC0 EQU H'0000' ;----- OSCCAL Bits ---------------------------------------------------- REXT EQU H'0007' OSC6 EQU H'0006' OSC5 EQU H'0005' OSC4 EQU H'0004' OSC3 EQU H'0003' OSC2 EQU H'0002' OSC1 EQU H'0001' OSC0 EQU H'0000' ;----- LEDDC Bits ------------------------------------------------------- LEDC2 EQU H'0002' LEDC1 EQU H'0001' LEDC0 EQU H'0000' ;----- WDTCON Bits ------------------------------------------------------- SWDTEN EQU H'0000' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 SCK EQU 0 SCL EQU 0 RA1 EQU 1 SDI EQU 1 SDA EQU 1 RA2 EQU 2 SS EQU 2 RA3 EQU 3 SDO EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 MCLR EQU 5 RA6 EQU 6 CLKI EQU 6 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 PGC EQU 6 P1C EQU 7 RB7 EQU 7 PGD EQU 7 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'200'-H'F7F' __BADRAM H'F82'-H'F88',H'F8B'-H'F8F',H'F94'-H'F99' __BADRAM H'FA3'-H'FA5',H'FAA'-H'FB0',H'FB6'-H'FBF' __BADRAM H'FD1'-H'FD2' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To use the Configuration Bits, place the following lines in your ; source code in the following format, and change the configuration ; value to the desired setting (such as WDT_OFF to WDT_ON). These are ; currently commented out here and each __CONFIG line should have the ; preceding semicolon removed when pasted into your source code. ; __CONFIG _CONFIG1L, 0x00 ; __CONFIG _CONFIG1H, 0x00 ; __CONFIG _CONFIG2L, 0x00 ; __CONFIG _CONFIG2H, _WDT_ON_2H ; __CONFIG _CONFIG3L, 0x00 ; __CONFIG _CONFIG3H, _MCLRE_ON_3H ; __CONFIG _CONFIG4L, _BKBUG_OFF_4L | _STVR_ON_4L ; __CONFIG _CONFIG4H, 0x00 ; __CONFIG _CONFIG5L, _CP01_OFF_5L | _CP23_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H | _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT01_OFF_6L | _WRT23_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H | _WRTB_OFF_6H | _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR01_OFF_7L | _EBTR23_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 2H Options _WDT_ON_2H EQU H'01' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'00' ; Watch Dog Timer disabled ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'80' ; MCLR enabled, RA5 input disabled _MCLRE_OFF_3H EQU H'00' ; MCLR disabled, RA5 input enabled ;Configuration Byte 4L Options _BKBUG_ON_4L EQU H'00' ; BacKground deBUGger enabled _BKBUG_OFF_4L EQU H'80' ; BacKground deBUGger disabled _STVR_ON_4L EQU H'01' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'00' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP01_ON_5L EQU H'00' ; Blocks 0 & 1 protected _CP01_OFF_5L EQU H'01' ; Blocks 0 & 1 readable/ may be writable _CP23_ON_5L EQU H'00' ; Blocks 2 & 3 protected _CP23_OFF_5L EQU H'02' ; Blocks 2 & 3 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'00' ; Boot Block protected _CPB_OFF_5H EQU H'40' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'00' ; Data EE memory protected _CPD_OFF_5H EQU H'80' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT01_ON_6L EQU H'00' ; Block 0 & 1 write protected _WRT01_OFF_6L EQU H'01' ; Block 0 & 1 writable _WRT23_ON_6L EQU H'00' ; Block 2 & 3 write protected _WRT23_OFF_6L EQU H'02' ; Block 2 & 3 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'00' ; Config registers write protected _WRTC_OFF_6H EQU H'20' ; Config registers writable _WRTB_ON_6H EQU H'00' ; Boot block write protected _WRTB_OFF_6H EQU H'40' ; Boot block writable _WRTD_ON_6H EQU H'00' ; Data EE write protected _WRTD_OFF_6H EQU H'80' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR01_ON_7L EQU H'00' ; Block 0 & 1 protected _EBTR01_OFF_7L EQU H'01' ; Block 0 & 1 readable _EBTR23_ON_7L EQU H'00' ; Block 2 & 3 protected _EBTR23_OFF_7L EQU H'02' ; Block 2 & 3 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'00' ; Boot block read protected _EBTRB_OFF_7H EQU H'40' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p18f86j16.inc0000644000175000017500000016344411156521301013421 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J16 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J16 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J16 ; 2. LIST directive in the source file ; LIST P=PIC18F86J16 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J16 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F5A' PMSTATL EQU H'0F5A' PMSTATH EQU H'0F5B' PMEL EQU H'0F5C' PMEN EQU H'0F5C' PMEH EQU H'0F5D' PMDIN2 EQU H'0F5E' PMDIN2L EQU H'0F5E' PMDIN2H EQU H'0F5F' PMDOUT2 EQU H'0F60' PMDOUT2L EQU H'0F60' PMDOUT2H EQU H'0F61' PMMODE EQU H'0F62' PMMODEL EQU H'0F62' PMMODEH EQU H'0F63' PMCON EQU H'0F64' PMCONL EQU H'0F64' PMCONH EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2OUT EQU H'0001' C1OUT EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7 ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled ; FOSC = EC EC Oscillator with clock out on RA6 ; FOSC = ECPLL EC Oscillator with PLL ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f4620.inc0000644000175000017500000011407611156521301013233 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4620 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4620 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4620 ; 2. LIST directive in the source file ; LIST P=PIC18F4620 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4620 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' DEBUG EQU H'0FD4' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO6 EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO6 RC-OSC2 as RA6 ; OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7 ; OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7 ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Osc. Switch Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON SBOREN Enabled ; BOREN = NOSLP Enabled except Sleep, SBOREN Disabled ; BOREN = SBORDIS Enabled, SBOREN Disabled ; ; Brown-out Voltage: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; T1 Oscillator Enable: ; LPT1OSC = OFF Disabled ; LPT1OSC = ON Enabled ; ; PORTB A/D Enable: ; PBADEN = OFF PORTB<4:0> digital on Reset ; PBADEN = ON PORTB<4:0> analog on Reset ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; XINST Enable: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO6_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO6_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_INTIO67_1H EQU H'F8' ; INTRC-OSC2 as RA6, OSC1 as RA7 _OSC_INTIO7_1H EQU H'F9' ; INTRC-OSC2 as Clock Out, OSC1 as RA7 _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'F9' ; Disabled _BOREN_ON_2L EQU H'FB' ; SBOREN Enabled _BOREN_NOSLP_2L EQU H'FD' ; Enabled except Sleep, SBOREN Disabled _BOREN_SBORDIS_2L EQU H'FF' ; Enabled, SBOREN Disabled _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _LPT1OSC_OFF_3H EQU H'FB' ; Disabled _LPT1OSC_ON_3H EQU H'FF' ; Enabled _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> digital on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> analog on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Disabled _XINST_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c432.inc0000644000175000017500000001436111156313161013142 00000000000000 LIST ; P16C432.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C432 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C432 ; 2. LIST directive in the source file ; LIST P=PIC16C432 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 31 Aug 2000 Initial Release ;1.10 28 Mar 2001 Corrected definition of LINTX ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C432 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' LININTF EQU H'0090' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PORTA Bits -------------------------------------------------------- LINRX EQU H'0001' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- LINPRT Bits ---------------------------------------------------------- LINTX EQU H'0002' LINVDD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'07'-H'09', H'0D'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E' __BADRAM H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f66j16.inc0000644000175000017500000015027611156521301013416 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J16 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J16 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J16 ; 2. LIST directive in the source file ; LIST P=PIC18F66J16 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J16 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F5A' PMSTATL EQU H'0F5A' PMSTATH EQU H'0F5B' PMEL EQU H'0F5C' PMEN EQU H'0F5C' PMEH EQU H'0F5D' PMDIN2 EQU H'0F5E' PMDIN2L EQU H'0F5E' PMDIN2H EQU H'0F5F' PMDOUT2 EQU H'0F60' PMDOUT2L EQU H'0F60' PMDOUT2H EQU H'0F61' PMMODE EQU H'0F62' PMMODEL EQU H'0F62' PMMODEH EQU H'0F63' PMCON EQU H'0F64' PMCONL EQU H'0F64' PMCONH EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2OUT EQU H'0001' C1OUT EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7 ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled ; FOSC = EC EC Oscillator with clock out on RA6 ; FOSC = ECPLL EC Oscillator with PLL ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f46j11.inc0000644000175000017500000016271211156521301013405 00000000000000 LIST ;========================================================================== ; MPASM PIC18F46J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F46J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F46J11 ; 2. LIST directive in the source file ; LIST P=PIC18F46J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F46J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F60'-H'0F65' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set : ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator : ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler : ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler : ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18lf13k50.inc0000644000175000017500000013416111156521301013554 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF13K50 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF13K50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF13K50 ; 2. LIST directive in the source file ; LIST P=PIC18LF13K50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF13K50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UEP0 EQU H'0F53' UEP1 EQU H'0F54' UEP2 EQU H'0F55' UEP3 EQU H'0F56' UEP4 EQU H'0F57' UEP5 EQU H'0F58' UEP6 EQU H'0F59' UEP7 EQU H'0F5A' UEIE EQU H'0F5B' UADDR EQU H'0F5C' UFRML EQU H'0F5D' UFRMH EQU H'0F5E' UEIR EQU H'0F5F' UIE EQU H'0F60' UCFG EQU H'0F61' UIR EQU H'0F62' USTAT EQU H'0F63' UCON EQU H'0F64' SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' REFCON0 EQU H'0FBA' VREFCON0 EQU H'0FBA' REFCON1 EQU H'0FBB' VREFCON1 EQU H'0FBB' REFCON2 EQU H'0FBC' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UPUEN EQU H'0004' UTEYE EQU H'0007' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' USBIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' USBIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' USBIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- REFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- REFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- REFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0100'-H'01FF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F65'-H'0F67' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F75' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; CPU System Clock Selection bit: ; CPUDIV = NOCLKDIV No CPU System Clock divide ; CPUDIV = CLKDIV2 CPU System Clock divided by 2 ; CPUDIV = CLKDIV3 CPU System Clock divided by 3 ; CPUDIV = CLKDIV4 CPU System Clock divided by 4 ; ; USB Clock Selection bit: ; USBDIV = OFF USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide ; USBDIV = ON USB clock comes from the OSC1/OSC2 divided by 2 ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 512W boot block size ; BBSIZ = ON 1kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _CPUDIV_NOCLKDIV_1L EQU H'E7' ; No CPU System Clock divide _CPUDIV_CLKDIV2_1L EQU H'EF' ; CPU System Clock divided by 2 _CPUDIV_CLKDIV3_1L EQU H'F7' ; CPU System Clock divided by 3 _CPUDIV_CLKDIV4_1L EQU H'FF' ; CPU System Clock divided by 4 _USBDIV_OFF_1L EQU H'DF' ; USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide _USBDIV_ON_1L EQU H'FF' ; USB clock comes from the OSC1/OSC2 divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 512W boot block size _BBSIZ_ON_4L EQU H'FF' ; 1kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f83.inc0000644000175000017500000001137511156313161013071 00000000000000 LIST ; P16F83.INC Standard Header File, Version 2.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F83 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F83 ; 2. LIST directive in the source file ; LIST P=PIC16F83 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;2.00 07/24/96 Renamed to reflect the name change to PIC16F83. ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F83 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' EEDATA EQU H'0008' EEADR EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' EECON1 EQU H'0088' EECON2 EQU H'0089' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' EEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEIF EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'AF' __BADRAM H'07', H'30'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'000F' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f84.inc0000644000175000017500000001144311156313161013066 00000000000000 LIST ; P16F84.INC Standard Header File, Version 2.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F84 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F84 ; 2. LIST directive in the source file ; LIST P=PIC16F84 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;2.00 07/24/96 Renamed to reflect the name change to PIC16F84. ;1.01 05/17/96 Corrected BADRAM map ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F84 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' EEDATA EQU H'0008' EEADR EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' EECON1 EQU H'0088' EECON2 EQU H'0089' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' EEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEIF EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'CF' __BADRAM H'07', H'50'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'000F' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f45j11.inc0000644000175000017500000015673411156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F45J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F45J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F45J11 ; 2. LIST directive in the source file ; LIST P=PIC18F45J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F45J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F60'-H'0F65' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select : ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f248.inc0000644000175000017500000014070711156521301013155 00000000000000 LIST ; P18F248.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F248 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F248 ; 2. LIST directive in the source file ; LIST P=PIC18F248 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ; ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.90 15 May 2001 Preliminary Release dzb ;0.99 29 June2001 Rev 1 dzb ;1.00 29 Oct.2001 Corrections & Additions cjh ;1.10 25 Jun 2002 Added CFGS as EECON1 bit 6 name pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F248 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' ECCPR1H EQU H'0FBC' ECCPR1L EQU H'0FBB' ECCP1CON EQU H'0FBA' ECCP1DEL EQU H'0FB7' ECCPAS EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TXERRCNT EQU H'0F76' RXERRCNT EQU H'0F75' COMSTAT EQU H'0F74' CIOCON EQU H'0F73' BRGCON3 EQU H'0F72' BRGCON2 EQU H'0F71' BRGCON1 EQU H'0F70' CANCON EQU H'0F6F' CANSTAT EQU H'0F6E' RXB0D7 EQU H'0F6D' RXB0D6 EQU H'0F6C' RXB0D5 EQU H'0F6B' RXB0D4 EQU H'0F6A' RXB0D3 EQU H'0F69' RXB0D2 EQU H'0F68' RXB0D1 EQU H'0F67' RXB0D0 EQU H'0F66' RXB0DLC EQU H'0F65' RXB0EIDL EQU H'0F64' RXB0EIDH EQU H'0F63' RXB0SIDL EQU H'0F62' RXB0SIDH EQU H'0F61' RXB0CON EQU H'0F60' CANSTATRO1 EQU H'0F5E' RXB1D7 EQU H'0F5D' RXB1D6 EQU H'0F5C' RXB1D5 EQU H'0F5B' RXB1D4 EQU H'0F5A' RXB1D3 EQU H'0F59' RXB1D2 EQU H'0F58' RXB1D1 EQU H'0F57' RXB1D0 EQU H'0F56' RXB1DLC EQU H'0F55' RXB1EIDL EQU H'0F54' RXB1EIDH EQU H'0F53' RXB1SIDL EQU H'0F52' RXB1SIDH EQU H'0F51' RXB1CON EQU H'0F50' CANSTATRO2 EQU H'0F4E' TXB0D7 EQU H'0F4D' TXB0D6 EQU H'0F4C' TXB0D5 EQU H'0F4B' TXB0D4 EQU H'0F4A' TXB0D3 EQU H'0F49' TXB0D2 EQU H'0F48' TXB0D1 EQU H'0F47' TXB0D0 EQU H'0F46' TXB0DLC EQU H'0F45' TXB0EIDL EQU H'0F44' TXB0EIDH EQU H'0F43' TXB0SIDL EQU H'0F42' TXB0SIDH EQU H'0F41' TXB0CON EQU H'0F40' CANSTATRO3 EQU H'0F3E' TXB1D7 EQU H'0F3D' TXB1D6 EQU H'0F3C' TXB1D5 EQU H'0F3B' TXB1D4 EQU H'0F3A' TXB1D3 EQU H'0F39' TXB1D2 EQU H'0F38' TXB1D1 EQU H'0F37' TXB1D0 EQU H'0F36' TXB1DLC EQU H'0F35' TXB1EIDL EQU H'0F34' TXB1EIDH EQU H'0F33' TXB1SIDL EQU H'0F32' TXB1SIDH EQU H'0F31' TXB1CON EQU H'0F30' CANSTATRO4 EQU H'0F2E' TXB2D7 EQU H'0F2D' TXB2D6 EQU H'0F2C' TXB2D5 EQU H'0F2B' TXB2D4 EQU H'0F2A' TXB2D3 EQU H'0F29' TXB2D2 EQU H'0F28' TXB2D1 EQU H'0F27' TXB2D0 EQU H'0F26' TXB2DLC EQU H'0F25' TXB2EIDL EQU H'0F24' TXB2EIDH EQU H'0F23' TXB2SIDL EQU H'0F22' TXB2SIDH EQU H'0F21' TXB2CON EQU H'0F20' RXM1EIDL EQU H'0F1F' RXM1EIDH EQU H'0F1E' RXM1SIDL EQU H'0F1D' RXM1SIDH EQU H'0F1C' RXM0EIDL EQU H'0F1B' RXM0EIDH EQU H'0F1A' RXM0SIDL EQU H'0F19' RXM0SIDH EQU H'0F18' RXF5EIDL EQU H'0F17' RXF5EIDH EQU H'0F16' RXF5SIDL EQU H'0F15' RXF5SIDH EQU H'0F14' RXF4EIDL EQU H'0F13' RXF4EIDH EQU H'0F12' RXF4SIDL EQU H'0F11' RXF4SIDH EQU H'0F10' RXF3EIDL EQU H'0F0F' RXF3EIDH EQU H'0F0E' RXF3SIDL EQU H'0F0D' RXF3SIDH EQU H'0F0C' RXF2EIDL EQU H'0F0B' RXF2EIDH EQU H'0F0A' RXF2SIDL EQU H'0F09' RXF2SIDH EQU H'0F08' RXF1EIDL EQU H'0F07' RXF1EIDH EQU H'0F06' RXF1SIDL EQU H'0F05' RXF1SIDH EQU H'0F04' RXF0EIDL EQU H'0F03' RXF0EIDH EQU H'0F02' RXF0SIDL EQU H'0F01' RXF0SIDH EQU H'0F00' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' SP4 EQU H'0004' SP3 EQU H'0003' SP2 EQU H'0002' SP1 EQU H'0001' SP0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IVRST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ECCP1CON Bits ------------------------------------------------------ EPWM1M1 EQU H'0007' EPWM1M0 EQU H'0006' EDC2B1 EQU H'0005' EDC2B0 EQU H'0004' ECCP1M3 EQU H'0003' ECCP1M2 EQU H'0002' ECCP1M1 EQU H'0001' ECCP1M0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' ; For backward compatibility CVRR EQU H'0005' CVRSS EQU H'0004' ; For backward compatibility CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' ; For backward compatibility C2INV EQU H'0005' C1INV EQU H'0004' ; For backward compatibility CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3ECCP1 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' EEFS EQU H'0006' ; Backward compatability only CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR3 Bits ---------------------------------------------------------- IRXIP EQU H'0007' WAKIP EQU H'0006' ERRIP EQU H'0005' TXB2IP EQU H'0004' TXB1IP EQU H'0003' TXB0IP EQU H'0002' RXB1IP EQU H'0001' RXB0IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- IRXIF EQU H'0007' WAKIF EQU H'0006' ERRIF EQU H'0005' TXB2IF EQU H'0004' TXB1IF EQU H'0003' TXB0IF EQU H'0002' RXB1IF EQU H'0001' RXB0IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- IRXIE EQU H'0007' WAKIE EQU H'0006' ERRIE EQU H'0005' TXB2IE EQU H'0004' TXB1IE EQU H'0003' TXB0IE EQU H'0002' RXB1IE EQU H'0001' RXB0IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' ECCP1IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' ECCP1IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' ECCP1IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- COMSTAT Bits --------------------------------------------------------- RX1OVFL EQU H'0007' RXB0OVFL EQU H'0007' RX2OVFL EQU H'0006' RXB1OVFL EQU H'0006' TXBO EQU H'0005' TXBP EQU H'0004' RXBP EQU H'0003' TXWARN EQU H'0002' RXWARN EQU H'0001' EWARN EQU H'0000' ;----- CIOCON Bits ----------------------------------------------------------- ENDRHI EQU H'0005' CANCAP EQU H'0004' ;----- BRGCON3 Bits ---------------------------------------------------------- WAKFIL EQU H'0006' SEG2PH2 EQU H'0002' SEG2PH1 EQU H'0001' SEG2PH0 EQU H'0000' ;----- BRGCON2 Bits ----------------------------------------------------------- SEG2PHTS EQU H'0007' SAM EQU H'0006' SEG1PH2 EQU H'0005' SEG1PH1 EQU H'0004' SEG1PH0 EQU H'0003' PRSEG2 EQU H'0002' PRSEG1 EQU H'0001' PRSEG0 EQU H'0000' ;----- BRGCON1 Bits ------------------------------------------------------------ SJW1 EQU H'0007' SJW0 EQU H'0006' BRP5 EQU H'0005' BRP4 EQU H'0004' BRP3 EQU H'0003' BRP2 EQU H'0002' BRP1 EQU H'0001' BRP0 EQU H'0000' ;----- CANCON Bits -------------------------------------------------------- REQOP2 EQU H'0007' REQOP1 EQU H'0006' REQOP0 EQU H'0005' ABAT EQU H'0004' WIN2 EQU H'0003' WIN1 EQU H'0002' WIN0 EQU H'0001' ;----- CANSTAT Bits ------------------------------------------------------- OPMODE2 EQU H'0007' OPMODE1 EQU H'0006' OPMODE0 EQU H'0005' ICODE2 EQU H'0003' ICODE1 EQU H'0002' ICODE0 EQU H'0001' ;----- RXBnCON Bits ------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' RXB0DBEN EQU H'0002' FILHIT2 EQU H'0002' JTOFF EQU H'0001' FILHIT1 EQU H'0001' FILHIT0 EQU H'0000' ;----- TXBnCON Bits ------------------------------------------------------- TXABT EQU H'0006' TXLARB EQU H'0005' TXERR EQU H'0004' TXREQ EQU H'0003' TXPRI1 EQU H'0001' TXPRI0 EQU H'0000' ;----- TXERRCNT Bits ---------------------------------------------------------- TEC7 EQU H'0007' TEC6 EQU H'0006' TEC5 EQU H'0005' TEC4 EQU H'0004' TEC3 EQU H'0003' TEC2 EQU H'0002' TEC1 EQU H'0001' TEC0 EQU H'0000' ;----- RXERRCNT Bits ---------------------------------------------------------- REC7 EQU H'0007' REC6 EQU H'0006' REC5 EQU H'0005' REC4 EQU H'0004' REC3 EQU H'0003' REC2 EQU H'0002' REC1 EQU H'0001' REC0 EQU H'0000' ;----- RXBnDLC and TXBnDLC Bits ----------------------------------------------- RXRTR EQU H'0006' TXRTR EQU H'0006' RESB1 EQU H'0005' RESB0 EQU H'0004' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DLC0 EQU H'0000' ;----- RXBnEIDL, RXFnEIDL, RXMnEIDL, and TXBnEIDL Bits ------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXBnEIDH, RXFnEIDH, RXMnEIDH, and TXBnEIDH Bits ------------------------- EID15 EQU H'0007' EID14 EQU H'0006' EID13 EQU H'0005' EID12 EQU H'0004' EID11 EQU H'0003' EID10 EQU H'0002' EID9 EQU H'0001' EID8 EQU H'0000' ;----- RXBnSIDL, RXFnSIDL, RXMnSIDL, and TXBnSIDL Bits ---------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' SRR EQU H'0004' EXID EQU H'0003' EXIDE EQU H'0003' EXIDEN EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXBnSIDH, RXFnSIDH, RXMnSIDH, and TXBnSIDH Bits ---------------------- SID10 EQU H'0007' SID9 EQU H'0006' SID8 EQU H'0005' SID7 EQU H'0004' SID6 EQU H'0003' SID5 EQU H'0002' SID4 EQU H'0001' SID3 EQU H'0001' ;----- RXB0D7 Bits ---------------------------------------------------------- RB0D77 EQU H'0007' RB0D76 EQU H'0006' RB0D75 EQU H'0005' RB0D74 EQU H'0004' RB0D73 EQU H'0003' RB0D72 EQU H'0002' RB0D71 EQU H'0001' RB0D70 EQU H'0000' ;----- RXB0D6 Bits ---------------------------------------------------------- RB0D67 EQU H'0007' RB0D66 EQU H'0006' RB0D65 EQU H'0005' RB0D64 EQU H'0004' RB0D63 EQU H'0003' RB0D62 EQU H'0002' RB0D61 EQU H'0001' RB0D60 EQU H'0000' ;----- RXB0D5 Bits ---------------------------------------------------------- RB0D57 EQU H'0007' RB0D56 EQU H'0006' RB0D55 EQU H'0005' RB0D54 EQU H'0004' RB0D53 EQU H'0003' RB0D52 EQU H'0002' RB0D51 EQU H'0001' RB0D50 EQU H'0000' ;----- RXB0D4 Bits ---------------------------------------------------------- RB0D47 EQU H'0007' RB0D46 EQU H'0006' RB0D45 EQU H'0005' RB0D44 EQU H'0004' RB0D43 EQU H'0003' RB0D42 EQU H'0002' RB0D41 EQU H'0001' RB0D40 EQU H'0000' ;----- RXB0D3 Bits ---------------------------------------------------------- RB0D37 EQU H'0007' RB0D36 EQU H'0006' RB0D35 EQU H'0005' RB0D34 EQU H'0004' RB0D33 EQU H'0003' RB0D32 EQU H'0002' RB0D31 EQU H'0001' RB0D30 EQU H'0000' ;----- RXB0D2 Bits ---------------------------------------------------------- RB0D27 EQU H'0007' RB0D26 EQU H'0006' RB0D25 EQU H'0005' RB0D24 EQU H'0004' RB0D23 EQU H'0003' RB0D22 EQU H'0002' RB0D21 EQU H'0001' RB0D20 EQU H'0000' ;----- RXB0D1 Bits ---------------------------------------------------------- RB0D17 EQU H'0007' RB0D16 EQU H'0006' RB0D15 EQU H'0005' RB0D14 EQU H'0004' RB0D13 EQU H'0003' RB0D12 EQU H'0002' RB0D11 EQU H'0001' RB0D10 EQU H'0000' ;----- RXB0D0 Bits ---------------------------------------------------------- RB0D07 EQU H'0007' RB0D06 EQU H'0006' RB0D05 EQU H'0005' RB0D04 EQU H'0004' RB0D03 EQU H'0003' RB0D02 EQU H'0002' RB0D01 EQU H'0001' RB0D00 EQU H'0000' ;----- RXB1D7 Bits ---------------------------------------------------------- RXB1D77 EQU H'0007' RXB1D76 EQU H'0006' RXB1D75 EQU H'0005' RXB1D74 EQU H'0004' RXB1D73 EQU H'0003' RXB1D72 EQU H'0002' RXB1D71 EQU H'0001' RXB1D70 EQU H'0000' ;----- RXB1D6 Bits ---------------------------------------------------------- RXB1D67 EQU H'0007' RXB1D66 EQU H'0006' RXB1D65 EQU H'0005' RXB1D64 EQU H'0004' RXB1D63 EQU H'0003' RXB1D62 EQU H'0002' RXB1D61 EQU H'0001' RXB1D60 EQU H'0000' ;----- RXB1D5 Bits ---------------------------------------------------------- RXB1D57 EQU H'0007' RXB1D56 EQU H'0006' RXB1D55 EQU H'0005' RXB1D54 EQU H'0004' RXB1D53 EQU H'0003' RXB1D52 EQU H'0002' RXB1D51 EQU H'0001' RXB1D50 EQU H'0000' ;----- RXB1D4 Bits ---------------------------------------------------------- RXB1D47 EQU H'0007' RXB1D46 EQU H'0006' RXB1D45 EQU H'0005' RXB1D44 EQU H'0004' RXB1D43 EQU H'0003' RXB1D42 EQU H'0002' RXB1D41 EQU H'0001' RXB1D40 EQU H'0000' ;----- RXB1D3 Bits ---------------------------------------------------------- RXB1D37 EQU H'0007' RXB1D36 EQU H'0006' RXB1D35 EQU H'0005' RXB1D34 EQU H'0004' RXB1D33 EQU H'0003' RXB1D32 EQU H'0002' RXB1D31 EQU H'0001' RXB1D30 EQU H'0000' ;----- RXB1D2 Bits ---------------------------------------------------------- RXB1D27 EQU H'0007' RXB1D26 EQU H'0006' RXB1D25 EQU H'0005' RXB1D24 EQU H'0004' RXB1D23 EQU H'0003' RXB1D22 EQU H'0002' RXB1D21 EQU H'0001' RXB1D20 EQU H'0000' ;----- RXB1D1 Bits ---------------------------------------------------------- RXB1D17 EQU H'0007' RXB1D16 EQU H'0006' RXB1D15 EQU H'0005' RXB1D14 EQU H'0004' RXB1D13 EQU H'0003' RXB1D12 EQU H'0002' RXB1D11 EQU H'0001' RXB1D10 EQU H'0000' ;----- RXB1D0 Bits ---------------------------------------------------------- RXB1D07 EQU H'0007' RXB1D06 EQU H'0006' RXB1D05 EQU H'0005' RXB1D04 EQU H'0004' RXB1D03 EQU H'0003' RXB1D02 EQU H'0002' RXB1D01 EQU H'0001' RXB1D00 EQU H'0000' ;----- TXB2D7 Bits ---------------------------------------------------------- TXB2D77 EQU H'0007' TXB2D76 EQU H'0006' TXB2D75 EQU H'0005' TXB2D74 EQU H'0004' TXB2D73 EQU H'0003' TXB2D72 EQU H'0002' TXB2D71 EQU H'0001' TXB2D70 EQU H'0000' ;----- TXB2D6 Bits ---------------------------------------------------------- TXB2D67 EQU H'0007' TXB2D66 EQU H'0006' TXB2D65 EQU H'0005' TXB2D64 EQU H'0004' TXB2D63 EQU H'0003' TXB2D62 EQU H'0002' TXB2D61 EQU H'0001' TXB2D60 EQU H'0000' ;----- TXB2D5 Bits ---------------------------------------------------------- TXB2D57 EQU H'0007' TXB2D56 EQU H'0006' TXB2D55 EQU H'0005' TXB2D54 EQU H'0004' TXB2D53 EQU H'0003' TXB2D52 EQU H'0002' TXB2D51 EQU H'0001' TXB2D50 EQU H'0000' ;----- TXB2D4 Bits ---------------------------------------------------------- TXB2D47 EQU H'0007' TXB2D46 EQU H'0006' TXB2D45 EQU H'0005' TXB2D44 EQU H'0004' TXB2D43 EQU H'0003' TXB2D42 EQU H'0002' TXB2D41 EQU H'0001' TXB2D40 EQU H'0000' ;----- TXB2D3 Bits ---------------------------------------------------------- TXB2D37 EQU H'0007' TXB2D36 EQU H'0006' TXB2D35 EQU H'0005' TXB2D34 EQU H'0004' TXB2D33 EQU H'0003' TXB2D32 EQU H'0002' TXB2D31 EQU H'0001' TXB2D30 EQU H'0000' ;----- TXB2D2 Bits ---------------------------------------------------------- TXB2D27 EQU H'0007' TXB2D26 EQU H'0006' TXB2D25 EQU H'0005' TXB2D24 EQU H'0004' TXB2D23 EQU H'0003' TXB2D22 EQU H'0002' TXB2D21 EQU H'0001' TXB2D20 EQU H'0000' ;----- TXB2D1 Bits ---------------------------------------------------------- TXB2D17 EQU H'0007' TXB2D16 EQU H'0006' TXB2D15 EQU H'0005' TXB2D14 EQU H'0004' TXB2D13 EQU H'0003' TXB2D12 EQU H'0002' TXB2D11 EQU H'0001' TXB2D10 EQU H'0000' ;----- TXB2D0 Bits ---------------------------------------------------------- TXB2D07 EQU H'0007' TXB2D06 EQU H'0006' TXB2D05 EQU H'0005' TXB2D04 EQU H'0004' TXB2D03 EQU H'0003' TXB2D02 EQU H'0002' TXB2D01 EQU H'0001' TXB2D00 EQU H'0000' ;----- TXB1D7 Bits ---------------------------------------------------------- TXB1D77 EQU H'0007' TXB1D76 EQU H'0006' TXB1D75 EQU H'0005' TXB1D74 EQU H'0004' TXB1D73 EQU H'0003' TXB1D72 EQU H'0002' TXB1D71 EQU H'0001' TXB1D70 EQU H'0000' ;----- TXB1D6 Bits ---------------------------------------------------------- TXB1D67 EQU H'0007' TXB1D66 EQU H'0006' TXB1D65 EQU H'0005' TXB1D64 EQU H'0004' TXB1D63 EQU H'0003' TXB1D62 EQU H'0002' TXB1D61 EQU H'0001' TXB1D60 EQU H'0000' ;----- TXB1D5 Bits ---------------------------------------------------------- TXB1D57 EQU H'0007' TXB1D56 EQU H'0006' TXB1D55 EQU H'0005' TXB1D54 EQU H'0004' TXB1D53 EQU H'0003' TXB1D52 EQU H'0002' TXB1D51 EQU H'0001' TXB1D50 EQU H'0000' ;----- TXB1D4 Bits ---------------------------------------------------------- TXB1D47 EQU H'0007' TXB1D46 EQU H'0006' TXB1D45 EQU H'0005' TXB1D44 EQU H'0004' TXB1D43 EQU H'0003' TXB1D42 EQU H'0002' TXB1D41 EQU H'0001' TXB1D40 EQU H'0000' ;----- TXB1D3 Bits ---------------------------------------------------------- TXB1D37 EQU H'0007' TXB1D36 EQU H'0006' TXB1D35 EQU H'0005' TXB1D34 EQU H'0004' TXB1D33 EQU H'0003' TXB1D32 EQU H'0002' TXB1D31 EQU H'0001' TXB1D30 EQU H'0000' ;----- TXB1D2 Bits ---------------------------------------------------------- TXB1D27 EQU H'0007' TXB1D26 EQU H'0006' TXB1D25 EQU H'0005' TXB1D24 EQU H'0004' TBB1D23 EQU H'0003' TXB1D22 EQU H'0002' TXB1D21 EQU H'0001' TXB1D20 EQU H'0000' ;----- TXB1D1 Bits ---------------------------------------------------------- TXB1D17 EQU H'0007' TXB1D16 EQU H'0006' TXB1D15 EQU H'0005' TXB1D14 EQU H'0004' TXB1D13 EQU H'0003' TXB1D12 EQU H'0002' TXB1D11 EQU H'0001' TXB1D10 EQU H'0000' ;----- TXB1D0 Bits ---------------------------------------------------------- TXB1D07 EQU H'0007' TXB1D06 EQU H'0006' TXB1D05 EQU H'0005' TXB1D04 EQU H'0004' TXB1D03 EQU H'0003' TXB1D02 EQU H'0002' TXB1D01 EQU H'0001' TXB1D00 EQU H'0000' ;----- TXB0D7 Bits ---------------------------------------------------------- TXB0D77 EQU H'0007' TXB0D76 EQU H'0006' TXB0D75 EQU H'0005' TXB0D74 EQU H'0004' TXB0D73 EQU H'0003' TXB0D72 EQU H'0002' TXB0D71 EQU H'0001' TXB0D70 EQU H'0000' ;----- TXB0D6 Bits ---------------------------------------------------------- TXB0D67 EQU H'0007' TXB0D66 EQU H'0006' TXB0D65 EQU H'0005' TXB0D64 EQU H'0004' TXB0D63 EQU H'0003' TXB0D62 EQU H'0002' TXB0D61 EQU H'0001' TXB0D60 EQU H'0000' ;----- TXB0D5 Bits ---------------------------------------------------------- TXB0D57 EQU H'0007' TXB0D56 EQU H'0006' TXB0D55 EQU H'0005' TXB0D54 EQU H'0004' TXB0D53 EQU H'0003' TXB0D52 EQU H'0002' TXB0D51 EQU H'0001' TXB0D50 EQU H'0000' ;----- TXB0D4 Bits ---------------------------------------------------------- TXB0D47 EQU H'0007' TXB0D46 EQU H'0006' TXB0D45 EQU H'0005' TXB0D44 EQU H'0004' TXB0D43 EQU H'0003' TXB0D42 EQU H'0002' TXB0D41 EQU H'0001' TXB0D40 EQU H'0000' ;----- TXB0D3 Bits ---------------------------------------------------------- TXB0D37 EQU H'0007' TXB0D36 EQU H'0006' TXB0D35 EQU H'0005' TXB0D34 EQU H'0004' TXB0D33 EQU H'0003' TXB0D32 EQU H'0002' TXB0D31 EQU H'0001' TXB0D30 EQU H'0000' ;----- TXB0D2 Bits ---------------------------------------------------------- TXB0D27 EQU H'0007' TXB0D26 EQU H'0006' TXB0D25 EQU H'0005' TXB0D24 EQU H'0004' TXB0D23 EQU H'0003' TXB0D22 EQU H'0002' TXB0D21 EQU H'0001' TXB0D20 EQU H'0000' ;----- TXB0D1 Bits ---------------------------------------------------------- TXB0D17 EQU H'0007' TXB0D16 EQU H'0006' TXB0D15 EQU H'0005' TXB0D14 EQU H'0004' TXB0D13 EQU H'0003' TXB0D12 EQU H'0002' TXB0D11 EQU H'0001' TXB0D10 EQU H'0000' ;----- TXB0D0 Bits ---------------------------------------------------------- TXB0D07 EQU H'0007' TXB0D06 EQU H'0006' TXB0D05 EQU H'0005' TXB0D04 EQU H'0004' TXB0D03 EQU H'0003' TXB0D02 EQU H'0002' TXB0D01 EQU H'0001' TXB0D00 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 NOT_SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 CANTX EQU 2 RB3 EQU 3 CANRX EQU 3 RB4 EQU 4 RB5 EQU 5 PGM EQU 5 RB6 EQU 6 PGC EQU 6 RB7 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'300'-H'EFF' __BADRAM H'FD4',H'FC0',H'FB9',H'FB8',H'FAA',H'F97'-H'F9C' __BADRAM H'F8E'-H'F91',H'F85'-H'F88', H'F79'-H'F7F',H'F77' __BADRAM H'F5F',H'F4F',H'F3F',H'F2F' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000Ah ; CONFIG6H = Configuration Byte 6H 30000Bh ; CONFIG7L = Configuration Byte 7L 30000Ch ; CONFIG7H = Configuration Byte 7H 30000Dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_25_2L EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;Configuration Byte 6H Options _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as _BOR_ON_2L). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_25_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p18f4520.inc0000644000175000017500000012761411156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4520 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4520 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4520 ; 2. LIST directive in the source file ; LIST P=PIC18F4520 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4520 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4510.inc0000644000175000017500000012627111156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4510 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4510 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4510 ; 2. LIST directive in the source file ; LIST P=PIC18F4510 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4510 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCPAS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCPAS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4515.inc0000644000175000017500000012357711156521301013244 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4515 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4515 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4515 ; 2. LIST directive in the source file ; LIST P=PIC18F4515 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4515 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCPAS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' DAD5 EQU H'0005' DAD6 EQU H'0006' DAD7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCPAS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c716.inc0000644000175000017500000002006111156313161013141 00000000000000 LIST ; P16C716.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C716 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C716 ; 2. LIST directive in the source file ; LIST P=PIC16C716 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 25 Jan 1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C716 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' DATACCP EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISCCP EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- DATACCP Bits -------------------------------------------------------- DCCP EQU H'0002' DT1CK EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISCCP Bits -------------------------------------------------------- TCCP EQU H'0002' TT1CK EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'13'-H'14', H'18'-H'1D' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'93'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f4221.inc0000644000175000017500000012140511156521301013222 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4221 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4221 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4221 ; 2. LIST directive in the source file ; LIST P=PIC18F4221 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4221 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1N EQU H'0000' C2N EQU H'0001' C2P EQU H'0002' C1P EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' HLVDIN EQU H'0005' CVREF EQU H'0002' T0CKI EQU H'0004' NOT_SS EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T016BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' T0IF EQU H'0002' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = RB3 CCP2 input/output is multiplexed with RB3 ; CCP2MX = RC1 CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPORT = OFF ICPORT disabled ; ICPORT = ON ICPORT enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Word ; BBSIZ = BB512 512 Word ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP Oscillator _OSC_XT_1H EQU H'F1' ; XT Oscillator _OSC_HS_1H EQU H'F2' ; HS Oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO2_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO1_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_DIG_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ANA_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_RB3_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_RC1_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _ICPORT_OFF_4L EQU H'F7' ; ICPORT disabled _ICPORT_ON_4L EQU H'FF' ; ICPORT enabled _BBSIZ_BB256_4L EQU H'CF' ; 256 Word _BBSIZ_BB512_4L EQU H'FF' ; 512 Word _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f8628.inc0000644000175000017500000021376711156521301013256 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8628 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8628 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8628 ; 2. LIST directive in the source file ; LIST P=PIC18F8628 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8628 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ECCP2_PORTB EQU H'0003' P2A_PORTB EQU H'0003' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C_PORTE EQU H'0003' P3B_PORTE EQU H'0004' P1C_PORTE EQU H'0005' P1B_PORTE EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' P3C_PORTH EQU H'0004' P3B_PORTH EQU H'0005' P1C_PORTH EQU H'0006' P1B_PORTH EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; Address Bus Width Select bits: ; ADDRBW = ADDR8BIT 8-bit Address Bus ; ADDRBW = ADDR12BIT 12-bit Address Bus ; ADDRBW = ADDR16BIT 16-bit Address Bus ; ADDRBW = ADDR20BIT 20-bit Address Bus ; ; Data Bus Width Select bit: ; DATABW = DATA8BIT 8-bit External Bus mode ; DATABW = DATA16BIT 16-bit External Bus mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits ; WAIT = OFF Wait selections are unavailable for table reads and table writes ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; ECCP MUX bit: ; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively ; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively ; ; CCP2 MUX bit: ; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _ADDRBW_ADDR8BIT_3L EQU H'CF' ; 8-bit Address Bus _ADDRBW_ADDR12BIT_3L EQU H'DF' ; 12-bit Address Bus _ADDRBW_ADDR16BIT_3L EQU H'EF' ; 16-bit Address Bus _ADDRBW_ADDR20BIT_3L EQU H'FF' ; 20-bit Address Bus _DATABW_DATA8BIT_3L EQU H'BF' ; 8-bit External Bus mode _DATABW_DATA16BIT_3L EQU H'FF' ; 16-bit External Bus mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits _WAIT_OFF_3L EQU H'FF' ; Wait selections are unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _ECCPMX_PORTH_3H EQU H'FD' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively _ECCPMX_PORTE_3H EQU H'FF' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively _CCP2MX_PORTBE_3H EQU H'FE' ; ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f43k20.inc0000644000175000017500000013212711156521301013400 00000000000000 LIST ;========================================================================== ; MPASM PIC18F43K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F43K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F43K20 ; 2. LIST directive in the source file ; LIST P=PIC18F43K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F43K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2458.inc0000644000175000017500000014130411156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2458 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2458 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2458 ; 2. LIST directive in the source file ; LIST P=PIC18F2458 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2458 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f873.inc0000644000175000017500000003402111156313161013151 00000000000000 LIST ; P16F873.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F873 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F873 ; 2. LIST directive in the source file ; LIST P=PIC16F873 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.12 01/12/00 Changed some bit names, a register name, configuration bits ; to match datasheet (DS30292B) ;1.11 10/18/98 Changes to file registers to match updated DOS ;1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1 ;1.00 08/07/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F873 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'0FCF' _CP_HALF EQU H'1FDF' _CP_UPPER_256 EQU H'2FEF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f6525.inc0000644000175000017500000014000011156521301013223 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6525 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6525 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6525 ; 2. LIST directive in the source file ; LIST P=PIC18F6525 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6525 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ECCP2DEL EQU H'0F67' PWM2CON EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' PWM3CON EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' PWM1CON EQU H'0F79' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' VPP EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' CCP3Y EQU H'0004' CCP3X EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F00'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; OSC = ECIOPLL EC-OSC2 as RA6 and PLL ; OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL ; OSC = HSSWPLL HS with SW PLL ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 or RE7 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC-OSC2 as RA6 and PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC-OSC2 as RA6 and SW PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS with SW PLL _OSCS_ON_1H EQU H'DF' ; Enabled _OSCS_OFF_1H EQU H'FF' ; Disabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 or RE7 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4410.inc0000644000175000017500000012137611156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4410 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4410 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4410 ; 2. LIST directive in the source file ; LIST P=PIC18F4410 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4410 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCPAS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' DAD5 EQU H'0005' DAD6 EQU H'0006' DAD7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCPAS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p17c766.inc0000644000175000017500000004552611156313161013164 00000000000000 LIST ; P17C766.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C766 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C766 ; 2. LIST directive in the source file ; LIST P=PIC17C766 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/01/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C766 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' BANK4 EQU H'0004' BANK5 EQU H'0005' BANK6 EQU H'0006' BANK7 EQU H'0007' BANK8 EQU H'0008' ; added 5/2/01 BD - Apps GPR_BANK0 EQU H'0000' GPR_BANK1 EQU H'0008' GPR_BANK2 EQU H'0010' GPR_BANK3 EQU H'0018' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' ;----- Bank 0 ------------------------------------------------------------- PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCSTA1 EQU H'0013' RCREG EQU H'0014' ; Backward compatibility only RCREG1 EQU H'0014' TXSTA EQU H'0015' ; Backward compatibility only TXSTA1 EQU H'0015' TXREG EQU H'0016' ; Backward compatibility only TXREG1 EQU H'0016' SPBRG EQU H'0017' ; Backward compatibility only SPBRG1 EQU H'0017' ;----- Bank 1 ------------------------------------------------------------- DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' ; Backward compatibility only PIR1 EQU H'0116' PIE EQU H'0117' ; Backward compatibility only PIE1 EQU H'0117' ;----- Bank 2 ------------------------------------------------------------- TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' ;----- Bank 3 ------------------------------------------------------------- PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- Bank 4 ------------------------------------------------------------- PIR2 EQU H'0410' PIE2 EQU H'0411' RCSTA2 EQU H'0413' RCREG2 EQU H'0414' TXSTA2 EQU H'0415' TXREG2 EQU H'0416' SPBRG2 EQU H'0417' ;----- Bank 5 ------------------------------------------------------------- DDRF EQU H'0510' PORTF EQU H'0511' DDRG EQU H'0512' PORTG EQU H'0513' ADCON0 EQU H'0514' ADCON1 EQU H'0515' ADRESL EQU H'0516' ADRESH EQU H'0517' ;----- Bank 6 ------------------------------------------------------------- SSPADD EQU H'0610' SSPCON1 EQU H'0611' SSPCON2 EQU H'0612' SSPSTAT EQU H'0613' SSPBUF EQU H'0614' ;----- Bank 7 ------------------------------------------------------------- PW3DCL EQU H'0710' PW3DCH EQU H'0711' CA3L EQU H'0712' CA3H EQU H'0713' CA4L EQU H'0714' CA4H EQU H'0715' TCON3 EQU H'0716' ;----- Bank 8 ------------------------------------------------------------- DDRH EQU H'0810' PORTH EQU H'0811' DDRJ EQU H'0812' PORTJ EQU H'0813' ;----- Unbanked ----------------------------------------------------------- PRODL EQU H'0018' PL EQU H'0018' ; Backward compatibility only PRODH EQU H'0019' PH EQU H'0019' ; Backward compatibility only ;----- Special Function Register Bit Definitions -------------------------- ; ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' ; Backward compatibility only TX1IF EQU H'0001' RCIF EQU H'0000' ; Backward compatibility only RC1IF EQU H'0000' ;----- PIE1 Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' ; Backward compatibility only TX1IE EQU H'0001' RCIE EQU H'0000' ; Backward compatibility only RC1IE EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' ;----- RCSTA1 and 2 Bits -------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' ; Backward compatibility only T0PS2 EQU H'0003' PS2 EQU H'0003' ; Backward compatibility only T0PS1 EQU H'0002' PS1 EQU H'0002' ; Backward compatibility only T0PS0 EQU H'0001' PS0 EQU H'0001' ; Backward compatibility only ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- SSPIF EQU H'0007' BCLIF EQU H'0006' ADIF EQU H'0005' CA4IF EQU H'0003' CA3IF EQU H'0002' TX2IF EQU H'0001' RC2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- SSPIE EQU H'0007' BCLIE EQU H'0006' ADIE EQU H'0005' CA4IE EQU H'0003' CA3IE EQU H'0002' TX2IE EQU H'0001' RC2IE EQU H'0000' ;----- TXSTA1 and 2 Bits -------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0007' CHS2 EQU H'0006' CHS1 EQU H'0005' CHS0 EQU H'0004' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' ADFM EQU H'0005' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- SSPCON1 Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' AKSTAT EQU H'0006' ACKDT EQU H'0005' AKDT EQU H'0005' ACKEN EQU H'0004' AKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' NOT_A EQU H'0005' D_A EQU H'0005' P EQU H'0004' S EQU H'0003' R EQU H'0002' NOT_W EQU H'0002' R_W EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TCON3 Bits --------------------------------------------------------- CA4OVF EQU H'0006' CA3OVF EQU H'0005' CA4ED1 EQU H'0004' CA4ED0 EQU H'0003' CA3ED1 EQU H'0002' CA3ED0 EQU H'0001' PWM3ON EQU H'0000' ;----- PW2DCL Bit --------------------------------------------------------- TM2PW2 EQU H'0005' ;----- PW3DCL Bit --------------------------------------------------------- TM2PW3 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'8FF' __BADRAM H'118'-H'11F', H'218'-H'21F', H'318'-H'31F' __BADRAM H'412', H'418'-H'4FF' __BADRAM H'518'-H'5FF' __BADRAM H'615'-H'6FF' __BADRAM H'717'-H'7FF' __BADRAM H'814'-H'8FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _BODEN_OFF EQU H'BFFF' _BODEN_ON EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _WDT_0 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p10f202.inc0000644000175000017500000001027011156313161013125 00000000000000 LIST ; P10F202.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC10F202 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P10F202 ; 2. LIST directive in the source file ; LIST P=10F202 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/14/04 Initial Release ;1.01 10/05/05 Add IntRC_OSC comment ;1.02 01/13/06 Added GPIO bit descriptions ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __10F202 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' FOSC4 EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' __BADRAM H'07' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _IntRC_OSC EQU H'0FFF';IntRC_OSC is the only option. ;It is here for backwards compatibility ;only. LIST gputils-0.13.7/header/p16f630.inc0000644000175000017500000001731511156521301013144 00000000000000 LIST ; P16F630.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F630 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F630 ; 2. LIST directive in the source file ; LIST P=PIC16F630 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 05/13/02 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F630 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' WPUA EQU H'0095' WPU EQU H'0095' IOCA EQU H'0096' IOC EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEDAT EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F' __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16lf727.inc0000644000175000017500000005105011156521301013321 00000000000000 LIST ; P16LF727.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16LF727 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16LF727 ; 2. LIST directive in the source file ; LIST P=PIC16LF727 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/25/07 Initial template ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF727 MESSG "Processor-header file mismatch. Verify selected processor." #define __16LF727 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' ANSELD EQU H'0188' ANSELE EQU H'0189' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- ANSELD Bits --------------------------------------------------------- ANSD7 EQU H'0007' ANSD6 EQU H'0006' ANSD5 EQU H'0005' ANSD4 EQU H'0004' ANSD3 EQU H'0003' ANSD2 EQU H'0002' ANSD1 EQU H'0001' ANSD0 EQU H'0000' ;----- ANSELE Bits --------------------------------------------------------- ANSE2 EQU H'0002' ANSE1 EQU H'0001' ANSE0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'187', H'18D'-H'18F' LIST gputils-0.13.7/header/p18f65j50.inc0000644000175000017500000017023711156521301013412 00000000000000 LIST ;========================================================================== ; MPASM PIC18F65J50 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F65J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F65J50 ; 2. LIST directive in the source file ; LIST P=PIC18F65J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F65J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p12f635.inc0000644000175000017500000002663611156521301013153 00000000000000 LIST ; P12F635.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F635 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12F635 ; 2. LIST directive in the source file ; LIST P=PIC12F635 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 12/07/03 Original ;1.10 04/19/04 Release to match first revision datasheet --kjd ;1.20 06/07/04 Update and correct badram definitions --kjd ;1.30 07/03/07 Added COUT and CINV to match datasheet --src ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F635 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ ;Bank 0 INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' WDTCON EQU H'0018' CMCON0 EQU H'0019' CMCON1 EQU H'001A' ;Bank 1 OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' LVDCON EQU H'0094' WPUDA EQU H'0095' IOCA EQU H'0096' WDA EQU H'0097' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ;Bank 2 CRCON EQU H'0110' CRDAT0 EQU H'0111' CRDAT1 EQU H'0112' CRDAT2 EQU H'0113' CRDAT3 EQU H'0114' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' LVDIF EQU H'0006' CRIF EQU H'0005' C1IF EQU H'0003' OSFIF EQU H'0002' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C1OUT EQU H'0006' COUT EQU H'0006' C1INV EQU H'0004' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1GSS EQU H'0001' C1SYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' LVDIE EQU H'0006' CRIE EQU H'0005' C1IE EQU H'0003' OSFIE EQU H'0002' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBODEN EQU H'0004' NOT_WUR EQU H'0003' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits ---------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CRCON Bits -------------------------------------------------------- GO EQU H'0007' ENC_DEC EQU H'0006' CRREG1 EQU H'0001' CRREG0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' PLVDEN EQU H'0004' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDA Bits ----------------------------------------------------------- WDA5 EQU H'0005' WDA4 EQU H'0004' WDA2 EQU H'0002' WDA1 EQU H'0001' WDA0 EQU H'0000' ;----- WPUDA Bits ----------------------------------------------------------- WPUDA5 EQU H'0005' WPUDA4 EQU H'0004' WPUDA2 EQU H'0002' WPUDA1 EQU H'0001' WPUDA0 EQU H'0000' ;----- PORTA Bits ----------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- GPIO Bits ----------------------------------------------------------- GP5 EQU H'0005' GP4 EQU H'0004' GP3 EQU H'0003' GP2 EQU H'0002' GP1 EQU H'0001' GP0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'06'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F', H'20'-H'3F' __BADRAM H'86'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'A0'-H'EF' __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106'-H'109', H'186'-H'189' __BADRAM H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _WUREN_ON EQU H'2FFF' _WUREN_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18f4523.inc0000644000175000017500000013061211156521301013227 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4523 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4523 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4523 ; 2. LIST directive in the source file ; LIST P=PIC18F4523 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4523 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' C1OUT_PORTA EQU H'0004' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' HLVDIN EQU H'0005' LVDIN EQU H'0005' C2OUT_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' P1A EQU H'0002' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTB CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTB_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f87j90.inc0000644000175000017500000017207411156521301013423 00000000000000 LIST ;========================================================================== ; MPASM PIC18F87J90 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F87J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F87J90 ; 2. LIST directive in the source file ; LIST P=PIC18F87J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F87J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PADCFG1 EQU H'0F54' CTMUICON EQU H'0F55' CTMUCONL EQU H'0F56' CTMUCONH EQU H'0F57' ALRMVALL EQU H'0F58' ALRMVALH EQU H'0F59' ALRMRPT EQU H'0F5A' ALRMCFG EQU H'0F5B' RTCVALL EQU H'0F5C' RTCVALH EQU H'0F5D' RTCCAL EQU H'0F5E' RTCCFG EQU H'0F5F' RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' ECCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' ECCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA5 EQU H'0F6B' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA11 EQU H'0F71' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA17 EQU H'0F77' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' LCDDATA23 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' TRISF EQU H'0F97' TRISG EQU H'0F98' TRISH EQU H'0F99' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDSE5 EQU H'0FBA' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PADCFG1 Bits ----------------------------------------------------- RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' SEG00COM3 EQU H'0000' SEG01COM3 EQU H'0001' SEG02COM3 EQU H'0002' SEG03COM3 EQU H'0003' SEG04COM3 EQU H'0004' SEG05COM3 EQU H'0005' SEG06COM3 EQU H'0006' SEG07COM3 EQU H'0007' S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' TOCKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' CTED1 EQU H'0002' CTED2 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' CTPLS EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' CVREF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' TX2 EQU H'0001' RX2 EQU H'0002' RTCC EQU H'0004' VLCAP1 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' CCP1IE EQU H'0001' CCP2IE EQU H'0002' CTMUIE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' CCP1IF EQU H'0001' CCP2IF EQU H'0002' CTMUIF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' CCP1IP EQU H'0001' CCP2IP EQU H'0002' CTMUIP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- TRIGSEL EQU H'0007' PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM_RCON EQU H'0005' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- MODE13 EQU H'0002' CPEN EQU H'0006' CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- IOFS EQU H'0002' OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled-Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Oscillator Selection bits: ; OSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; OSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; OSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; OSC = INTOSCPLLO INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 ; OSC = HS HS oscillator ; OSC = HSPLL HS oscillator, PLL enabled ; OSC = EC EC Oscillator with clock out on RA6 ; OSC = ECPLL EC Oscillator with PLL ; ; Secondary Clock Source T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = ON Timer1 oscillator configured for low-power operation ; LPT1OSC = OFF Timer1 oscillator configured for higher power operation ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Reference Clock Select bit: ; RTCSOSC = INTOSCREF RTCC uses INTOSC/INTRC as reference clock ; RTCSOSC = T1OSCREF RTCC uses T1OSC/T1CKI as reference clock ; ; CCP2 MUX: ; CCP2MX = ALTERNATE RE7 / RB3 ; CCP2MX = DEFAULT RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f687.inc0000644000175000017500000005023011156521302013152 00000000000000 LIST ; P16F687.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F687 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F687 ; 2. LIST directive in the source file ; LIST P=PIC16F687 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/12/04 Original ;2.00 04/21/05 Modified to match released datasheet ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F687 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' SSPBUF EQU H'0013' SSPCON EQU H'0014' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPADD EQU H'0093' MSK EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' WDTCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' BAUDCTL EQU H'009B' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDAT EQU H'010C' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' WPUB EQU H'0115' IOCB EQU H'0116' VRCON EQU H'0118' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' ANSEL EQU H'011E' ANSELH EQU H'011F' EECON1 EQU H'018C' EECON2 EQU H'018D' SRCON EQU H'019E' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RABIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RABIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION Bits -------------------------------------------------------- NOT_RABPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TRISB7 EQU H'0007' TRISB6 EQU H'0006' TRISB5 EQU H'0005' TRISB4 EQU H'0004' ;----- TRISC Bits -------------------------------------------------------- TRISC7 EQU H'0007' TRISC6 EQU H'0006' TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits -------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' SENB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' ;----- IOCB Bits --------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'- H'1D' __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D', H'C0'-H'EF' __BADRAM H'108'-H'109', H'10E'-H'114', H'117', H'11C'-H'11D', H'120'-H'16F' __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f45k20.inc0000644000175000017500000013650511156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F45K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F45K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F45K20 ; 2. LIST directive in the source file ; LIST P=PIC18F45K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F45K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2553.inc0000644000175000017500000014350711156521301013237 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2553 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2553 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2553 ; 2. LIST directive in the source file ; LIST P=PIC18F2553 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2553 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f46j50.inc0000644000175000017500000020234011156521301013400 00000000000000 LIST ;========================================================================== ; MPASM PIC18F46J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F46J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F46J50 ; 2. LIST directive in the source file ; LIST P=PIC18F46J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F46J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f2221.inc0000644000175000017500000011261711156521302013226 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2221 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2221 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2221 ; 2. LIST directive in the source file ; LIST P=PIC18F2221 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2221 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1N EQU H'0000' C2N EQU H'0001' C2P EQU H'0002' C1P EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' HLVDIN EQU H'0005' CVREF EQU H'0002' T0CKI EQU H'0004' NOT_SS EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T016BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' T0IF EQU H'0002' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = RB3 CCP2 input/output is multiplexed with RB3 ; CCP2MX = RC1 CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Word ; BBSIZ = BB512 512 Word ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP Oscillator _OSC_XT_1H EQU H'F1' ; XT Oscillator _OSC_HS_1H EQU H'F2' ; HS Oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO2_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO1_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_DIG_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ANA_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_RB3_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_RC1_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB256_4L EQU H'CF' ; 256 Word _BBSIZ_BB512_4L EQU H'FF' ; 512 Word _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f1934.inc0000644000175000017500000012543711156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC16F1934 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16F1934 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16F1934 ; 2. LIST directive in the source file ; LIST P=PIC16F1934 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F1934 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTD EQU H'000F' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISD EQU H'008F' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATD EQU H'010F' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' ANSELD EQU H'018F' ANSELE EQU H'0190' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDSE2 EQU H'079A' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA2 EQU H'07A2' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA5 EQU H'07A5' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA8 EQU H'07A8' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' LCDDATA11 EQU H'07AB' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' CPSCH3 EQU H'0003' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- ANSELD Bits ----------------------------------------------------- ANSD0 EQU H'0000' ANSD1 EQU H'0001' ANSD2 EQU H'0002' ANSD3 EQU H'0003' ANSD4 EQU H'0004' ANSD5 EQU H'0005' ANSD6 EQU H'0006' ANSD7 EQU H'0007' ;----- ANSELE Bits ----------------------------------------------------- ANSE0 EQU H'0000' ANSE1 EQU H'0001' ANSE2 EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SEG16 EQU H'0000' SEG17 EQU H'0001' SEG18 EQU H'0002' SEG19 EQU H'0003' SEG20 EQU H'0004' SEG21 EQU H'0005' SEG22 EQU H'0006' SEG23 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA2 Bits ----------------------------------------------------- SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA8 Bits ----------------------------------------------------- SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E' __BADRAM H'0197'-H'0198' __BADRAM H'01A0'-H'01EF' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'0220'-H'026F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'02A0'-H'02EF' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0320'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079B'-H'079F' __BADRAM H'07AC'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _nPWRTE_OFF EQU H'FFDF' ; PWRT enabled _nPWRTE_ON EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _nDEBUG_ON EQU H'EFFF' ; Background debugger is enabled _nDEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p18lf24j11.inc0000644000175000017500000013646511156521302013564 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF24J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF24J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF24J11 ; 2. LIST directive in the source file ; LIST P=PIC18LF24J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF24J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ULPWU EQU H'0000' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F65' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/rf675f.inc0000644000175000017500000002156311156313161013161 00000000000000 LIST ; RF675F.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the rfPIC12F675F microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PICRF675F ; 2. LIST directive in the source file ; LIST P=RF675F ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 02/19/03 Original -- copied from P12F675.INC (pas) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __RF675F MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' WPU EQU H'0095' IOC EQU H'0096' IOCB EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 ------------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ANSEL -------------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16c72.inc0000644000175000017500000002243711156313161013065 00000000000000 LIST ; P16C72.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C72 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C72 ; 2. LIST directive in the source file ; LIST P=PIC16C72 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C72 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1D' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f4580.inc0000644000175000017500000042475411156521301013247 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4580 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4580 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4580 ; 2. LIST directive in the source file ; LIST P=PIC18F4580 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4580 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' ECCP1CON EQU H'0FBA' ECCPR1 EQU H'0FBB' ECCPR1L EQU H'0FBB' ECCPR1H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREFA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' C1INB EQU H'0000' C1INA EQU H'0001' C2INB EQU H'0002' C2INA EQU H'0003' P1A EQU H'0004' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ECCP1 EQU H'0004' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- ECCP1IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- ECCP1IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- ECCP1IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- ECCP1M0 EQU H'0000' ECCP1M1 EQU H'0001' ECCP1M2 EQU H'0002' ECCP1M3 EQU H'0003' EDC1B0 EQU H'0004' EDC1B1 EQU H'0005' EPWM1M0 EQU H'0006' EPWM1M1 EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0CFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'EF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'FF' ; 2K words (4K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/migrate.inc0000644000175000017500000000105311156313161013562 00000000000000 LIST ; MIGRATE.INC NOLIST ; This file provides macros for ease of migration from ; 16 and 17 devices to 18 devices. ; As is, it must be assembled with case sensitivity enabled (/c+). ; To assemble with /c-, remove the lowercase (or uppercase) version ; of each macro. #define clrw clrf WREG #define CLRW CLRF WREG #define negw negf WREG #define NEGW NEGF WREG #define movpf movff #define MOVPF MOVFF #define movfp movff #define MOVFP MOVFF #define lcall call #define LCALL CALL #define lgoto goto #define LGOTO GOTO LIST gputils-0.13.7/header/p18f44k20.inc0000644000175000017500000013212711156521301013401 00000000000000 LIST ;========================================================================== ; MPASM PIC18F44K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F44K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F44K20 ; 2. LIST directive in the source file ; LIST P=PIC18F44K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F44K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p10f222.inc0000644000175000017500000001226411156313161013134 00000000000000 LIST ; P10F222.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC10F222 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P10F222 ; 2. LIST directive in the source file ; LIST P=10F222 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 01/19/05 Initial Release ;1.01 08/09/05 Fixed formatting and correct osc speed select fuse name ;1.02 01/13/06 Added GPIO bit descriptions ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __10F222 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ADCON0 EQU H'0007' ADRES EQU H'0008' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' FOSC4 EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- ADRES Bits -------------------------------------------------------- ADRES7 EQU H'0007' ADRES6 EQU H'0006' ADRES5 EQU H'0005' ADRES4 EQU H'0004' ADRES3 EQU H'0003' ADRES2 EQU H'0002' ADRES1 EQU H'0001' ADRES0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _MCPU_ON EQU H'0FFD' _MCPU_OFF EQU H'0FFF' _IOFSCS_8MHZ EQU H'0FFF' _IOFSCS_4MHZ EQU H'0FFE' _IOSCFS_8MHZ EQU H'0FFF';matches datasheet _IOSCFS_4MHZ EQU H'0FFE';matches datasheet LIST gputils-0.13.7/header/p18f83j11.inc0000644000175000017500000013061711156521301013405 00000000000000 LIST ;========================================================================== ; MPASM PIC18F83J11 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F83J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F83J11 ; 2. LIST directive in the source file ; LIST P=PIC18F83J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F83J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' TX2 EQU H'0001' RX2 EQU H'0002' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F6B'-H'0F7D' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB6'-H'0FBF' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode, 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode, 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode, 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 1FF8h ; CONFIG1H 1FF9h ; CONFIG2L 1FFAh ; CONFIG2H 1FFBh ; CONFIG3L 1FFCh ; CONFIG3H 1FFDh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'1FF8' _CONFIG1H EQU H'1FF9' _CONFIG2L EQU H'1FFA' _CONFIG2H EQU H'1FFB' _CONFIG3L EQU H'1FFC' _CONFIG3H EQU H'1FFD' ;----- CONFIG1L Options -------------------------------------------------- _DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled _STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled _WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit) _WDTEN_ON_1L EQU H'FF' ; WDT enabled ;----- CONFIG1H Options -------------------------------------------------- _CP0_ON_1H EQU H'FB' ; Program memory is code-protected _CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected ;----- CONFIG2L Options -------------------------------------------------- _IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled _FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled _FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00 _FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 _FOSC_HS_2L EQU H'FC' ; HS oscillator _FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control _FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2 _FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2 ;----- CONFIG2H Options -------------------------------------------------- _WDTPS_1_2H EQU H'F0' ; 1:1 _WDTPS_2_2H EQU H'F1' ; 1:2 _WDTPS_4_2H EQU H'F2' ; 1:4 _WDTPS_8_2H EQU H'F3' ; 1:8 _WDTPS_16_2H EQU H'F4' ; 1:16 _WDTPS_32_2H EQU H'F5' ; 1:32 _WDTPS_64_2H EQU H'F6' ; 1:64 _WDTPS_128_2H EQU H'F7' ; 1:128 _WDTPS_256_2H EQU H'F8' ; 1:256 _WDTPS_512_2H EQU H'F9' ; 1:512 _WDTPS_1024_2H EQU H'FA' ; 1:1024 _WDTPS_2048_2H EQU H'FB' ; 1:2048 _WDTPS_4096_2H EQU H'FC' ; 1:4096 _WDTPS_8192_2H EQU H'FD' ; 1:8192 _WDTPS_16384_2H EQU H'FE' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _WAIT_ON_3L EQU H'7F' ; Wait states for operations on external memory bus enabled _WAIT_OFF_3L EQU H'FF' ; Wait states for operations on external memory bus disabled _BW_8_3L EQU H'BF' ; 8-bit external bus mode _BW_16_3L EQU H'FF' ; 16-bit external bus mode _MODE_XM20_3L EQU H'CF' ; Extended Microcontroller mode, 20-bit Address mode _MODE_XM16_3L EQU H'DF' ; Extended Microcontroller mode, 16-bit Address mode _MODE_XM12_3L EQU H'EF' ; Extended Microcontroller mode, 12-bit Address mode _MODE_MM_3L EQU H'FF' ; Microcontroller mode - External bus disabled _EASHFT_OFF_3L EQU H'F7' ; Address shifting disabled, address on external bus reflects the PC value _EASHFT_ON_3L EQU H'FF' ; Address shifting enabled, address on external bus is offset to start at 000000h ;----- CONFIG3H Options -------------------------------------------------- _CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode _CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1 _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f8520.inc0000644000175000017500000013214211156521301013230 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8520 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8520 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8520 ; 2. LIST directive in the source file ; LIST P=PIC18F8520 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8520 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DCCP3Y EQU H'0004' DCCP3X EQU H'0005' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F79'-H'0F7F' __BADRAM H'0F9B' __BADRAM H'0FB6' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC-OSC2 as Clock Out ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Processor Mode Selection: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait: ; WAIT = ON Enabled ; WAIT = OFF Disabled ; ; CCP2 MUX: ; CCP2MUX = OFF Uses RE7 ; CCP2MUX = RE7 Uses RE7 ; CCP2MUX = ON Uses RC1 ; CCP2MUX = RC1 Uses RC1 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F8' ; LP _OSC_XT_1H EQU H'F9' ; XT _OSC_HS_1H EQU H'FA' ; HS _OSC_RC_1H EQU H'FB' ; RC-OSC2 as Clock Out _OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6 _OSCS_ON_1H EQU H'DF' ; Enabled _OSCS_OFF_1H EQU H'FF' ; Disabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_25_2L EQU H'FF' ; 2.5V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'F1' ; 1:1 _WDTPS_2_2H EQU H'F3' ; 1:2 _WDTPS_4_2H EQU H'F5' ; 1:4 _WDTPS_8_2H EQU H'F7' ; 1:8 _WDTPS_16_2H EQU H'F9' ; 1:16 _WDTPS_32_2H EQU H'FB' ; 1:32 _WDTPS_64_2H EQU H'FD' ; 1:64 _WDTPS_128_2H EQU H'FF' ; 1:128 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _WAIT_ON_3L EQU H'7F' ; Enabled _WAIT_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _CCP2MUX_OFF_3H EQU H'FE' ; Uses RE7 _CCP2MUX_RE7_3H EQU H'FE' ; Uses RE7 _CCP2MUX_ON_3H EQU H'FF' ; Uses RC1 _CCP2MUX_RC1_3H EQU H'FF' ; Uses RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4220.inc0000644000175000017500000010530111156313161013221 00000000000000 LIST ; P18F4220.INC Standard Header File, Version 0.1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4220 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F4220 ; 2. LIST directive in the source file ; LIST P=PIC18F4220 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 07 Dec 2001 Initial revision BD ;0.11 22 Mar 2002 ECCP registers and bit names revised BD ;0.12 16 Apr 2002 Configuration bit MCLRE moved from 2L to 3H BD ;0.13 22 Apr 2002 T0CON changed back to T0CON BD ;0.14 09 May 2002 ECCP1CON changed to CCP1CON BD ;0.15 5 May 2002 _OSO_ON_1H changed to _IESO_ON_1H BD ; _MCLRE_ON_2L moved/changed to _MCLRE_ON_3H ; ;0.16 24 May 2002 OSCCON bit name corrected BD ; OSCCON register name above bit equates fixed ; T1CON added ; _MCLRE_ON_3H moved to correct register and renamed (again) ;0.17 30 May 2002 _PBAD_DIG_3H had wrong bit cleared BD ;0.18 13 Jun 2002 LVDCON,IRVST added to LVDCON BD ;0.19 09/26/02 Include both names SWDTE and SWDTEN pas ; ;0.20 27 Sep 2002 Add IOFS bit name to OSCCON register BD ; Add ECIO, RCIO, INTIO1, INTIO2 bits to Config Reg 1H ; Add DEBUG bits to Config Reg 4L ;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD ; ;0.22 1 Oct 2003 Bit names changed BD ; LVVn to LVDLn IVRST to IRVST ; FSCMEN to FSCM ; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1, ; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0, ; CVREF,CVRSS ; Removed redundant bit names ; RCIO6 use RCIO INTIO7 use INTIO1 ; ECIO6 use ECIO INTIO67 use INTIO2 ; BKBUG use DEBUG SWDTE use SWDTEN ; T0IE use TMR0IE INT0E use INT0IE ; T0IF use TMR0IF INT0F use INT0IE ; BGST use IRVST T1INSYNC use T1SYNC ; TXD8 use TX9D T3INSYNC use T3SYNC ; TX8_9 use TX9 NOT_TX8 use TX9 ; RC9 use RX9 NOT_RC8 use RX9 ; RC8_9 use RX9 RCD8 use RX9D ; INT2P use INT2IP INT1P use INT1IP ; INT2E use INT2IE INT1E use INT1IE ; INT2F use INT2IF INT1F use INT1IF ; Added equates for PIC16 Compatability ; ADRES, INTF, INTE, CCPnX, CCPnY ; General clean-up (removed some comments) ;======================================================================= ; ; Verify Processor ; ;======================================================================= IFNDEF __18F4220 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution #define ADRES ADRESH ; PIC16 SFR substitution #define INTE INT0IE ; PIC16 bit substitution #define INTF INT0IF ; PIC16 bit substitution #define CCP1X DC1B1 ; PIC16 bit substitution #define CCP1Y DC1B0 ; PIC16 bit substitution #define CCP2X DC2B1 ; PIC16 bit substitution #define CCP2Y DC2B0 ; PIC16 bit substitution #define SCS SCS0 ; PIC18 bit substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ; reserved EQU H'0FB9' ; reserved EQU H'0FB8' PWM1CON EQU H'0FB7' ECCPAS EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ; reserved EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ; reserved EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' ; reserved EQU H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' OSCTUNE EQU H'0F9B' ; reserved EQU H'0F9A' ; reserved EQU H'0F99' ; reserved EQU H'0F98' ; reserved EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ; reserved EQU H'0F91' ; reserved EQU H'0F90' ; reserved EQU H'0F8F' ; reserved EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved EQU H'0F88' ; reserved EQU H'0F87' ; reserved EQU H'0F86' ; reserved EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' INT0IE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' FLTS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ---------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' D_A EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' R_W EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits ---------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ---------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ----------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ---------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- PWM1CON bits ---------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits ----------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- CVRCON Bits ----------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits ------------------------------------------------------ C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------ CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------ SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- OSCFIP EQU H'0007' CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ------------------------------------------------------- OSCFIF EQU H'0007' CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ------------------------------------------------------- OSCFIE EQU H'0007' CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- OSCTUNE Bits ---------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- TRISE Bits ------------------------------------------------------ IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 RA7 EQU 7 OSC1 EQU 7 CLKI EQU 7 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 AN12 EQU 0 RB1 EQU 1 INT1 EQU 1 AN10 EQU 1 RB2 EQU 2 INT2 EQU 2 AN8 EQU 2 RB3 EQU 3 CCP2A EQU 3 AN9 EQU 3 RB4 EQU 4 AN11 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ----------------------------------------------------------- RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 P1A EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;----- PORTD ----------------------------------------------------------- RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 P1B EQU 5 RD6 EQU 6 PSP6 EQU 6 P1C EQU 6 RD7 EQU 7 PSP7 EQU 7 P1D EQU 7 ;----- PORTE ----------------------------------------------------------- RE0 EQU 0 RD EQU 0 AN5 EQU 0 RE1 EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 AN7 EQU 2 RE3 EQU 3 MCLR EQU 3 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'200'-H'F7F' __BADRAM H'F85'-H'F88',H'F8E'-H'F91',H'F97'-H'F9A',H'F9C' __BADRAM H'FA3'-H'FA5',H'FAA',H'FB0',H'FB8'-H'FB9' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = EC External Clock on OSC1, OSC2 as FOSC/4 ; OSC = ECIO External Clock on OSC1, OSC2 as RA6 ; OSC = HSPLL HS + PLL ; OSC = RCIO External RC on OSC1, OSC2 as RA6 ; OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6 ; OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4 ; OSC = RC External RC on OSC1, OSC2 as FOSC/4 ; ; Fail-Safe Clock Monitor: ; FSCM = OFF Fail-Safe Clock Monitor disabled ; FSCM = ON Fail-Safe Clock Monitor enabled ; ; Internal External Switch Over mode: ; IESO = OFF Internal External Switch Over mode disabled ; IESO = ON Internal External Switch Over mode enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; PORTB A/D Enable: ; PBAD = DIG Digital ; PBAD = ANA Analog ; ; CCP2 Pin Function: ; CCP2MX = B3 RB3 ; CCP2MX = OFF RB3 ; CCP2MX = C1 RC1 ; CCP2MX = ON RC1 ; ; Stack Full/Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To embed the Configuration Bits in your source code, paste the ; following lines into your source code in the following format, ; and change the configuration value to the desired setting (such ; as WDT_OFF to WDT_ON). ; These lines are commented out - each __CONFIG line should have the ; preceding semicolon (;) removed when pasted into your source code. ; __CONFIG _CONFIG1H, _IESO_OFF_1H & _FSCM_OFF_1H & _RC_OSC_1H ; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_20_2L ; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H ; __CONFIG _CONFIG3H, _MCLRE_ON_3H & _PBAD_DIG_3H & _CCP2MX_C1_3H ; __CONFIG _CONFIG4L, _BKBUG_OFF_4L & _LVP_OFF_4L & _STVR_OFF_4L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 1H Options _IESO_ON_1H EQU H'FF' ; Internal External oscillator Switch Over mode enabled _IESO_OFF_1H EQU H'7F' ; Internal External oscillator Switch Over mode disabled _FSCM_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _FSCM_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as FOSC/4 _RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6 _LP_OSC_1H EQU H'F0' ; LP Oscillator _XT_OSC_1H EQU H'F1' ; XT Oscillator _HS_OSC_1H EQU H'F2' ; HS Oscillator _HSPLL_OSC_1H EQU H'F6' ; HS + PLL _EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as FOSC/4 _ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6 _INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4 _INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _PWRT_OFF_2L EQU H'FF' ; Power-up Timer disabled _PWRT_ON_2L EQU H'FE' ; Power-up Timer enabled ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled _WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio _WDTPS_16K_2H EQU H'FD' ; 1:16,384 _WDTPS_8K_2H EQU H'FB' ; 1: 8,192 _WDTPS_4K_2H EQU H'F9' ; 1: 4,096 _WDTPS_2K_2H EQU H'F7' ; 1: 2,048 _WDTPS_1K_2H EQU H'F5' ; 1: 1,024 _WDTPS_512_2H EQU H'F3' ; 1: 512 _WDTPS_256_2H EQU H'F1' ; 1: 256 _WDTPS_128_2H EQU H'EF' ; 1: 128 _WDTPS_64_2H EQU H'ED' ; 1: 64 _WDTPS_32_2H EQU H'EB' ; 1: 32 _WDTPS_16_2H EQU H'E9' ; 1: 16 _WDTPS_8_2H EQU H'E7' ; 1: 8 _WDTPS_4_2H EQU H'E5' ; 1: 4 _WDTPS_2_2H EQU H'E3' ; 1: 2 _WDTPS_1_2H EQU H'E1' ; 1: 1 ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'FF' ; MCLR enabled, RE3 input disabled _MCLRE_OFF_3H EQU H'7F' ; MCLR disabled, RE3 input enabled _PBAD_ANA_3H EQU H'FF' ; ADCON<3:0> resets to B'0000' _PBAD_DIG_3H EQU H'FD' ; ADCON<3:0> resets to B'0111' _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin function on RC1 _CCP2MX_OFF_3H EQU H'FE' ; CCP2 pin function on RB3 _CCP2MX_C1_3H EQU H'FF' ; CCP2 pin function on RC1 (alt defn) _CCP2MX_B3_3H EQU H'FE' ; CCP2 pin function on RB3 (alt defn) ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; DEBUGger enabled _DEBUG_OFF_4L EQU H'FF' ; DEBUGger disabled _LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled _LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP0_ON_5L EQU H'FE' ; Block 0 protected _CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable _CP1_ON_5L EQU H'FD' ; Block 1 protected _CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'BF' ; Boot Block protected _CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'7F' ; Data EE memory protected _CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT0_ON_6L EQU H'FE' ; Block 0 write protected _WRT0_OFF_6L EQU H'FF' ; Block 0 writable _WRT1_ON_6L EQU H'FD' ; Block 1 write protected _WRT1_OFF_6L EQU H'FF' ; Block 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'DF' ; Config registers write protected _WRTC_OFF_6H EQU H'FF' ; Config registers writable _WRTB_ON_6H EQU H'BF' ; Boot block write protected _WRTB_OFF_6H EQU H'FF' ; Boot block writable _WRTD_ON_6H EQU H'7F' ; Data EE write protected _WRTD_OFF_6H EQU H'FF' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR0_ON_7L EQU H'FE' ; Block 0 protected _EBTR0_OFF_7L EQU H'FF' ; Block 0 readable _EBTR1_ON_7L EQU H'FD' ; Block 1 protected _EBTR1_OFF_7L EQU H'FF' ; Block 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'BF' ; Boot block read protected _EBTRB_OFF_7H EQU H'FF' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p16cr63.inc0000644000175000017500000002562111156313161013245 00000000000000 LIST ; P16CR63.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR63 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR63 ; 2. LIST directive in the source file ; LIST P=PIC16CR63 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/27/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR63 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09', H'1E'-H'1F' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f877.inc0000644000175000017500000003474611156313161013173 00000000000000 LIST ; P16F877.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F877 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F877 ; 2. LIST directive in the source file ; LIST P=PIC16F877 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.12 01/12/00 Changed some bit names, a register name, configuration bits ; to match datasheet (DS30292B) ;1.00 08/07/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F877 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' __BADRAM H'105', H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'0FCF' _CP_HALF EQU H'1FDF' _CP_UPPER_256 EQU H'2FEF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f24j10.inc0000644000175000017500000006631211156521301013377 00000000000000 LIST ;========================================================================== ; MPASM PIC18F24J10 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F24J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F24J10 ; 2. LIST directive in the source file ; LIST P=PIC18F24J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F24J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' SPBRGH EQU H'0FB0' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' VREFM EQU H'0002' VREFP EQU H'0003' SS1 EQU H'0005' CVREF EQU H'0002' C2OUT_PORTA EQU H'0005' NOT_SS1 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0006' PGD EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' T0CKI EQU H'0005' FLT0 EQU H'0000' C1OUT_PORTB EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' SCL EQU H'0003' SDA EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' T0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F7F' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB1'-H'0FB3' __BADRAM H'0FB9' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; CCP2 MUX bit: ; CCP2MX = ALTERNATE CCP2 is multiplexed with RB3 ; CCP2MX = DEFAULT CCP2 is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f64j11.inc0000644000175000017500000011570611156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F64J11 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F64J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F64J11 ; 2. LIST directive in the source file ; LIST P=PIC18F64J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F64J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' REPU EQU H'0006' RDPU EQU H'0007' TX2 EQU H'0001' RX2 EQU H'0002' CK2 EQU H'0001' DT2 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F6B'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB6'-H'0FBF' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 3FF8h ; CONFIG1H 3FF9h ; CONFIG2L 3FFAh ; CONFIG2H 3FFBh ; CONFIG3L 3FFCh ; CONFIG3H 3FFDh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'3FF8' _CONFIG1H EQU H'3FF9' _CONFIG2L EQU H'3FFA' _CONFIG2H EQU H'3FFB' _CONFIG3L EQU H'3FFC' _CONFIG3H EQU H'3FFD' ;----- CONFIG1L Options -------------------------------------------------- _DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled _STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled _WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit) _WDTEN_ON_1L EQU H'FF' ; WDT enabled ;----- CONFIG1H Options -------------------------------------------------- _CP0_ON_1H EQU H'FB' ; Program memory is code-protected _CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected ;----- CONFIG2L Options -------------------------------------------------- _IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled _FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled _FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00 _FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 _FOSC_HS_2L EQU H'FC' ; HS oscillator _FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control _FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2 _FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2 ;----- CONFIG2H Options -------------------------------------------------- _WDTPS_1_2H EQU H'F0' ; 1:1 _WDTPS_2_2H EQU H'F1' ; 1:2 _WDTPS_4_2H EQU H'F2' ; 1:4 _WDTPS_8_2H EQU H'F3' ; 1:8 _WDTPS_16_2H EQU H'F4' ; 1:16 _WDTPS_32_2H EQU H'F5' ; 1:32 _WDTPS_64_2H EQU H'F6' ; 1:64 _WDTPS_128_2H EQU H'F7' ; 1:128 _WDTPS_256_2H EQU H'F8' ; 1:256 _WDTPS_512_2H EQU H'F9' ; 1:512 _WDTPS_1024_2H EQU H'FA' ; 1:1024 _WDTPS_2048_2H EQU H'FB' ; 1:2048 _WDTPS_4096_2H EQU H'FC' ; 1:4096 _WDTPS_8192_2H EQU H'FD' ; 1:8192 _WDTPS_16384_2H EQU H'FE' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode _CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1 _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p10f206.inc0000644000175000017500000001116711156313161013137 00000000000000 LIST ; P10F206.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC10F206 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P10F206 ; 2. LIST directive in the source file ; LIST P=10F206 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/14/04 Initial Release ;1.01 10/05/05 Add IntRC_OSC comment ;1.02 01/13/06 Added GPIO bit descriptions ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __10F206 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' CMCON0 EQU H'0007' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' CWUF EQU H'0006' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' FOSC4 EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' ;----- CMCON0 Bits -------------------------------------------------------- CMPOUT EQU H'0007' NOT_COUTEN EQU H'0006' POL EQU H'0005' NOT_CMPT0CS EQU H'0004' CMPON EQU H'0003' CNREF EQU H'0002' CPREF EQU H'0001' NOT_CWU EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _IntRC_OSC EQU H'0FFF';IntRC_OSC is the only option. ;It is here for backwards compatibility ;only. LIST gputils-0.13.7/header/p18f86j11.inc0000644000175000017500000016344411156521301013414 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J11 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J11 ; 2. LIST directive in the source file ; LIST P=PIC18F86J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F5A' PMSTATL EQU H'0F5A' PMSTATH EQU H'0F5B' PMEL EQU H'0F5C' PMEN EQU H'0F5C' PMEH EQU H'0F5D' PMDIN2 EQU H'0F5E' PMDIN2L EQU H'0F5E' PMDIN2H EQU H'0F5F' PMDOUT2 EQU H'0F60' PMDOUT2L EQU H'0F60' PMDOUT2H EQU H'0F61' PMMODE EQU H'0F62' PMMODEL EQU H'0F62' PMMODEH EQU H'0F63' PMCON EQU H'0F64' PMCONL EQU H'0F64' PMCONH EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2OUT EQU H'0001' C1OUT EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7 ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled ; FOSC = EC EC Oscillator with clock out on RA6 ; FOSC = ECPLL EC Oscillator with PLL ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p12ce519.inc0000644000175000017500000000762411156313161013315 00000000000000 LIST ; P12CE519.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12CE519 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12CE519 ; 2. LIST directive in the source file ; LIST P=12CE519 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12CE519 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' OSCFST EQU H'0003' CAL1 EQU H'0003' OSCSLW EQU H'0002' CAL0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f14k22.inc0000644000175000017500000012025311156521301013375 00000000000000 LIST ;========================================================================== ; MPASM PIC18F14K22 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F14K22 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F14K22 ; 2. LIST directive in the source file ; LIST P=PIC18F14K22 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F14K22 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' APFCON EQU H'0F75' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' VREFCON0 EQU H'0FBA' VREFCON1 EQU H'0FBB' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- C1SEL EQU H'0000' T0CKISEL EQU H'0001' INT2SEL EQU H'0002' SRQSEL EQU H'0003' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA0 EQU H'0000' WPUA1 EQU H'0001' WPUA2 EQU H'0002' WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA2 EQU H'0002' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F3F' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F74' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 1kW boot block size ; BBSIZ = ON 2kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size _BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2685.inc0000644000175000017500000042017211156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2685 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2685 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2685 ; 2. LIST directive in the source file ; LIST P=PIC18F2685 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2685 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB4'-H'0FB7' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; BackGround Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size Select Bits: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot Block (000000-0007FFh) write-protected ; WRTB = OFF Boot Block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot Block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f727.inc0000644000175000017500000005113311156521301013147 00000000000000 LIST ; P16F727.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F727 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F727 ; 2. LIST directive in the source file ; LIST P=PIC16F727 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/09/06 Initial template ;0.02 10/25/07 Remove 188h from BADRAM (actually ANSELD) ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F727 MESSG "Processor-header file mismatch. Verify selected processor." #define __16F727 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' ANSELD EQU H'0188' ANSELE EQU H'0189' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- ANSELD Bits --------------------------------------------------------- ANSD7 EQU H'0007' ANSD6 EQU H'0006' ANSD5 EQU H'0005' ANSD4 EQU H'0004' ANSD3 EQU H'0003' ANSD2 EQU H'0002' ANSD1 EQU H'0001' ANSD0 EQU H'0000' ;----- ANSELE Bits --------------------------------------------------------- ANSE2 EQU H'0002' ANSE1 EQU H'0001' ANSE0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'187', H'18D'-H'18F' LIST gputils-0.13.7/header/p14000.inc0000644000175000017500000002356311156313161012770 00000000000000 LIST ; P14000.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC14000 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC14000 ; 2. LIST directive in the source file ; LIST P=PIC14000 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/18/96 SSR 2824 Updated according to Applications' requirements ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __14000 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PORTD EQU H'0008' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADTMRL EQU H'000E' ADTMRH EQU H'000F' I2CBUF EQU H'0013' I2CCON EQU H'0014' ADCAPL EQU H'0015' ADCAPH EQU H'0016' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' TRISD EQU H'0088' PIE1 EQU H'008C' PCON EQU H'008E' SLPCON EQU H'008F' I2CADD EQU H'0093' I2CSTAT EQU H'0094' LDACA EQU H'009B' PREFA EQU H'009B' LDACB EQU H'009C' PREFB EQU H'009C' CHGCON EQU H'009D' CMCON EQU H'009D' MISC EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' T0IF EQU H'0002' ;----- PIR1 Bits ---------------------------------------------------------- WUIF EQU H'0007' CMIF EQU H'0007' PBIF EQU H'0004' I2CIF EQU H'0003' RCIF EQU H'0002' ADCIF EQU H'0001' OVFIF EQU H'0000' ;----- I2CCON Bits -------------------------------------------------------- WCOL EQU H'0007' I2COV EQU H'0006' I2CEN EQU H'0005' CKP EQU H'0004' I2CM3 EQU H'0003' I2CM2 EQU H'0002' I2CM1 EQU H'0001' I2CM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS3 EQU H'0007' ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' AMUXOE EQU H'0002' ADRST EQU H'0001' ADZERO EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RCPU EQU H'0007' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;---- PIE1 Bits ---------------------------------------------------------- WUIE EQU H'0007' CMIE EQU H'0007' PBIE EQU H'0004' I2CIE EQU H'0003' RCIE EQU H'0002' ADCIE EQU H'0001' OVFIE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_LVD EQU H'0000' ;----- SLPCON ------------------------------------------------------------- HIBEN EQU H'0007' REFOFF EQU H'0005' BIASOFF EQU H'0004' LSOFF EQU H'0004' OSCOFF EQU H'0003' CWUOFF EQU H'0002' CMOFF EQU H'0002' TEMPOFF EQU H'0001' ADOFF EQU H'0000' ;----- I2CSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- CMCON -------------------------------------------------------------- CCOMPB EQU H'0006' CMBOUT EQU H'0006' CCBEN EQU H'0005' CMBOE EQU H'0005' CPOLB EQU H'0004' CCOMPA EQU H'0002' CMAOUT EQU H'0002' CCAEN EQU H'0001' CMAOE EQU H'0001' CPOLA EQU H'0000' ;----- MISC Bits ---------------------------------------------------------- SMHOG EQU H'0007' SPGNDB EQU H'0006' SPGNDA EQU H'0005' I2CSEL EQU H'0004' SMBUS EQU H'0003' INCLKEN EQU H'0002' OSC2 EQU H'0001' OSC1 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADDAC3 EQU H'0007' ADDAC2 EQU H'0006' ADDAC1 EQU H'0005' ADDAC0 EQU H'0004' ACFG3 EQU H'0003' PCFG3 EQU H'0003' ACFG2 EQU H'0002' PCFG2 EQU H'0002' ACFG1 EQU H'0001' ACFG1 EQU H'0001' ACFG0 EQU H'0000' ACFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'06',H'09',H'0D',H'10'-H'12',H'17'-H'1E' __BADRAM H'86',H'89',H'8D',H'90'-H'92',H'95'-H'9A' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPC_ON EQU H'1E7F' _CPC_OFF EQU H'3FFF' _CPU_ON EQU H'2DDF' _CPU_OFF EQU H'3FFF' _CPP_ON EQU H'33EF' _CPP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _FOSC_HS EQU H'3FFE' _FOSC_RC EQU H'3FFF' LIST gputils-0.13.7/header/p16f628a.inc0000644000175000017500000002501611156313161013314 00000000000000 LIST ; P16F628A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F628A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F628A ; 2. LIST directive in the source file ; LIST P=PIC16F628A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR ;1.00 22 Aug 2002 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F628A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' CMIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits --------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' CMIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' NOT_BOD EQU H'0000' ;Backwards compatability to 16F62X ;----- TXSTA Bits ---------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' ;Backwards compatability to 16F62X _BODEN_OFF EQU H'3FBF' ;Backwards compatability to 16F62X _BOREN_ON EQU H'3FFF' _BOREN_OFF EQU H'3FBF' _CP_ON EQU H'1FFF' _CP_OFF EQU H'3FFF' _DATA_CP_ON EQU H'3EFF' _DATA_CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _RC_OSC_CLKOUT EQU H'3FFF' _RC_OSC_NOCLKOUT EQU H'3FFE' _ER_OSC_CLKOUT EQU H'3FFF' ;Backwards compatability to 16F62X _ER_OSC_NOCLKOUT EQU H'3FFE' ;Backwards compatability to 16F62X _INTOSC_OSC_CLKOUT EQU H'3FFD' _INTOSC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' ;Backwards compatability to 16F62X _INTRC_OSC_NOCLKOUT EQU H'3FFC' ;Backwards compatability to 16F62X _EXTCLK_OSC EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' LIST gputils-0.13.7/header/p16c63.inc0000644000175000017500000002570611156313161013067 00000000000000 LIST ; P16C63.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C63 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C63 ; 2. LIST directive in the source file ; LIST P=PIC16C63 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C63 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09', H'1E'-H'1F' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16ce623.inc0000644000175000017500000001416011156313161013306 00000000000000 LIST ; P16CE623.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CE623 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CE623 ; 2. LIST directive in the source file ; LIST P=PIC16CE623 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Initial Release ;1.01 02 Apr 1998 Fix incorrect BADRAM and MAXRAM information ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CE623 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' EEINTF EQU H'0090' VRCON EQU H'009F' ;----- STATUS Bits ---- --------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EEINTF Bits ---------------------------------------------------------- EESDA EQU H'0001' EESCL EQU H'0002' EEVDD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'07'-H'09', H'0D'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E' __BADRAM H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ON EQU H'00CF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f66j50.inc0000644000175000017500000017023711156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J50 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J50 ; 2. LIST directive in the source file ; LIST P=PIC18F66J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f6680.inc0000644000175000017500000041017411156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6680 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6680 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6680 ; 2. LIST directive in the source file ; LIST P=PIC18F6680 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6680 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' ECCP1DEL EQU H'0F79' BAUDCON EQU H'0F7E' SPBRGH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' TXRTR EQU H'0006' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDM EQU H'0003' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXRTRR0 EQU H'0003' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RTRR0 EQU H'0005' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE0 EQU H'0001' ICODE1 EQU H'0002' ICODE2 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' TX2EN EQU H'0006' TX2SRC EQU H'0007' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' NOT_FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' P1C EQU H'0005' P1B EQU H'0006' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CANTX1 EQU H'0000' CANTX2 EQU H'0001' CANRX EQU H'0002' P1D EQU H'0004' MCLR EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E2E'-H'0E2F' __BADRAM H'0E3E'-H'0E3F' __BADRAM H'0E4E'-H'0E4F' __BADRAM H'0E5E'-H'0E5F' __BADRAM H'0E6E'-H'0E6F' __BADRAM H'0E7E'-H'0EFF' __BADRAM H'0F2E'-H'0F2F' __BADRAM H'0F3E'-H'0F3F' __BADRAM H'0F4E'-H'0F4F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F78' __BADRAM H'0F7A'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9C' __BADRAM H'0FB7'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC RC oscillator with OSC2 configured as divide by 4 clock output ; OSC = EC EC oscillator with OSC2 configured as divide by 4 clock output ; OSC = ECIO EC oscillator with OSC2 configured as RA6 ; OSC = HSPLL HS oscillator with HW enabled 4x PLL ; OSC = RCIO RC oscillator with OSC2 configured as RA6 ; OSC = ECIOPLL EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL ; OSC = ECIOSWPLL EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL ; OSC = HSSWPLL HS oscillator with SW enabled 4x PLL ; ; Oscillator System Clock Switch Enable bit: ; OSCS = ON Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) ; OSCS = OFF Oscillator system clock switch option is disabled (main oscillator is source) ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bit: ; BOR = OFF Brown-out Reset disabled ; BOR = ON Brown-out Reset enabled ; ; Brown-out Reset Voltage bits: ; BORV = 45 VBOR set to 4.5V ; BORV = 42 VBOR set to 4.2V ; BORV = 27 VBOR set to 2.7V ; BORV = 20 VBOR set to 2.0V ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable bit: ; MCLRE = OFF RG5 input enabled, MCLR disabled ; MCLRE = ON MCLR pin enabled, RG5 input pin disabled ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RE7 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVR = OFF Stack full/underflow will not cause Reset ; STVR = ON Stack full/underflow will cause Reset ; ; Low-Voltage ICSP Enable bit: ; LVP = OFF Low-voltage ICSP disabled ; LVP = ON Low-voltage ICSP enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. ; DEBUG = OFF Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; RC oscillator with OSC2 configured as divide by 4 clock output _OSC_EC_1H EQU H'F4' ; EC oscillator with OSC2 configured as divide by 4 clock output _OSC_ECIO_1H EQU H'F5' ; EC oscillator with OSC2 configured as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator with HW enabled 4x PLL _OSC_RCIO_1H EQU H'F7' ; RC oscillator with OSC2 configured as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS oscillator with SW enabled 4x PLL _OSCS_ON_1H EQU H'DF' ; Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) _OSCS_OFF_1H EQU H'FF' ; Oscillator system clock switch option is disabled (main oscillator is source) ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BORV_45_2L EQU H'F3' ; VBOR set to 4.5V _BORV_42_2L EQU H'F7' ; VBOR set to 4.2V _BORV_27_2L EQU H'FB' ; VBOR set to 2.7V _BORV_20_2L EQU H'FF' ; VBOR set to 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input enabled, MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RG5 input pin disabled _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVR_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Low-voltage ICSP disabled _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2525.inc0000644000175000017500000010421311156521301013225 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2525 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2525 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2525 ; 2. LIST directive in the source file ; LIST P=PIC18F2525 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2525 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' DEBUG EQU H'0FD4' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB6'-H'0FB7' __BADRAM H'0FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO6 EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO6 RC-OSC2 as RA6 ; OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7 ; OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7 ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Osc. Switch Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON SBOREN Enabled ; BOREN = NOSLP Enabled except Sleep, SBOREN Disabled ; BOREN = SBORDIS Enabled, SBOREN Disabled ; ; Brown-out Voltage: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; T1 Oscillator Enable: ; LPT1OSC = OFF Disabled ; LPT1OSC = ON Enabled ; ; PORTB A/D Enable: ; PBADEN = OFF PORTB<4:0> digital on Reset ; PBADEN = ON PORTB<4:0> analog on Reset ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; XINST Enable: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO6_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO6_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_INTIO67_1H EQU H'F8' ; INTRC-OSC2 as RA6, OSC1 as RA7 _OSC_INTIO7_1H EQU H'F9' ; INTRC-OSC2 as Clock Out, OSC1 as RA7 _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'F9' ; Disabled _BOREN_ON_2L EQU H'FB' ; SBOREN Enabled _BOREN_NOSLP_2L EQU H'FD' ; Enabled except Sleep, SBOREN Disabled _BOREN_SBORDIS_2L EQU H'FF' ; Enabled, SBOREN Disabled _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _LPT1OSC_OFF_3H EQU H'FB' ; Disabled _LPT1OSC_ON_3H EQU H'FF' ; Enabled _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> digital on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> analog on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Disabled _XINST_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f66j55.inc0000644000175000017500000017023711156521301013420 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J55 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J55 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J55 ; 2. LIST directive in the source file ; LIST P=PIC18F66J55 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J55 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f883.inc0000644000175000017500000005552011156521301013156 00000000000000 LIST ; P16F883.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F883 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F883 ; 2. LIST directive in the source file ; LIST P=PIC16F883 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ; ;1.00 11/18/05 Original ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F883 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' MSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' VRCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' PWM1CON EQU H'009B' ECCPAS EQU H'009C' PSTRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' CM1CON0 EQU H'0107' CM2CON0 EQU H'0108' CM2CON1 EQU H'0109' EEDATA EQU H'010C' EEDAT EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' SRCON EQU H'0185' BAUDCTL EQU H'0187' ANSEL EQU H'0188' ANSELH EQU H'0189' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' BCLIF EQU H'0003' ULPWUIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GIV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' CCP1X EQU H'0005' ; Backward compatibility only DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' ; Backward compatibility only DC2B1 EQU H'0005' CCP2Y EQU H'0004' ; Backward compatibility only DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' BCLIE EQU H'0003' ULPWUIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- IOCB Bits ---------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' C1RSEL EQU H'0005' C2RSEL EQU H'0004' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' FVREN EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS13 EQU H'0005' ANS12 EQU H'0004' ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'110'-H'11F' __BADRAM H'18E'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word1 ------------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'2FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word2 ------------------------------------------------ _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _BOR21V EQU H'3EFF' _BOR40V EQU H'3FFF' LIST gputils-0.13.7/header/p16c71.inc0000644000175000017500000001175311156313161013063 00000000000000 LIST ; P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C71 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C71 ; 2. LIST directive in the source file ; LIST P=PIC16C71 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C71 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ADCON0 EQU H'0008' ADRES EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' ADCON1 EQU H'0088' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADIF EQU H'0001' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' ADIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'AF' __BADRAM H'07', H'30'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FFF' _PWRTE_OFF EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f8620.inc0000644000175000017500000011362611156313161013242 00000000000000 LIST ; P18F8620.INC Standard Header File, Version .1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F8620 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F8620 ; 2. LIST directive in the source file ; LIST P=PIC18F8620 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ; 1.09 10/12/04 Added SPBRG, TXREG, TXSTA and RCSTA src ; 1.08 09/26/02 Include both names SWDTE and SWDTEN pas ; 1.07 11/16/2001 Changed CVREF_CVRCON => CVRSS, ADEN => ADDEN pas ; 1.06 10/23/01 Corrected CONFIG bits/registers, LVDCON bits tr/pas ; 1.05 10/08/01 Corrected names of T2CON and T4CON bits ; (TOUTPS3 => T2OUTPS3 and T4OUTPS3, etc.) pas ; 1.04 10/03/01 Changed T0CON bit 3 name from T0PS3 to PSA. pas ; 1.03 10/01/01 Added definitions of the CCP4, CCP5, TMR4, and ; USART2 registers (0x0F6B to 0x0F78); corrected names ; of INTCON3 bits (i.e., INT2P => INT2IP). pas ; 1.02 09/18/01 Some bits have identical names in the data sheet; ; for instance, CCP2 in PORTB and CCP2 in PORTC. ; The assembler does not allow multiple definitions of ; the same name, however. So I postfixed these names ; with the name of the register to make them ; unique. (Now we have CCP2_PORTB and CCP2_PORTC). pas ; 1.01 09/14/01 Preliminary release tr ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8620 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution #define DDRF TRISF ; PIC17Cxxx SFR substitution #define DDRG TRISG ; PIC17Cxxx SFR substitution #define DDRH TRISH ; PIC17Cxxx SFR substitution #define DDRJ TRISJ ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' CCPR3H EQU H'0FB9' CCPR3L EQU H'0FB8' CCP3CON EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' RCREG1 EQU H'0FAE' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' EEADRH EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' TRISJ EQU H'0F9A' TRISH EQU H'0F99' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATJ EQU H'0F91' LATH EQU H'0F90' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTJ EQU H'0F88' PORTH EQU H'0F87' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TMR4 EQU H'0F78' PR4 EQU H'0F77' T4CON EQU H'0F76' CCPR4H EQU H'0F75' CCPR4L EQU H'0F74' CCP4CON EQU H'0F73' CCPR5H EQU H'0F72' CCPR5L EQU H'0F71' CCP5CON EQU H'0F70' SPBRG2 EQU H'0F6F' RCREG2 EQU H'0F6E' TXREG2 EQU H'0F6D' TXSTA2 EQU H'0F6C' RCSTA2 EQU H'0F6B' ;----- STKPTR Bits -------------------------------------------------------- STKOVF EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' INTEDG3 EQU H'0003' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF INT3P EQU H'0001' RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT3IE EQU H'0005' INT2IE EQU H'0004' INT1IE EQU H'0003' INT3IF EQU H'0002' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- T2OUTPS3 EQU H'0006' T2OUTPS2 EQU H'0005' T2OUTPS1 EQU H'0004' T2OUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DCCP1X EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DCCP1Y EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DCCP2X EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCP2Y EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- DCCP3X EQU H'0005' DCCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- CCP4CON Bits ------------------------------------------------------- DCCP4X EQU H'0005' DCCP4Y EQU H'0004' CCP4M3 EQU H'0003' CCP4M2 EQU H'0002' CCP4M1 EQU H'0001' CCP4M0 EQU H'0000' ;----- CCP5CON Bits ------------------------------------------------------- DCCP5X EQU H'0005' DCCP5Y EQU H'0004' CCP5M3 EQU H'0003' CCP5M2 EQU H'0002' CCP5M1 EQU H'0001' CCP5M0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVRSS EQU H'0004' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT_CMCON EQU H'0007' C1OUT_CMCON EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- T4CON Bits --------------------------------------------------------- T4OUTPS3 EQU H'0006' T4OUTPS2 EQU H'0005' T4OUTPS1 EQU H'0004' T4OUTPS0 EQU H'0003' TMR4ON EQU H'0002' T4CKPS1 EQU H'0001' T4CKPS0 EQU H'0000' ;----- TXSTA, TXSTA1 and TXSTA2 Bits -------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA, RCSTA1 and RCSTA2 Bits -------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR3 Bits ---------------------------------------------------------- RC2IP EQU H'0005' TX2IP EQU H'0004' TMR4IP EQU H'0003' CCP5IP EQU H'0002' CCP4IP EQU H'0001' CCP3IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- RC2IF EQU H'0005' TX2IF EQU H'0004' TMR4IF EQU H'0003' CCP5IF EQU H'0002' CCP4IF EQU H'0001' CCP3IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- RC2IE EQU H'0005' TX2IE EQU H'0004' TMR4IE EQU H'0003' CCP5IE EQU H'0002' CCP4IE EQU H'0001' CCP3IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' RC1IP EQU H'0005' TX1IP EQU H'0004' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' RC1IF EQU H'0005' TX1IF EQU H'0004' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' RC1IE EQU H'0005' TX1IE EQU H'0004' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- MEMCON Bits -------------------------------------------------------- EBDIS EQU H'0007' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 INT3 EQU 3 RB4 EQU 4 KBI0 EQU 4 RB5 EQU 5 KBI1 EQU 5 PGM EQU 5 RB6 EQU 6 KBI2 EQU 6 PGC EQU 6 RB7 EQU 7 KBI3 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T13CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 AD00 EQU 0 RD1 EQU 1 PSP1 EQU 1 AD01 EQU 1 RD2 EQU 2 PSP2 EQU 2 AD02 EQU 2 RD3 EQU 3 PSP3 EQU 3 AD03 EQU 3 RD4 EQU 4 PSP4 EQU 4 AD04 EQU 4 RD5 EQU 5 PSP5 EQU 5 AD05 EQU 5 RD6 EQU 6 PSP6 EQU 6 AD06 EQU 6 RD7 EQU 7 PSP7 EQU 7 AD07 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 AD08 EQU 0 RE1 EQU 1 WR EQU 1 AD09 EQU 1 RE2 EQU 2 CS EQU 2 AD10 EQU 2 RE3 EQU 3 AD11 EQU 3 RE4 EQU 4 AD12 EQU 4 RE5 EQU 5 AD13 EQU 5 RE6 EQU 6 AD14 EQU 6 RE7 EQU 7 AD15 EQU 7 CCP2C EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 C2OUT EQU 1 RF2 EQU 2 AN7 EQU 2 C1OUT EQU 2 RF3 EQU 3 AN8 EQU 3 RF4 EQU 4 AN9 EQU 4 RF5 EQU 5 AN10 EQU 5 CVREF EQU 5 RF6 EQU 6 AN11 EQU 6 RF7 EQU 7 SS EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 CCP3 EQU 0 RG1 EQU 1 TX2 EQU 1 CK2 EQU 1 RG2 EQU 2 RX2 EQU 2 DT2 EQU 2 RG3 EQU 3 CCP4 EQU 3 RG4 EQU 4 CCP5 EQU 4 ;----- PORTH ------------------------------------------------------------------ RH0 EQU 0 AD16 EQU 0 RH1 EQU 1 AD17 EQU 1 RH2 EQU 2 AD18 EQU 2 RH3 EQU 3 AD19 EQU 3 RH4 EQU 4 AD12 EQU 4 RH5 EQU 5 AD13 EQU 5 RH6 EQU 6 AD14 EQU 6 RH7 EQU 7 AD15 EQU 7 ;----- PORTJ ------------------------------------------------------------------ RJ0 EQU 0 ALE EQU 0 RJ1 EQU 1 OE EQU 1 RJ2 EQU 2 WRL EQU 2 RJ3 EQU 3 WRH EQU 3 RJ4 EQU 4 BA0 EQU 4 RJ5 EQU 5 RJ6 EQU 6 LB EQU 6 RJ7 EQU 7 UB EQU 7 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'F00'-H'F6A' __BADRAM H'F79'-H'F7F' __BADRAM H'F9B',H'FB6',H'FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Processor Mode Selection: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait: ; WAIT = ON Enabled ; WAIT = OFF Disabled ; ; CCP2 MUX: ; CCP2MUX = OFF Disabled ; CCP2MUX = ON Enabled ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3L Options _MC_MODE_3L EQU H'FF' ; Processor Mode Select bits _MP_MODE_3L EQU H'FE' _MPB_MODE_3L EQU H'FD' _XMC_MODE_3L EQU H'FC' _WAIT_ON_3L EQU H'7F' ; External Bus Data Wait Enable _WAIT_OFF_3L EQU H'FF' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' _CP4_ON_5L EQU H'EF' _CP4_OFF_5L EQU H'FF' _CP5_ON_5L EQU H'DF' _CP5_OFF_5L EQU H'FF' _CP6_ON_5L EQU H'BF' _CP6_OFF_5L EQU H'FF' _CP7_ON_5L EQU H'7F' _CP7_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' _WRT4_ON_6L EQU H'EF' _WRT4_OFF_6L EQU H'FF' _WRT5_ON_6L EQU H'DF' _WRT5_OFF_6L EQU H'FF' _WRT6_ON_6L EQU H'BF' _WRT6_OFF_6L EQU H'FF' _WRT7_ON_6L EQU H'7F' _WRT7_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' _EBTR4_ON_7L EQU H'EF' _EBTR4_OFF_7L EQU H'FF' _EBTR5_ON_7L EQU H'DF' _EBTR5_OFF_7L EQU H'FF' _EBTR6_ON_7L EQU H'BF' _EBTR6_OFF_7L EQU H'FF' _EBTR7_ON_7L EQU H'7F' _EBTR7_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3L ; __CONFIG _CONFIG3L, _WAIT_OFF_3L & _MC_MODE_3L ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L & _CP4_OFF_5L & _CP5_OFF_5L & _CP6_OFF_5L & _CP7_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L & _WRT4_OFF_6L & _WRT5_OFF_6L & _WRT6_OFF_6L & _WRT7_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L & _EBTR4_OFF_7L & _EBTR5_OFF_7L & _EBTR6_OFF_7L & _EBTR7_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p12f629.inc0000644000175000017500000002142511156521301013145 00000000000000 LIST ; P12F629.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F629 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12F629 ; 2. LIST directive in the source file ; LIST P=PIC12F629 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.04 07/01/02 Updated configuration bit names ;1.03 05/10/02 Added IOC register ;1.02 02/28/02 Updated per datasheet ;1.01 01/31/02 Updated per datasheet ;1.00 08/24/01 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F629 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' WPU EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEDAT EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- IOCB Bits -------------------------------------------------------- IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits -------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16f872.inc0000644000175000017500000002767511156313161013171 00000000000000 LIST ; P16F872.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F872 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F872 ; 2. LIST directive in the source file ; LIST P=PIC16F872 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/17/05 Added the INTCON bits TMR0IE and TMR0IF ;1.00 01/25/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F872 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'008'-H'009', H'018'-H'01D', H'088'-H'089' __BADRAM H'08F'-H'090', H'095'-H'09D', H'0C0'-H'0EF' __BADRAM H'105', H'107'-H'109' __BADRAM H'110'-H'11F', H'185' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F',H'1C0'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ; Code protection for the PIC16C872 is different than for other PIC16C87X devices. ; The CP_ALL and CP_OFF switches operate as expected. ; CP_HALF protects the lower half of program memory. The upper half is open. ; CP_UPPER_256 protects everything EXCEPT the top 256 words. ;========================================================================== _CP_ALL EQU H'0FCF' _CP_HALF EQU H'1FDF' _CP_UPPER_256 EQU H'2FEF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c62.inc0000644000175000017500000002033411156313161013056 00000000000000 LIST ; P16C62.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C62 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C62 ; 2. LIST directive in the source file ; LIST P=PIC16C62 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C62 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1F' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3F8F' _CP_75 EQU H'3F9F' _CP_50 EQU H'3FAF' _CP_OFF EQU H'3FBF' _PWRTE_ON EQU H'3FBF' _PWRTE_OFF EQU H'3FB7' _WDT_ON EQU H'3FBF' _WDT_OFF EQU H'3FBB' _LP_OSC EQU H'3FBC' _XT_OSC EQU H'3FBD' _HS_OSC EQU H'3FBE' _RC_OSC EQU H'3FBF' LIST gputils-0.13.7/header/p18f1330.inc0000644000175000017500000010641411156521302013224 00000000000000 LIST ;========================================================================== ; MPASM PIC18F1330 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F1330 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F1330 ; 2. LIST directive in the source file ; LIST P=PIC18F1330 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F1330 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' OVDCONS EQU H'0F82' OVDCOND EQU H'0F83' DTCON EQU H'0F84' PWMCON1 EQU H'0F85' PWMCON0 EQU H'0F86' SEVTCMPH EQU H'0F87' SEVTCMPL EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' FLTCONFIG EQU H'0F8B' PDC2H EQU H'0F8C' PDC2L EQU H'0F8D' PDC1H EQU H'0F8E' PDC1L EQU H'0F8F' PDC0H EQU H'0F90' PDC0L EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' PTPERH EQU H'0F95' PTPERL EQU H'0F96' PTMRH EQU H'0F97' PTMRL EQU H'0F98' PTCON1 EQU H'0F99' PTCON0 EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' TX EQU H'0002' RX EQU H'0003' AN2 EQU H'0004' MCLR EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' CK EQU H'0002' ; DT is a reserved word ; DT EQU H'0003' T0CKI EQU H'0004' CLKO EQU H'0006' CLKI EQU H'0007' KBI0 EQU H'0000' KBI1 EQU H'0001' VREFP EQU H'0004' T1OSO_PORTA EQU H'0006' T1OSI_PORTA EQU H'0007' CMP0 EQU H'0000' NOT_MCLR EQU H'0005' AN3 EQU H'0006' T1CKI_PORTA EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' PWM0 EQU H'0000' PWM1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' PWM2 EQU H'0004' PWM3 EQU H'0005' PWM4 EQU H'0006' PWM5 EQU H'0007' KBI2 EQU H'0002' KBI3 EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' CMP2 EQU H'0002' CMP1 EQU H'0003' T1OSO_PORTB EQU H'0002' T1OSI_PORTB EQU H'0003' T1CKI_PORTB EQU H'0002' ;----- OVDCONS Bits ----------------------------------------------------- POUT0 EQU H'0000' POUT1 EQU H'0001' POUT2 EQU H'0002' POUT3 EQU H'0003' POUT4 EQU H'0004' POUT5 EQU H'0005' ;----- OVDCOND Bits ----------------------------------------------------- POVD0 EQU H'0000' POVD1 EQU H'0001' POVD2 EQU H'0002' POVD3 EQU H'0003' POVD4 EQU H'0004' POVD5 EQU H'0005' ;----- DTCON Bits ----------------------------------------------------- DT0 EQU H'0000' DT1 EQU H'0001' DT2 EQU H'0002' DT3 EQU H'0003' DT4 EQU H'0004' DT5 EQU H'0005' DTPS0 EQU H'0006' DTPS1 EQU H'0007' ;----- PWMCON1 Bits ----------------------------------------------------- OSYNC EQU H'0000' UDIS EQU H'0001' SEVTDIR EQU H'0003' SEVOPS0 EQU H'0004' SEVOPS1 EQU H'0005' SEVOPS2 EQU H'0006' SEVOPS3 EQU H'0007' ;----- PWMCON0 Bits ----------------------------------------------------- PMOD0 EQU H'0000' PMOD1 EQU H'0001' PMOD2 EQU H'0002' PWMEN0 EQU H'0004' PWMEN1 EQU H'0005' PWMEN2 EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- FLTCONFIG Bits ----------------------------------------------------- FLTAEN EQU H'0000' FLTAMOD EQU H'0001' FLTAS EQU H'0002' BRFEN EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- PTCON1 Bits ----------------------------------------------------- PTDIR EQU H'0006' PTEN EQU H'0007' ;----- PTCON0 Bits ----------------------------------------------------- PTMOD0 EQU H'0000' PTMOD1 EQU H'0001' PTCKPS0 EQU H'0002' PTCKPS1 EQU H'0003' PTOPS0 EQU H'0004' PTOPS1 EQU H'0005' PTOPS2 EQU H'0006' PTOPS3 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' CMP0IE EQU H'0001' CMP1IE EQU H'0002' CMP2IE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' CMP0IF EQU H'0001' CMP1IF EQU H'0002' CMP2IF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' CMP0IP EQU H'0001' CMP1IP EQU H'0002' CMP2IP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- LVDIE EQU H'0002' EEIE EQU H'0004' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- LVDIF EQU H'0002' EEIF EQU H'0004' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- LVDIP EQU H'0002' EEIP EQU H'0004' OSCFIP EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- PTIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- PTIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- PTIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- CMCON Bits ----------------------------------------------------- CMEN0 EQU H'0000' CMEN1 EQU H'0001' CMEN2 EQU H'0002' C0OUT EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' SEVTEN EQU H'0007' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0006' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0100'-H'0F7F' __BADRAM H'0F94' __BADRAM H'0F9C' __BADRAM H'0FAA' __BADRAM H'0FB1'-H'0FB3' __BADRAM H'0FB6'-H'0FB7' __BADRAM H'0FB9'-H'0FBF' __BADRAM H'0FC5'-H'0FCC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit): ; HPOL = LOW PWM1, PWM3 and PWM5 are active-low ; HPOL = HIGH PWM1, PWM3 and PWM5 are active-high (default) ; ; Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit): ; LPOL = LOW PWM0, PWM2 and PWM4 are active-low ; LPOL = HIGH PWM0, PWM2 and PWM4 are active-high (default) ; ; PWM Output Pins Reset State Control bit: ; PWMPIN = ON PWM outputs drive active states upon Reset ; PWMPIN = OFF PWM outputs disabled upon Reset ; ; FLTA MUX bit: ; FLTAMX = RA7 FLTA input is muxed onto RA7 ; FLTAMX = RA5 FLTA input is muxed onto RA5 ; ; T1OSO/T1CKI MUX bit: ; T1OSCMX = LOW T1OSO/T1CKI pin resides on RB2 ; T1OSCMX = HIGH T1OSO/T1CKI pin resides on RA6 ; ; Master Clear Enable bit: ; MCLRE = OFF RA5 input pin enabled, MCLR pin disabled ; MCLRE = ON MCLR pin enabled, RA5 input pin disabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Words (512 Bytes) ; BBSIZ = BB512 512 Words (1024 Bytes) ; BBSIZ = BB1K 1K Words (2048 Bytes) ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0 (00800-00FFF): ; CP0 = ON Block 0 is code-protected ; CP0 = OFF Block 0 is not code-protected ; ; Code Protection bit Block 1 (01000-01FFF): ; CP1 = ON Block 1 is code-protected ; CP1 = OFF Block 1 is not code-protected ; ; Code Protection bit (Boot Block Memory Area): ; CPB = ON Boot Block is code-protected ; CPB = OFF Boot Block is not code-protected ; ; Code Protection bit (Data EEPROM): ; CPD = ON Data EEPROM is code-protected ; CPD = OFF Data EEPROM is not code-protected ; ; Write Protection bit Block 0 (00800-00FFF): ; WRT0 = ON Block 0 is write-protected ; WRT0 = OFF Block 0 is not write-protected ; ; Write Protection bit Block 1 (01000-01FFF): ; WRT1 = ON Block 1 is write-protected ; WRT1 = OFF Block 1 is not write-protected ; ; Write Protection bit (Boot Block Memory Area): ; WRTB = ON Boot Block is write-protected ; WRTB = OFF Boot Block is not write-protected ; ; Write Protection bit (Configuration Registers): ; WRTC = ON Configuration registers are write-protected ; WRTC = OFF Configuration registers are not write-protected ; ; Write Protection bit (Data EEPROM): ; WRTD = ON Data EEPROM is write-protected ; WRTD = OFF Data EEPROM is not write-protected ; ; Table Read Protection bit Block 0 (00800-00FFF): ; EBTR0 = ON Block 0 is protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 is not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1 (01000-01FFF): ; EBTR1 = ON Block 1 is protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 is not protected from table reads executed in other blocks ; ; Table Read Protection bit (Boot Block Memory Area): ; EBTRB = ON Boot Block is protected from table reads executed in other blocks ; EBTRB = OFF Boot Block is not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP Oscillator _OSC_XT_1H EQU H'F1' ; XT Oscillator _OSC_HS_1H EQU H'F2' ; HS Oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO2_1H EQU H'F8' ; Internal oscillator, port function on RA6 and RA7 _OSC_INTIO1_1H EQU H'F9' ; Internal oscillator, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'F3' ; Maximum setting _BORV_1_2L EQU H'F7' ; _BORV_2_2L EQU H'FB' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _HPOL_LOW_3L EQU H'F7' ; PWM1, PWM3 and PWM5 are active-low _HPOL_HIGH_3L EQU H'FF' ; PWM1, PWM3 and PWM5 are active-high (default) _LPOL_LOW_3L EQU H'FB' ; PWM0, PWM2 and PWM4 are active-low _LPOL_HIGH_3L EQU H'FF' ; PWM0, PWM2 and PWM4 are active-high (default) _PWMPIN_ON_3L EQU H'FD' ; PWM outputs drive active states upon Reset _PWMPIN_OFF_3L EQU H'FF' ; PWM outputs disabled upon Reset ;----- CONFIG3H Options -------------------------------------------------- _FLTAMX_RA7_3H EQU H'FE' ; FLTA input is muxed onto RA7 _FLTAMX_RA5_3H EQU H'FF' ; FLTA input is muxed onto RA5 _T1OSCMX_LOW_3H EQU H'F7' ; T1OSO/T1CKI pin resides on RB2 _T1OSCMX_HIGH_3H EQU H'FF' ; T1OSO/T1CKI pin resides on RA6 _MCLRE_OFF_3H EQU H'7F' ; RA5 input pin enabled, MCLR pin disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RA5 input pin disabled ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Reset on stack overflow/underflow disabled _STVREN_ON_4L EQU H'FF' ; Reset on stack overflow/underflow enabled _BBSIZ_BB256_4L EQU H'CF' ; 256 Words (512 Bytes) _BBSIZ_BB512_4L EQU H'DF' ; 512 Words (1024 Bytes) _BBSIZ_BB1K_4L EQU H'FF' ; 1K Words (2048 Bytes) _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 is code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 is not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 is code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 is not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block is code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block is not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM is code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM is not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 is write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 is not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 is write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 is not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block is write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block is not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers are write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers are not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM is write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM is not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 is protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 is not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 is protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 is not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block is protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block is not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2431.inc0000644000175000017500000011505211156521301013224 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2431 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2431 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2431 ; 2. LIST directive in the source file ; LIST P=PIC18F2431 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2431 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- DFLTCON EQU H'0F60' CAP3CON EQU H'0F61' CAP2CON EQU H'0F62' CAP1CON EQU H'0F63' CAP3BUFL EQU H'0F64' MAXCNTL EQU H'0F64' CAP3BUFH EQU H'0F65' MAXCNTH EQU H'0F65' CAP2BUFL EQU H'0F66' POSCNTL EQU H'0F66' CAP2BUFH EQU H'0F67' POSCNTH EQU H'0F67' CAP1BUFL EQU H'0F68' VELRL EQU H'0F68' CAP1BUFH EQU H'0F69' VELRH EQU H'0F69' OVDCONS EQU H'0F6A' OVDCOND EQU H'0F6B' FLTCONFIG EQU H'0F6C' DTCON EQU H'0F6D' PWMCON1 EQU H'0F6E' PWMCON0 EQU H'0F6F' SEVTCMPH EQU H'0F70' SEVTCMPL EQU H'0F71' PDC2H EQU H'0F74' PDC2L EQU H'0F75' PDC1H EQU H'0F76' PDC1L EQU H'0F77' PDC0H EQU H'0F78' PDC0L EQU H'0F79' PTPERH EQU H'0F7A' PTPERL EQU H'0F7B' PTMRH EQU H'0F7C' PTMRL EQU H'0F7D' PTCON1 EQU H'0F7E' PTCON0 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' TMR5L EQU H'0F87' TMR5H EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' PR5L EQU H'0F90' PR5H EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' ADCHS EQU H'0F99' ADCON3 EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' BAUDCON EQU H'0FAA' BAUDCTL EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' QEICON EQU H'0FB6' T5CON EQU H'0FB7' ANSEL0 EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- DFLTCON Bits ----------------------------------------------------- FLTCK0 EQU H'0000' FLTCK1 EQU H'0001' FLTCK2 EQU H'0002' FLT1EN EQU H'0003' FLT2EN EQU H'0004' FLT3EN EQU H'0005' FLT4EN EQU H'0006' ;----- CAP3CON Bits ----------------------------------------------------- CAP3M0 EQU H'0000' CAP3M1 EQU H'0001' CAP3M2 EQU H'0002' CAP3M3 EQU H'0003' CAP3TMR EQU H'0005' CAP3REN EQU H'0006' ;----- CAP2CON Bits ----------------------------------------------------- CAP2M0 EQU H'0000' CAP2M1 EQU H'0001' CAP2M2 EQU H'0002' CAP2M3 EQU H'0003' CAP2TMR EQU H'0005' CAP2REN EQU H'0006' ;----- CAP1CON Bits ----------------------------------------------------- CAP1M0 EQU H'0000' CAP1M1 EQU H'0001' CAP1M2 EQU H'0002' CAP1M3 EQU H'0003' CAP1TMR EQU H'0005' CAP1REN EQU H'0006' ;----- OVDCONS Bits ----------------------------------------------------- POUT0 EQU H'0000' POUT1 EQU H'0001' POUT2 EQU H'0002' POUT3 EQU H'0003' POUT4 EQU H'0004' POUT5 EQU H'0005' POUT6 EQU H'0006' POUT7 EQU H'0007' ;----- OVDCOND Bits ----------------------------------------------------- POVD0 EQU H'0000' POVD1 EQU H'0001' POVD2 EQU H'0002' POVD3 EQU H'0003' POVD4 EQU H'0004' POVD5 EQU H'0005' POVD6 EQU H'0006' POVD7 EQU H'0007' ;----- FLTCONFIG Bits ----------------------------------------------------- FLTAEN EQU H'0000' FLTAMOD EQU H'0001' FLTAS EQU H'0002' FLTCON EQU H'0003' FLTBEN EQU H'0004' FLTBMOD EQU H'0005' FLTBS EQU H'0006' ;----- DTCON Bits ----------------------------------------------------- DT0 EQU H'0000' DT1 EQU H'0001' DT2 EQU H'0002' DT3 EQU H'0003' DT4 EQU H'0004' DT5 EQU H'0005' DTPS0 EQU H'0006' DTPS1 EQU H'0007' DTA0 EQU H'0000' DTA1 EQU H'0001' DTA2 EQU H'0002' DTA3 EQU H'0003' DTA4 EQU H'0004' DTA5 EQU H'0005' DTAPS0 EQU H'0006' DTAPS1 EQU H'0007' ;----- PWMCON1 Bits ----------------------------------------------------- OSYNC EQU H'0000' UDIS EQU H'0001' SEVTDIR EQU H'0003' SEVOPS0 EQU H'0004' SEVOPS1 EQU H'0005' SEVOPS2 EQU H'0006' SEVOPS3 EQU H'0007' ;----- PWMCON0 Bits ----------------------------------------------------- PMOD0 EQU H'0000' PMOD1 EQU H'0001' PMOD2 EQU H'0002' PMOD3 EQU H'0003' PWMEN0 EQU H'0004' PWMEN1 EQU H'0005' PWMEN2 EQU H'0006' ;----- PTCON1 Bits ----------------------------------------------------- PTDIR EQU H'0006' PTEN EQU H'0007' ;----- PTCON0 Bits ----------------------------------------------------- PTMOD0 EQU H'0000' PTMOD1 EQU H'0001' PTCKPS0 EQU H'0002' PTCKPS1 EQU H'0003' PTOPS0 EQU H'0004' PTOPS1 EQU H'0005' PTOPS2 EQU H'0006' PTOPS3 EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' INT0 EQU H'0003' INT1 EQU H'0004' INT2 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' T0CKI EQU H'0003' SDA EQU H'0004' SCK EQU H'0005' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' NOT_FLTA EQU H'0001' NOT_FLTB EQU H'0002' T5CKI EQU H'0003' SDI EQU H'0004' SCL EQU H'0005' NOT_SS EQU H'0006' SDO EQU H'0007' FLTA EQU H'0001' FLTB EQU H'0002' SS EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- ADCHS Bits ----------------------------------------------------- GASEL0 EQU H'0000' GASEL1 EQU H'0001' GCSEL0 EQU H'0002' GCSEL1 EQU H'0003' GBSEL0 EQU H'0004' GBSEL1 EQU H'0005' GDSEL0 EQU H'0006' GDSEL1 EQU H'0007' SASEL0 EQU H'0000' SASEL1 EQU H'0001' SCSEL0 EQU H'0002' SCSEL1 EQU H'0003' SBSEL0 EQU H'0004' SBSEL1 EQU H'0005' SDSEL0 EQU H'0006' SDSEL1 EQU H'0007' ;----- ADCON3 Bits ----------------------------------------------------- SSRC0 EQU H'0000' SSRC1 EQU H'0001' SSRC2 EQU H'0002' SSRC3 EQU H'0003' SSRC4 EQU H'0004' ADRS0 EQU H'0006' ADRS1 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TBIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TBIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LVDIE EQU H'0002' EEIE EQU H'0004' OSFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LVDIF EQU H'0002' EEIF EQU H'0004' OSFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' LVDIP EQU H'0002' EEIP EQU H'0004' OSFIP EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR5IE EQU H'0000' IC1IE EQU H'0001' IC2QEIE EQU H'0002' IC3DRIE EQU H'0003' PTIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- TMR5IF EQU H'0000' IC1IF EQU H'0001' IC2QEIF EQU H'0002' IC3DRIF EQU H'0003' PTIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- TMR5IP EQU H'0000' IC1IP EQU H'0001' IC2QEIP EQU H'0002' IC3DRIP EQU H'0003' PTIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- QEICON Bits ----------------------------------------------------- PDEC0 EQU H'0000' PDEC1 EQU H'0001' QEIM0 EQU H'0002' QEIM1 EQU H'0003' QEIM2 EQU H'0004' UP_DOWN EQU H'0005' ; ERROR is a reserved word ; ERROR EQU H'0006' VELM EQU H'0007' UP EQU H'0005' DOWN EQU H'0005' NOT_DOWN EQU H'0005' NOT_VELM EQU H'0007' ;----- T5CON Bits ----------------------------------------------------- TMR5ON EQU H'0000' TMR5CS EQU H'0001' T5SYNC EQU H'0002' T5PS0 EQU H'0003' T5PS1 EQU H'0004' T5MOD EQU H'0005' RESEN EQU H'0006' T5SEN EQU H'0007' NOT_T5SYNC EQU H'0002' NOT_RESEN EQU H'0006' ;----- ANSEL0 Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ACQT3 EQU H'0006' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- ADPNT0 EQU H'0000' ADPNT1 EQU H'0001' BFOVFL EQU H'0002' BFEMT EQU H'0003' FIFOEN EQU H'0004' VCFG0 EQU H'0006' VCFG1 EQU H'0007' FFOVFL EQU H'0002' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' ACMOD0 EQU H'0002' ACMOD1 EQU H'0003' ACSCH EQU H'0004' ACONV EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDT0 EQU H'0001' WDT1 EQU H'0002' WDT2 EQU H'0003' WDT3 EQU H'0004' WDT4 EQU H'0005' WDT5 EQU H'0006' WDT6 EQU H'0007' WDTW EQU H'0007' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F5F' __BADRAM H'0F72'-H'0F73' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F86' __BADRAM H'0F8C'-H'0F8F' __BADRAM H'0F95'-H'0F98' __BADRAM H'0F9C' __BADRAM H'0FB1'-H'0FB5' __BADRAM H'0FB9' __BADRAM H'0FC5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC2 External RC, RA6 is CLKOUT ; OSC = EC EC, RA6 is CLKOUT ; OSC = ECIO EC, RA6 is I/O ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO External RC, RA6 is I/O ; OSC = IRCIO Internal RC, RA6 & RA7 are I/O ; OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O ; OSC = RC1 External RC, RA6 is CLKOUT ; OSC = RC External RC, RA6 is CLKOUT ; ; Fail-Safe Clock Monitor Enable: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal/External Switch-Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRTEN = ON Enabled ; PWRTEN = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDTEN = OFF Disabled ; WDTEN = ON Enabled ; ; Watchdog Timer Enable Window: ; WINEN = ON Enabled ; WINEN = OFF Disabled ; ; Watchdog Postscaler: ; WDPS = 1 1:1 ; WDPS = 2 1:2 ; WDPS = 4 1:4 ; WDPS = 8 1:8 ; WDPS = 16 1:16 ; WDPS = 32 1:32 ; WDPS = 64 1:64 ; WDPS = 128 1:128 ; WDPS = 256 1:256 ; WDPS = 512 1:512 ; WDPS = 1024 1:1024 ; WDPS = 2048 1:2048 ; WDPS = 4096 1:4096 ; WDPS = 8192 1:8192 ; WDPS = 16384 1:16384 ; WDPS = 32768 1:32768 ; ; Timer1 Oscillator MUX: ; T1OSCMX = OFF Active ; T1OSCMX = ON Inactive ; ; High-Side Transistors Polarity: ; HPOL = LOW Active low ; HPOL = HIGH Active high ; ; Low-Side Transistors Polarity: ; LPOL = LOW Active low ; LPOL = HIGH Active high ; ; PWM output pins Reset state control: ; PWMPIN = ON Enabled ; PWMPIN = OFF Disabled ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC2_1H EQU H'F3' ; External RC, RA6 is CLKOUT _OSC_EC_1H EQU H'F4' ; EC, RA6 is CLKOUT _OSC_ECIO_1H EQU H'F5' ; EC, RA6 is I/O _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; External RC, RA6 is I/O _OSC_IRCIO_1H EQU H'F8' ; Internal RC, RA6 & RA7 are I/O _OSC_IRC_1H EQU H'F9' ; Internal RC, RA6 is CLKOUT, RA7 is I/O _OSC_RC1_1H EQU H'FB' ; External RC, RA6 is CLKOUT _OSC_RC_1H EQU H'FF' ; External RC, RA6 is CLKOUT _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; Enabled _PWRTEN_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'FD' ; Disabled _BOREN_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; Disabled _WDTEN_ON_2H EQU H'FF' ; Enabled _WINEN_ON_2H EQU H'DF' ; Enabled _WINEN_OFF_2H EQU H'FF' ; Disabled _WDPS_1_2H EQU H'E1' ; 1:1 _WDPS_2_2H EQU H'E3' ; 1:2 _WDPS_4_2H EQU H'E5' ; 1:4 _WDPS_8_2H EQU H'E7' ; 1:8 _WDPS_16_2H EQU H'E9' ; 1:16 _WDPS_32_2H EQU H'EB' ; 1:32 _WDPS_64_2H EQU H'ED' ; 1:64 _WDPS_128_2H EQU H'EF' ; 1:128 _WDPS_256_2H EQU H'F1' ; 1:256 _WDPS_512_2H EQU H'F3' ; 1:512 _WDPS_1024_2H EQU H'F5' ; 1:1024 _WDPS_2048_2H EQU H'F7' ; 1:2048 _WDPS_4096_2H EQU H'F9' ; 1:4096 _WDPS_8192_2H EQU H'FB' ; 1:8192 _WDPS_16384_2H EQU H'FD' ; 1:16384 _WDPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _T1OSCMX_OFF_3L EQU H'DF' ; Active _T1OSCMX_ON_3L EQU H'FF' ; Inactive _HPOL_LOW_3L EQU H'EF' ; Active low _HPOL_HIGH_3L EQU H'FF' ; Active high _LPOL_LOW_3L EQU H'F7' ; Active low _LPOL_HIGH_3L EQU H'FF' ; Active high _PWMPIN_ON_3L EQU H'FB' ; Enabled _PWMPIN_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f452.inc0000644000175000017500000007330211156313161013151 00000000000000 LIST ; P18F452.INC Standard Header File, Version 1.4 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F452 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F452 ; 2. LIST directive in the source file ; LIST P=PIC18F452 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;1.0 03/23/01 Modified C452 for F452 tr ;1.1 08/01/01 Added EECON1 bits, corrected code protect config bit inserts ;1.2 09/17/01 Corrected MAXRAM,BADRAM tr ;1.3 10/23/01 Corrected CONFIG bits/registers tr/pas ;1.4 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F452 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR2 Bits ---------------------------------------------------------- EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 AN5 EQU 0 RE1 EQU 1 WR EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 AN7 EQU 2 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'600'-H'F7F' __BADRAM H'F85'-H'F88' __BADRAM H'F8E'-H'F91' __BADRAM H'F97'-H'F9C' __BADRAM H'FA3'-H'FA5' __BADRAM H'FAA' __BADRAM H'FB4'-H'FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p16c710.inc0000644000175000017500000001250511156313161013137 00000000000000 LIST ; P16C710.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C710 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C710 ; 2. LIST directive in the source file ; LIST P=PIC16C710 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C710 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ADCON0 EQU H'0008' ADRES EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PCON EQU H'0087' ADCON1 EQU H'0088' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADIF EQU H'0001' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' ADIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'AF' __BADRAM H'07', H'30'-H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ON EQU H'004F' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f917.inc0000644000175000017500000007236111156521301013156 00000000000000 LIST ; P16F917.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F917 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F917 ; 2. LIST directive in the source file ; LIST P=PIC16F917 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 06/11/04 Initial Release ;1.01 08/16/04 Added EECON2 ;1.02 05/20/05 Removed EECON2 from badram ;1.03 10/05/05 Correct names of bits in ANSEL, Add EEADRH and EEADRL bit ;1.04 10/30/06 Added Alias of go_done, go ; definitions ;1.05 02/26/07 Added Alias of EEADR and EEDATA ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F917 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' WPU EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' CMCON1 EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON0 EQU H'009C' VRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LCDCON EQU H'0107' LCDPS EQU H'0108' LVDCON EQU H'0109' EEDATL EQU H'010C' EEDATA EQU H'010C' EEADRL EQU H'010D' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' LCDDATA0 EQU H'0110' LCDDATA1 EQU H'0111' LCDDATA2 EQU H'0112' LCDDATA3 EQU H'0113' LCDDATA4 EQU H'0114' LCDDATA5 EQU H'0115' LCDDATA6 EQU H'0116' LCDDATA7 EQU H'0117' LCDDATA8 EQU H'0118' LCDDATA9 EQU H'0119' LCDDATA10 EQU H'011A' LCDDATA11 EQU H'011B' LCDSE0 EQU H'011C' LCDSE1 EQU H'011D' LCDSE2 EQU H'011E' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' LCDIF EQU H'0004' LVDIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0006' VCFG0 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' GO EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' LCDIE EQU H'0004' LVDIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' AN7 EQU H'0007' ; Backward compatibility only ANS6 EQU H'0006' AN6 EQU H'0006' ; Backward compatibility only ANS5 EQU H'0005' AN5 EQU H'0005' ; Backward compatibility only ANS4 EQU H'0004' AN4 EQU H'0004' ; Backward compatibility only ANS3 EQU H'0003' AN3 EQU H'0003' ; Backward compatibility only ANS2 EQU H'0002' AN2 EQU H'0002' ; Backward compatibility only ANS1 EQU H'0001' AN1 EQU H'0001' ; Backward compatibility only ANS0 EQU H'0000' AN0 EQU H'0000' ; Backward compatibility only ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' WPU6 EQU H'0006' WPU5 EQU H'0005' WPU4 EQU H'0004' WPU3 EQU H'0003' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' IOC6 EQU H'0006' IOC5 EQU H'0005' IOC4 EQU H'0004' ;----- CMCON1 Bits -------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON0 Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- VRCON Bits -------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' VLCDEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- WFT EQU H'0007' BIASMD EQU H'0006' LCDA EQU H'0005' WA EQU H'0004' LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- LCDDATA0 Bits ------------------------------------------------------- SEG7COM0 EQU H'0007' SEG6COM0 EQU H'0006' SEG5COM0 EQU H'0005' SEG4COM0 EQU H'0004' SEG3COM0 EQU H'0003' SEG2COM0 EQU H'0002' SEG1COM0 EQU H'0001' SEG0COM0 EQU H'0000' S7C0 EQU H'0007' S6C0 EQU H'0006' S5C0 EQU H'0005' S4C0 EQU H'0004' S3C0 EQU H'0003' S2C0 EQU H'0002' S1C0 EQU H'0001' S0C0 EQU H'0000' ;----- LCDDATA1 Bits ------------------------------------------------------- SEG15COM0 EQU H'0007' SEG14COM0 EQU H'0006' SEG13COM0 EQU H'0005' SEG12COM0 EQU H'0004' SEG11COM0 EQU H'0003' SEG10COM0 EQU H'0002' SEG9COM0 EQU H'0001' SEG8COM0 EQU H'0000' S15C0 EQU H'0007' S14C0 EQU H'0006' S13C0 EQU H'0005' S12C0 EQU H'0004' S11C0 EQU H'0003' S10C0 EQU H'0002' S9C0 EQU H'0001' S8C0 EQU H'0000' ;----- LCDDATA2 Bits ------------------------------------------------------- SEG23COM0 EQU H'0007' SEG22COM0 EQU H'0006' SEG21COM0 EQU H'0005' SEG20COM0 EQU H'0004' SEG19COM0 EQU H'0003' SEG18COM0 EQU H'0002' SEG17COM0 EQU H'0001' SEG16COM0 EQU H'0000' S23C0 EQU H'0007' S22C0 EQU H'0006' S21C0 EQU H'0005' S20C0 EQU H'0004' S19C0 EQU H'0003' S18C0 EQU H'0002' S17C0 EQU H'0001' S16C0 EQU H'0000' ;----- LCDDATA3 Bits ------------------------------------------------------- SEG7COM1 EQU H'0007' SEG6COM1 EQU H'0006' SEG5COM1 EQU H'0005' SEG4COM1 EQU H'0004' SEG3COM1 EQU H'0003' SEG2COM1 EQU H'0002' SEG1COM1 EQU H'0001' SEG0COM1 EQU H'0000' S7C1 EQU H'0007' S6C1 EQU H'0006' S5C1 EQU H'0005' S4C1 EQU H'0004' S3C1 EQU H'0003' S2C1 EQU H'0002' S1C1 EQU H'0001' S0C1 EQU H'0000' ;----- LCDDATA4 Bits ------------------------------------------------------- SEG15COM1 EQU H'0007' SEG14COM1 EQU H'0006' SEG13COM1 EQU H'0005' SEG12COM1 EQU H'0004' SEG11COM1 EQU H'0003' SEG10COM1 EQU H'0002' SEG9COM1 EQU H'0001' SEG8COM1 EQU H'0000' S15C1 EQU H'0007' S14C1 EQU H'0006' S13C1 EQU H'0005' S12C1 EQU H'0004' S11C1 EQU H'0003' S10C1 EQU H'0002' S9C1 EQU H'0001' S8C1 EQU H'0000' ;----- LCDDATA5 Bits ------------------------------------------------------- SEG23COM1 EQU H'0007' SEG22COM1 EQU H'0006' SEG21COM1 EQU H'0005' SEG20COM1 EQU H'0004' SEG19COM1 EQU H'0003' SEG18COM1 EQU H'0002' SEG17COM1 EQU H'0001' SEG16COM1 EQU H'0000' S23C1 EQU H'0007' S22C1 EQU H'0006' S21C1 EQU H'0005' S20C1 EQU H'0004' S19C1 EQU H'0003' S18C1 EQU H'0002' S17C1 EQU H'0001' S16C1 EQU H'0000' ;----- LCDDATA6 Bits ------------------------------------------------------- SEG7COM2 EQU H'0007' SEG6COM2 EQU H'0006' SEG5COM2 EQU H'0005' SEG4COM2 EQU H'0004' SEG3COM2 EQU H'0003' SEG2COM2 EQU H'0002' SEG1COM2 EQU H'0001' SEG0COM2 EQU H'0000' S7C2 EQU H'0007' S6C2 EQU H'0006' S5C2 EQU H'0005' S4C2 EQU H'0004' S3C2 EQU H'0003' S2C2 EQU H'0002' S1C2 EQU H'0001' S0C2 EQU H'0000' ;----- LCDDATA7 Bits ------------------------------------------------------- SEG15COM2 EQU H'0007' SEG14COM2 EQU H'0006' SEG13COM2 EQU H'0005' SEG12COM2 EQU H'0004' SEG11COM2 EQU H'0003' SEG10COM2 EQU H'0002' SEG9COM2 EQU H'0001' SEG8COM2 EQU H'0000' S15C2 EQU H'0007' S14C2 EQU H'0006' S13C2 EQU H'0005' S12C2 EQU H'0004' S11C2 EQU H'0003' S10C2 EQU H'0002' S9C2 EQU H'0001' S8C2 EQU H'0000' ;----- LCDDATA8 Bits ------------------------------------------------------- SEG23COM2 EQU H'0007' SEG22COM2 EQU H'0006' SEG21COM2 EQU H'0005' SEG20COM2 EQU H'0004' SEG19COM2 EQU H'0003' SEG18COM2 EQU H'0002' SEG17COM2 EQU H'0001' SEG16COM2 EQU H'0000' S23C2 EQU H'0007' S22C2 EQU H'0006' S21C2 EQU H'0005' S20C2 EQU H'0004' S19C2 EQU H'0003' S18C2 EQU H'0002' S17C2 EQU H'0001' S16C2 EQU H'0000' ;----- LCDDATA9 Bits ------------------------------------------------------- SEG7COM3 EQU H'0007' SEG6COM3 EQU H'0006' SEG5COM3 EQU H'0005' SEG4COM3 EQU H'0004' SEG3COM3 EQU H'0003' SEG2COM3 EQU H'0002' SEG1COM3 EQU H'0001' SEG0COM3 EQU H'0000' S7C3 EQU H'0007' S6C3 EQU H'0006' S5C3 EQU H'0005' S4C3 EQU H'0004' S3C3 EQU H'0003' S2C3 EQU H'0002' S1C3 EQU H'0001' S0C3 EQU H'0000' ;----- LCDDATA10 Bits ------------------------------------------------------- SEG15COM3 EQU H'0007' SEG14COM3 EQU H'0006' SEG13COM3 EQU H'0005' SEG12COM3 EQU H'0004' SEG11COM3 EQU H'0003' SEG10COM3 EQU H'0002' SEG9COM3 EQU H'0001' SEG8COM3 EQU H'0000' S15C3 EQU H'0007' S14C3 EQU H'0006' S13C3 EQU H'0005' S12C3 EQU H'0004' S11C3 EQU H'0003' S10C3 EQU H'0002' S9C3 EQU H'0001' S8C3 EQU H'0000' ;----- LCDDATA11 Bits ------------------------------------------------------- SEG23COM3 EQU H'0007' SEG22COM3 EQU H'0006' SEG21COM3 EQU H'0005' SEG20COM3 EQU H'0004' SEG19COM3 EQU H'0003' SEG18COM3 EQU H'0002' SEG17COM3 EQU H'0001' SEG16COM3 EQU H'0000' S23C3 EQU H'0007' S22C3 EQU H'0006' S21C3 EQU H'0005' S20C3 EQU H'0004' S19C3 EQU H'0003' S18C3 EQU H'0002' S17C3 EQU H'0001' S16C3 EQU H'0000' ;----- LCDSE0 Bits -------------------------------------------------------- SE7 EQU H'0007' SE6 EQU H'0006' SE5 EQU H'0005' SE4 EQU H'0004' SE3 EQU H'0003' SE2 EQU H'0002' SE1 EQU H'0001' SE0 EQU H'0000' SEGEN7 EQU H'0007' SEGEN6 EQU H'0006' SEGEN5 EQU H'0005' SEGEN4 EQU H'0004' SEGEN3 EQU H'0003' SEGEN2 EQU H'0002' SEGEN1 EQU H'0001' SEGEN0 EQU H'0000' ;----- LCDSE1 Bits -------------------------------------------------------- SE15 EQU H'0007' SE14 EQU H'0006' SE13 EQU H'0005' SE12 EQU H'0004' SE11 EQU H'0003' SE10 EQU H'0002' SE9 EQU H'0001' SE8 EQU H'0000' SEGEN15 EQU H'0007' SEGEN14 EQU H'0006' SEGEN13 EQU H'0005' SEGEN12 EQU H'0004' SEGEN11 EQU H'0003' SEGEN10 EQU H'0002' SEGEN9 EQU H'0001' SEGEN8 EQU H'0000' ;----- LCDSE2 Bits -------------------------------------------------------- SE23 EQU H'0007' SE22 EQU H'0006' SE21 EQU H'0005' SE20 EQU H'0004' SE19 EQU H'0003' SE18 EQU H'0002' SE17 EQU H'0001' SE16 EQU H'0000' SEGEN23 EQU H'0007' SEGEN22 EQU H'0006' SEGEN21 EQU H'0005' SEGEN20 EQU H'0004' SEGEN19 EQU H'0003' SEGEN18 EQU H'0002' SEGEN17 EQU H'0001' SEGEN16 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' EEWR EQU H'0001' RD EQU H'0000' EERD EQU H'0000' ;----- EEADRH Bits -------------------------------------------------------- EEADRH4 EQU H'0004' EEADRH3 EQU H'0003' EEADRH2 EQU H'0002' EEADRH1 EQU H'0001' EEADRH0 EQU H'0000' ;----- EEADRL Bits -------------------------------------------------------- EEADRL7 EQU H'0007' EEADRL6 EQU H'0006' EEADRL5 EQU H'0005' EEADRL4 EQU H'0004' EEADRL3 EQU H'0003' EEADRL2 EQU H'0002' EEADRL1 EQU H'0001' EEADRL0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'9A'-H'9B' __BADRAM H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG EQU H'2007' ;Configuration Byte 1 Options _DEBUG_ON EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16c73.inc0000644000175000017500000002714411156313161013066 00000000000000 LIST ; P16C73.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C73 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C73 ; 2. LIST directive in the source file ; LIST P=PIC16C73 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 05/17/96 Updated BADRAM map ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C73 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3F8F' _CP_75 EQU H'3F9F' _CP_50 EQU H'3FAF' _CP_OFF EQU H'3FBF' _PWRTE_ON EQU H'3FBF' _PWRTE_OFF EQU H'3FB7' _WDT_ON EQU H'3FBF' _WDT_OFF EQU H'3FBB' _LP_OSC EQU H'3FBC' _XT_OSC EQU H'3FBD' _HS_OSC EQU H'3FBE' _RC_OSC EQU H'3FBF' LIST gputils-0.13.7/header/p16f610.inc0000644000175000017500000003125511156521302013142 00000000000000 LIST ; P16F610.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F610 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F610 ; 2. LIST directive in the source file ; LIST P=PIC16F610 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 07/10/06 Original ;1.01 12/04/06 Added WPU, BOR and IOC aliases ;1.02 01/15/07 Added PORTC, TRISA & TRISC bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F610 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' VRCON EQU H'0019' CM1CON0 EQU H'001A' CM2CON0 EQU H'001B' CM2CON1 EQU H'001C' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' ANSEL EQU H'0091' WPUA EQU H'0095' WPU EQU H'0095' IOCA EQU H'0096' IOC EQU H'0096' SRCON0 EQU H'0099' SRCON1 EQU H'009A' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- PORTC Bits --------------------------------------------------------- RC5 EQU H'0005' RC4 EQU H'0004' RC3 EQU H'0003' RC2 EQU H'0002' RC1 EQU H'0001' RC0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- C2IF EQU H'0004' C1IF EQU H'0003' TMR1IF EQU H'0000' T1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' FVREN EQU H'0004' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1ACS EQU H'0004' C1HYS EQU H'0003' C2HYS EQU H'0002' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISC Bits -------------------------------------------------------- TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- C2IE EQU H'0004' C1IE EQU H'0003' TMR1IE EQU H'0000' T1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- WPU Bits --------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- SRCON0 Bits ------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' SRCLKEN EQU H'0000' ;----- SRCON1 Bits ------------------------------------------------------- SRCS1 EQU H'0007' SRCS0 EQU H'0006' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'11' -H'18', H'1D'-H'1F', H'20' -H'3F' __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'9B' -H'9F', H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOD_ON EQU H'3FFF' _BOR_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOR_NSLEEP EQU H'3EFF' _BOD_OFF EQU H'3CFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f83j90.inc0000644000175000017500000016532011156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F83J90 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F83J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F83J90 ; 2. LIST directive in the source file ; LIST P=PIC18F83J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F83J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA5 EQU H'0F6B' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA11 EQU H'0F71' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA17 EQU H'0F77' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' LCDDATA23 EQU H'0F7D' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDSE5 EQU H'0FBA' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP1 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' MODE13 EQU H'0002' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' CPEN EQU H'0006' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16lf1936.inc0000644000175000017500000011626111156521301013412 00000000000000 LIST ;========================================================================== ; MPASM PIC16LF1936 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16LF1936 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16LF1936 ; 2. LIST directive in the source file ; LIST P=PIC16LF1936 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF1936 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'000F' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'008F' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'010F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E'-H'0190' __BADRAM H'0197'-H'0198' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0330'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079A'-H'079F' __BADRAM H'07A2' __BADRAM H'07A5' __BADRAM H'07A8' __BADRAM H'07AB'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _nPWRTE_OFF EQU H'FFDF' ; PWRT enabled _nPWRTE_ON EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _nDEBUG_ON EQU H'EFFF' ; Background debugger is enabled _nDEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p18f85j90.inc0000644000175000017500000016532011156521301013415 00000000000000 LIST ;========================================================================== ; MPASM PIC18F85J90 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F85J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F85J90 ; 2. LIST directive in the source file ; LIST P=PIC18F85J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F85J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA5 EQU H'0F6B' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA11 EQU H'0F71' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA17 EQU H'0F77' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' LCDDATA23 EQU H'0F7D' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDSE5 EQU H'0FBA' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP1 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' MODE13 EQU H'0002' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' CPEN EQU H'0006' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c72a.inc0000644000175000017500000002257611156313161013232 00000000000000 LIST ; P16C72A.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C72A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C72A ; 2. LIST directive in the source file ; LIST P=PIC16C72A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C72A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1D' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18lf46j50.inc0000644000175000017500000020020311156521301013550 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF46J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF46J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF46J50 ; 2. LIST directive in the source file ; LIST P=PIC18LF46J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF46J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f628.inc0000644000175000017500000002412711156313161013155 00000000000000 LIST ; P16F628.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F628 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F628 ; 2. LIST directive in the source file ; LIST P=PIC16F628 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 13 Sept 2001 Added _DATA_CP_ON and _DATA_CP_OFF ;1.00 10 Feb 1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F628 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' CMIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits --------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' CMIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' NOT_BOD EQU H'0000' ;----- TXSTA Bits ---------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'03FF' _CP_75 EQU H'17FF' _CP_50 EQU H'2BFF' _CP_OFF EQU H'3FFF' _DATA_CP_ON EQU H'3EFF' _DATA_CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FEF' _LP_OSC EQU H'3FEC' _XT_OSC EQU H'3FED' _HS_OSC EQU H'3FEE' LIST gputils-0.13.7/header/p18f24j11.inc0000644000175000017500000014062211156521301013375 00000000000000 LIST ;========================================================================== ; MPASM PIC18F24J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F24J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F24J11 ; 2. LIST directive in the source file ; LIST P=PIC18F24J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F24J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ULPWU EQU H'0000' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F65' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f648a.inc0000644000175000017500000002467011156313161013323 00000000000000 LIST ; P16F648A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F648A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F648A ; 2. LIST directive in the source file ; LIST P=PIC16F648A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 14 Nov 2002 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F648A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' CMIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits --------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' CMIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' NOT_BOD EQU H'0000' ;Backwards compatability to 16F62X ;----- TXSTA Bits ---------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' ;Backwards compatability to 16F62X _BODEN_OFF EQU H'3FBF' ;Backwards compatability to 16F62X _BOREN_ON EQU H'3FFF' _BOREN_OFF EQU H'3FBF' _CP_ON EQU H'1FFF' _CP_OFF EQU H'3FFF' _DATA_CP_ON EQU H'3EFF' _DATA_CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _RC_OSC_CLKOUT EQU H'3FFF' _RC_OSC_NOCLKOUT EQU H'3FFE' _ER_OSC_CLKOUT EQU H'3FFF' ;Backwards compatability to 16F62X _ER_OSC_NOCLKOUT EQU H'3FFE' ;Backwards compatability to 16F62X _INTOSC_OSC_CLKOUT EQU H'3FFD' _INTOSC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' ;Backwards compatability to 16F62X _INTRC_OSC_NOCLKOUT EQU H'3FFC' ;Backwards compatability to 16F62X _EXTCLK_OSC EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' LIST gputils-0.13.7/header/p17c43.inc0000644000175000017500000002517611156313161013067 00000000000000 LIST ; P17C43.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C43 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C43 ; 2. LIST directive in the source file ; LIST P=PIC17C43 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.04 03/14/97 Corrected configuration bits value for protected ; microcontroller mode ;1.03 07/15/96 Corrected MAXRAM ;1.02 06/28/96 Corrected MAXRAM, BADRAM, and registers in upper banks ;1.01 04/10/96 Added _WDT_OFF value, PSx values, fixed MAXRAM value ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C43 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCREG EQU H'0014' TXSTA EQU H'0015' TXREG EQU H'0016' SPBRG EQU H'0017' PRODL EQU H'0018' PRODH EQU H'0019' DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' PIE EQU H'0117' TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' NOT_PD EQU H'0002' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIE Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' RCIE EQU H'0000' ;----- PIR Bits ----------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' RCIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' T0CKI EQU H'0001' INT EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' T0PS2 EQU H'0003' PS2 EQU H'0003' T0PS1 EQU H'0002' PS1 EQU H'0002' T0PS0 EQU H'0001' PS0 EQU H'0001' ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3FF' __BADRAM H'118'-H'11F', H'218'-H'2FF', H'318'-H'3FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p18f64j90.inc0000644000175000017500000015023611156521302013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F64J90 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F64J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F64J90 ; 2. LIST directive in the source file ; LIST P=PIC18F64J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F64J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' SEG32COM1 EQU H'0000' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' SEG32COM2 EQU H'0000' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' SEG32COM3 EQU H'0000' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP1 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SEGEN32 EQU H'0000' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' SEG32COM0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' MODE13 EQU H'0002' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' CPEN EQU H'0006' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F6B' __BADRAM H'0F71' __BADRAM H'0F77' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FBA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f8622.inc0000644000175000017500000020736111156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8622 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8622 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8622 ; 2. LIST directive in the source file ; LIST P=PIC18F8622 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8622 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ECCP2_PORTB EQU H'0003' P2A_PORTB EQU H'0003' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C_PORTE EQU H'0003' P3B_PORTE EQU H'0004' P1C_PORTE EQU H'0005' P1B_PORTE EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' P3C_PORTH EQU H'0004' P3B_PORTH EQU H'0005' P1C_PORTH EQU H'0006' P1B_PORTH EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; Address Bus Width Select bits: ; ADDRBW = ADDR8BIT 8-bit Address Bus ; ADDRBW = ADDR12BIT 12-bit Address Bus ; ADDRBW = ADDR16BIT 16-bit Address Bus ; ADDRBW = ADDR20BIT 20-bit Address Bus ; ; Data Bus Width Select bit: ; DATABW = DATA8BIT 8-bit External Bus mode ; DATABW = DATA16BIT 16-bit External Bus mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits ; WAIT = OFF Wait selections are unavailable for table reads and table writes ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; ECCP MUX bit: ; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively ; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively ; ; CCP2 MUX bit: ; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _ADDRBW_ADDR8BIT_3L EQU H'CF' ; 8-bit Address Bus _ADDRBW_ADDR12BIT_3L EQU H'DF' ; 12-bit Address Bus _ADDRBW_ADDR16BIT_3L EQU H'EF' ; 16-bit Address Bus _ADDRBW_ADDR20BIT_3L EQU H'FF' ; 20-bit Address Bus _DATABW_DATA8BIT_3L EQU H'BF' ; 8-bit External Bus mode _DATABW_DATA16BIT_3L EQU H'FF' ; 16-bit External Bus mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits _WAIT_OFF_3L EQU H'FF' ; Wait selections are unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _ECCPMX_PORTH_3H EQU H'FD' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively _ECCPMX_PORTE_3H EQU H'FF' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively _CCP2MX_PORTBE_3H EQU H'FE' ; ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f723.inc0000644000175000017500000005006511156521301013146 00000000000000 LIST ; P16F723.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F723 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F723 ; 2. LIST directive in the source file ; LIST P=PIC16F723 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/09/06 Initial template ;0.02 10/25/07 Add 189h to BADRAM ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F723 MESSG "Processor-header file mismatch. Verify selected processor." #define __16F723 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'08' __BADRAM H'88' __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'110'-H'11F', H'130'-H'16F' __BADRAM H'187'-H'189', H'18D'-H'18F' __BADRAM H'190'-H'1EF' LIST gputils-0.13.7/header/p16lf1933.inc0000644000175000017500000011642411156521301013410 00000000000000 LIST ;========================================================================== ; MPASM PIC16LF1933 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16LF1933 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16LF1933 ; 2. LIST directive in the source file ; LIST P=PIC16LF1933 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF1933 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'000F' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'008F' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'010F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E'-H'0190' __BADRAM H'0197'-H'0198' __BADRAM H'01A0'-H'01EF' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'0220'-H'026F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'02A0'-H'02EF' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0320'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079A'-H'079F' __BADRAM H'07A2' __BADRAM H'07A5' __BADRAM H'07A8' __BADRAM H'07AB'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _nPWRTE_OFF EQU H'FFDF' ; PWRT enabled _nPWRTE_ON EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _nDEBUG_ON EQU H'EFFF' ; Background debugger is enabled _nDEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p18f2480.inc0000644000175000017500000040722411156521301013235 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2480 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2480 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2480 ; 2. LIST directive in the source file ; LIST P=PIC18F2480 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2480 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREFA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0CFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FAA' __BADRAM H'0FB4'-H'0FB6' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'EF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'FF' ; 2K words (4K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4680.inc0000644000175000017500000042503611156521302013243 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4680 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4680 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4680 ; 2. LIST directive in the source file ; LIST P=PIC18F4680 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4680 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' ECCP1CON EQU H'0FBA' ECCPR1 EQU H'0FBB' ECCPR1L EQU H'0FBB' ECCPR1H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXBODBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXB0DBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF_PORTA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' C1INB EQU H'0000' C1INA EQU H'0001' C2INB EQU H'0002' C2INA EQU H'0003' P1A EQU H'0004' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ECCP1 EQU H'0004' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- ECCP1IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- ECCP1IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- ECCP1IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF_CVRCON EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- ECCP1M0 EQU H'0000' ECCP1M1 EQU H'0001' ECCP1M2 EQU H'0002' ECCP1M3 EQU H'0003' EDC1B0 EQU H'0004' EDC1B1 EQU H'0005' EPWM1M0 EQU H'0006' EPWM1M1 EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18lf45j11.inc0000644000175000017500000015457711156521301013572 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF45J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF45J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF45J11 ; 2. LIST directive in the source file ; LIST P=PIC18LF45J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF45J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F60'-H'0F65' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f87j60.inc0000644000175000017500000014701611156521301013416 00000000000000 LIST ;========================================================================== ; MPASM PIC18F87J60 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F87J60 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F87J60 ; 2. LIST directive in the source file ; LIST P=PIC18F87J60 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F87J60 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RJPU EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2_PORTC EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2_PORTE EQU H'0007' ECCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' ECCP3 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ4 EQU H'0004' RJ5 EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ4 EQU H'0004' LATJ5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ4 EQU H'0004' RJ5 EQU H'0005' ;----- TRISJ Bits ----------------------------------------------------- TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0F62'-H'0F66' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ; ECCP MUX bit: ; ECCPMX = OFF ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = ON ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = OFF ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) ; CCP2MX = ON ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f6723.inc0000644000175000017500000020322311156521301013232 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6723 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6723 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6723 ; 2. LIST directive in the source file ; LIST P=PIC18F6723 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6723 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Code Protection bit Block 6: ; CP6 = ON Block 6 (01BFFF-018000h) code-protected ; CP6 = OFF Block 6 (01BFFF-018000h) not code-protected ; ; Code Protection bit Block 7: ; CP7 = ON Block 7 (01C000-01FFFFh) code-protected ; CP7 = OFF Block 7 (01C000-01FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Write Protection bit Block 6: ; WRT6 = ON Block 6 (01BFFF-018000h) write-protected ; WRT6 = OFF Block 6 (01BFFF-018000h) not write-protected ; ; Write Protection bit Block 7: ; WRT7 = ON Block 7 (01C000-01FFFFh) write-protected ; WRT7 = OFF Block 7 (01C000-01FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 6: ; EBTR6 = ON Block 6 (018000-01BFFFh) protected from table reads executed in other blocks ; EBTR6 = OFF Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 7: ; EBTR7 = ON Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks ; EBTR7 = OFF Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected _CP6_ON_5L EQU H'BF' ; Block 6 (01BFFF-018000h) code-protected _CP6_OFF_5L EQU H'FF' ; Block 6 (01BFFF-018000h) not code-protected _CP7_ON_5L EQU H'7F' ; Block 7 (01C000-01FFFFh) code-protected _CP7_OFF_5L EQU H'FF' ; Block 7 (01C000-01FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected _WRT6_ON_6L EQU H'BF' ; Block 6 (01BFFF-018000h) write-protected _WRT6_OFF_6L EQU H'FF' ; Block 6 (01BFFF-018000h) not write-protected _WRT7_ON_6L EQU H'7F' ; Block 7 (01C000-01FFFFh) write-protected _WRT7_OFF_6L EQU H'FF' ; Block 7 (01C000-01FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks _EBTR6_ON_7L EQU H'BF' ; Block 6 (018000-01BFFFh) protected from table reads executed in other blocks _EBTR6_OFF_7L EQU H'FF' ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks _EBTR7_ON_7L EQU H'7F' ; Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks _EBTR7_OFF_7L EQU H'FF' ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f448.inc0000644000175000017500000014377011156521301013162 00000000000000 LIST ; P18F448.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F448 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F448 ; 2. LIST directive in the source file ; LIST P=PIC18F448 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.90 15 May 2001 Preliminary Release dzb ;0.99 29 June2001 Rev 1 dzb ;1.00 29 Oct.2001 Corrections & Additions cjh ;1.10 25 Jun 2002 Added CFGS as EECON1 bit 6 name pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F448 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' ECCPR1H EQU H'0FBC' ECCPR1L EQU H'0FBB' ECCP1CON EQU H'0FBA' ECCP1DEL EQU H'0FB7' ECCPAS EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TXERRCNT EQU H'0F76' RXERRCNT EQU H'0F75' COMSTAT EQU H'0F74' CIOCON EQU H'0F73' BRGCON3 EQU H'0F72' BRGCON2 EQU H'0F71' BRGCON1 EQU H'0F70' CANCON EQU H'0F6F' CANSTAT EQU H'0F6E' RXB0D7 EQU H'0F6D' RXB0D6 EQU H'0F6C' RXB0D5 EQU H'0F6B' RXB0D4 EQU H'0F6A' RXB0D3 EQU H'0F69' RXB0D2 EQU H'0F68' RXB0D1 EQU H'0F67' RXB0D0 EQU H'0F66' RXB0DLC EQU H'0F65' RXB0EIDL EQU H'0F64' RXB0EIDH EQU H'0F63' RXB0SIDL EQU H'0F62' RXB0SIDH EQU H'0F61' RXB0CON EQU H'0F60' CANSTATRO1 EQU H'0F5E' RXB1D7 EQU H'0F5D' RXB1D6 EQU H'0F5C' RXB1D5 EQU H'0F5B' RXB1D4 EQU H'0F5A' RXB1D3 EQU H'0F59' RXB1D2 EQU H'0F58' RXB1D1 EQU H'0F57' RXB1D0 EQU H'0F56' RXB1DLC EQU H'0F55' RXB1EIDL EQU H'0F54' RXB1EIDH EQU H'0F53' RXB1SIDL EQU H'0F52' RXB1SIDH EQU H'0F51' RXB1CON EQU H'0F50' CANSTATRO2 EQU H'0F4E' TXB0D7 EQU H'0F4D' TXB0D6 EQU H'0F4C' TXB0D5 EQU H'0F4B' TXB0D4 EQU H'0F4A' TXB0D3 EQU H'0F49' TXB0D2 EQU H'0F48' TXB0D1 EQU H'0F47' TXB0D0 EQU H'0F46' TXB0DLC EQU H'0F45' TXB0EIDL EQU H'0F44' TXB0EIDH EQU H'0F43' TXB0SIDL EQU H'0F42' TXB0SIDH EQU H'0F41' TXB0CON EQU H'0F40' CANSTATRO3 EQU H'0F3E' TXB1D7 EQU H'0F3D' TXB1D6 EQU H'0F3C' TXB1D5 EQU H'0F3B' TXB1D4 EQU H'0F3A' TXB1D3 EQU H'0F39' TXB1D2 EQU H'0F38' TXB1D1 EQU H'0F37' TXB1D0 EQU H'0F36' TXB1DLC EQU H'0F35' TXB1EIDL EQU H'0F34' TXB1EIDH EQU H'0F33' TXB1SIDL EQU H'0F32' TXB1SIDH EQU H'0F31' TXB1CON EQU H'0F30' CANSTATRO4 EQU H'0F2E' TXB2D7 EQU H'0F2D' TXB2D6 EQU H'0F2C' TXB2D5 EQU H'0F2B' TXB2D4 EQU H'0F2A' TXB2D3 EQU H'0F29' TXB2D2 EQU H'0F28' TXB2D1 EQU H'0F27' TXB2D0 EQU H'0F26' TXB2DLC EQU H'0F25' TXB2EIDL EQU H'0F24' TXB2EIDH EQU H'0F23' TXB2SIDL EQU H'0F22' TXB2SIDH EQU H'0F21' TXB2CON EQU H'0F20' RXM1EIDL EQU H'0F1F' RXM1EIDH EQU H'0F1E' RXM1SIDL EQU H'0F1D' RXM1SIDH EQU H'0F1C' RXM0EIDL EQU H'0F1B' RXM0EIDH EQU H'0F1A' RXM0SIDL EQU H'0F19' RXM0SIDH EQU H'0F18' RXF5EIDL EQU H'0F17' RXF5EIDH EQU H'0F16' RXF5SIDL EQU H'0F15' RXF5SIDH EQU H'0F14' RXF4EIDL EQU H'0F13' RXF4EIDH EQU H'0F12' RXF4SIDL EQU H'0F11' RXF4SIDH EQU H'0F10' RXF3EIDL EQU H'0F0F' RXF3EIDH EQU H'0F0E' RXF3SIDL EQU H'0F0D' RXF3SIDH EQU H'0F0C' RXF2EIDL EQU H'0F0B' RXF2EIDH EQU H'0F0A' RXF2SIDL EQU H'0F09' RXF2SIDH EQU H'0F08' RXF1EIDL EQU H'0F07' RXF1EIDH EQU H'0F06' RXF1SIDL EQU H'0F05' RXF1SIDH EQU H'0F04' RXF0EIDL EQU H'0F03' RXF0EIDH EQU H'0F02' RXF0SIDL EQU H'0F01' RXF0SIDH EQU H'0F00' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' SP4 EQU H'0004' SP3 EQU H'0003' SP2 EQU H'0002' SP1 EQU H'0001' SP0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IVRST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ECCP1CON Bits ------------------------------------------------------ EPWM1M1 EQU H'0007' EPWM1M0 EQU H'0006' EDC2B1 EQU H'0005' EDC2B0 EQU H'0004' ECCP1M3 EQU H'0003' ECCP1M2 EQU H'0002' ECCP1M1 EQU H'0001' ECCP1M0 EQU H'0000' ;----- ECCP1DEL Bits ----------------------------------------------------- EPDC0 EQU H'0000' EPDC1 EQU H'0001' EPDC2 EQU H'0002' EPDC3 EQU H'0003' EPDC4 EQU H'0004' EPDC5 EQU H'0005' EPDC6 EQU H'0006' EPDC7 EQU H'0007' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' ; For backward compatibility CVRR EQU H'0005' CVRSS EQU H'0004' ; For backward compatibility CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' ; For backward compatibility C2INV EQU H'0005' C1INV EQU H'0004' ; For backward compatibility CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3ECCP1 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' EEFS EQU H'0006' ; Backward compatibility only CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR3 Bits ---------------------------------------------------------- IRXIP EQU H'0007' WAKIP EQU H'0006' ERRIP EQU H'0005' TXB2IP EQU H'0004' TXB1IP EQU H'0003' TXB0IP EQU H'0002' RXB1IP EQU H'0001' RXB0IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- IRXIF EQU H'0007' WAKIF EQU H'0006' ERRIF EQU H'0005' TXB2IF EQU H'0004' TXB1IF EQU H'0003' TXB0IF EQU H'0002' RXB1IF EQU H'0001' RXB0IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- IRXIE EQU H'0007' WAKIE EQU H'0006' ERRIE EQU H'0005' TXB2IE EQU H'0004' TXB1IE EQU H'0003' TXB0IE EQU H'0002' RXB1IE EQU H'0001' RXB0IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' ECCP1IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' ECCP1IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' ECCP1IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- COMSTAT Bits --------------------------------------------------------- RX1OVFL EQU H'0007' RXB0OVFL EQU H'0007' RX2OVFL EQU H'0006' RXB1OVFL EQU H'0006' TXBO EQU H'0005' TXBP EQU H'0004' RXBP EQU H'0003' TXWARN EQU H'0002' RXWARN EQU H'0001' EWARN EQU H'0000' ;----- CIOCON Bits ----------------------------------------------------------- ENDRHI EQU H'0005' CANCAP EQU H'0004' ;----- BRGCON3 Bits ---------------------------------------------------------- WAKFIL EQU H'0006' SEG2PH2 EQU H'0002' SEG2PH1 EQU H'0001' SEG2PH0 EQU H'0000' ;----- BRGCON2 Bits ----------------------------------------------------------- SEG2PHTS EQU H'0007' SAM EQU H'0006' SEG1PH2 EQU H'0005' SEG1PH1 EQU H'0004' SEG1PH0 EQU H'0003' PRSEG2 EQU H'0002' PRSEG1 EQU H'0001' PRSEG0 EQU H'0000' ;----- BRGCON1 Bits ------------------------------------------------------------ SJW1 EQU H'0007' SJW0 EQU H'0006' BRP5 EQU H'0005' BRP4 EQU H'0004' BRP3 EQU H'0003' BRP2 EQU H'0002' BRP1 EQU H'0001' BRP0 EQU H'0000' ;----- CANCON Bits ------------------------------------------------------------- REQOP2 EQU H'0007' REQOP1 EQU H'0006' REQOP0 EQU H'0005' ABAT EQU H'0004' WIN2 EQU H'0003' WIN1 EQU H'0002' WIN0 EQU H'0001' ;----- CANSTAT Bits ----------------------------------------------------------- OPMODE2 EQU H'0007' OPMODE1 EQU H'0006' OPMODE0 EQU H'0005' ICODE2 EQU H'0003' ICODE1 EQU H'0002' ICODE0 EQU H'0001' ;----- RXBnCON Bits ----------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' RXB0DBEN EQU H'0002' FILHIT2 EQU H'0002' JTOFF EQU H'0001' FILHIT1 EQU H'0001' FILHIT0 EQU H'0000' ;----- TXBnCON Bits ---------------------------------------------------------- TXABT EQU H'0006' TXLARB EQU H'0005' TXERR EQU H'0004' TXREQ EQU H'0003' TXPRI1 EQU H'0001' TXPRI0 EQU H'0000' ;----- TXERRCNT Bits ---------------------------------------------------------- TEC7 EQU H'0007' TEC6 EQU H'0006' TEC5 EQU H'0005' TEC4 EQU H'0004' TEC3 EQU H'0003' TEC2 EQU H'0002' TEC1 EQU H'0001' TEC0 EQU H'0000' ;----- RXERRCNT Bits ---------------------------------------------------------- REC7 EQU H'0007' REC6 EQU H'0006' REC5 EQU H'0005' REC4 EQU H'0004' REC3 EQU H'0003' REC2 EQU H'0002' REC1 EQU H'0001' REC0 EQU H'0000' ;----- RXBnDLC and TXBnDLC Bits ----------------------------------------------- RXRTR EQU H'0006' TXRTR EQU H'0006' RESB1 EQU H'0005' RESB0 EQU H'0004' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DLC0 EQU H'0000' ;----- RXBnEIDL, RXFnEIDL, RXMnEIDL, and TXBnEIDL Bits ------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXBnEIDH, RXFnEIDH, RXMnEIDH, and TXBnEIDH Bits ------------------------- EID15 EQU H'0007' EID14 EQU H'0006' EID13 EQU H'0005' EID12 EQU H'0004' EID11 EQU H'0003' EID10 EQU H'0002' EID9 EQU H'0001' EID8 EQU H'0000' ;----- RXBnSIDL, RXFnSIDL, RXMnSIDL, and TXBnSIDL Bits ---------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' SRR EQU H'0004' EXID EQU H'0003' EXIDE EQU H'0003' EXIDEN EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXBnSIDH, RXFnSIDH, RXMnSIDH, and TXBnSIDH Bits ---------------------- SID10 EQU H'0007' SID9 EQU H'0006' SID8 EQU H'0005' SID7 EQU H'0004' SID6 EQU H'0003' SID5 EQU H'0002' SID4 EQU H'0001' SID3 EQU H'0001' ;----- RXB0D7 Bits ---------------------------------------------------------- RB0D77 EQU H'0007' RB0D76 EQU H'0006' RB0D75 EQU H'0005' RB0D74 EQU H'0004' RB0D73 EQU H'0003' RB0D72 EQU H'0002' RB0D71 EQU H'0001' RB0D70 EQU H'0000' ;----- RXB0D6 Bits ---------------------------------------------------------- RB0D67 EQU H'0007' RB0D66 EQU H'0006' RB0D65 EQU H'0005' RB0D64 EQU H'0004' RB0D63 EQU H'0003' RB0D62 EQU H'0002' RB0D61 EQU H'0001' RB0D60 EQU H'0000' ;----- RXB0D5 Bits ---------------------------------------------------------- RB0D57 EQU H'0007' RB0D56 EQU H'0006' RB0D55 EQU H'0005' RB0D54 EQU H'0004' RB0D53 EQU H'0003' RB0D52 EQU H'0002' RB0D51 EQU H'0001' RB0D50 EQU H'0000' ;----- RXB0D4 Bits ---------------------------------------------------------- RB0D47 EQU H'0007' RB0D46 EQU H'0006' RB0D45 EQU H'0005' RB0D44 EQU H'0004' RB0D43 EQU H'0003' RB0D42 EQU H'0002' RB0D41 EQU H'0001' RB0D40 EQU H'0000' ;----- RXB0D3 Bits ---------------------------------------------------------- RB0D37 EQU H'0007' RB0D36 EQU H'0006' RB0D35 EQU H'0005' RB0D34 EQU H'0004' RB0D33 EQU H'0003' RB0D32 EQU H'0002' RB0D31 EQU H'0001' RB0D30 EQU H'0000' ;----- RXB0D2 Bits ---------------------------------------------------------- RB0D27 EQU H'0007' RB0D26 EQU H'0006' RB0D25 EQU H'0005' RB0D24 EQU H'0004' RB0D23 EQU H'0003' RB0D22 EQU H'0002' RB0D21 EQU H'0001' RB0D20 EQU H'0000' ;----- RXB0D1 Bits ---------------------------------------------------------- RB0D17 EQU H'0007' RB0D16 EQU H'0006' RB0D15 EQU H'0005' RB0D14 EQU H'0004' RB0D13 EQU H'0003' RB0D12 EQU H'0002' RB0D11 EQU H'0001' RB0D10 EQU H'0000' ;----- RXB0D0 Bits ---------------------------------------------------------- RB0D07 EQU H'0007' RB0D06 EQU H'0006' RB0D05 EQU H'0005' RB0D04 EQU H'0004' RB0D03 EQU H'0003' RB0D02 EQU H'0002' RB0D01 EQU H'0001' RB0D00 EQU H'0000' ;----- RXB1D7 Bits ---------------------------------------------------------- RXB1D77 EQU H'0007' RXB1D76 EQU H'0006' RXB1D75 EQU H'0005' RXB1D74 EQU H'0004' RXB1D73 EQU H'0003' RXB1D72 EQU H'0002' RXB1D71 EQU H'0001' RXB1D70 EQU H'0000' ;----- RXB1D6 Bits ---------------------------------------------------------- RXB1D67 EQU H'0007' RXB1D66 EQU H'0006' RXB1D65 EQU H'0005' RXB1D64 EQU H'0004' RXB1D63 EQU H'0003' RXB1D62 EQU H'0002' RXB1D61 EQU H'0001' RXB1D60 EQU H'0000' ;----- RXB1D5 Bits ---------------------------------------------------------- RXB1D57 EQU H'0007' RXB1D56 EQU H'0006' RXB1D55 EQU H'0005' RXB1D54 EQU H'0004' RXB1D53 EQU H'0003' RXB1D52 EQU H'0002' RXB1D51 EQU H'0001' RXB1D50 EQU H'0000' ;----- RXB1D4 Bits ---------------------------------------------------------- RXB1D47 EQU H'0007' RXB1D46 EQU H'0006' RXB1D45 EQU H'0005' RXB1D44 EQU H'0004' RXB1D43 EQU H'0003' RXB1D42 EQU H'0002' RXB1D41 EQU H'0001' RXB1D40 EQU H'0000' ;----- RXB1D3 Bits ---------------------------------------------------------- RXB1D37 EQU H'0007' RXB1D36 EQU H'0006' RXB1D35 EQU H'0005' RXB1D34 EQU H'0004' RXB1D33 EQU H'0003' RXB1D32 EQU H'0002' RXB1D31 EQU H'0001' RXB1D30 EQU H'0000' ;----- RXB1D2 Bits ---------------------------------------------------------- RXB1D27 EQU H'0007' RXB1D26 EQU H'0006' RXB1D25 EQU H'0005' RXB1D24 EQU H'0004' RXB1D23 EQU H'0003' RXB1D22 EQU H'0002' RXB1D21 EQU H'0001' RXB1D20 EQU H'0000' ;----- RXB1D1 Bits ---------------------------------------------------------- RXB1D17 EQU H'0007' RXB1D16 EQU H'0006' RXB1D15 EQU H'0005' RXB1D14 EQU H'0004' RXB1D13 EQU H'0003' RXB1D12 EQU H'0002' RXB1D11 EQU H'0001' RXB1D10 EQU H'0000' ;----- RXB1D0 Bits ---------------------------------------------------------- RXB1D07 EQU H'0007' RXB1D06 EQU H'0006' RXB1D05 EQU H'0005' RXB1D04 EQU H'0004' RXB1D03 EQU H'0003' RXB1D02 EQU H'0002' RXB1D01 EQU H'0001' RXB1D00 EQU H'0000' ;----- TXB2D7 Bits ---------------------------------------------------------- TXB2D77 EQU H'0007' TXB2D76 EQU H'0006' TXB2D75 EQU H'0005' TXB2D74 EQU H'0004' TXB2D73 EQU H'0003' TXB2D72 EQU H'0002' TXB2D71 EQU H'0001' TXB2D70 EQU H'0000' ;----- TXB2D6 Bits ---------------------------------------------------------- TXB2D67 EQU H'0007' TXB2D66 EQU H'0006' TXB2D65 EQU H'0005' TXB2D64 EQU H'0004' TXB2D63 EQU H'0003' TXB2D62 EQU H'0002' TXB2D61 EQU H'0001' TXB2D60 EQU H'0000' ;----- TXB2D5 Bits ---------------------------------------------------------- TXB2D57 EQU H'0007' TXB2D56 EQU H'0006' TXB2D55 EQU H'0005' TXB2D54 EQU H'0004' TXB2D53 EQU H'0003' TXB2D52 EQU H'0002' TXB2D51 EQU H'0001' TXB2D50 EQU H'0000' ;----- TXB2D4 Bits ---------------------------------------------------------- TXB2D47 EQU H'0007' TXB2D46 EQU H'0006' TXB2D45 EQU H'0005' TXB2D44 EQU H'0004' TXB2D43 EQU H'0003' TXB2D42 EQU H'0002' TXB2D41 EQU H'0001' TXB2D40 EQU H'0000' ;----- TXB2D3 Bits ---------------------------------------------------------- TXB2D37 EQU H'0007' TXB2D36 EQU H'0006' TXB2D35 EQU H'0005' TXB2D34 EQU H'0004' TXB2D33 EQU H'0003' TXB2D32 EQU H'0002' TXB2D31 EQU H'0001' TXB2D30 EQU H'0000' ;----- TXB2D2 Bits ---------------------------------------------------------- TXB2D27 EQU H'0007' TXB2D26 EQU H'0006' TXB2D25 EQU H'0005' TXB2D24 EQU H'0004' TXB2D23 EQU H'0003' TXB2D22 EQU H'0002' TXB2D21 EQU H'0001' TXB2D20 EQU H'0000' ;----- TXB2D1 Bits ---------------------------------------------------------- TXB2D17 EQU H'0007' TXB2D16 EQU H'0006' TXB2D15 EQU H'0005' TXB2D14 EQU H'0004' TXB2D13 EQU H'0003' TXB2D12 EQU H'0002' TXB2D11 EQU H'0001' TXB2D10 EQU H'0000' ;----- TXB2D0 Bits ---------------------------------------------------------- TXB2D07 EQU H'0007' TXB2D06 EQU H'0006' TXB2D05 EQU H'0005' TXB2D04 EQU H'0004' TXB2D03 EQU H'0003' TXB2D02 EQU H'0002' TXB2D01 EQU H'0001' TXB2D00 EQU H'0000' ;----- TXB1D7 Bits ---------------------------------------------------------- TXB1D77 EQU H'0007' TXB1D76 EQU H'0006' TXB1D75 EQU H'0005' TXB1D74 EQU H'0004' TXB1D73 EQU H'0003' TXB1D72 EQU H'0002' TXB1D71 EQU H'0001' TXB1D70 EQU H'0000' ;----- TXB1D6 Bits ---------------------------------------------------------- TXB1D67 EQU H'0007' TXB1D66 EQU H'0006' TXB1D65 EQU H'0005' TXB1D64 EQU H'0004' TXB1D63 EQU H'0003' TXB1D62 EQU H'0002' TXB1D61 EQU H'0001' TXB1D60 EQU H'0000' ;----- TXB1D5 Bits ---------------------------------------------------------- TXB1D57 EQU H'0007' TXB1D56 EQU H'0006' TXB1D55 EQU H'0005' TXB1D54 EQU H'0004' TXB1D53 EQU H'0003' TXB1D52 EQU H'0002' TXB1D51 EQU H'0001' TXB1D50 EQU H'0000' ;----- TXB1D4 Bits ---------------------------------------------------------- TXB1D47 EQU H'0007' TXB1D46 EQU H'0006' TXB1D45 EQU H'0005' TXB1D44 EQU H'0004' TXB1D43 EQU H'0003' TXB1D42 EQU H'0002' TXB1D41 EQU H'0001' TXB1D40 EQU H'0000' ;----- TXB1D3 Bits ---------------------------------------------------------- TXB1D37 EQU H'0007' TXB1D36 EQU H'0006' TXB1D35 EQU H'0005' TXB1D34 EQU H'0004' TXB1D33 EQU H'0003' TXB1D32 EQU H'0002' TXB1D31 EQU H'0001' TXB1D30 EQU H'0000' ;----- TXB1D2 Bits ---------------------------------------------------------- TXB1D27 EQU H'0007' TXB1D26 EQU H'0006' TXB1D25 EQU H'0005' TXB1D24 EQU H'0004' TBB1D23 EQU H'0003' TXB1D22 EQU H'0002' TXB1D21 EQU H'0001' TXB1D20 EQU H'0000' ;----- TXB1D1 Bits ---------------------------------------------------------- TXB1D17 EQU H'0007' TXB1D16 EQU H'0006' TXB1D15 EQU H'0005' TXB1D14 EQU H'0004' TXB1D13 EQU H'0003' TXB1D12 EQU H'0002' TXB1D11 EQU H'0001' TXB1D10 EQU H'0000' ;----- TXB1D0 Bits ---------------------------------------------------------- TXB1D07 EQU H'0007' TXB1D06 EQU H'0006' TXB1D05 EQU H'0005' TXB1D04 EQU H'0004' TXB1D03 EQU H'0003' TXB1D02 EQU H'0002' TXB1D01 EQU H'0001' TXB1D00 EQU H'0000' ;----- TXB0D7 Bits ---------------------------------------------------------- TXB0D77 EQU H'0007' TXB0D76 EQU H'0006' TXB0D75 EQU H'0005' TXB0D74 EQU H'0004' TXB0D73 EQU H'0003' TXB0D72 EQU H'0002' TXB0D71 EQU H'0001' TXB0D70 EQU H'0000' ;----- TXB0D6 Bits ---------------------------------------------------------- TXB0D67 EQU H'0007' TXB0D66 EQU H'0006' TXB0D65 EQU H'0005' TXB0D64 EQU H'0004' TXB0D63 EQU H'0003' TXB0D62 EQU H'0002' TXB0D61 EQU H'0001' TXB0D60 EQU H'0000' ;----- TXB0D5 Bits ---------------------------------------------------------- TXB0D57 EQU H'0007' TXB0D56 EQU H'0006' TXB0D55 EQU H'0005' TXB0D54 EQU H'0004' TXB0D53 EQU H'0003' TXB0D52 EQU H'0002' TXB0D51 EQU H'0001' TXB0D50 EQU H'0000' ;----- TXB0D4 Bits ---------------------------------------------------------- TXB0D47 EQU H'0007' TXB0D46 EQU H'0006' TXB0D45 EQU H'0005' TXB0D44 EQU H'0004' TXB0D43 EQU H'0003' TXB0D42 EQU H'0002' TXB0D41 EQU H'0001' TXB0D40 EQU H'0000' ;----- TXB0D3 Bits ---------------------------------------------------------- TXB0D37 EQU H'0007' TXB0D36 EQU H'0006' TXB0D35 EQU H'0005' TXB0D34 EQU H'0004' TXB0D33 EQU H'0003' TXB0D32 EQU H'0002' TXB0D31 EQU H'0001' TXB0D30 EQU H'0000' ;----- TXB0D2 Bits ---------------------------------------------------------- TXB0D27 EQU H'0007' TXB0D26 EQU H'0006' TXB0D25 EQU H'0005' TXB0D24 EQU H'0004' TXB0D23 EQU H'0003' TXB0D22 EQU H'0002' TXB0D21 EQU H'0001' TXB0D20 EQU H'0000' ;----- TXB0D1 Bits ---------------------------------------------------------- TXB0D17 EQU H'0007' TXB0D16 EQU H'0006' TXB0D15 EQU H'0005' TXB0D14 EQU H'0004' TXB0D13 EQU H'0003' TXB0D12 EQU H'0002' TXB0D11 EQU H'0001' TXB0D10 EQU H'0000' ;----- TXB0D0 Bits ---------------------------------------------------------- TXB0D07 EQU H'0007' TXB0D06 EQU H'0006' TXB0D05 EQU H'0005' TXB0D04 EQU H'0004' TXB0D03 EQU H'0003' TXB0D02 EQU H'0002' TXB0D01 EQU H'0001' TXB0D00 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 CVREF EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 NOT_SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 CANTX EQU 2 RB3 EQU 3 CANRX EQU 3 RB4 EQU 4 RB5 EQU 5 PGM EQU 5 RB6 EQU 6 PGC EQU 6 RB7 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 C1INP EQU 0 RD1 EQU 1 PSP1 EQU 1 C1INM EQU 1 RD2 EQU 2 PSP2 EQU 2 C2INP EQU 2 RD3 EQU 3 PSP3 EQU 3 C2INM EQU 3 RD4 EQU 4 PSP4 EQU 4 ECCP1 EQU 4 P1A EQU 4 RD5 EQU 5 PSP5 EQU 5 P1B EQU 5 RD6 EQU 6 PSP6 EQU 6 P1C EQU 6 RD7 EQU 7 PSP7 EQU 7 P1D EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 NOT_RD EQU 0 AN5 EQU 0 RE1 EQU 1 ;WR EQU 1 *** Already defined by EECON.WR, also bit 1 NOT_WR EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 NOT_CS EQU 2 AN7 EQU 2 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'300'-H'EFF' __BADRAM H'FD4',H'FC0',H'FB9',H'FB8',H'FAA',H'F97'-H'F9C' __BADRAM H'F8E'-H'F91',H'F85'-H'F88', H'F79'-H'F7F',H'F77' __BADRAM H'F5F',H'F4F',H'F3F',H'F2F' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000Ah ; CONFIG6H = Configuration Byte 6H 30000Bh ; CONFIG7L = Configuration Byte 7L 30000Ch ; CONFIG7H = Configuration Byte 7H 30000Dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_25_2L EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;Configuration Byte 6H Options _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as _BOR_ON_2L). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_25_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16c61.inc0000644000175000017500000001026311156313161013055 00000000000000 LIST ; P16C61.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C61 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C61 ; 2. LIST directive in the source file ; LIST P=PIC16C61 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C61 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'AF' __BADRAM H'07'-H'09', H'30'-H'7F', H'87'-H'89' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FFF' _PWRTE_OFF EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16cr72.inc0000644000175000017500000002227511156313161013247 00000000000000 LIST ; P16CR72.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR72 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR72 ; 2. LIST directive in the source file ; LIST P=PIC16CR72 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/27/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR72 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1INSYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1D' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f2610.inc0000644000175000017500000011641411156521301013226 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2610 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2610 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2610 ; 2. LIST directive in the source file ; LIST P=PIC18F2610 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2610 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' DAD5 EQU H'0005' DAD6 EQU H'0006' DAD7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f67j90.inc0000644000175000017500000015446711156521301013427 00000000000000 LIST ;========================================================================== ; MPASM PIC18F67J90 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F67J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F67J90 ; 2. LIST directive in the source file ; LIST P=PIC18F67J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F67J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PADCFG1 EQU H'0F54' CTMUICON EQU H'0F55' CTMUCONL EQU H'0F56' CTMUCONH EQU H'0F57' ALRMVALL EQU H'0F58' ALRMVALH EQU H'0F59' ALRMRPT EQU H'0F5A' ALRMCFG EQU H'0F5B' RTCVALL EQU H'0F5C' RTCVALH EQU H'0F5D' RTCCAL EQU H'0F5E' RTCCFG EQU H'0F5F' RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' ECCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' ECCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' TRISF EQU H'0F97' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PADCFG1 Bits ----------------------------------------------------- RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- LCDDATA6 Bits ----------------------------------------------------- S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' SEG32COM1 EQU H'0000' ;----- LCDDATA12 Bits ----------------------------------------------------- S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' SEG32COM2 EQU H'0000' ;----- LCDDATA18 Bits ----------------------------------------------------- S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' SEG00COM3 EQU H'0000' SEG01COM3 EQU H'0001' SEG02COM3 EQU H'0002' SEG03COM3 EQU H'0003' SEG04COM3 EQU H'0004' SEG05COM3 EQU H'0005' SEG06COM3 EQU H'0006' SEG07COM3 EQU H'0007' S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' SEG32COM3 EQU H'0000' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' TOCKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' CTED1 EQU H'0002' CTED2 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' CTPLS EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' CVREF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' TX2 EQU H'0001' RX2 EQU H'0002' RTCC EQU H'0004' VLCAP1 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' CCP1IE EQU H'0001' CCP2IE EQU H'0002' CTMUIE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' CCP1IF EQU H'0001' CCP2IF EQU H'0002' CTMUIF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' CCP1IP EQU H'0001' CCP2IP EQU H'0002' CTMUIP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SEGEN32 EQU H'0000' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- TRIGSEL EQU H'0007' PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM_RCON EQU H'0005' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- MODE13 EQU H'0002' CPEN EQU H'0006' CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- IOFS EQU H'0002' OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F6B' __BADRAM H'0F71' __BADRAM H'0F77' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FBA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled-Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Oscillator Selection bits: ; OSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; OSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; OSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; OSC = INTOSCPLLO INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 ; OSC = HS HS oscillator ; OSC = HSPLL HS oscillator, PLL enabled ; OSC = EC EC Oscillator with clock out on RA6 ; OSC = ECPLL EC Oscillator with PLL ; ; Secondary Clock Source T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = ON Timer1 oscillator configured for low-power operation ; LPT1OSC = OFF Timer1 oscillator configured for higher power operation ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Reference Clock Select bit: ; RTCSOSC = INTOSCREF RTCC uses INTOSC/INTRC as reference clock ; RTCSOSC = T1OSCREF RTCC uses T1OSC/T1CKI as reference clock ; ; CCP2 MUX: ; CCP2MX = ALTERNATE RE7 / RB3 ; CCP2MX = DEFAULT RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f505.inc0000644000175000017500000001014311156313161013140 00000000000000 LIST ; P16F505.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F505 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16F505 ; 2. LIST directive in the source file ; LIST P=16F505 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/09/03 Initial Release ;1.01 04/14/04 Update for EC osc mode ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F505 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' ;----- STATUS Bits -------------------------------------------------------- RBWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBWU EQU H'0007' NOT_RBPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FDF' _CP_ON EQU H'002F' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FF7' _LP_OSC EQU H'0FF8' _XT_OSC EQU H'0FF9' _HS_OSC EQU H'0FFA' _EC_RB4EN EQU H'0FFB' _IntRC_OSC_RB4EN EQU H'0FFC' _IntRC_OSC_CLKOUTEN EQU H'0FFD' _ExtRC_OSC_RB4EN EQU H'0FFE' _ExtRC_OSC_CLKOUTEN EQU H'0FFF' LIST gputils-0.13.7/header/p18f14k50.inc0000644000175000017500000013411111156521301013374 00000000000000 LIST ;========================================================================== ; MPASM PIC18F14K50 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F14K50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F14K50 ; 2. LIST directive in the source file ; LIST P=PIC18F14K50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F14K50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UEP0 EQU H'0F53' UEP1 EQU H'0F54' UEP2 EQU H'0F55' UEP3 EQU H'0F56' UEP4 EQU H'0F57' UEP5 EQU H'0F58' UEP6 EQU H'0F59' UEP7 EQU H'0F5A' UEIE EQU H'0F5B' UADDR EQU H'0F5C' UFRML EQU H'0F5D' UFRMH EQU H'0F5E' UEIR EQU H'0F5F' UIE EQU H'0F60' UCFG EQU H'0F61' UIR EQU H'0F62' USTAT EQU H'0F63' UCON EQU H'0F64' SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' REFCON0 EQU H'0FBA' VREFCON0 EQU H'0FBA' REFCON1 EQU H'0FBB' VREFCON1 EQU H'0FBB' REFCON2 EQU H'0FBC' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UPUEN EQU H'0004' UTEYE EQU H'0007' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' USBIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' USBIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' USBIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- REFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- REFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- REFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F65'-H'0F67' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F75' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; CPU System Clock Selection bit: ; CPUDIV = NOCLKDIV No CPU System Clock divide ; CPUDIV = CLKDIV2 CPU System Clock divided by 2 ; CPUDIV = CLKDIV3 CPU System Clock divided by 3 ; CPUDIV = CLKDIV4 CPU System Clock divided by 4 ; ; USB Clock Selection bit: ; USBDIV = OFF USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide ; USBDIV = ON USB clock comes from the OSC1/OSC2 divided by 2 ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 1kW boot block size ; BBSIZ = ON 2kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _CPUDIV_NOCLKDIV_1L EQU H'E7' ; No CPU System Clock divide _CPUDIV_CLKDIV2_1L EQU H'EF' ; CPU System Clock divided by 2 _CPUDIV_CLKDIV3_1L EQU H'F7' ; CPU System Clock divided by 3 _CPUDIV_CLKDIV4_1L EQU H'FF' ; CPU System Clock divided by 4 _USBDIV_OFF_1L EQU H'DF' ; USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide _USBDIV_ON_1L EQU H'FF' ; USB clock comes from the OSC1/OSC2 divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size _BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4480.inc0000644000175000017500000042037611156521301013242 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4480 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4480 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4480 ; 2. LIST directive in the source file ; LIST P=PIC18F4480 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4480 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' ECCP1CON EQU H'0FBA' ECCPR1 EQU H'0FBB' ECCPR1L EQU H'0FBB' ECCPR1H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREFA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' C1INB EQU H'0000' C1INA EQU H'0001' C2INB EQU H'0002' C2INA EQU H'0003' P1A EQU H'0004' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ECCP1 EQU H'0004' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- ECCP1IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- ECCP1IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- ECCP1IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- ECCP1M0 EQU H'0000' ECCP1M1 EQU H'0001' ECCP1M2 EQU H'0002' ECCP1M3 EQU H'0003' EDC1B0 EQU H'0004' EDC1B1 EQU H'0005' EPWM1M0 EQU H'0006' EPWM1M1 EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0CFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'EF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'FF' ; 2K words (4K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4431.inc0000644000175000017500000012637511156521301013240 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4431 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4431 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4431 ; 2. LIST directive in the source file ; LIST P=PIC18F4431 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4431 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- DFLTCON EQU H'0F60' CAP3CON EQU H'0F61' CAP2CON EQU H'0F62' CAP1CON EQU H'0F63' CAP3BUFL EQU H'0F64' MAXCNTL EQU H'0F64' CAP3BUFH EQU H'0F65' MAXCNTH EQU H'0F65' CAP2BUFL EQU H'0F66' POSCNTL EQU H'0F66' CAP2BUFH EQU H'0F67' POSCNTH EQU H'0F67' CAP1BUFL EQU H'0F68' VELRL EQU H'0F68' CAP1BUFH EQU H'0F69' VELRH EQU H'0F69' OVDCONS EQU H'0F6A' OVDCOND EQU H'0F6B' FLTCONFIG EQU H'0F6C' DTCON EQU H'0F6D' PWMCON1 EQU H'0F6E' PWMCON0 EQU H'0F6F' SEVTCMPH EQU H'0F70' SEVTCMPL EQU H'0F71' PDC3H EQU H'0F72' PDC3L EQU H'0F73' PDC2H EQU H'0F74' PDC2L EQU H'0F75' PDC1H EQU H'0F76' PDC1L EQU H'0F77' PDC0H EQU H'0F78' PDC0L EQU H'0F79' PTPERH EQU H'0F7A' PTPERL EQU H'0F7B' PTMRH EQU H'0F7C' PTMRL EQU H'0F7D' PTCON1 EQU H'0F7E' PTCON0 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' TMR5L EQU H'0F87' TMR5H EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' PR5L EQU H'0F90' PR5H EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' ADCHS EQU H'0F99' ADCON3 EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' BAUDCON EQU H'0FAA' BAUDCTL EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' QEICON EQU H'0FB6' T5CON EQU H'0FB7' ANSEL0 EQU H'0FB8' ANSEL1 EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- DFLTCON Bits ----------------------------------------------------- FLTCK0 EQU H'0000' FLTCK1 EQU H'0001' FLTCK2 EQU H'0002' FLT1EN EQU H'0003' FLT2EN EQU H'0004' FLT3EN EQU H'0005' FLT4EN EQU H'0006' ;----- CAP3CON Bits ----------------------------------------------------- CAP3M0 EQU H'0000' CAP3M1 EQU H'0001' CAP3M2 EQU H'0002' CAP3M3 EQU H'0003' CAP3TMR EQU H'0005' CAP3REN EQU H'0006' ;----- CAP2CON Bits ----------------------------------------------------- CAP2M0 EQU H'0000' CAP2M1 EQU H'0001' CAP2M2 EQU H'0002' CAP2M3 EQU H'0003' CAP2TMR EQU H'0005' CAP2REN EQU H'0006' ;----- CAP1CON Bits ----------------------------------------------------- CAP1M0 EQU H'0000' CAP1M1 EQU H'0001' CAP1M2 EQU H'0002' CAP1M3 EQU H'0003' CAP1TMR EQU H'0005' CAP1REN EQU H'0006' ;----- OVDCONS Bits ----------------------------------------------------- POUT0 EQU H'0000' POUT1 EQU H'0001' POUT2 EQU H'0002' POUT3 EQU H'0003' POUT4 EQU H'0004' POUT5 EQU H'0005' POUT6 EQU H'0006' POUT7 EQU H'0007' ;----- OVDCOND Bits ----------------------------------------------------- POVD0 EQU H'0000' POVD1 EQU H'0001' POVD2 EQU H'0002' POVD3 EQU H'0003' POVD4 EQU H'0004' POVD5 EQU H'0005' POVD6 EQU H'0006' POVD7 EQU H'0007' ;----- FLTCONFIG Bits ----------------------------------------------------- FLTAEN EQU H'0000' FLTAMOD EQU H'0001' FLTAS EQU H'0002' FLTCON EQU H'0003' FLTBEN EQU H'0004' FLTBMOD EQU H'0005' FLTBS EQU H'0006' ;----- DTCON Bits ----------------------------------------------------- DT0 EQU H'0000' DT1 EQU H'0001' DT2 EQU H'0002' DT3 EQU H'0003' DT4 EQU H'0004' DT5 EQU H'0005' DTPS0 EQU H'0006' DTPS1 EQU H'0007' DTA0 EQU H'0000' DTA1 EQU H'0001' DTA2 EQU H'0002' DTA3 EQU H'0003' DTA4 EQU H'0004' DTA5 EQU H'0005' DTAPS0 EQU H'0006' DTAPS1 EQU H'0007' ;----- PWMCON1 Bits ----------------------------------------------------- OSYNC EQU H'0000' UDIS EQU H'0001' SEVTDIR EQU H'0003' SEVOPS0 EQU H'0004' SEVOPS1 EQU H'0005' SEVOPS2 EQU H'0006' SEVOPS3 EQU H'0007' ;----- PWMCON0 Bits ----------------------------------------------------- PMOD0 EQU H'0000' PMOD1 EQU H'0001' PMOD2 EQU H'0002' PMOD3 EQU H'0003' PWMEN0 EQU H'0004' PWMEN1 EQU H'0005' PWMEN2 EQU H'0006' ;----- PTCON1 Bits ----------------------------------------------------- PTDIR EQU H'0006' PTEN EQU H'0007' ;----- PTCON0 Bits ----------------------------------------------------- PTMOD0 EQU H'0000' PTMOD1 EQU H'0001' PTCKPS0 EQU H'0002' PTCKPS1 EQU H'0003' PTOPS0 EQU H'0004' PTOPS1 EQU H'0005' PTOPS2 EQU H'0006' PTOPS3 EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' INT0 EQU H'0003' INT1 EQU H'0004' INT2 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' T0CKI EQU H'0003' SDA EQU H'0004' SCK EQU H'0005' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' NOT_FLTA EQU H'0001' NOT_FLTB EQU H'0002' T5CKI EQU H'0003' SDI EQU H'0004' SCL EQU H'0005' NOT_SS EQU H'0006' SDO EQU H'0007' FLTA EQU H'0001' FLTB EQU H'0002' SS EQU H'0006' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' NOT_MCLR EQU H'0003' MCLR EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- ADCHS Bits ----------------------------------------------------- GASEL0 EQU H'0000' GASEL1 EQU H'0001' GCSEL0 EQU H'0002' GCSEL1 EQU H'0003' GBSEL0 EQU H'0004' GBSEL1 EQU H'0005' GDSEL0 EQU H'0006' GDSEL1 EQU H'0007' SASEL0 EQU H'0000' SASEL1 EQU H'0001' SCSEL0 EQU H'0002' SCSEL1 EQU H'0003' SBSEL0 EQU H'0004' SBSEL1 EQU H'0005' SDSEL0 EQU H'0006' SDSEL1 EQU H'0007' ;----- ADCON3 Bits ----------------------------------------------------- SSRC0 EQU H'0000' SSRC1 EQU H'0001' SSRC2 EQU H'0002' SSRC3 EQU H'0003' SSRC4 EQU H'0004' ADRS0 EQU H'0006' ADRS1 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TBIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TBIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LVDIE EQU H'0002' EEIE EQU H'0004' OSFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LVDIF EQU H'0002' EEIF EQU H'0004' OSFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' LVDIP EQU H'0002' EEIP EQU H'0004' OSFIP EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR5IE EQU H'0000' IC1IE EQU H'0001' IC2QEIE EQU H'0002' IC3DRIE EQU H'0003' PTIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- TMR5IF EQU H'0000' IC1IF EQU H'0001' IC2QEIF EQU H'0002' IC3DRIF EQU H'0003' PTIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- TMR5IP EQU H'0000' IC1IP EQU H'0001' IC2QEIP EQU H'0002' IC3DRIP EQU H'0003' PTIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- QEICON Bits ----------------------------------------------------- PDEC0 EQU H'0000' PDEC1 EQU H'0001' QEIM0 EQU H'0002' QEIM1 EQU H'0003' QEIM2 EQU H'0004' UP_DOWN EQU H'0005' ; ERROR is a reserved word ; ERROR EQU H'0006' VELM EQU H'0007' UP EQU H'0005' DOWN EQU H'0005' NOT_DOWN EQU H'0005' NOT_VELM EQU H'0007' ;----- T5CON Bits ----------------------------------------------------- TMR5ON EQU H'0000' TMR5CS EQU H'0001' T5SYNC EQU H'0002' T5PS0 EQU H'0003' T5PS1 EQU H'0004' T5MOD EQU H'0005' RESEN EQU H'0006' T5SEN EQU H'0007' NOT_T5SYNC EQU H'0002' NOT_RESEN EQU H'0006' ;----- ANSEL0 Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSEL1 Bits ----------------------------------------------------- ANS8 EQU H'0000' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ACQT3 EQU H'0006' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- ADPNT0 EQU H'0000' ADPNT1 EQU H'0001' BFOVFL EQU H'0002' BFEMT EQU H'0003' FIFOEN EQU H'0004' VCFG0 EQU H'0006' VCFG1 EQU H'0007' FFOVFL EQU H'0002' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' ACMOD0 EQU H'0002' ACMOD1 EQU H'0003' ACSCH EQU H'0004' ACONV EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDT0 EQU H'0001' WDT1 EQU H'0002' WDT2 EQU H'0003' WDT3 EQU H'0004' WDT4 EQU H'0005' WDT5 EQU H'0006' WDT6 EQU H'0007' WDTW EQU H'0007' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F5F' __BADRAM H'0F85'-H'0F86' __BADRAM H'0F8E'-H'0F8F' __BADRAM H'0F97'-H'0F98' __BADRAM H'0F9C' __BADRAM H'0FB1'-H'0FB5' __BADRAM H'0FC5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC2 External RC, RA6 is CLKOUT ; OSC = EC EC, RA6 is CLKOUT ; OSC = ECIO EC, RA6 is I/O ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO External RC, RA6 is I/O ; OSC = IRCIO Internal RC, RA6 & RA7 are I/O ; OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O ; OSC = RC1 External RC, RA6 is CLKOUT ; OSC = RC External RC, RA6 is CLKOUT ; ; Fail-Safe Clock Monitor Enable: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal/External Switch-Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRTEN = ON Enabled ; PWRTEN = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDTEN = OFF Disabled ; WDTEN = ON Enabled ; ; Watchdog Timer Enable Window: ; WINEN = ON Enabled ; WINEN = OFF Disabled ; ; Watchdog Postscaler: ; WDPS = 1 1:1 ; WDPS = 2 1:2 ; WDPS = 4 1:4 ; WDPS = 8 1:8 ; WDPS = 16 1:16 ; WDPS = 32 1:32 ; WDPS = 64 1:64 ; WDPS = 128 1:128 ; WDPS = 256 1:256 ; WDPS = 512 1:512 ; WDPS = 1024 1:1024 ; WDPS = 2048 1:2048 ; WDPS = 4096 1:4096 ; WDPS = 8192 1:8192 ; WDPS = 16384 1:16384 ; WDPS = 32768 1:32768 ; ; Timer1 Oscillator MUX: ; T1OSCMX = OFF Active ; T1OSCMX = ON Inactive ; ; High-Side Transistors Polarity: ; HPOL = LOW Active low ; HPOL = HIGH Active high ; ; Low-Side Transistors Polarity: ; LPOL = LOW Active low ; LPOL = HIGH Active high ; ; PWM output pins Reset state control: ; PWMPIN = ON Enabled ; PWMPIN = OFF Disabled ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; External clock MUX bit: ; EXCLKMX = RD0 Multiplexed with RD0 ; EXCLKMX = RC3 Multiplexed with RC3 ; ; PWM4 MUX bit: ; PWM4MX = RD5 Multiplexed with RD5 ; PWM4MX = RB5 Multiplexed with RB5 ; ; SSP I/O MUX bit: ; SSPMX = RD1 SDO output is multiplexed with RD1 ; SSPMX = RC7 SD0 output is multiplexed with RC7 ; ; FLTA MUX bit: ; FLTAMX = RD4 Multiplexed with RD4 ; FLTAMX = RC1 Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC2_1H EQU H'F3' ; External RC, RA6 is CLKOUT _OSC_EC_1H EQU H'F4' ; EC, RA6 is CLKOUT _OSC_ECIO_1H EQU H'F5' ; EC, RA6 is I/O _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; External RC, RA6 is I/O _OSC_IRCIO_1H EQU H'F8' ; Internal RC, RA6 & RA7 are I/O _OSC_IRC_1H EQU H'F9' ; Internal RC, RA6 is CLKOUT, RA7 is I/O _OSC_RC1_1H EQU H'FB' ; External RC, RA6 is CLKOUT _OSC_RC_1H EQU H'FF' ; External RC, RA6 is CLKOUT _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; Enabled _PWRTEN_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'FD' ; Disabled _BOREN_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; Disabled _WDTEN_ON_2H EQU H'FF' ; Enabled _WINEN_ON_2H EQU H'DF' ; Enabled _WINEN_OFF_2H EQU H'FF' ; Disabled _WDPS_1_2H EQU H'E1' ; 1:1 _WDPS_2_2H EQU H'E3' ; 1:2 _WDPS_4_2H EQU H'E5' ; 1:4 _WDPS_8_2H EQU H'E7' ; 1:8 _WDPS_16_2H EQU H'E9' ; 1:16 _WDPS_32_2H EQU H'EB' ; 1:32 _WDPS_64_2H EQU H'ED' ; 1:64 _WDPS_128_2H EQU H'EF' ; 1:128 _WDPS_256_2H EQU H'F1' ; 1:256 _WDPS_512_2H EQU H'F3' ; 1:512 _WDPS_1024_2H EQU H'F5' ; 1:1024 _WDPS_2048_2H EQU H'F7' ; 1:2048 _WDPS_4096_2H EQU H'F9' ; 1:4096 _WDPS_8192_2H EQU H'FB' ; 1:8192 _WDPS_16384_2H EQU H'FD' ; 1:16384 _WDPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _T1OSCMX_OFF_3L EQU H'DF' ; Active _T1OSCMX_ON_3L EQU H'FF' ; Inactive _HPOL_LOW_3L EQU H'EF' ; Active low _HPOL_HIGH_3L EQU H'FF' ; Active high _LPOL_LOW_3L EQU H'F7' ; Active low _LPOL_HIGH_3L EQU H'FF' ; Active high _PWMPIN_ON_3L EQU H'FB' ; Enabled _PWMPIN_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _EXCLKMX_RD0_3H EQU H'EF' ; Multiplexed with RD0 _EXCLKMX_RC3_3H EQU H'FF' ; Multiplexed with RC3 _PWM4MX_RD5_3H EQU H'F7' ; Multiplexed with RD5 _PWM4MX_RB5_3H EQU H'FF' ; Multiplexed with RB5 _SSPMX_RD1_3H EQU H'FB' ; SDO output is multiplexed with RD1 _SSPMX_RC7_3H EQU H'FF' ; SD0 output is multiplexed with RC7 _FLTAMX_RD4_3H EQU H'FE' ; Multiplexed with RD4 _FLTAMX_RC1_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f913.inc0000644000175000017500000006276411156521301013160 00000000000000 LIST ; P16F913.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F913 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F913 ; 2. LIST directive in the source file ; LIST P=PIC16F913 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 06/11/04 Initial Release ;1.01 06/18/04 Corrected typo in 'bad ram' section ;1.02 08/16/04 Added EECON2 ;1.03 05/20/05 Removed EECON2 from badram ;1.04 10/05/05 Correct names of bits in ANSEL, Add EEADRH and EEADRL bit ;1.05 10/30/06 Added Alias of go_done, go ; definitions ;1.06 02/26/07 Added Alias of EEADR and EEDATA ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F913 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' WPU EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' CMCON1 EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON0 EQU H'009C' VRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LCDCON EQU H'0107' LCDPS EQU H'0108' LVDCON EQU H'0109' EEDATL EQU H'010C' EEDATA EQU H'010C' EEADRL EQU H'010D' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' LCDDATA0 EQU H'0110' LCDDATA1 EQU H'0111' LCDDATA3 EQU H'0113' LCDDATA4 EQU H'0114' LCDDATA6 EQU H'0116' LCDDATA7 EQU H'0117' LCDDATA9 EQU H'0119' LCDDATA10 EQU H'011A' LCDSE0 EQU H'011C' LCDSE1 EQU H'011D' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' LCDIF EQU H'0004' LVDIF EQU H'0002' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0006' VCFG0 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' GO EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' LCDIE EQU H'0004' LVDIE EQU H'0002' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS4 EQU H'0004' AN4 EQU H'0004' ; Backward compatibility only ANS3 EQU H'0003' AN3 EQU H'0003' ; Backward compatibility only ANS2 EQU H'0002' AN2 EQU H'0002' ; Backward compatibility only ANS1 EQU H'0001' AN1 EQU H'0001' ; Backward compatibility only ANS0 EQU H'0000' AN0 EQU H'0000' ; Backward compatibility only ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' WPU6 EQU H'0006' WPU5 EQU H'0005' WPU4 EQU H'0004' WPU3 EQU H'0003' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' IOC6 EQU H'0006' IOC5 EQU H'0005' IOC4 EQU H'0004' ;----- CMCON1 Bits -------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON0 Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- VRCON Bits -------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' VLCDEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- WFT EQU H'0007' BIASMD EQU H'0006' LCDA EQU H'0005' WA EQU H'0004' LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- LCDDATA0 Bits ------------------------------------------------------- SEG7COM0 EQU H'0007' SEG6COM0 EQU H'0006' SEG5COM0 EQU H'0005' SEG4COM0 EQU H'0004' SEG3COM0 EQU H'0003' SEG2COM0 EQU H'0002' SEG1COM0 EQU H'0001' SEG0COM0 EQU H'0000' S7C0 EQU H'0007' S6C0 EQU H'0006' S5C0 EQU H'0005' S4C0 EQU H'0004' S3C0 EQU H'0003' S2C0 EQU H'0002' S1C0 EQU H'0001' S0C0 EQU H'0000' ;----- LCDDATA1 Bits ------------------------------------------------------- SEG15COM0 EQU H'0007' SEG14COM0 EQU H'0006' SEG13COM0 EQU H'0005' SEG12COM0 EQU H'0004' SEG11COM0 EQU H'0003' SEG10COM0 EQU H'0002' SEG9COM0 EQU H'0001' SEG8COM0 EQU H'0000' S15C0 EQU H'0007' S14C0 EQU H'0006' S13C0 EQU H'0005' S12C0 EQU H'0004' S11C0 EQU H'0003' S10C0 EQU H'0002' S9C0 EQU H'0001' S8C0 EQU H'0000' ;----- LCDDATA3 Bits ------------------------------------------------------- SEG7COM1 EQU H'0007' SEG6COM1 EQU H'0006' SEG5COM1 EQU H'0005' SEG4COM1 EQU H'0004' SEG3COM1 EQU H'0003' SEG2COM1 EQU H'0002' SEG1COM1 EQU H'0001' SEG0COM1 EQU H'0000' S7C1 EQU H'0007' S6C1 EQU H'0006' S5C1 EQU H'0005' S4C1 EQU H'0004' S3C1 EQU H'0003' S2C1 EQU H'0002' S1C1 EQU H'0001' S0C1 EQU H'0000' ;----- LCDDATA4 Bits ------------------------------------------------------- SEG15COM1 EQU H'0007' SEG14COM1 EQU H'0006' SEG13COM1 EQU H'0005' SEG12COM1 EQU H'0004' SEG11COM1 EQU H'0003' SEG10COM1 EQU H'0002' SEG9COM1 EQU H'0001' SEG8COM1 EQU H'0000' S15C1 EQU H'0007' S14C1 EQU H'0006' S13C1 EQU H'0005' S12C1 EQU H'0004' S11C1 EQU H'0003' S10C1 EQU H'0002' S9C1 EQU H'0001' S8C1 EQU H'0000' ;----- LCDDATA6 Bits ------------------------------------------------------- SEG7COM2 EQU H'0007' SEG6COM2 EQU H'0006' SEG5COM2 EQU H'0005' SEG4COM2 EQU H'0004' SEG3COM2 EQU H'0003' SEG2COM2 EQU H'0002' SEG1COM2 EQU H'0001' SEG0COM2 EQU H'0000' S7C2 EQU H'0007' S6C2 EQU H'0006' S5C2 EQU H'0005' S4C2 EQU H'0004' S3C2 EQU H'0003' S2C2 EQU H'0002' S1C2 EQU H'0001' S0C2 EQU H'0000' ;----- LCDDATA7 Bits ------------------------------------------------------- SEG15COM2 EQU H'0007' SEG14COM2 EQU H'0006' SEG13COM2 EQU H'0005' SEG12COM2 EQU H'0004' SEG11COM2 EQU H'0003' SEG10COM2 EQU H'0002' SEG9COM2 EQU H'0001' SEG8COM2 EQU H'0000' S15C2 EQU H'0007' S14C2 EQU H'0006' S13C2 EQU H'0005' S12C2 EQU H'0004' S11C2 EQU H'0003' S10C2 EQU H'0002' S9C2 EQU H'0001' S8C2 EQU H'0000' ;----- LCDDATA9 Bits ------------------------------------------------------- SEG7COM3 EQU H'0007' SEG6COM3 EQU H'0006' SEG5COM3 EQU H'0005' SEG4COM3 EQU H'0004' SEG3COM3 EQU H'0003' SEG2COM3 EQU H'0002' SEG1COM3 EQU H'0001' SEG0COM3 EQU H'0000' S7C3 EQU H'0007' S6C3 EQU H'0006' S5C3 EQU H'0005' S4C3 EQU H'0004' S3C3 EQU H'0003' S2C3 EQU H'0002' S1C3 EQU H'0001' S0C3 EQU H'0000' ;----- LCDDATA10 Bits ------------------------------------------------------- SEG15COM3 EQU H'0007' SEG14COM3 EQU H'0006' SEG13COM3 EQU H'0005' SEG12COM3 EQU H'0004' SEG11COM3 EQU H'0003' SEG10COM3 EQU H'0002' SEG9COM3 EQU H'0001' SEG8COM3 EQU H'0000' S15C3 EQU H'0007' S14C3 EQU H'0006' S13C3 EQU H'0005' S12C3 EQU H'0004' S11C3 EQU H'0003' S10C3 EQU H'0002' S9C3 EQU H'0001' S8C3 EQU H'0000' ;----- LCDSE0 Bits -------------------------------------------------------- SE7 EQU H'0007' SE6 EQU H'0006' SE5 EQU H'0005' SE4 EQU H'0004' SE3 EQU H'0003' SE2 EQU H'0002' SE1 EQU H'0001' SE0 EQU H'0000' SEGEN7 EQU H'0007' SEGEN6 EQU H'0006' SEGEN5 EQU H'0005' SEGEN4 EQU H'0004' SEGEN3 EQU H'0003' SEGEN2 EQU H'0002' SEGEN1 EQU H'0001' SEGEN0 EQU H'0000' ;----- LCDSE1 Bits -------------------------------------------------------- SE15 EQU H'0007' SE14 EQU H'0006' SE13 EQU H'0005' SE12 EQU H'0004' SE11 EQU H'0003' SE10 EQU H'0002' SE9 EQU H'0001' SE8 EQU H'0000' SEGEN15 EQU H'0007' SEGEN14 EQU H'0006' SEGEN13 EQU H'0005' SEGEN12 EQU H'0004' SEGEN11 EQU H'0003' SEGEN10 EQU H'0002' SEGEN9 EQU H'0001' SEGEN8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' EEWR EQU H'0001' RD EQU H'0000' EERD EQU H'0000' ;----- EEADRH Bits -------------------------------------------------------- EEADRH4 EQU H'0004' EEADRH3 EQU H'0003' EEADRH2 EQU H'0002' EEADRH1 EQU H'0001' EEADRH0 EQU H'0000' ;----- EEADRL Bits -------------------------------------------------------- EEADRL7 EQU H'0007' EEADRL6 EQU H'0006' EEADRL5 EQU H'0005' EEADRL4 EQU H'0004' EEADRL3 EQU H'0003' EEADRL2 EQU H'0002' EEADRL1 EQU H'0001' EEADRL0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08', H'1B'-H'1D' __BADRAM H'88', H'9A'-H'9B' __BADRAM H'112', H'115', H'118', H'11B',H'11E'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG EQU H'2007' ;Configuration Byte 1 Options _DEBUG_ON EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f242.inc0000644000175000017500000007006411156313161013150 00000000000000 LIST ; P18F242.INC Standard Header File, Version 1.4 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F242 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F242 ; 2. LIST directive in the source file ; LIST P=PIC18F242 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;1.0 03/23/01 Modified C242 for F242 tr ;1.1 08/01/01 Added EECON1 bits, corrected code protect config bit inserts ;1.2 09/17/01 Corrected MAXRAM,BADRAM tr ;1.3 10/23/01 Corrected CONFIG bits/registers tr/pas ;1.4 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F242 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' ;RESERVED_0F96 EQU H'0F96' ;RESERVED_0F95 EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' ;RESERVED_0F8D EQU H'0F8D' ;RESERVED_0F8C EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' ;RESERVED_0F84 EQU H'0F84' ;RESERVED_0F83 EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR2 Bits ---------------------------------------------------------- EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'300'-H'F7F' __BADRAM H'F85'-H'F88' __BADRAM H'F8E'-H'F91' __BADRAM H'F97'-H'F9C' __BADRAM H'FA3'-H'FA5' __BADRAM H'FAA' __BADRAM H'FB4'-H'FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p16f722.inc0000644000175000017500000005010211156521301013135 00000000000000 LIST ; P16F722.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F722 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F722 ; 2. LIST directive in the source file ; LIST P=PIC16F722 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/09/06 Initial template ;0.02 10/25/07 Fix BADRAM definitions ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F722 MESSG "Processor-header file mismatch. Verify selected processor." #define __16F722 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'08' __BADRAM H'88' __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'C0'-H'EF' __BADRAM H'105'-H'107' __BADRAM H'110'-H'16F' __BADRAM H'187'-H'189', H'18D'-H'18F' __BADRAM H'190'-H'1EF' LIST gputils-0.13.7/header/p18lf24j50.inc0000644000175000017500000015623311156521302013562 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF24J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF24J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF24J50 ; 2. LIST directive in the source file ; LIST P=PIC18LF24J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF24J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F5F' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p10f204.inc0000644000175000017500000001124711156313161013134 00000000000000 LIST ; P10F204.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC10f204 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P10F204 ; 2. LIST directive in the source file ; LIST P=10F204 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/14/04 Initial Release ;1.01 07/07/04 Add bad ram ;1.02 10/05/05 Add IntRC_OSC comment ;1.03 01/13/06 Added GPIO bit descriptions ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __10F204 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' CMCON0 EQU H'0007' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' CWUF EQU H'0006' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' FOSC4 EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' ;----- CMCON0 Bits -------------------------------------------------------- CMPOUT EQU H'0007' NOT_COUTEN EQU H'0006' POL EQU H'0005' NOT_CMPT0CS EQU H'0004' CMPON EQU H'0003' CNREF EQU H'0002' CPREF EQU H'0001' NOT_CWU EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' __BADRAM H'08'-H'0F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _IntRC_OSC EQU H'0FFF';IntRC_OSC is the only option. ;It is here for backwards compatibility ;only. LIST gputils-0.13.7/header/p18f6490.inc0000644000175000017500000016620411156521301013242 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6490 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6490 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6490 ; 2. LIST directive in the source file ; LIST P=PIC18F6490 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6490 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2620.inc0000644000175000017500000010510011156521301013215 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2620 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2620 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2620 ; 2. LIST directive in the source file ; LIST P=PIC18F2620 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2620 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' DEBUG EQU H'0FD4' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB6'-H'0FB7' __BADRAM H'0FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO6 EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO6 RC-OSC2 as RA6 ; OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7 ; OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7 ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Osc. Switch Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON SBOREN Enabled ; BOREN = NOSLP Enabled except Sleep, SBOREN Disabled ; BOREN = SBORDIS Enabled, SBOREN Disabled ; ; Brown-out Voltage: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; T1 Oscillator Enable: ; LPT1OSC = OFF Disabled ; LPT1OSC = ON Enabled ; ; PORTB A/D Enable: ; PBADEN = OFF PORTB<4:0> digital on Reset ; PBADEN = ON PORTB<4:0> analog on Reset ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; XINST Enable: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO6_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO6_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_INTIO67_1H EQU H'F8' ; INTRC-OSC2 as RA6, OSC1 as RA7 _OSC_INTIO7_1H EQU H'F9' ; INTRC-OSC2 as Clock Out, OSC1 as RA7 _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'F9' ; Disabled _BOREN_ON_2L EQU H'FB' ; SBOREN Enabled _BOREN_NOSLP_2L EQU H'FD' ; Enabled except Sleep, SBOREN Disabled _BOREN_SBORDIS_2L EQU H'FF' ; Enabled, SBOREN Disabled _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _LPT1OSC_OFF_3H EQU H'FB' ; Disabled _LPT1OSC_ON_3H EQU H'FF' ; Enabled _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> digital on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> analog on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Disabled _XINST_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p17c42a.inc0000644000175000017500000002515711156313161013226 00000000000000 LIST ; P17C42A.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C42A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C42A ; 2. LIST directive in the source file ; LIST P=PIC17C42A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.04 03/14/97 Corrected configuration bits value for protected ; microcontroller mode ;1.03 07/15/96 Corrected MAXRAM ;1.02 06/28/96 Corrected MAXRAM, BADRAM, and registers in upper banks ;1.01 04/10/96 Added _WDT_OFF value, PSx values ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C42A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCREG EQU H'0014' TXSTA EQU H'0015' TXREG EQU H'0016' SPBRG EQU H'0017' PRODL EQU H'0018' PRODH EQU H'0019' DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' PIE EQU H'0117' TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' NOT_PD EQU H'0002' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIE Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' RCIE EQU H'0000' ;----- PIR Bits ----------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' RCIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' T0CKI EQU H'0001' INT EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' T0PS2 EQU H'0003' PS2 EQU H'0003' T0PS1 EQU H'0002' PS1 EQU H'0002' T0PS0 EQU H'0001' PS0 EQU H'0001' ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3FF' __BADRAM H'118'-H'11F', H'218'-H'2FF', H'318'-H'3FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p18f2523.inc0000644000175000017500000012204111156521301013222 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2523 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2523 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2523 ; 2. LIST directive in the source file ; LIST P=PIC18F2523 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2523 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' C1OUT_PORTA EQU H'0004' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' HLVDIN EQU H'0005' LVDIN EQU H'0005' C2OUT_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTB CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTB_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4550.inc0000644000175000017500000015437611156521301013244 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4550 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4550 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4550 ; 2. LIST directive in the source file ; LIST P=PIC18F4550 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4550 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SPPDATA EQU H'0F62' SPPCFG EQU H'0F63' SPPEPS EQU H'0F64' SPPCON EQU H'0F65' UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SPPCFG Bits ----------------------------------------------------- WS0 EQU H'0000' WS1 EQU H'0001' WS2 EQU H'0002' WS3 EQU H'0003' CLK1EN EQU H'0004' CSEN EQU H'0005' CLKCFG0 EQU H'0006' CLKCFG1 EQU H'0007' ;----- SPPEPS Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' SPPBUSY EQU H'0004' WRSPP EQU H'0006' RDSPP EQU H'0007' ;----- SPPCON Bits ----------------------------------------------------- SPPEN EQU H'0000' SPPOWN EQU H'0001' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SPP0 EQU H'0000' SPP1 EQU H'0001' SPP2 EQU H'0002' SPP3 EQU H'0003' SPP4 EQU H'0004' SPP5 EQU H'0005' SPP6 EQU H'0006' SPP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RDPU EQU H'0007' CK1SPP EQU H'0000' CK2SPP EQU H'0001' OESPP EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SPPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SPPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SPPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPRT = OFF ICPORT disabled ; ICPRT = ON ICPORT enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _ICPRT_OFF_4L EQU H'DF' ; ICPORT disabled _ICPRT_ON_4L EQU H'FF' ; ICPORT enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f1936.inc0000644000175000017500000011625411156521301013240 00000000000000 LIST ;========================================================================== ; MPASM PIC16F1936 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16F1936 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16F1936 ; 2. LIST directive in the source file ; LIST P=PIC16F1936 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F1936 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'000F' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'008F' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'010F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E'-H'0190' __BADRAM H'0197'-H'0198' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0330'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079A'-H'079F' __BADRAM H'07A2' __BADRAM H'07A5' __BADRAM H'07A8' __BADRAM H'07AB'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _nPWRTE_OFF EQU H'FFDF' ; PWRT enabled _nPWRTE_ON EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _nDEBUG_ON EQU H'EFFF' ; Background debugger is enabled _nDEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p18f63j90.inc0000644000175000017500000015023611156521301013411 00000000000000 LIST ;========================================================================== ; MPASM PIC18F63J90 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F63J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F63J90 ; 2. LIST directive in the source file ; LIST P=PIC18F63J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F63J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' SEG32COM1 EQU H'0000' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' SEG32COM2 EQU H'0000' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' SEG32COM3 EQU H'0000' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP1 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SEGEN32 EQU H'0000' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' SEG32COM0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' MODE13 EQU H'0002' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' CPEN EQU H'0006' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F6B' __BADRAM H'0F71' __BADRAM H'0F77' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FBA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p17cr42.inc0000644000175000017500000002507511156313161013246 00000000000000 LIST ; P17CR42.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17CR42 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17CR42 ; 2. LIST directive in the source file ; LIST P=PIC17CR42 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 03/14/97 Corrected configuration bits value for protected ; microcontroller mode ;1.02 07/15/96 Corrected MAXRAM ;1.01 06/28/96 Corrected MAXRAM, BADRAM, and registers in upper banks ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17CR42 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCREG EQU H'0014' TXSTA EQU H'0015' TXREG EQU H'0016' SPBRG EQU H'0017' PRODL EQU H'0018' PRODH EQU H'0019' DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' PIE EQU H'0117' TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' NOT_PD EQU H'0002' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIE Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' RCIE EQU H'0000' ;----- PIR Bits ----------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' RCIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' T0CKI EQU H'0001' INT EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' T0PS2 EQU H'0003' PS2 EQU H'0003' T0PS1 EQU H'0002' PS1 EQU H'0002' T0PS0 EQU H'0001' PS0 EQU H'0001' ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3FF' __BADRAM H'118'-H'11F', H'218'-H'2FF', H'318'-H'3FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p18f2320.inc0000644000175000017500000010450511156313161013225 00000000000000 LIST ; P18F2320.INC Standard Header File, Version 0.1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2320 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F2320 ; 2. LIST directive in the source file ; LIST P=PIC18F2320 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 07 Dec 2001 Initial revision BD ;0.11 22 Mar 2002 ECCP registers revised BD ;0.12 16 Apr 2002 Configuration bit MCLRE moved from 2L to 3H BD ;0.13 22 Apr 2002 T0CON changed back to T0CON BD ;0.14 09 May 2002 Removed PWM1CON and ECCPAS registers BD ; ECCP1CON changed to CCP1CON ;0.15 5 May 2002 _OSO_ON_1H changed to _IESO_ON_1H BD ; _MCLRE_ON_2L moved/changed to _MCLRE_ON_3H ; ;0.16 24 May 2002 OSCCON bit name corrected BD ; OSCCON register name above bit equates fixed ; T1CON added ; _MCLRE_ON_3H moved to correct register and renamed (again) ;0.17 30 May 2002 _PBAD_DIG_3H had wrong bit cleared BD ;0.18 13 Jun 2002 LVDCON,IRVST added to LVDCON BD ;0.19 09/26/02 Include both names SWDTE and SWDTEN pas ; ;0.20 27 Sep 2002 Add IOFS bit name to OSCCON register BD ; Add ECIO, RCIO, INTIO1, INTIO2 bits to Config Reg 1H ; Add DEBUG bits to Config Reg 4L ;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD ; ;0.22 1 Oct 2003 Bit names changed BD ; LVVn to LVDLn IVRST to IRVST ; FSCMEN to FSCM ; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1, ; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0, ; CVREF,CVRSS ; Removed redundant bit names ; RCIO6 use RCIO INTIO7 use INTIO1 ; ECIO6 use ECIO INTIO67 use INTIO2 ; BKBUG use DEBUG SWDTE use SWDTEN ; T0IE use TMR0IE INT0E use INT0IE ; T0IF use TMR0IF INT0F use INT0IE ; BGST use IRVST T1INSYNC use T1SYNC ; TXD8 use TX9D T3INSYNC use T3SYNC ; TX8_9 use TX9 NOT_TX8 use TX9 ; RC9 use RX9 NOT_RC8 use RX9 ; RC8_9 use RX9 RCD8 use RX9D ; INT2P use INT2IP INT1P use INT1IP ; INT2E use INT2IE INT1E use INT1IE ; INT2F use INT2IF INT1F use INT1IF ; Added equates for PIC16 Compatability ; ADRES, INTF, INTE, CCPnX, CCPnY ; General clean-up (removed some comments) ; Corrected RAM space definitions ; ;0.23 30 Mar 2004 References to RE3 removed, badram adjusted BD ;======================================================================= ; ; Verify Processor ; ;======================================================================= IFNDEF __18F2320 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define ADRES ADRESH ; PIC16 SFR substitution #define INTE INT0IE ; PIC16 bit substitution #define INTF INT0IF ; PIC16 bit substitution #define CCP1X DC1B1 ; PIC16 bit substitution #define CCP1Y DC1B0 ; PIC16 bit substitution #define CCP2X DC2B1 ; PIC16 bit substitution #define CCP2Y DC2B0 ; PIC16 bit substitution #define SCS SCS0 ; PIC18 bit substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ; reserved EQU H'0FB9' ; reserved EQU H'0FB8' ; reserved EQU H'0FB7' ; reserved EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ; reserved EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ; reserved EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' ; reserved EQU H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' OSCTUNE EQU H'0F9B' ; reserved EQU H'0F9A' ; reserved EQU H'0F99' ; reserved EQU H'0F98' ; reserved EQU H'0F97' ; reserved EQU H'0F96' ; reserved EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ; reserved EQU H'0F91' ; reserved EQU H'0F90' ; reserved EQU H'0F8F' ; reserved EQU H'0F8E' ; reserved EQU H'0F8D' ; reserved EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved EQU H'0F88' ; reserved EQU H'0F87' ; reserved EQU H'0F86' ; reserved EQU H'0F85' ; reserved EQU H'0F84' ; reserved EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' INT0IE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' FLTS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ---------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' D_A EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' R_W EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits ---------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ---------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ----------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ---------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- CVRCON Bits ----------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits ------------------------------------------------------ C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------ CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------ SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- OSCFIP EQU H'0007' CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ------------------------------------------------------- OSCFIF EQU H'0007' CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ------------------------------------------------------- OSCFIE EQU H'0007' CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ------------------------------------------------------- ; reserved EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- ; reserved EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- ; reserved EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- OSCTUNE Bits ---------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 RA7 EQU 7 OSC1 EQU 7 CLKI EQU 7 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 AN12 EQU 0 RB1 EQU 1 INT1 EQU 1 AN10 EQU 1 RB2 EQU 2 INT2 EQU 2 AN8 EQU 2 RB3 EQU 3 CCP2A EQU 3 AN9 EQU 3 RB4 EQU 4 AN11 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ----------------------------------------------------------- RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 P1A EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'200'-H'F7F' __BADRAM H'F83'-H'F88',H'F8C'-H'F91',H'F95'-H'F9A',H'F9C' __BADRAM H'FA3'-H'FA5',H'FAA',H'FB0',H'FB6'-H'FB9' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = EC External Clock on OSC1, OSC2 as FOSC/4 ; OSC = ECIO External Clock on OSC1, OSC2 as RA6 ; OSC = HSPLL HS + PLL ; OSC = RCIO External RC on OSC1, OSC2 as RA6 ; OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6 ; OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4 ; OSC = RC External RC on OSC1, OSC2 as FOSC/4 ; ; Fail-Safe Clock Monitor: ; FSCM = OFF Fail-Safe Clock Monitor disabled ; FSCM = ON Fail-Safe Clock Monitor enabled ; ; Internal External Switch Over mode: ; IESO = OFF Internal External Switch Over mode disabled ; IESO = ON Internal External Switch Over mode enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; PORTB A/D Enable: ; PBAD = DIG Digital ; PBAD = ANA Analog ; ; CCP2 Pin Function: ; CCP2MX = B3 RB3 ; CCP2MX = OFF RB3 ; CCP2MX = C1 RC1 ; CCP2MX = ON RC1 ; ; Stack Full/Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To use the Configuration Bits, place the following lines in your ; source code in the following format, and change the configuration ; value to the desired setting (such as WDT_OFF to WDT_ON). These are ; currently commented out here. Each __CONFIG line should have the ; preceding semicolon removed when pasted into your source code. ; __CONFIG _CONFIG1H, _IESO_OFF_1H & _FSCM_OFF_1H & _RC_OSC_1H ; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_20_2L ; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H ; __CONFIG _CONFIG3H, _MCLRE_ON_3H & _PBAD_DIG_3H & _CCP2MX_C1_3H ; __CONFIG _CONFIG4L, _BKBUG_OFF_4L & _LVP_OFF_4L & _STVR_OFF_4L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 1H Options _IESO_ON_1H EQU H'FF' ; Internal External oscillator Switch Over mode enabled _IESO_OFF_1H EQU H'7F' ; Internal External oscillator Switch Over mode disabled _FSCM_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _FSCM_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as FOSC/4 _RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6 _LP_OSC_1H EQU H'F0' ; LP Oscillator _XT_OSC_1H EQU H'F1' ; XT Oscillator _HS_OSC_1H EQU H'F2' ; HS Oscillator _HSPLL_OSC_1H EQU H'F6' ; HS + PLL _EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as FOSC/4 _ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6 _INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4 _INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _PWRT_OFF_2L EQU H'FF' ; Power-up Timer disabled _PWRT_ON_2L EQU H'FE' ; Power-up Timer enabled ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled _WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio _WDTPS_16K_2H EQU H'FD' ; 1:16,384 _WDTPS_8K_2H EQU H'FB' ; 1: 8,192 _WDTPS_4K_2H EQU H'F9' ; 1: 4,096 _WDTPS_2K_2H EQU H'F7' ; 1: 2,048 _WDTPS_1K_2H EQU H'F5' ; 1: 1,024 _WDTPS_512_2H EQU H'F3' ; 1: 512 _WDTPS_256_2H EQU H'F1' ; 1: 256 _WDTPS_128_2H EQU H'EF' ; 1: 128 _WDTPS_64_2H EQU H'ED' ; 1: 64 _WDTPS_32_2H EQU H'EB' ; 1: 32 _WDTPS_16_2H EQU H'E9' ; 1: 16 _WDTPS_8_2H EQU H'E7' ; 1: 8 _WDTPS_4_2H EQU H'E5' ; 1: 4 _WDTPS_2_2H EQU H'E3' ; 1: 2 _WDTPS_1_2H EQU H'E1' ; 1: 1 ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'FF' ; MCLR enabled _MCLRE_OFF_3H EQU H'7F' ; MCLR disabled _PBAD_ANA_3H EQU H'FF' ; PORTB<4:0> pins reset as analog pins _PBAD_DIG_3H EQU H'FD' ; PORTB<4:0> pins reset as digital pins _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin function on RC1 _CCP2MX_OFF_3H EQU H'FE' ; CCP2 pin function on RB3 _CCP2MX_C1_3H EQU H'FF' ; CCP2 pin function on RC1 (alt defn) _CCP2MX_B3_3H EQU H'FE' ; CCP2 pin function on RB3 (alt defn) ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; BacKground deBUGger enabled _DEBUG_OFF_4L EQU H'FF' ; BacKground deBUGger disabled _LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled _LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP0_ON_5L EQU H'FE' ; Block 0 protected _CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable _CP1_ON_5L EQU H'FD' ; Block 1 protected _CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable _CP2_ON_5L EQU H'FB' ; Block 2 protected _CP2_OFF_5L EQU H'FF' ; Block 2 readable/ may be writable _CP3_ON_5L EQU H'F7' ; Block 3 protected _CP3_OFF_5L EQU H'FF' ; Block 3 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'BF' ; Boot Block protected _CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'7F' ; Data EE memory protected _CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT0_ON_6L EQU H'FE' ; Block 0 write protected _WRT0_OFF_6L EQU H'FF' ; Block 0 writable _WRT1_ON_6L EQU H'FD' ; Block 1 write protected _WRT1_OFF_6L EQU H'FF' ; Block 1 writable _WRT2_ON_6L EQU H'FB' ; Block 2 write protected _WRT2_OFF_6L EQU H'FF' ; Block 2 writable _WRT3_ON_6L EQU H'F7' ; Block 3 write protected _WRT3_OFF_6L EQU H'FF' ; Block 3 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'DF' ; Config registers write protected _WRTC_OFF_6H EQU H'FF' ; Config registers writable _WRTB_ON_6H EQU H'BF' ; Boot block write protected _WRTB_OFF_6H EQU H'FF' ; Boot block writable _WRTD_ON_6H EQU H'7F' ; Data EE write protected _WRTD_OFF_6H EQU H'FF' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR0_ON_7L EQU H'FE' ; Block 0 protected _EBTR0_OFF_7L EQU H'FF' ; Block 0 readable _EBTR1_ON_7L EQU H'FD' ; Block 1 protected _EBTR1_OFF_7L EQU H'FF' ; Block 1 readable _EBTR2_ON_7L EQU H'FB' ; Block 2 protected _EBTR2_OFF_7L EQU H'FF' ; Block 2 readable _EBTR3_ON_7L EQU H'F7' ; Block 3 protected _EBTR3_OFF_7L EQU H'FF' ; Block 3 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'BF' ; Boot block read protected _EBTRB_OFF_7H EQU H'FF' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p16f818.inc0000644000175000017500000002725011156313161013156 00000000000000 LIST ; P16F818.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F818 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F818 ; 2. LIST directive in the source file ; LIST P=PIC16F818 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 06/15/02 Initial Release ;1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F818 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' IOFS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'18'-H'1D' __BADRAM H'87'-H'89', H'91', H'95'-H'9D' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP1_RB2 EQU H'3FFF' _CCP1_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_ENABLE_OFF EQU H'3FFF' _WRT_ENABLE_512 EQU H'3DFF' _WRT_ENABLE_1024 EQU H'3BFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' LIST gputils-0.13.7/header/p12c509.inc0000644000175000017500000000742111156313161013142 00000000000000 LIST ; P12C509.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12C509 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12C509 ; 2. LIST directive in the source file ; LIST P=12C509 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.02 05/12/97 Correct STATUS and OPTION register bits ;1.01 08/21/96 Removed VCLMP fuse, corrected oscillators, fixed MAXRAM ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12C509 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL0 EQU H'0004' CAL1 EQU H'0005' CAL2 EQU H'0006' CAL3 EQU H'0007' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f6393.inc0000644000175000017500000016620411156521301013244 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6393 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6393 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6393 ; 2. LIST directive in the source file ; LIST P=PIC18F6393 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6393 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f1230.inc0000644000175000017500000010624011156521301013217 00000000000000 LIST ;========================================================================== ; MPASM PIC18F1230 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F1230 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F1230 ; 2. LIST directive in the source file ; LIST P=PIC18F1230 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F1230 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' OVDCONS EQU H'0F82' OVDCOND EQU H'0F83' DTCON EQU H'0F84' PWMCON1 EQU H'0F85' PWMCON0 EQU H'0F86' SEVTCMPH EQU H'0F87' SEVTCMPL EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' FLTCONFIG EQU H'0F8B' PDC2H EQU H'0F8C' PDC2L EQU H'0F8D' PDC1H EQU H'0F8E' PDC1L EQU H'0F8F' PDC0H EQU H'0F90' PDC0L EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' PTPERH EQU H'0F95' PTPERL EQU H'0F96' PTMRH EQU H'0F97' PTMRL EQU H'0F98' PTCON1 EQU H'0F99' PTCON0 EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' TX EQU H'0002' RX EQU H'0003' AN2 EQU H'0004' MCLR EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' CK EQU H'0002' ; DT is a reserved word ; DT EQU H'0003' T0CKI EQU H'0004' CLKO EQU H'0006' CLKI EQU H'0007' KBI0 EQU H'0000' KBI1 EQU H'0001' VREFP EQU H'0004' T1OSO_PORTA EQU H'0006' T1OSI_PORTA EQU H'0007' CMP0 EQU H'0000' NOT_MCLR EQU H'0005' AN3 EQU H'0006' T1CKI_PORTA EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' PWM0 EQU H'0000' PWM1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' PWM2 EQU H'0004' PWM3 EQU H'0005' PWM4 EQU H'0006' PWM5 EQU H'0007' KBI2 EQU H'0002' KBI3 EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' CMP2 EQU H'0002' CMP1 EQU H'0003' T1OSO_PORTB EQU H'0002' T1OSI_PORTB EQU H'0003' T1CKI_PORTB EQU H'0002' ;----- OVDCONS Bits ----------------------------------------------------- POUT0 EQU H'0000' POUT1 EQU H'0001' POUT2 EQU H'0002' POUT3 EQU H'0003' POUT4 EQU H'0004' POUT5 EQU H'0005' ;----- OVDCOND Bits ----------------------------------------------------- POVD0 EQU H'0000' POVD1 EQU H'0001' POVD2 EQU H'0002' POVD3 EQU H'0003' POVD4 EQU H'0004' POVD5 EQU H'0005' ;----- DTCON Bits ----------------------------------------------------- DT0 EQU H'0000' DT1 EQU H'0001' DT2 EQU H'0002' DT3 EQU H'0003' DT4 EQU H'0004' DT5 EQU H'0005' DTPS0 EQU H'0006' DTPS1 EQU H'0007' ;----- PWMCON1 Bits ----------------------------------------------------- OSYNC EQU H'0000' UDIS EQU H'0001' SEVTDIR EQU H'0003' SEVOPS0 EQU H'0004' SEVOPS1 EQU H'0005' SEVOPS2 EQU H'0006' SEVOPS3 EQU H'0007' ;----- PWMCON0 Bits ----------------------------------------------------- PMOD0 EQU H'0000' PMOD1 EQU H'0001' PMOD2 EQU H'0002' PWMEN0 EQU H'0004' PWMEN1 EQU H'0005' PWMEN2 EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- FLTCONFIG Bits ----------------------------------------------------- FLTAEN EQU H'0000' FLTAMOD EQU H'0001' FLTAS EQU H'0002' BRFEN EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- PTCON1 Bits ----------------------------------------------------- PTDIR EQU H'0006' PTEN EQU H'0007' ;----- PTCON0 Bits ----------------------------------------------------- PTMOD0 EQU H'0000' PTMOD1 EQU H'0001' PTCKPS0 EQU H'0002' PTCKPS1 EQU H'0003' PTOPS0 EQU H'0004' PTOPS1 EQU H'0005' PTOPS2 EQU H'0006' PTOPS3 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' CMP0IE EQU H'0001' CMP1IE EQU H'0002' CMP2IE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' CMP0IF EQU H'0001' CMP1IF EQU H'0002' CMP2IF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' CMP0IP EQU H'0001' CMP1IP EQU H'0002' CMP2IP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- LVDIE EQU H'0002' EEIE EQU H'0004' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- LVDIF EQU H'0002' EEIF EQU H'0004' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- LVDIP EQU H'0002' EEIP EQU H'0004' OSCFIP EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- PTIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- PTIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- PTIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- CMCON Bits ----------------------------------------------------- CMEN0 EQU H'0000' CMEN1 EQU H'0001' CMEN2 EQU H'0002' C0OUT EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' SEVTEN EQU H'0007' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0006' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0100'-H'0F7F' __BADRAM H'0F94' __BADRAM H'0F9C' __BADRAM H'0FAA' __BADRAM H'0FB1'-H'0FB3' __BADRAM H'0FB6'-H'0FB7' __BADRAM H'0FB9'-H'0FBF' __BADRAM H'0FC5'-H'0FCC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit): ; HPOL = LOW PWM1, PWM3 and PWM5 are active-low ; HPOL = HIGH PWM1, PWM3 and PWM5 are active-high (default) ; ; Low-Side Transistors Polarity bit (Even PWM Output Polarity Control bit): ; LPOL = LOW PWM0, PWM2 and PWM4 are active-low ; LPOL = HIGH PWM0, PWM2 and PWM4 are active-high (default) ; ; PWM Output Pins Reset State Control bit: ; PWMPIN = ON PWM outputs drive active states upon Reset ; PWMPIN = OFF PWM outputs disabled upon Reset ; ; FLTA MUX bit: ; FLTAMX = RA7 FLTA input is muxed onto RA7 ; FLTAMX = RA5 FLTA input is muxed onto RA5 ; ; T1OSO/T1CKI MUX bit: ; T1OSCMX = LOW T1OSO/T1CKI pin resides on RB2 ; T1OSCMX = HIGH T1OSO/T1CKI pin resides on RA6 ; ; Master Clear Enable bit: ; MCLRE = OFF RA5 input pin enabled, MCLR pin disabled ; MCLRE = ON MCLR pin enabled, RA5 input pin disabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Words (512 Bytes) ; BBSIZ = BB512 512 Words (1024 Bytes) ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0 (00400-007FF): ; CP0 = ON Block 0 is code-protected ; CP0 = OFF Block 0 is not code-protected ; ; Code Protection bit Block 1 (00800-00FFF): ; CP1 = ON Block 1 is code-protected ; CP1 = OFF Block 1 is not code-protected ; ; Code Protection bit (Boot Block Memory Area): ; CPB = ON Boot Block is code-protected ; CPB = OFF Boot Block is not code-protected ; ; Code Protection bit (Data EEPROM): ; CPD = ON Data EEPROM is code-protected ; CPD = OFF Data EEPROM is not code-protected ; ; Write Protection bit Block 0 (00400-007FF): ; WRT0 = ON Block 0 is write-protected ; WRT0 = OFF Block 0 is not write-protected ; ; Write Protection bit Block 1 (00800-00FFF): ; WRT1 = ON Block 1 is write-protected ; WRT1 = OFF Block 1 is not write-protected ; ; Write Protection bit (Boot Block Memory Area): ; WRTB = ON Boot Block is write-protected ; WRTB = OFF Boot Block is not write-protected ; ; Write Protection bit (Configuration Registers): ; WRTC = ON Configuration registers are write-protected ; WRTC = OFF Configuration registers are not write-protected ; ; Write Protection bit (Data EEPROM): ; WRTD = ON Data EEPROM is write-protected ; WRTD = OFF Data EEPROM is not write-protected ; ; Table Read Protection bit Block 0 (00400-007FF): ; EBTR0 = ON Block 0 is protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 is not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1 (00800-00FFF): ; EBTR1 = ON Block 1 is protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 is not protected from table reads executed in other blocks ; ; Table Read Protection bit (Boot Block Memory Area): ; EBTRB = ON Boot Block is protected from table reads executed in other blocks ; EBTRB = OFF Boot Block is not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP Oscillator _OSC_XT_1H EQU H'F1' ; XT Oscillator _OSC_HS_1H EQU H'F2' ; HS Oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO2_1H EQU H'F8' ; Internal oscillator, port function on RA6 and RA7 _OSC_INTIO1_1H EQU H'F9' ; Internal oscillator, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'F3' ; Maximum setting _BORV_1_2L EQU H'F7' ; _BORV_2_2L EQU H'FB' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _HPOL_LOW_3L EQU H'F7' ; PWM1, PWM3 and PWM5 are active-low _HPOL_HIGH_3L EQU H'FF' ; PWM1, PWM3 and PWM5 are active-high (default) _LPOL_LOW_3L EQU H'FB' ; PWM0, PWM2 and PWM4 are active-low _LPOL_HIGH_3L EQU H'FF' ; PWM0, PWM2 and PWM4 are active-high (default) _PWMPIN_ON_3L EQU H'FD' ; PWM outputs drive active states upon Reset _PWMPIN_OFF_3L EQU H'FF' ; PWM outputs disabled upon Reset ;----- CONFIG3H Options -------------------------------------------------- _FLTAMX_RA7_3H EQU H'FE' ; FLTA input is muxed onto RA7 _FLTAMX_RA5_3H EQU H'FF' ; FLTA input is muxed onto RA5 _T1OSCMX_LOW_3H EQU H'F7' ; T1OSO/T1CKI pin resides on RB2 _T1OSCMX_HIGH_3H EQU H'FF' ; T1OSO/T1CKI pin resides on RA6 _MCLRE_OFF_3H EQU H'7F' ; RA5 input pin enabled, MCLR pin disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RA5 input pin disabled ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Reset on stack overflow/underflow disabled _STVREN_ON_4L EQU H'FF' ; Reset on stack overflow/underflow enabled _BBSIZ_BB256_4L EQU H'CF' ; 256 Words (512 Bytes) _BBSIZ_BB512_4L EQU H'FF' ; 512 Words (1024 Bytes) _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 is code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 is not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 is code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 is not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block is code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block is not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM is code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM is not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 is write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 is not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 is write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 is not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block is write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block is not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers are write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers are not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM is write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM is not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 is protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 is not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 is protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 is not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block is protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block is not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18lf14k22.inc0000644000175000017500000012026011156521301013547 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF14K22 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF14K22 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF14K22 ; 2. LIST directive in the source file ; LIST P=PIC18LF14K22 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF14K22 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' APFCON EQU H'0F75' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' VREFCON0 EQU H'0FBA' VREFCON1 EQU H'0FBB' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- C1SEL EQU H'0000' T0CKISEL EQU H'0001' INT2SEL EQU H'0002' SRQSEL EQU H'0003' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA0 EQU H'0000' WPUA1 EQU H'0001' WPUA2 EQU H'0002' WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA2 EQU H'0002' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F3F' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F74' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 1kW boot block size ; BBSIZ = ON 2kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size _BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c62b.inc0000644000175000017500000002070211156313161013217 00000000000000 LIST ; P16C62B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C62B microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C62B ; 2. LIST directive in the source file ; LIST P=PIC16C62B ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/01/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C62B MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1F' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/rf509af.inc0000644000175000017500000000773311156313161013321 00000000000000 LIST ; RF509AF.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the rfPIC12C509AF microcontroller. These names are taken to ; match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /p=RF509AF ; 2. LIST directive in the source file ; LIST P=RF509AF ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 09/18/01 Shortened processor name to RF509AF for COD format (pas) ;1.00 08/31/01 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __RF509AF MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' OSCFST EQU H'0003' CAL1 EQU H'0003' OSCSLW EQU H'0002' CAL0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18c242.inc0000644000175000017500000006003111156313161013136 00000000000000 LIST ; P18C242.INC Standard Header File, Version 0.12 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C242 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C242 ; 2. LIST directive in the source file ; LIST P=PIC18C242 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.02 25 Nov 98 Preliminary Release drj ;0.03 07 Dec 98 Added compatibility #defines drj ;0.04 10 Dec 98 Added bits defs and new config jt ;0.05 14 Dec 98 Incorporated ko comments dj ;0.06 12 Jan 99 Changed config bits dj ;0.07 13 Jan 99 Changed BODEN to BOREN dj ;0.08 1 Apr 99 Added TRIS aliases ;0.09 17 Jun 99 Clean up ;0.10 23 Sep 99 Compatibility with PIC18Cxx2 Data Sheet (Rev B) ; and Added I/O Pin definitions mp ;0.11 29 Jun 00 Added support for Device ID/Revision & ID locations rr ;0.12 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C242 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' ;RESERVED_0FA7 EQU H'0FA7' ;RESERVED_0FA6 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' ;RESERVED_0F96 EQU H'0F96' ;RESERVED_0F95 EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' ;RESERVED_0F8D EQU H'0F8D' ;RESERVED_0F8C EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' ;RESERVED_0F84 EQU H'0F84' ;RESERVED_0F83 EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' LWRT EQU H'0006' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- IPR2 Bits ---------------------------------------------------------- BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM H'1FF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Code Protect: ; CP = ON Enabled ; CP = OFF Disabled ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 0 300000h ; CONFIG1H = Configuration Byte 1 300001h ; CONFIG2L = Configuration Byte 3 300002h ; CONFIG2H = Configuration Byte 4 300003h ; CONFIG3L = Configuration Byte 5 300004h ; CONFIG3H = Configuration Byte 6 300005h ; CONFIG4L = Configuration Byte 7 300006h ; CONFIG4H = Configuration Byte 8 300007h ; ;========================================================================== ; ;Configuration Byte 0 Options _CP_ON_0 EQU H'00' ; Code Protect enable _CP_OFF_0 EQU H'FF' ;Configuration Byte 1 Options _OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1 EQU H'FF' _LP_OSC_1 EQU H'F8' ; Oscillator type _XT_OSC_1 EQU H'F9' _HS_OSC_1 EQU H'FA' _RC_OSC_1 EQU H'FB' _EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1 EQU H'FE' ; HS PLL _RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options _BOR_ON_2 EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2 EQU H'FD' _PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable _PWRT_ON_2 EQU H'FE' _BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2 EQU H'FB' ; 2.7v _BORV_42_2 EQU H'F7' ; 4.2v _BORV_45_2 EQU H'F3' ; 4.5v ;Configuration Byte 3 Options _WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_3 EQU H'FE' _WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_3 EQU H'FD' _WDTPS_32_3 EQU H'FB' _WDTPS_16_3 EQU H'F9' _WDTPS_8_3 EQU H'F7' _WDTPS_4_3 EQU H'F5' _WDTPS_2_3 EQU H'F3' _WDTPS_1_3 EQU H'F1' ;Configuration Byte 5 Options _CCP2MX_ON_5 EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_5 EQU H'FE' ;Configuration Byte 6 Options _STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_6 EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG0 EQU H'300000' _CONFIG1 EQU H'300001' _CONFIG2 EQU H'300002' _CONFIG3 EQU H'300003' _CONFIG4 EQU H'300004' _CONFIG5 EQU H'300005' _CONFIG6 EQU H'300006' _CONFIG7 EQU H'300007' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 0 ; __CONFIG _CONFIG0, _CP_OFF_0 ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1 ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2 ;Program Configuration Register 3 ; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3 ;Program Configuration Register 5 ;__CONFIG _CONFIG5, _CCP2MX_ON_5 ;Program Configuration Register 6 ; __CONFIG _CONFIG6, _STVR_ON_6 ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16f631.inc0000644000175000017500000003462011156521301013143 00000000000000 LIST ; P16F631.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F631 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F631 ; 2. LIST directive in the source file ; LIST P=PIC16F631 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/28/05 Original ;1.01 11/08/05 Removed unimplemented bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F631 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' WDTCON EQU H'0097' EEDAT EQU H'010C' EEDATA EQU H'010C' EEADR EQU H'010D' WPUB EQU H'0115' IOCB EQU H'0116' VRCON EQU H'0118' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' ANSEL EQU H'011E' EECON1 EQU H'018C' EECON2 EQU H'018D' SRCON EQU H'019E' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RABIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RABIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION Bits -------------------------------------------------------- NOT_RABPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TRISB7 EQU H'0007' TRISB6 EQU H'0006' TRISB5 EQU H'0005' TRISB4 EQU H'0004' ;----- TRISC Bits -------------------------------------------------------- TRISC7 EQU H'0007' TRISC6 EQU H'0006' TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' POR EQU H'0001' NOT_POR EQU H'0001' BOR EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' ;----- IOCB Bits --------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'11'-H'3F' __BADRAM H'88'-H'89', H'91'-H'94', H'98'-H'EF' __BADRAM H'108'-H'109', H'10E'-H'114', H'117', H'11C'-H'11D', H'11F'-H'16F' __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p12hv609.inc0000644000175000017500000002776311156521301013346 00000000000000 LIST ; P12HV609.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; Based on P12F609.INC ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12HV609 microcontroller. These names are taken to ; match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12HV609 ; 2. LIST directive in the source file ; LIST P=PIC12HV609 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 07/10/06 Original ;1.01 12/04/06 Added WPU, BOR and IOC aliases ;1.02 12/06/06 IOCA, WPUA aliases added ;1.03 01/15/06 Added GPIO & TRISIO bits, and PORTA alias ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12HV609 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PORTA EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' VRCON EQU H'0019' CMCON0 EQU H'001A' CMCON1 EQU H'001C' OPTION_REG EQU H'0081' TRISIO EQU H'0085' TRISA EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits ----------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- PORTA Bits ---------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- C1IF EQU H'0003' CMIF EQU H'0003' TMR1IF EQU H'0000' T1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' CMVREN EQU H'0007' VRR EQU H'0005' FVREN EQU H'0004' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C1ON EQU H'0007' CMON EQU H'0007' C1OUT EQU H'0006' COUT EQU H'0006' C1OE EQU H'0005' CMOE EQU H'0005' C1POL EQU H'0004' CMPOL EQU H'0004' C1R EQU H'0002' CMR EQU H'0002' C1CH0 EQU H'0000' CMCH EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1ACS EQU H'0004' C1HYS EQU H'0003' CMHYS EQU H'0003' T1GSS EQU H'0001' C1SYNC EQU H'0000' CMSYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISIO Bits -------------------------------------------------------- TRISIO5 EQU H'0005' TRISIO4 EQU H'0004' TRISIO3 EQU H'0003' TRISIO2 EQU H'0002' TRISIO1 EQU H'0001' TRISIO0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- C1IE EQU H'0003' CMIE EQU H'0003' TMR1IE EQU H'0000' T1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- WPU Bits ---------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- WPUA Bits ---------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits ---------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS3 EQU H'0003' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06' -H'09', H'0D', H'11' -H'18', H'1B', H'1D'-H'1F', H'20' -H'3F' __BADRAM H'86' -H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'9E', H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOD_ON EQU H'3FFF' _BOR_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOR_NSLEEP EQU H'3EFF' _BOD_OFF EQU H'3CFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f84j11.inc0000644000175000017500000013061711156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F84J11 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F84J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F84J11 ; 2. LIST directive in the source file ; LIST P=PIC18F84J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F84J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' TX2 EQU H'0001' RX2 EQU H'0002' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F6B'-H'0F7D' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB6'-H'0FBF' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode, 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode, 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode, 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 3FF8h ; CONFIG1H 3FF9h ; CONFIG2L 3FFAh ; CONFIG2H 3FFBh ; CONFIG3L 3FFCh ; CONFIG3H 3FFDh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'3FF8' _CONFIG1H EQU H'3FF9' _CONFIG2L EQU H'3FFA' _CONFIG2H EQU H'3FFB' _CONFIG3L EQU H'3FFC' _CONFIG3H EQU H'3FFD' ;----- CONFIG1L Options -------------------------------------------------- _DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled _STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled _WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit) _WDTEN_ON_1L EQU H'FF' ; WDT enabled ;----- CONFIG1H Options -------------------------------------------------- _CP0_ON_1H EQU H'FB' ; Program memory is code-protected _CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected ;----- CONFIG2L Options -------------------------------------------------- _IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled _FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled _FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00 _FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 _FOSC_HS_2L EQU H'FC' ; HS oscillator _FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control _FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2 _FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2 ;----- CONFIG2H Options -------------------------------------------------- _WDTPS_1_2H EQU H'F0' ; 1:1 _WDTPS_2_2H EQU H'F1' ; 1:2 _WDTPS_4_2H EQU H'F2' ; 1:4 _WDTPS_8_2H EQU H'F3' ; 1:8 _WDTPS_16_2H EQU H'F4' ; 1:16 _WDTPS_32_2H EQU H'F5' ; 1:32 _WDTPS_64_2H EQU H'F6' ; 1:64 _WDTPS_128_2H EQU H'F7' ; 1:128 _WDTPS_256_2H EQU H'F8' ; 1:256 _WDTPS_512_2H EQU H'F9' ; 1:512 _WDTPS_1024_2H EQU H'FA' ; 1:1024 _WDTPS_2048_2H EQU H'FB' ; 1:2048 _WDTPS_4096_2H EQU H'FC' ; 1:4096 _WDTPS_8192_2H EQU H'FD' ; 1:8192 _WDTPS_16384_2H EQU H'FE' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _WAIT_ON_3L EQU H'7F' ; Wait states for operations on external memory bus enabled _WAIT_OFF_3L EQU H'FF' ; Wait states for operations on external memory bus disabled _BW_8_3L EQU H'BF' ; 8-bit external bus mode _BW_16_3L EQU H'FF' ; 16-bit external bus mode _MODE_XM20_3L EQU H'CF' ; Extended Microcontroller mode, 20-bit Address mode _MODE_XM16_3L EQU H'DF' ; Extended Microcontroller mode, 16-bit Address mode _MODE_XM12_3L EQU H'EF' ; Extended Microcontroller mode, 12-bit Address mode _MODE_MM_3L EQU H'FF' ; Microcontroller mode - External bus disabled _EASHFT_OFF_3L EQU H'F7' ; Address shifting disabled, address on external bus reflects the PC value _EASHFT_ON_3L EQU H'FF' ; Address shifting enabled, address on external bus is offset to start at 000000h ;----- CONFIG3H Options -------------------------------------------------- _CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode _CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1 _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p17c752.inc0000644000175000017500000004504411156313161013152 00000000000000 LIST ; P17C752.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C752 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C752 ; 2. LIST directive in the source file ; LIST P=PIC17C752 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/01/98 Initial Release ;1.01 05/13/98 Replaced original 17C752 with what was once called 17C752A ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C752 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' BANK4 EQU H'0004' BANK5 EQU H'0005' BANK6 EQU H'0006' BANK7 EQU H'0007' GPR_BANK0 EQU H'0000' GPR_BANK1 EQU H'0008' GPR_BANK2 EQU H'0010' GPR_BANK3 EQU H'0018' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' ;----- Bank 0 ------------------------------------------------------------- PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCSTA1 EQU H'0013' RCREG EQU H'0014' ; Backward compatibility only RCREG1 EQU H'0014' TXSTA EQU H'0015' ; Backward compatibility only TXSTA1 EQU H'0015' TXREG EQU H'0016' ; Backward compatibility only TXREG1 EQU H'0016' SPBRG EQU H'0017' ; Backward compatibility only SPBRG1 EQU H'0017' ;----- Bank 1 ------------------------------------------------------------- DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' ; Backward compatibility only PIR1 EQU H'0116' PIE EQU H'0117' ; Backward compatibility only PIE1 EQU H'0117' ;----- Bank 2 ------------------------------------------------------------- TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' ;----- Bank 3 ------------------------------------------------------------- PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- Bank 4 ------------------------------------------------------------- PIR2 EQU H'0410' PIE2 EQU H'0411' RCSTA2 EQU H'0413' RCREG2 EQU H'0414' TXSTA2 EQU H'0415' TXREG2 EQU H'0416' SPBRG2 EQU H'0417' ;----- Bank 5 ------------------------------------------------------------- DDRF EQU H'0510' PORTF EQU H'0511' DDRG EQU H'0512' PORTG EQU H'0513' ADCON0 EQU H'0514' ADCON1 EQU H'0515' ADRESL EQU H'0516' ADRESH EQU H'0517' ;----- Bank 6 ------------------------------------------------------------- SSPADD EQU H'0610' SSPCON1 EQU H'0611' SSPCON2 EQU H'0612' SSPSTAT EQU H'0613' SSPBUF EQU H'0614' ;----- Bank 7 ------------------------------------------------------------- PW3DCL EQU H'0710' PW3DCH EQU H'0711' CA3L EQU H'0712' CA3H EQU H'0713' CA4L EQU H'0714' CA4H EQU H'0715' TCON3 EQU H'0716' ;----- Unbanked ----------------------------------------------------------- PRODL EQU H'0018' PL EQU H'0018' ; Backward compatibility only PRODH EQU H'0019' PH EQU H'0019' ; Backward compatibility only ;----- Special Function Register Bit Definitions -------------------------- ; ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' ; Backward compatibility only TX1IF EQU H'0001' RCIF EQU H'0000' ; Backward compatibility only RC1IF EQU H'0000' ;----- PIE1 Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' ; Backward compatibility only TX1IE EQU H'0001' RCIE EQU H'0000' ; Backward compatibility only RC1IE EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' ;----- RCSTA1 and 2 Bits -------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' ; Backward compatibility only T0PS2 EQU H'0003' PS2 EQU H'0003' ; Backward compatibility only T0PS1 EQU H'0002' PS1 EQU H'0002' ; Backward compatibility only T0PS0 EQU H'0001' PS0 EQU H'0001' ; Backward compatibility only ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- SSPIF EQU H'0007' BCLIF EQU H'0006' ADIF EQU H'0005' CA4IF EQU H'0003' CA3IF EQU H'0002' TX2IF EQU H'0001' RC2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- SSPIE EQU H'0007' BCLIE EQU H'0006' ADIE EQU H'0005' CA4IE EQU H'0003' CA3IE EQU H'0002' TX2IE EQU H'0001' RC2IE EQU H'0000' ;----- TXSTA1 and 2 Bits -------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0007' CHS2 EQU H'0006' CHS1 EQU H'0005' CHS0 EQU H'0004' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' ADFM EQU H'0005' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- SSPCON1 Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' AKSTAT EQU H'0006' ACKDT EQU H'0005' AKDT EQU H'0005' ACKEN EQU H'0004' AKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' NOT_A EQU H'0005' D_A EQU H'0005' P EQU H'0004' S EQU H'0003' R EQU H'0002' NOT_W EQU H'0002' R_W EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TCON3 Bits --------------------------------------------------------- CA4OVF EQU H'0006' CA3OVF EQU H'0005' CA4ED1 EQU H'0004' CA4ED0 EQU H'0003' CA3ED1 EQU H'0002' CA3ED0 EQU H'0001' PWM3ON EQU H'0000' ;----- PW2DCL Bit --------------------------------------------------------- TM2PW2 EQU H'0005' ;----- PW3DCL Bit --------------------------------------------------------- TM2PW3 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7FF' __BADRAM H'118'-H'11F', H'218'-H'21F', H'318'-H'31F' __BADRAM H'412', H'418'-H'4FF' __BADRAM H'518'-H'5FF' __BADRAM H'615'-H'6FF' __BADRAM H'717'-H'7FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _BODEN_OFF EQU H'BFFF' _BODEN_ON EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _WDT_0 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p16c924.inc0000644000175000017500000003016311156313161013146 00000000000000 LIST ; P16C924.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C924 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C924 ; 2. LIST directive in the source file ; LIST P=PIC16C924 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 09/13/01 Added the SSPSTAT bits CKE and SMP ;1.02 04/23/00 Added LCD controller bits ;1.01 05/12/97 Corrected ports F and G addresses ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C924 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADCON1 EQU H'009F' PORTF EQU H'0107' PORTG EQU H'0108' LCDSE EQU H'010D' LCDPS EQU H'010E' LCDCON EQU H'010F' LCDD00 EQU H'0110' LCDD01 EQU H'0111' LCDD02 EQU H'0112' LCDD03 EQU H'0113' LCDD04 EQU H'0114' LCDD05 EQU H'0115' LCDD06 EQU H'0116' LCDD07 EQU H'0117' LCDD08 EQU H'0118' LCDD09 EQU H'0119' LCDD10 EQU H'011A' LCDD11 EQU H'011B' LCDD12 EQU H'011C' LCDD13 EQU H'011D' LCDD14 EQU H'011E' LCDD15 EQU H'011F' TRISF EQU H'0187' TRISG EQU H'0188' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- LCDIF EQU H'0007' ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- LCDIE EQU H'0007' ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- LCDSE Bits --------------------------------------------------------- SE29 EQU H'0007' SE27 EQU H'0006' SE20 EQU H'0005' SE16 EQU H'0004' SE12 EQU H'0003' SE9 EQU H'0002' SE5 EQU H'0001' SE0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' VGEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'0D', H'18'-H'1D' __BADRAM H'8D', H'8F'-H'91', H'95'-H'9E' __BADRAM H'105', H'109', H'10C', H'120'-H'16F' __BADRAM H'185', H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p12f609.inc0000644000175000017500000002772711156521301013156 00000000000000 LIST ; P12F609.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F609 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12F609 ; 2. LIST directive in the source file ; LIST P=PIC12F609 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 07/10/06 Original ;1.01 12/04/06 Added WPU, BOR and IOC aliases ;1.02 12/06/06 IOCA, WPUA aliases added ;1.03 01/15/06 Added GPIO & TRISIO bits, and PORTA alias ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F609 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PORTA EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' VRCON EQU H'0019' CMCON0 EQU H'001A' CMCON1 EQU H'001C' OPTION_REG EQU H'0081' TRISIO EQU H'0085' TRISA EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits ----------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- PORTA Bits ---------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- C1IF EQU H'0003' CMIF EQU H'0003' TMR1IF EQU H'0000' T1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' CMVREN EQU H'0007' VRR EQU H'0005' FVREN EQU H'0004' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C1ON EQU H'0007' CMON EQU H'0007' C1OUT EQU H'0006' COUT EQU H'0006' C1OE EQU H'0005' CMOE EQU H'0005' C1POL EQU H'0004' CMPOL EQU H'0004' C1R EQU H'0002' CMR EQU H'0002' C1CH0 EQU H'0000' CMCH EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1ACS EQU H'0004' C1HYS EQU H'0003' CMHYS EQU H'0003' T1GSS EQU H'0001' C1SYNC EQU H'0000' CMSYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISIO Bits -------------------------------------------------------- TRISIO5 EQU H'0005' TRISIO4 EQU H'0004' TRISIO3 EQU H'0003' TRISIO2 EQU H'0002' TRISIO1 EQU H'0001' TRISIO0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- C1IE EQU H'0003' CMIE EQU H'0003' TMR1IE EQU H'0000' T1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- WPU Bits ---------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- WPUA Bits ---------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits ---------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS3 EQU H'0003' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06' -H'09', H'0D', H'11' -H'18', H'1B', H'1D'-H'1F', H'20' -H'3F' __BADRAM H'86' -H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'9E', H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOD_ON EQU H'3FFF' _BOR_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOR_NSLEEP EQU H'3EFF' _BOD_OFF EQU H'3CFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16f882.inc0000755000175000017500000005637411156521301013170 00000000000000 LIST ; P16F882.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F882 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F882 ; 2. LIST directive in the source file ; LIST P=PIC16F882 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ; ;1.00 11/28/06 Original ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F882 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' MSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' VRCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' PWM1CON EQU H'009B' ECCPAS EQU H'009C' PSTRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' CM1CON0 EQU H'0107' CM2CON0 EQU H'0108' CM2CON1 EQU H'0109' EEDATA EQU H'010C' EEDAT EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' SRCON EQU H'0185' BAUDCTL EQU H'0187' ANSEL EQU H'0188' ANSELH EQU H'0189' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' BCLIF EQU H'0003' ULPWUIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GIV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' CCP1X EQU H'0005' ; Backward compatibility only DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' ; Backward compatibility only DC2B1 EQU H'0005' CCP2Y EQU H'0004' ; Backward compatibility only DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' BCLIE EQU H'0003' ULPWUIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- IOCB Bits ---------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' C1RSEL EQU H'0005' C2RSEL EQU H'0004' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' FVREN EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS13 EQU H'0005' ANS12 EQU H'0004' ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08' __BADRAM H'88', H'C0'-H'EF' __BADRAM H'110'-H'16F' __BADRAM H'18E'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word1 ------------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'2FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word2 ------------------------------------------------ ; Code protection for the PIC16C882 is different than for other PIC16F88X devices. ; The CP_ON and CP_OFF switches operate as expected. ; WRT_256 protects the first 256 words of memmory. ; WRT_1FOURTH protects the lower half of program memory. The upper half is open. ; WRT_HALF protects all program memory. ;========================================================================== _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First half memmory write protected _WRT_HALF EQU H'39FF' ; All memmory write protected _BOR21V EQU H'3EFF' _BOR40V EQU H'3FFF' LIST gputils-0.13.7/header/p18f4455.inc0000644000175000017500000015217311156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4455 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4455 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4455 ; 2. LIST directive in the source file ; LIST P=PIC18F4455 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4455 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SPPDATA EQU H'0F62' SPPCFG EQU H'0F63' SPPEPS EQU H'0F64' SPPCON EQU H'0F65' UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SPPCFG Bits ----------------------------------------------------- WS0 EQU H'0000' WS1 EQU H'0001' WS2 EQU H'0002' WS3 EQU H'0003' CLK1EN EQU H'0004' CSEN EQU H'0005' CLKCFG0 EQU H'0006' CLKCFG1 EQU H'0007' ;----- SPPEPS Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' SPPBUSY EQU H'0004' WRSPP EQU H'0006' RDSPP EQU H'0007' ;----- SPPCON Bits ----------------------------------------------------- SPPEN EQU H'0000' SPPOWN EQU H'0001' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SPP0 EQU H'0000' SPP1 EQU H'0001' SPP2 EQU H'0002' SPP3 EQU H'0003' SPP4 EQU H'0004' SPP5 EQU H'0005' SPP6 EQU H'0006' SPP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RDPU EQU H'0007' CK1SPP EQU H'0000' CK2SPP EQU H'0001' OESPP EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SPPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SPPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SPPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPRT = OFF ICPORT disabled ; ICPRT = ON ICPORT enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _ICPRT_OFF_4L EQU H'DF' ; ICPORT disabled _ICPRT_ON_4L EQU H'FF' ; ICPORT enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f26k20.inc0000644000175000017500000013221611156521302013401 00000000000000 LIST ;========================================================================== ; MPASM PIC18F26K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F26K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F26K20 ; 2. LIST directive in the source file ; LIST P=PIC18F26K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F26K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' P1C EQU H'0001' P1B EQU H'0002' P1D EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f8525.inc0000644000175000017500000015075111156521301013243 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8525 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8525 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8525 ; 2. LIST directive in the source file ; LIST P=PIC18F8525 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8525 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ECCP2DEL EQU H'0F67' PWM2CON EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' PWM3CON EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' PWM1CON EQU H'0F79' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' VPP EQU H'0005' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' CCP3Y EQU H'0004' CCP3X EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F00'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F9B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; OSC = ECIOPLL EC-OSC2 as RA6 and PLL ; OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL ; OSC = HSSWPLL HS with SW PLL ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Mode Selection: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait: ; WAIT = ON Enabled ; WAIT = OFF Disabled ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; ECCP MUX: ; ECCPMX = PORTH Multiplexed with RH7:4 ; ECCPMX = PORTE Multiplexed with RE6:3 ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 or RE7 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC-OSC2 as RA6 and PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC-OSC2 as RA6 and SW PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS with SW PLL _OSCS_ON_1H EQU H'DF' ; Enabled _OSCS_OFF_1H EQU H'FF' ; Disabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _WAIT_ON_3L EQU H'7F' ; Enabled _WAIT_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _ECCPMX_PORTH_3H EQU H'FD' ; Multiplexed with RH7:4 _ECCPMX_PORTE_3H EQU H'FF' ; Multiplexed with RE6:3 _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 or RE7 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p12ce518.inc0000644000175000017500000000761711156313161013316 00000000000000 LIST ; P12CE518.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12CE518 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12CE518 ; 2. LIST directive in the source file ; LIST P=12CE518 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12CE518 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' OSCFST EQU H'0003' CAL1 EQU H'0003' OSCSLW EQU H'0002' CAL0 EQU H'0002' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f6410.inc0000644000175000017500000012175711156521301013236 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6410 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6410 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6410 ; 2. LIST directive in the source file ; LIST P=PIC18F6410 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6410 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2E EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DCCP3Y EQU H'0004' DCCP3X EQU H'0005' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F70'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block code-protected ; CP = OFF Program memory block not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG7L 30000Ch ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG7L EQU H'30000C' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block code-protected _CP_OFF_5L EQU H'FF' ; Program memory block not code-protected ;----- CONFIG7L Options -------------------------------------------------- _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2680.inc0000644000175000017500000041345111156521301013236 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2680 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2680 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2680 ; 2. LIST directive in the source file ; LIST P=PIC18F2680 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2680 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXBODBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXB0DBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB4'-H'0FB7' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f97j60.inc0000644000175000017500000016427511156521301013425 00000000000000 LIST ;========================================================================== ; MPASM PIC18F97J60 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F97J60 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F97J60 ; 2. LIST directive in the source file ; LIST P=PIC18F97J60 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F97J60 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RJPU EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ECCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2_PORTC EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ECCP2_PORTE EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' RG6 EQU H'0006' RG7 EQU H'0007' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' ECCP3 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' LATG6 EQU H'0006' LATG7 EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' RG6 EQU H'0006' RG7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' TRISG6 EQU H'0006' TRISG7 EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled and selected by MEMCON<5:4> ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-Bit Data Width mode ; BW = 16 16-Bit Data Width mode ; ; External Memory Bus Configuration bits: ; MODE = XM20 Extended Microcontroller mode, 20-Bit Address mode ; MODE = XM16 Extended Microcontroller mode,16-Bit Address mode ; MODE = XM12 Extended Microcontroller mode,12-Bit Address mode ; MODE = MM Microcontroller mode, external bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled; address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled; address on external bus is offset to start at 000000h ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ; ECCP MUX bit: ; ECCPMX = OFF ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = ON ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = OFF ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) ; CCP2MX = ON ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f84a.inc0000644000175000017500000001127711156313161013234 00000000000000 LIST ; P16F84A.INC Standard Header File, Version 2.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F84 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F84A ; 2. LIST directive in the source file ; LIST P=PIC16F84A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 2/15/99 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F84A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' EEDATA EQU H'0008' EEADR EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' EECON1 EQU H'0088' EECON2 EQU H'0089' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' EEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEIF EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'CF' __BADRAM H'07', H'50'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'000F' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f2450.inc0000644000175000017500000011565511156521301013236 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2450 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2450 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2450 ; 2. LIST directive in the source file ; LIST P=PIC18F2450 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2450 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' RCV EQU H'0004' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' VMO EQU H'0002' VPO EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' NOT_UOE EQU H'0001' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' UOE EQU H'0001' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- LVDIE EQU H'0002' USBIE EQU H'0005' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- LVDIF EQU H'0002' USBIF EQU H'0005' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- LVDIP EQU H'0002' USBIP EQU H'0005' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'03FF' __BADRAM H'0500'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB1'-H'0FB7' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FC5'-H'0FC9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; 96 MHz PLL Prescaler: ; PLLDIV = 1 No divide (4 MHz input) ; PLLDIV = 2 Divide by 2 (8 MHz input) ; PLLDIV = 3 Divide by 3 (12 MHz input) ; PLLDIV = 4 Divide by 4 (16 MHz input) ; PLLDIV = 5 Divide by 5 (20 MHz input) ; PLLDIV = 6 Divide by 6 (24 MHz input) ; PLLDIV = 10 Divide by 10 (40 MHz input) ; PLLDIV = 12 Divide by 12 (48 MHz input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; Full-Speed USB Clock Source Selection: ; USBDIV = 1 Clock source from OSC1/OSC2 ; USBDIV = 2 Clock source from 96 MHz PLL/2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal/External Switch Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = SOFT Controlled by SBOREN ; BOR = ON_ACTIVE Enabled when the device is not in Sleep, SBOREN bit is disabled ; BOR = ON Enabled, SBOREN bit is disabled ; ; Brown-out Voltage: ; BORV = 46 4.6V ; BORV = 43 4.3V ; BORV = 28 2.8V ; BORV = 21 2.1V ; ; USB Voltage Regulator Enable: ; VREGEN = OFF Disabled ; VREGEN = ON Enabled ; ; Watchdog Timer: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; Low Power Timer1 Oscillator Enable: ; LPT1OSC = OFF Timer1 oscillator configured for high power ; LPT1OSC = ON Timer1 oscillator configured for low power ; ; PORTB A/D Enable: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input on Reset ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Boot Block Size Select Bit: ; BBSIZ = BB1K 1KW Boot Block Size ; BBSIZ = BB2K 2KW Boot Block Size ; ; Dedicated In-Circuit Debug/Programming Enable: ; ICPRT = OFF Disabled ; ICPRT = ON Enabled ; ; Extended Instruction Set Enable: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No divide (4 MHz input) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; Clock source from OSC1/OSC2 _USBDIV_2_1L EQU H'FF' ; Clock source from 96 MHz PLL/2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'F9' ; Disabled _BOR_SOFT_2L EQU H'FB' ; Controlled by SBOREN _BOR_ON_ACTIVE_2L EQU H'FD' ; Enabled when the device is not in Sleep, SBOREN bit is disabled _BOR_ON_2L EQU H'FF' ; Enabled, SBOREN bit is disabled _BORV_46_2L EQU H'E7' ; 4.6V _BORV_43_2L EQU H'EF' ; 4.3V _BORV_28_2L EQU H'F7' ; 2.8V _BORV_21_2L EQU H'FF' ; 2.1V _VREGEN_OFF_2L EQU H'DF' ; Disabled _VREGEN_ON_2L EQU H'FF' ; Enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 oscillator configured for high power _LPT1OSC_ON_3H EQU H'FF' ; Timer1 oscillator configured for low power _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input on Reset ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _BBSIZ_BB1K_4L EQU H'F7' ; 1KW Boot Block Size _BBSIZ_BB2K_4L EQU H'FF' ; 2KW Boot Block Size _ICPRT_OFF_4L EQU H'DF' ; Disabled _ICPRT_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Disabled _XINST_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2220.inc0000644000175000017500000010212511156313161013220 00000000000000 LIST ; P18F2220.INC Standard Header File, Version 0.1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2220 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F2220 ; 2. LIST directive in the source file ; LIST P=PIC18F2220 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 07 Dec 2001 Initial revision BD ;0.11 22 Mar 2002 ECCP registers and bit names revised BD ;0.12 16 Apr 2002 Configuration bit MCLRE moved from 2L to 3H BD ;0.13 22 Apr 2002 T0CON changed back to T0CON BD ;0.14 09 May 2002 Removed PWM1CON and ECCPAS registers BD ; ECCP1CON changed to CCP1CON ;0.15 5 May 2002 _OSO_ON_1H changed to _IESO_ON_1H BD ; _MCLRE_ON_2L moved/changed to _MCLRE_ON_3H ; ;0.16 24 May 2002 OSCCON bit name corrected BD ; OSCCON register name above bit equates fixed ; T1CON added ; _MCLRE_ON_3H moved to correct register and renamed (again) ;0.17 30 May 2002 _PBAD_DIG_3H had wrong bit cleared BD ;0.18 13 Jun 2002 LVDCON,IRVST added to LVDCON BD ;0.19 09/26/02 Include both names SWDTE and SWDTEN pas ; ;0.20 27 Sep 2002 Add IOFS bit name to OSCCON register BD ; Add ECIO, RCIO, INTIO1, INTIO2 bits to Config Reg 1H ; Add DEBUG bits to Config Reg 4L ;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD ; ;0.22 1 Oct 2003 Bit names changed BD ; LVVn to LVDLn IVRST to IRVST ; FSCMEN to FSCM ; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1, ; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0, ; CVREF,CVRSS ; Removed redundant bit names ; RCIO6 use RCIO INTIO7 use INTIO1 ; ECIO6 use ECIO INTIO67 use INTIO2 ; BKBUG use DEBUG SWDTE use SWDTEN ; T0IE use TMR0IE INT0E use INT0IE ; T0IF use TMR0IF INT0F use INT0IE ; BGST use IRVST T1INSYNC use T1SYNC ; TXD8 use TX9D T3INSYNC use T3SYNC ; TX8_9 use TX9 NOT_TX8 use TX9 ; RC9 use RX9 NOT_RC8 use RX9 ; RC8_9 use RX9 RCD8 use RX9D ; INT2P use INT2IP INT1P use INT1IP ; INT2E use INT2IE INT1E use INT1IE ; INT2F use INT2IF INT1F use INT1IF ; Added equates for PIC16 Compatability ; ADRES, INTF, INTE, CCPnX, CCPnY ; General clean-up (removed some comments) ; Corrected RAM space definitions ; ;0.23 30 Mar 2004 References to RE3 removed, badram adjusted BD ;======================================================================= ; ; Verify Processor ; ;======================================================================= IFNDEF __18F2220 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define ADRES ADRESH ; PIC16 SFR substitution #define INTE INT0IE ; PIC16 bit substitution #define INTF INT0IF ; PIC16 bit substitution #define CCP1X DC1B1 ; PIC16 bit substitution #define CCP1Y DC1B0 ; PIC16 bit substitution #define CCP2X DC2B1 ; PIC16 bit substitution #define CCP2Y DC2B0 ; PIC16 bit substitution #define SCS SCS0 ; PIC18 bit substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ; reserved EQU H'0FB9' ; reserved EQU H'0FB8' ; reserved EQU H'0FB7' ; reserved EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ; reserved EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ; reserved EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' ; reserved EQU H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' OSCTUNE EQU H'0F9B' ; reserved EQU H'0F9A' ; reserved EQU H'0F99' ; reserved EQU H'0F98' ; reserved EQU H'0F97' ; reserved EQU H'0F96' ; reserved EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ; reserved EQU H'0F91' ; reserved EQU H'0F90' ; reserved EQU H'0F8F' ; reserved EQU H'0F8E' ; reserved EQU H'0F8D' ; reserved EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved EQU H'0F88' ; reserved EQU H'0F87' ; reserved EQU H'0F86' ; reserved EQU H'0F85' ; reserved EQU H'0F84' ; reserved EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' INT0IE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' FLTS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ---------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' D_A EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' R_W EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits ---------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ---------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ----------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ---------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- CVRCON Bits ----------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits ------------------------------------------------------ C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------ CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------ SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- OSCFIP EQU H'0007' CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ------------------------------------------------------- OSCFIF EQU H'0007' CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ------------------------------------------------------- OSCFIE EQU H'0007' CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ------------------------------------------------------- ; reserved EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- ; reserved EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- ; reserved EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- OSCTUNE Bits ---------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 RA7 EQU 7 OSC1 EQU 7 CLKI EQU 7 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 AN12 EQU 0 RB1 EQU 1 INT1 EQU 1 AN10 EQU 1 RB2 EQU 2 INT2 EQU 2 AN8 EQU 2 RB3 EQU 3 CCP2A EQU 3 AN9 EQU 3 RB4 EQU 4 AN11 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ----------------------------------------------------------- RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 P1A EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'200'-H'F7F' __BADRAM H'F83'-H'F88',H'F8C'-H'F91',H'F95'-H'F9A',H'F9C' __BADRAM H'FA3'-H'FA5',H'FAA',H'FB0',H'FB6'-H'FB9' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = EC External Clock on OSC1, OSC2 as FOSC/4 ; OSC = ECIO External Clock on OSC1, OSC2 as RA6 ; OSC = HSPLL HS + PLL ; OSC = RCIO External RC on OSC1, OSC2 as RA6 ; OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6 ; OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4 ; OSC = RC External RC on OSC1, OSC2 as FOSC/4 ; ; Fail-Safe Clock Monitor: ; FSCM = OFF Fail-Safe Clock Monitor disabled ; FSCM = ON Fail-Safe Clock Monitor enabled ; ; Internal External Switch Over mode: ; IESO = OFF Internal External Switch Over mode disabled ; IESO = ON Internal External Switch Over mode enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; PORTB A/D Enable: ; PBAD = DIG Digital ; PBAD = ANA Analog ; ; CCP2 Pin Function: ; CCP2MX = B3 RB3 ; CCP2MX = OFF RB3 ; CCP2MX = C1 RC1 ; CCP2MX = ON RC1 ; ; Stack Full/Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To embed the Configuration Bits in your source code, paste the ; following lines into your source code in the following format, ; and change the configuration value to the desired setting (such ; as WDT_OFF to WDT_ON). ; These lines are commented out - each __CONFIG line should have the ; preceding semicolon (;) removed when pasted into your source code. ; __CONFIG _CONFIG1H, _IESO_OFF_1H & _FSCM_OFF_1H & _RC_OSC_1H ; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_20_2L ; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H ; __CONFIG _CONFIG3H, _MCLRE_ON_3H & _PBAD_DIG_3H & _CCP2MX_C1_3H ; __CONFIG _CONFIG4L, _DEBUG_OFF_4L & _LVP_OFF_4L & _STVR_OFF_4L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 1H Options _IESO_ON_1H EQU H'FF' ; Internal External oscillator Switch Over mode enabled _IESO_OFF_1H EQU H'7F' ; Internal External oscillator Switch Over mode disabled _FSCM_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _FSCM_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as FOSC/4 _RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6 _LP_OSC_1H EQU H'F0' ; LP Oscillator _XT_OSC_1H EQU H'F1' ; XT Oscillator _HS_OSC_1H EQU H'F2' ; HS Oscillator _HSPLL_OSC_1H EQU H'F6' ; HS + PLL _EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as FOSC/4 _ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6 _INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4 _INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _PWRT_OFF_2L EQU H'FF' ; Power-up Timer disabled _PWRT_ON_2L EQU H'FE' ; Power-up Timer enabled ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled _WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio _WDTPS_16K_2H EQU H'FD' ; 1:16,384 _WDTPS_8K_2H EQU H'FB' ; 1: 8,192 _WDTPS_4K_2H EQU H'F9' ; 1: 4,096 _WDTPS_2K_2H EQU H'F7' ; 1: 2,048 _WDTPS_1K_2H EQU H'F5' ; 1: 1,024 _WDTPS_512_2H EQU H'F3' ; 1: 512 _WDTPS_256_2H EQU H'F1' ; 1: 256 _WDTPS_128_2H EQU H'EF' ; 1: 128 _WDTPS_64_2H EQU H'ED' ; 1: 64 _WDTPS_32_2H EQU H'EB' ; 1: 32 _WDTPS_16_2H EQU H'E9' ; 1: 16 _WDTPS_8_2H EQU H'E7' ; 1: 8 _WDTPS_4_2H EQU H'E5' ; 1: 4 _WDTPS_2_2H EQU H'E3' ; 1: 2 _WDTPS_1_2H EQU H'E1' ; 1: 1 ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'FF' ; MCLR enabled _MCLRE_OFF_3H EQU H'7F' ; MCLR disabled _PBAD_ANA_3H EQU H'FF' ; PORTB<4:0> pins reset as analog pins _PBAD_DIG_3H EQU H'FD' ; PORTB<4:0> pins reset as digital pins _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin function on RC1 _CCP2MX_OFF_3H EQU H'FE' ; CCP2 pin function on RB3 _CCP2MX_C1_3H EQU H'FF' ; CCP2 pin function on RC1 (alt defn) _CCP2MX_B3_3H EQU H'FE' ; CCP2 pin function on RB3 (alt defn) ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; DEBUGger enabled _DEBUG_OFF_4L EQU H'FF' ; DEBUGger disabled _LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled _LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP0_ON_5L EQU H'FE' ; Block 0 protected _CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable _CP1_ON_5L EQU H'FD' ; Block 1 protected _CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'BF' ; Boot Block protected _CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'7F' ; Data EE memory protected _CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT0_ON_6L EQU H'FE' ; Block 0 write protected _WRT0_OFF_6L EQU H'FF' ; Block 0 writable _WRT1_ON_6L EQU H'FD' ; Block 1 write protected _WRT1_OFF_6L EQU H'FF' ; Block 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'DF' ; Config registers write protected _WRTC_OFF_6H EQU H'FF' ; Config registers writable _WRTB_ON_6H EQU H'BF' ; Boot block write protected _WRTB_OFF_6H EQU H'FF' ; Boot block writable _WRTD_ON_6H EQU H'7F' ; Data EE write protected _WRTD_OFF_6H EQU H'FF' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR0_ON_7L EQU H'FE' ; Block 0 protected _EBTR0_OFF_7L EQU H'FF' ; Block 0 readable _EBTR1_ON_7L EQU H'FD' ; Block 1 protected _EBTR1_OFF_7L EQU H'FF' ; Block 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'BF' ; Boot block read protected _EBTRB_OFF_7H EQU H'FF' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p16f870.inc0000644000175000017500000002575411156313161013163 00000000000000 LIST ; P16F870.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F870 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F870 ; 2. LIST directive in the source file ; LIST P=PIC16F870 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 08/07/98 Initial Release - cloned from 16F873 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F870 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'13'-H'14', H'1B'-H'1D' __BADRAM H'88'-H'89',H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'0FCF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c926.inc0000644000175000017500000003244411156313161013154 00000000000000 LIST ; P16C926.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C926 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C926 ; 2. LIST directive in the source file ; LIST P=PIC16C926 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/11/00 Initial Release ;1.01 02/27/01 Changes to reflect design changes to data memory map: ; 1.) Locations of PMDATA and PMCON1 swapped. ; 2.) Locations of PMDATH and PMADR swapped. ;1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected. ;1.03 03/06/01 RD bit in PMCON1 defined. ;1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01. ;1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04. ;1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C926 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADRESL EQU H'009E' ADCON1 EQU H'009F' PORTF EQU H'0107' PORTG EQU H'0108' PMCON1 EQU H'010C' LCDSE EQU H'010D' LCDPS EQU H'010E' LCDCON EQU H'010F' LCDD00 EQU H'0110' LCDD01 EQU H'0111' LCDD02 EQU H'0112' LCDD03 EQU H'0113' LCDD04 EQU H'0114' LCDD05 EQU H'0115' LCDD06 EQU H'0116' LCDD07 EQU H'0117' LCDD08 EQU H'0118' LCDD09 EQU H'0119' LCDD10 EQU H'011A' LCDD11 EQU H'011B' LCDD12 EQU H'011C' LCDD13 EQU H'011D' LCDD14 EQU H'011E' LCDD15 EQU H'011F' TRISF EQU H'0187' TRISG EQU H'0188' PMDATA EQU H'018C' PMDATH EQU H'018D' PMADR EQU H'018E' PMADRH EQU H'018F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- LCDIF EQU H'0007' ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- LCDIE EQU H'0007' ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- LCDSE Bits --------------------------------------------------------- SE29 EQU H'0007' SE27 EQU H'0006' SE20 EQU H'0005' SE16 EQU H'0004' SE12 EQU H'0003' SE9 EQU H'0002' SE5 EQU H'0001' SE0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' BIAS EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'0D', H'18'-H'1D' __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D' __BADRAM H'105', H'109' __BADRAM H'185', H'189', H'190'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3FCF' _CP_75 EQU H'3FDF' _CP_50 EQU H'3FEF' _CP_OFF EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _BODEN_ON EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c620.inc0000644000175000017500000001350111156313161013134 00000000000000 LIST ; P16C620.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C620 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C620 ; 2. LIST directive in the source file ; LIST P=PIC16C620 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C620 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'09F' __BADRAM H'07'-H'09', H'0D'-H'1E', H'70'-H'7F' __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ON EQU H'00CF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f2539.inc0000644000175000017500000006605111156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2539 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2539 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2539 ; 2. LIST directive in the source file ; LIST P=PIC18F2539 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2539 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' CLK0 EQU H'0006' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2 EQU H'0001' CCP1 EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCPX EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0002' CHS0 EQU H'0003' CHS1 EQU H'0004' CHS2 EQU H'0005' ADCS0 EQU H'0006' ADCS1 EQU H'0007' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' TMR0IP EQU H'0002' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0580'-H'0F7F' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB4'-H'0FB9' __BADRAM H'0FC0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F8' ; LP _OSC_XT_1H EQU H'F9' ; XT _OSC_HS_1H EQU H'FA' ; HS _OSC_RC_1H EQU H'FB' ; RC _OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6 ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_25_2L EQU H'FF' ; 2.5V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'F1' ; 1:1 _WDTPS_2_2H EQU H'F3' ; 1:2 _WDTPS_4_2H EQU H'F5' ; 1:4 _WDTPS_8_2H EQU H'F7' ; 1:8 _WDTPS_16_2H EQU H'F9' ; 1:16 _WDTPS_32_2H EQU H'FB' ; 1:32 _WDTPS_64_2H EQU H'FD' ; 1:64 _WDTPS_128_2H EQU H'FF' ; 1:128 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f6722.inc0000644000175000017500000020322311156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6722 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6722 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6722 ; 2. LIST directive in the source file ; LIST P=PIC18F6722 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6722 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Code Protection bit Block 6: ; CP6 = ON Block 6 (01BFFF-018000h) code-protected ; CP6 = OFF Block 6 (01BFFF-018000h) not code-protected ; ; Code Protection bit Block 7: ; CP7 = ON Block 7 (01C000-01FFFFh) code-protected ; CP7 = OFF Block 7 (01C000-01FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Write Protection bit Block 6: ; WRT6 = ON Block 6 (01BFFF-018000h) write-protected ; WRT6 = OFF Block 6 (01BFFF-018000h) not write-protected ; ; Write Protection bit Block 7: ; WRT7 = ON Block 7 (01C000-01FFFFh) write-protected ; WRT7 = OFF Block 7 (01C000-01FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 6: ; EBTR6 = ON Block 6 (018000-01BFFFh) protected from table reads executed in other blocks ; EBTR6 = OFF Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 7: ; EBTR7 = ON Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks ; EBTR7 = OFF Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected _CP6_ON_5L EQU H'BF' ; Block 6 (01BFFF-018000h) code-protected _CP6_OFF_5L EQU H'FF' ; Block 6 (01BFFF-018000h) not code-protected _CP7_ON_5L EQU H'7F' ; Block 7 (01C000-01FFFFh) code-protected _CP7_OFF_5L EQU H'FF' ; Block 7 (01C000-01FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected _WRT6_ON_6L EQU H'BF' ; Block 6 (01BFFF-018000h) write-protected _WRT6_OFF_6L EQU H'FF' ; Block 6 (01BFFF-018000h) not write-protected _WRT7_ON_6L EQU H'7F' ; Block 7 (01C000-01FFFFh) write-protected _WRT7_OFF_6L EQU H'FF' ; Block 7 (01C000-01FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks _EBTR6_ON_7L EQU H'BF' ; Block 6 (018000-01BFFFh) protected from table reads executed in other blocks _EBTR6_OFF_7L EQU H'FF' ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks _EBTR7_ON_7L EQU H'7F' ; Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks _EBTR7_OFF_7L EQU H'FF' ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p12f615.inc0000644000175000017500000003563511156521301013150 00000000000000 LIST ; P12F615.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F615 microcontroller. The names are taken to match ; the data sheet as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12F615 ; 2. LIST directive in the source file ; LIST P=PIC12F615 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 04/19/06 Original ;1.01 05/03/06 Remove references to 12HV615 ;1.02 12/08/06 Corrected references of comparator C1 to CM, with aliases ;1.03 12/11/06 Added TRISA and IOCA aliases ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F615 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PORTA EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' PWM1CON EQU H'0016' ECCPAS EQU H'0017' VRCON EQU H'0019' CMCON0 EQU H'001A' CMCON1 EQU H'001C' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' TRISA EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' PR2 EQU H'0092' APFCON EQU H'0093' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits ---------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0005' C1IF EQU H'0003' CMIF EQU H'0003' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M EQU H'0007' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- VRCON Bits ------------------------------------------------------- C1VREN EQU H'0007' CMVREN EQU H'0007' VRR EQU H'0005' VP6EN EQU H'0004' FVREN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C1ON EQU H'0007' CMON EQU H'0007' C1OUT EQU H'0006' COUT EQU H'0006' C1OE EQU H'0005' CMOE EQU H'0005' C1POL EQU H'0004' CMPOL EQU H'0004' C1R EQU H'0002' CMR EQU H'0002' C1CH0 EQU H'0000' CMCH EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1ACS EQU H'0004' C1HYS EQU H'0003' CMHYS EQU H'0003' T1GSS EQU H'0001' C1SYNC EQU H'0000' CMSYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISIO Bits -------------------------------------------------------- TRISIO5 EQU H'0005' TRISIO4 EQU H'0004' TRISIO3 EQU H'0003' TRISIO2 EQU H'0002' TRISIO1 EQU H'0001' TRISIO0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0005' C1IE EQU H'0003' CMIE EQU H'0003' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- APFCON Bits -------------------------------------------------------- T1GSEL EQU H'0004' P1BSEL EQU H'0001' P1ASEL EQU H'0000' ;----- WPU Bits --------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' AN3 EQU H'0003' AN2 EQU H'0002' AN1 EQU H'0001' AN0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'18', H'1B', H'1D', H'20'-H'3F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91', H'94', H'97'-H'9D', H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f85j15.inc0000644000175000017500000014201611156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F85J15 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F85J15 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F85J15 ; 2. LIST directive in the source file ; LIST P=PIC18F85J15 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F85J15 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f67j50.inc0000644000175000017500000017023711156521301013414 00000000000000 LIST ;========================================================================== ; MPASM PIC18F67J50 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F67J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F67J50 ; 2. LIST directive in the source file ; LIST P=PIC18F67J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F67J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16cr84.inc0000644000175000017500000001150111156313161013240 00000000000000 LIST ; P16CR84.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR84 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR84 ; 2. LIST directive in the source file ; LIST P=PIC16CR84 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 05/17/96 Corrected BADRAM map ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR84 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' EEDATA EQU H'0008' EEADR EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' EECON1 EQU H'0088' EECON2 EQU H'0089' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' EEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEIF EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'CF' __BADRAM H'07', H'50'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'008F' _CP_OFF EQU H'3FFF' _DP_ON EQU H'3F7F' _DP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f96j65.inc0000644000175000017500000016427511156521301013431 00000000000000 LIST ;========================================================================== ; MPASM PIC18F96J65 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F96J65 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F96J65 ; 2. LIST directive in the source file ; LIST P=PIC18F96J65 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F96J65 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RJPU EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ECCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2_PORTC EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ECCP2_PORTE EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' RG6 EQU H'0006' RG7 EQU H'0007' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' ECCP3 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' LATG6 EQU H'0006' LATG7 EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' RG6 EQU H'0006' RG7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' TRISG6 EQU H'0006' TRISG7 EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled and selected by MEMCON<5:4> ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-Bit Data Width mode ; BW = 16 16-Bit Data Width mode ; ; External Memory Bus Configuration bits: ; MODE = XM20 Extended Microcontroller mode, 20-Bit Address mode ; MODE = XM16 Extended Microcontroller mode,16-Bit Address mode ; MODE = XM12 Extended Microcontroller mode,12-Bit Address mode ; MODE = MM Microcontroller mode, external bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled; address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled; address on external bus is offset to start at 000000h ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ; ECCP MUX bit: ; ECCPMX = OFF ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = ON ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = OFF ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) ; CCP2MX = ON ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16cr62.inc0000644000175000017500000002062511156313161013243 00000000000000 LIST ; P16CR62.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR62 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR62 ; 2. LIST directive in the source file ; LIST P=PIC16CR62 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR62 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1F' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16lf724.inc0000644000175000017500000005114511156521301013323 00000000000000 LIST ; P16LF724.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16LF724 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16LF724 ; 2. LIST directive in the source file ; LIST P=PIC16LF724 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/25/07 Initial template ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF724 MESSG "Processor-header file mismatch. Verify selected processor." #define __16LF724 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' ANSELD EQU H'0188' ANSELE EQU H'0189' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- ANSELD Bits --------------------------------------------------------- ANSD7 EQU H'0007' ANSD6 EQU H'0006' ANSD5 EQU H'0005' ANSD4 EQU H'0004' ANSD3 EQU H'0003' ANSD2 EQU H'0002' ANSD1 EQU H'0001' ANSD0 EQU H'0000' ;----- ANSELE Bits --------------------------------------------------------- ANSE2 EQU H'0002' ANSE1 EQU H'0001' ANSE0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'110'-H'11F',H'130'-H'16F' __BADRAM H'187', H'18D'-H'18F' __BADRAM H'190'-H'1EF' LIST gputils-0.13.7/header/rf675h.inc0000644000175000017500000002156311156313161013163 00000000000000 LIST ; RF675H.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the rfPIC12F675H microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PICRF675H ; 2. LIST directive in the source file ; LIST P=RF675H ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 02/19/03 Original -- copied from P12F675.INC (pas) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __RF675H MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' WPU EQU H'0095' IOC EQU H'0096' IOCB EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 ------------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ANSEL -------------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16c63a.inc0000644000175000017500000002575311156313161013232 00000000000000 LIST ; P16C63A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C63A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C63A ; 2. LIST directive in the source file ; LIST P=PIC16C63A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/17/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C63A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09', H'1E'-H'1F' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f87j11.inc0000644000175000017500000016344411156521301013415 00000000000000 LIST ;========================================================================== ; MPASM PIC18F87J11 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F87J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F87J11 ; 2. LIST directive in the source file ; LIST P=PIC18F87J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F87J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F5A' PMSTATL EQU H'0F5A' PMSTATH EQU H'0F5B' PMEL EQU H'0F5C' PMEN EQU H'0F5C' PMEH EQU H'0F5D' PMDIN2 EQU H'0F5E' PMDIN2L EQU H'0F5E' PMDIN2H EQU H'0F5F' PMDOUT2 EQU H'0F60' PMDOUT2L EQU H'0F60' PMDOUT2H EQU H'0F61' PMMODE EQU H'0F62' PMMODEL EQU H'0F62' PMMODEH EQU H'0F63' PMCON EQU H'0F64' PMCONL EQU H'0F64' PMCONH EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2OUT EQU H'0001' C1OUT EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7 ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled ; FOSC = EC EC Oscillator with clock out on RA6 ; FOSC = ECPLL EC Oscillator with PLL ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f677.inc0000644000175000017500000004305011156521301013152 00000000000000 LIST ; P16F677.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F677 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F677 ; 2. LIST directive in the source file ; LIST P=PIC16F677 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/28/05 Original ;1.01 11/08/05 Removed unimplemented bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F677 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' SSPBUF EQU H'0013' SSPCON EQU H'0014' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPADD EQU H'0093' MSK EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' WDTCON EQU H'0097' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDAT EQU H'010C' EEDATA EQU H'010C' EEADR EQU H'010D' WPUB EQU H'0115' IOCB EQU H'0116' VRCON EQU H'0118' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' ANSEL EQU H'011E' ANSELH EQU H'011F' EECON1 EQU H'018C' EECON2 EQU H'018D' SRCON EQU H'019E' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RABIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RABIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION Bits -------------------------------------------------------- NOT_RABPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TRISB7 EQU H'0007' TRISB6 EQU H'0006' TRISB5 EQU H'0005' TRISB4 EQU H'0004' ;----- TRISC Bits -------------------------------------------------------- TRISC7 EQU H'0007' TRISC6 EQU H'0006' TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' POR EQU H'0001' NOT_POR EQU H'0001' BOR EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits -------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' ;----- IOCB Bits --------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'1D' __BADRAM H'88'-H'89', H'91'-H'92', H'98'-H'9D', H'C0'-H'EF' __BADRAM H'108'-H'109', H'10E'-H'114', H'117', H'11C'-H'11D', H'120'-H'16F' __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16f777.inc0000644000175000017500000004632711156313161013170 00000000000000 LIST ; P16F777.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F777 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F777 ; 2. LIST directive in the source file ; LIST P=PIC16F777 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/05/03 Initial Release ;1.01 10/21/03 Made changes to Program Memory register names. ;1.02 04/07/04 Added INT0IE & INT0IF bit names. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F777 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' CCPR3L EQU H'0095' CCPR3H EQU H'0096' CCP3CON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON2 EQU H'009B' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LVDCON EQU H'0109' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' INT0IE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' CMIF EQU H'0006' LVDIF EQU H'0005' BCLIF EQU H'0003' CCP3IF EQU H'0001' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE3 EQU H'0003' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' CMIE EQU H'0006' LVDIE EQU H'0005' BCLIE EQU H'0003' CCP3IE EQU H'0001' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- CCP3X EQU H'0005' CCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON2 Bits --------------------------------------------------------- ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'9A' __BADRAM H'107'-H'108' __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;Configuration Byte 1 Options _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP2_RC1 EQU H'3FFF' _CCP2_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _VBOR_2_0 EQU H'3FFF' _VBOR_2_7 EQU H'3F7F' _VBOR_4_2 EQU H'3EFF' _VBOR_4_5 EQU H'3E7F' _BOREN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _BOREN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' ;Configuration Byte 2 Options _BORSEN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _BORSEN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3FFD' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'3FFE' ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ALL). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF LIST gputils-0.13.7/header/p18f4610.inc0000644000175000017500000012600211156521301013222 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4610 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4610 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4610 ; 2. LIST directive in the source file ; LIST P=PIC18F4610 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4610 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCPAS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' DAD5 EQU H'0005' DAD6 EQU H'0006' DAD7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCPAS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f914.inc0000644000175000017500000007236111156521301013153 00000000000000 LIST ; P16F914.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F914 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F914 ; 2. LIST directive in the source file ; LIST P=PIC16F914 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 06/11/04 Initial Release ;1.01 08/16/04 Added EECON2 ;1.02 05/20/05 Removed EECON2 from badram ;1.03 10/05/05 Correct names of bits in ANSEL, Add EEADRH and EEADRL bit ;1.04 10/30/06 Added Alias of go_done, go ; definitions ;1.05 02/26/07 Added Alias of EEADR and EEDATA ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F914 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' WPU EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' CMCON1 EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON0 EQU H'009C' VRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LCDCON EQU H'0107' LCDPS EQU H'0108' LVDCON EQU H'0109' EEDATL EQU H'010C' EEDATA EQU H'010C' EEADRL EQU H'010D' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' LCDDATA0 EQU H'0110' LCDDATA1 EQU H'0111' LCDDATA2 EQU H'0112' LCDDATA3 EQU H'0113' LCDDATA4 EQU H'0114' LCDDATA5 EQU H'0115' LCDDATA6 EQU H'0116' LCDDATA7 EQU H'0117' LCDDATA8 EQU H'0118' LCDDATA9 EQU H'0119' LCDDATA10 EQU H'011A' LCDDATA11 EQU H'011B' LCDSE0 EQU H'011C' LCDSE1 EQU H'011D' LCDSE2 EQU H'011E' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' LCDIF EQU H'0004' LVDIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0006' VCFG0 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' GO EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' LCDIE EQU H'0004' LVDIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' AN7 EQU H'0007' ; Backward compatibility only ANS6 EQU H'0006' AN6 EQU H'0006' ; Backward compatibility only ANS5 EQU H'0005' AN5 EQU H'0005' ; Backward compatibility only ANS4 EQU H'0004' AN4 EQU H'0004' ; Backward compatibility only ANS3 EQU H'0003' AN3 EQU H'0003' ; Backward compatibility only ANS2 EQU H'0002' AN2 EQU H'0002' ; Backward compatibility only ANS1 EQU H'0001' AN1 EQU H'0001' ; Backward compatibility only ANS0 EQU H'0000' AN0 EQU H'0000' ; Backward compatibility only ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' WPU6 EQU H'0006' WPU5 EQU H'0005' WPU4 EQU H'0004' WPU3 EQU H'0003' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' IOC6 EQU H'0006' IOC5 EQU H'0005' IOC4 EQU H'0004' ;----- CMCON1 Bits -------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON0 Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- VRCON Bits -------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' VLCDEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- WFT EQU H'0007' BIASMD EQU H'0006' LCDA EQU H'0005' WA EQU H'0004' LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- LCDDATA0 Bits ------------------------------------------------------- SEG7COM0 EQU H'0007' SEG6COM0 EQU H'0006' SEG5COM0 EQU H'0005' SEG4COM0 EQU H'0004' SEG3COM0 EQU H'0003' SEG2COM0 EQU H'0002' SEG1COM0 EQU H'0001' SEG0COM0 EQU H'0000' S7C0 EQU H'0007' S6C0 EQU H'0006' S5C0 EQU H'0005' S4C0 EQU H'0004' S3C0 EQU H'0003' S2C0 EQU H'0002' S1C0 EQU H'0001' S0C0 EQU H'0000' ;----- LCDDATA1 Bits ------------------------------------------------------- SEG15COM0 EQU H'0007' SEG14COM0 EQU H'0006' SEG13COM0 EQU H'0005' SEG12COM0 EQU H'0004' SEG11COM0 EQU H'0003' SEG10COM0 EQU H'0002' SEG9COM0 EQU H'0001' SEG8COM0 EQU H'0000' S15C0 EQU H'0007' S14C0 EQU H'0006' S13C0 EQU H'0005' S12C0 EQU H'0004' S11C0 EQU H'0003' S10C0 EQU H'0002' S9C0 EQU H'0001' S8C0 EQU H'0000' ;----- LCDDATA2 Bits ------------------------------------------------------- SEG23COM0 EQU H'0007' SEG22COM0 EQU H'0006' SEG21COM0 EQU H'0005' SEG20COM0 EQU H'0004' SEG19COM0 EQU H'0003' SEG18COM0 EQU H'0002' SEG17COM0 EQU H'0001' SEG16COM0 EQU H'0000' S23C0 EQU H'0007' S22C0 EQU H'0006' S21C0 EQU H'0005' S20C0 EQU H'0004' S19C0 EQU H'0003' S18C0 EQU H'0002' S17C0 EQU H'0001' S16C0 EQU H'0000' ;----- LCDDATA3 Bits ------------------------------------------------------- SEG7COM1 EQU H'0007' SEG6COM1 EQU H'0006' SEG5COM1 EQU H'0005' SEG4COM1 EQU H'0004' SEG3COM1 EQU H'0003' SEG2COM1 EQU H'0002' SEG1COM1 EQU H'0001' SEG0COM1 EQU H'0000' S7C1 EQU H'0007' S6C1 EQU H'0006' S5C1 EQU H'0005' S4C1 EQU H'0004' S3C1 EQU H'0003' S2C1 EQU H'0002' S1C1 EQU H'0001' S0C1 EQU H'0000' ;----- LCDDATA4 Bits ------------------------------------------------------- SEG15COM1 EQU H'0007' SEG14COM1 EQU H'0006' SEG13COM1 EQU H'0005' SEG12COM1 EQU H'0004' SEG11COM1 EQU H'0003' SEG10COM1 EQU H'0002' SEG9COM1 EQU H'0001' SEG8COM1 EQU H'0000' S15C1 EQU H'0007' S14C1 EQU H'0006' S13C1 EQU H'0005' S12C1 EQU H'0004' S11C1 EQU H'0003' S10C1 EQU H'0002' S9C1 EQU H'0001' S8C1 EQU H'0000' ;----- LCDDATA5 Bits ------------------------------------------------------- SEG23COM1 EQU H'0007' SEG22COM1 EQU H'0006' SEG21COM1 EQU H'0005' SEG20COM1 EQU H'0004' SEG19COM1 EQU H'0003' SEG18COM1 EQU H'0002' SEG17COM1 EQU H'0001' SEG16COM1 EQU H'0000' S23C1 EQU H'0007' S22C1 EQU H'0006' S21C1 EQU H'0005' S20C1 EQU H'0004' S19C1 EQU H'0003' S18C1 EQU H'0002' S17C1 EQU H'0001' S16C1 EQU H'0000' ;----- LCDDATA6 Bits ------------------------------------------------------- SEG7COM2 EQU H'0007' SEG6COM2 EQU H'0006' SEG5COM2 EQU H'0005' SEG4COM2 EQU H'0004' SEG3COM2 EQU H'0003' SEG2COM2 EQU H'0002' SEG1COM2 EQU H'0001' SEG0COM2 EQU H'0000' S7C2 EQU H'0007' S6C2 EQU H'0006' S5C2 EQU H'0005' S4C2 EQU H'0004' S3C2 EQU H'0003' S2C2 EQU H'0002' S1C2 EQU H'0001' S0C2 EQU H'0000' ;----- LCDDATA7 Bits ------------------------------------------------------- SEG15COM2 EQU H'0007' SEG14COM2 EQU H'0006' SEG13COM2 EQU H'0005' SEG12COM2 EQU H'0004' SEG11COM2 EQU H'0003' SEG10COM2 EQU H'0002' SEG9COM2 EQU H'0001' SEG8COM2 EQU H'0000' S15C2 EQU H'0007' S14C2 EQU H'0006' S13C2 EQU H'0005' S12C2 EQU H'0004' S11C2 EQU H'0003' S10C2 EQU H'0002' S9C2 EQU H'0001' S8C2 EQU H'0000' ;----- LCDDATA8 Bits ------------------------------------------------------- SEG23COM2 EQU H'0007' SEG22COM2 EQU H'0006' SEG21COM2 EQU H'0005' SEG20COM2 EQU H'0004' SEG19COM2 EQU H'0003' SEG18COM2 EQU H'0002' SEG17COM2 EQU H'0001' SEG16COM2 EQU H'0000' S23C2 EQU H'0007' S22C2 EQU H'0006' S21C2 EQU H'0005' S20C2 EQU H'0004' S19C2 EQU H'0003' S18C2 EQU H'0002' S17C2 EQU H'0001' S16C2 EQU H'0000' ;----- LCDDATA9 Bits ------------------------------------------------------- SEG7COM3 EQU H'0007' SEG6COM3 EQU H'0006' SEG5COM3 EQU H'0005' SEG4COM3 EQU H'0004' SEG3COM3 EQU H'0003' SEG2COM3 EQU H'0002' SEG1COM3 EQU H'0001' SEG0COM3 EQU H'0000' S7C3 EQU H'0007' S6C3 EQU H'0006' S5C3 EQU H'0005' S4C3 EQU H'0004' S3C3 EQU H'0003' S2C3 EQU H'0002' S1C3 EQU H'0001' S0C3 EQU H'0000' ;----- LCDDATA10 Bits ------------------------------------------------------- SEG15COM3 EQU H'0007' SEG14COM3 EQU H'0006' SEG13COM3 EQU H'0005' SEG12COM3 EQU H'0004' SEG11COM3 EQU H'0003' SEG10COM3 EQU H'0002' SEG9COM3 EQU H'0001' SEG8COM3 EQU H'0000' S15C3 EQU H'0007' S14C3 EQU H'0006' S13C3 EQU H'0005' S12C3 EQU H'0004' S11C3 EQU H'0003' S10C3 EQU H'0002' S9C3 EQU H'0001' S8C3 EQU H'0000' ;----- LCDDATA11 Bits ------------------------------------------------------- SEG23COM3 EQU H'0007' SEG22COM3 EQU H'0006' SEG21COM3 EQU H'0005' SEG20COM3 EQU H'0004' SEG19COM3 EQU H'0003' SEG18COM3 EQU H'0002' SEG17COM3 EQU H'0001' SEG16COM3 EQU H'0000' S23C3 EQU H'0007' S22C3 EQU H'0006' S21C3 EQU H'0005' S20C3 EQU H'0004' S19C3 EQU H'0003' S18C3 EQU H'0002' S17C3 EQU H'0001' S16C3 EQU H'0000' ;----- LCDSE0 Bits -------------------------------------------------------- SE7 EQU H'0007' SE6 EQU H'0006' SE5 EQU H'0005' SE4 EQU H'0004' SE3 EQU H'0003' SE2 EQU H'0002' SE1 EQU H'0001' SE0 EQU H'0000' SEGEN7 EQU H'0007' SEGEN6 EQU H'0006' SEGEN5 EQU H'0005' SEGEN4 EQU H'0004' SEGEN3 EQU H'0003' SEGEN2 EQU H'0002' SEGEN1 EQU H'0001' SEGEN0 EQU H'0000' ;----- LCDSE1 Bits -------------------------------------------------------- SE15 EQU H'0007' SE14 EQU H'0006' SE13 EQU H'0005' SE12 EQU H'0004' SE11 EQU H'0003' SE10 EQU H'0002' SE9 EQU H'0001' SE8 EQU H'0000' SEGEN15 EQU H'0007' SEGEN14 EQU H'0006' SEGEN13 EQU H'0005' SEGEN12 EQU H'0004' SEGEN11 EQU H'0003' SEGEN10 EQU H'0002' SEGEN9 EQU H'0001' SEGEN8 EQU H'0000' ;----- LCDSE2 Bits -------------------------------------------------------- SE23 EQU H'0007' SE22 EQU H'0006' SE21 EQU H'0005' SE20 EQU H'0004' SE19 EQU H'0003' SE18 EQU H'0002' SE17 EQU H'0001' SE16 EQU H'0000' SEGEN23 EQU H'0007' SEGEN22 EQU H'0006' SEGEN21 EQU H'0005' SEGEN20 EQU H'0004' SEGEN19 EQU H'0003' SEGEN18 EQU H'0002' SEGEN17 EQU H'0001' SEGEN16 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' EEWR EQU H'0001' RD EQU H'0000' EERD EQU H'0000' ;----- EEADRH Bits -------------------------------------------------------- EEADRH4 EQU H'0004' EEADRH3 EQU H'0003' EEADRH2 EQU H'0002' EEADRH1 EQU H'0001' EEADRH0 EQU H'0000' ;----- EEADRL Bits -------------------------------------------------------- EEADRL7 EQU H'0007' EEADRL6 EQU H'0006' EEADRL5 EQU H'0005' EEADRL4 EQU H'0004' EEADRL3 EQU H'0003' EEADRL2 EQU H'0002' EEADRL1 EQU H'0001' EEADRL0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'9A'-H'9B' __BADRAM H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG EQU H'2007' ;Configuration Byte 1 Options _DEBUG_ON EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f6390.inc0000644000175000017500000016620411156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6390 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6390 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6390 ; 2. LIST directive in the source file ; LIST P=PIC18F6390 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6390 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16cr83.inc0000644000175000017500000001143311156313161013243 00000000000000 LIST ; P16CR83.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR83 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR83 ; 2. LIST directive in the source file ; LIST P=PIC16CR83 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR83 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' EEDATA EQU H'0008' EEADR EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' EECON1 EQU H'0088' EECON2 EQU H'0089' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' EEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEIF EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'AF' __BADRAM H'07', H'30'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'008F' _CP_OFF EQU H'3FFF' _DP_ON EQU H'3F7F' _DP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f767.inc0000644000175000017500000004623311156313161013163 00000000000000 LIST ; P16F767.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F767 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F767 ; 2. LIST directive in the source file ; LIST P=PIC16F767 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/05/03 Initial Release ;1.01 10/21/03 Made changes to Program Memory register names. ;1.02 04/07/04 Added INT0IE & INT0IF bit names. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F767 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' CCPR3L EQU H'0095' CCPR3H EQU H'0096' CCP3CON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON2 EQU H'009B' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LVDCON EQU H'0109' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' INT0IE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' CMIF EQU H'0006' LVDIF EQU H'0005' BCLIF EQU H'0003' CCP3IF EQU H'0001' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE3 EQU H'0003' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' CMIE EQU H'0006' LVDIE EQU H'0005' BCLIE EQU H'0003' CCP3IE EQU H'0001' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- CCP3X EQU H'0005' CCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON2 Bits --------------------------------------------------------- ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08' __BADRAM H'88', H'9A' __BADRAM H'107'-H'108' __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;Configuration Byte 1 Options _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP2_RC1 EQU H'3FFF' _CCP2_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _VBOR_2_0 EQU H'3FFF' _VBOR_2_7 EQU H'3F7F' _VBOR_4_2 EQU H'3EFF' _VBOR_4_5 EQU H'3E7F' _BOREN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _BOREN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' ;Configuration Byte 2 Options _BORSEN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _BORSEN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3FFD' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'3FFE' ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ALL). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF LIST gputils-0.13.7/header/p18lf13k22.inc0000644000175000017500000012026211156521302013551 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF13K22 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF13K22 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF13K22 ; 2. LIST directive in the source file ; LIST P=PIC18LF13K22 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF13K22 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' APFCON EQU H'0F75' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' VREFCON0 EQU H'0FBA' VREFCON1 EQU H'0FBB' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- C1SEL EQU H'0000' T0CKISEL EQU H'0001' INT2SEL EQU H'0002' SRQSEL EQU H'0003' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA0 EQU H'0000' WPUA1 EQU H'0001' WPUA2 EQU H'0002' WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA2 EQU H'0002' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0100'-H'0F3F' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F74' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 512W boot block size ; BBSIZ = ON 1kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 512W boot block size _BBSIZ_ON_4L EQU H'FF' ; 1kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f88.inc0000644000175000017500000004050411156313161013072 00000000000000 LIST ; P16F88.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F88 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F88 ; 2. LIST directive in the source file ; LIST P=PIC16F88 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 07/29/02 Initial Release ;1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS ;1.02 01/10/03 Added bit names for TXSTA & RCSTA registers. ;1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0 ;1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1. ;1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F88 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ANSEL EQU H'009B' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' CMIF EQU H'0006' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' CMIE EQU H'0006' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'1B'-H'1D' __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A' __BADRAM H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;Configuration Byte 1 Options _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP1_RB0 EQU H'3FFF' _CCP1_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_PROTECT_OFF EQU H'3FFF' ;No program memory write protection _WRT_PROTECT_256 EQU H'3DFF' ;First 256 program memory protected _WRT_PROTECT_2048 EQU H'3BFF' ;First 2048 program memory protected _WRT_PROTECT_ALL EQU H'39FF' ;All of program memory protected _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' ;Configuration Byte 2 Options _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3FFD' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'3FFE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ALL). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF LIST gputils-0.13.7/header/p18f4320.inc0000644000175000017500000010770511156313161013234 00000000000000 LIST ; P18F4320.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4320 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F4320 ; 2. LIST directive in the source file ; LIST P=PIC18F4320 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 07 Dec 2001 Initial revision BD ;0.11 22 Mar 2002 ECCP registers and bit names revised BD ;0.12 16 Apr 2002 Configuration bit MCLRE moved from 2L to 3H BD ;0.13 22 Apr 2002 T0CON changed back to T0CON BD ;0.14 09 May 2002 ECCP1CON changed to CCP1CON BD ; ;0.15 5 May 2002 _OSO_ON_1H changed to _IESO_ON_1H BD ; _MCLRE_ON_2L moved/changed to _MCLRE_ON_3H ; ;0.16 24 May 2002 OSCCON bit name corrected BD ; OSCCON register name above bit equates fixed ; T1CON added ; _MCLRE_ON_3H moved to correct register and renamed (again) ; ;0.17 30 May 2002 _PBAD_DIG_3H had wrong bit cleared BD ;0.18 13 Jun 2002 LVDCON,IRVST added to LVDCON BD ;0.19 09/26/02 Include both names SWDTE and SWDTEN pas ; ;0.20 27 Sep 2002 Add IOFS bit name to OSCCON register BD ; Add ECIO, RCIO, INTIO1, INTIO2 bits to Config Reg 1H ; Add DEBUG bits to Config Reg 4L ; ;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD ; ;0.22 1 Oct 2003 Bit names changed BD ; LVVn to LVDLn IVRST to IRVST ; FSCMEN to FSCM ; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1, ; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0, ; CVREF,CVRSS ; Removed redundant bit names ; RCIO6 use RCIO INTIO7 use INTIO1 ; ECIO6 use ECIO INTIO67 use INTIO2 ; BKBUG use DEBUG SWDTE use SWDTEN ; T0IE use TMR0IE INT0E use INT0IE ; T0IF use TMR0IF INT0F use INT0IE ; BGST use IRVST T1INSYNC use T1SYNC ; TXD8 use TX9D T3INSYNC use T3SYNC ; TX8_9 use TX9 NOT_TX8 use TX9 ; RC9 use RX9 NOT_RC8 use RX9 ; RC8_9 use RX9 RCD8 use RX9D ; INT2P use INT2IP INT1P use INT1IP ; INT2E use INT2IE INT1E use INT1IE ; INT2F use INT2IF INT1F use INT1IF ; Added equates for PIC16 Compatability ; ADRES, INTF, INTE, CCPnX, CCPnY ; General clean-up (removed some comments) ;======================================================================= ; ; Verify Processor ; ;======================================================================= IFNDEF __18F4320 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution #define ADRES ADRESH ; PIC16 SFR substitution #define INTE INT0IE ; PIC16 bit substitution #define INTF INT0IF ; PIC16 bit substitution #define CCP1X DC1B1 ; PIC16 bit substitution #define CCP1Y DC1B0 ; PIC16 bit substitution #define CCP2X DC2B1 ; PIC16 bit substitution #define CCP2Y DC2B0 ; PIC16 bit substitution #define SCS SCS0 ; PIC18 bit substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ; reserved EQU H'0FB9' ; reserved EQU H'0FB8' PWM1CON EQU H'0FB7' ECCPAS EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ; reserved EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ; reserved EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' ; reserved EQU H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ; reserved EQU H'0F9C' ; BD OSCTUNE EQU H'0F9B' ; reserved EQU H'0F9A' ; reserved EQU H'0F99' ; reserved EQU H'0F98' ; reserved EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ; reserved EQU H'0F91' ; reserved EQU H'0F90' ; reserved EQU H'0F8F' ; reserved EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved EQU H'0F88' ; reserved EQU H'0F87' ; reserved EQU H'0F86' ; reserved EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' INT0IE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' FLTS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ---------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' D_A EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' R_W EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits ---------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ---------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ----------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ---------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- PWM1CON bits ---------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits ----------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- CVRCON Bits ----------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits ------------------------------------------------------ C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------ CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------ SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- OSCFIP EQU H'0007' CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ------------------------------------------------------- OSCFIF EQU H'0007' CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ------------------------------------------------------- OSCFIE EQU H'0007' CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- OSCTUNE Bits ---------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- TRISE Bits ------------------------------------------------------ IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 RA7 EQU 7 OSC1 EQU 7 CLKI EQU 7 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 AN12 EQU 0 RB1 EQU 1 INT1 EQU 1 AN10 EQU 1 RB2 EQU 2 INT2 EQU 2 AN8 EQU 2 RB3 EQU 3 CCP2A EQU 3 AN9 EQU 3 RB4 EQU 4 AN11 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ----------------------------------------------------------- RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 P1A EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;----- PORTD ----------------------------------------------------------- RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 P1B EQU 5 RD6 EQU 6 PSP6 EQU 6 P1C EQU 6 RD7 EQU 7 PSP7 EQU 7 P1D EQU 7 ;----- PORTE ----------------------------------------------------------- RE0 EQU 0 RD EQU 0 AN5 EQU 0 RE1 EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 AN7 EQU 2 RE3 EQU 3 MCLR EQU 3 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'200'-H'F7F' __BADRAM H'F85'-H'F88',H'F8E'-H'F91',H'F97'-H'F9A',H'F9C' __BADRAM H'FA3'-H'FA5',H'FAA',H'FB0',H'FB8'-H'FB9' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = EC External Clock on OSC1, OSC2 as FOSC/4 ; OSC = ECIO External Clock on OSC1, OSC2 as RA6 ; OSC = HSPLL HS + PLL ; OSC = RCIO External RC on OSC1, OSC2 as RA6 ; OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6 ; OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4 ; OSC = RC External RC on OSC1, OSC2 as FOSC/4 ; ; Fail-Safe Clock Monitor: ; FSCM = OFF Fail-Safe Clock Monitor disabled ; FSCM = ON Fail-Safe Clock Monitor enabled ; ; Internal External Switch Over mode: ; IESO = OFF Internal External Switch Over mode disabled ; IESO = ON Internal External Switch Over mode enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; PORTB A/D Enable: ; PBAD = DIG Digital ; PBAD = ANA Analog ; ; CCP2 Pin Function: ; CCP2MX = B3 RB3 ; CCP2MX = OFF RB3 ; CCP2MX = C1 RC1 ; CCP2MX = ON RC1 ; ; Stack Full/Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To embed the Configuration Bits in your source code, paste the ; following lines into your source code in the following format, ; and change the configuration value to the desired setting (such ; as WDT_OFF to WDT_ON). ; These lines are commented out - each __CONFIG line should have the ; preceding semicolon (;) removed when pasted into your source code. ; __CONFIG _CONFIG1H, _IESO_OFF_1H & _FSCM_OFF_1H & _RC_OSC_1H ; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_20_2L ; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H ; __CONFIG _CONFIG3H, _MCLRE_ON_3H & _PBAD_DIG_3H & _CCP2MX_C1_3H ; __CONFIG _CONFIG4L, _DEBUG_OFF_4L & _LVP_OFF_4L & _STVR_OFF_4L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 1H Options _IESO_ON_1H EQU H'FF' ; Internal External oscillator Switch Over mode enabled _IESO_OFF_1H EQU H'7F' ; Internal External oscillator Switch Over mode disabled _FSCM_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _FSCM_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as FOSC/4 _RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6 _LP_OSC_1H EQU H'F0' ; LP Oscillator _XT_OSC_1H EQU H'F1' ; XT Oscillator _HS_OSC_1H EQU H'F2' ; HS Oscillator _HSPLL_OSC_1H EQU H'F6' ; HS + PLL _EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as FOSC/4 _ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6 _INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4 _INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _PWRT_OFF_2L EQU H'FF' ; Power-up Timer disabled _PWRT_ON_2L EQU H'FE' ; Power-up Timer enabled ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled _WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio _WDTPS_16K_2H EQU H'FD' ; 1:16,384 _WDTPS_8K_2H EQU H'FB' ; 1: 8,192 _WDTPS_4K_2H EQU H'F9' ; 1: 4,096 _WDTPS_2K_2H EQU H'F7' ; 1: 2,048 _WDTPS_1K_2H EQU H'F5' ; 1: 1,024 _WDTPS_512_2H EQU H'F3' ; 1: 512 _WDTPS_256_2H EQU H'F1' ; 1: 256 _WDTPS_128_2H EQU H'EF' ; 1: 128 _WDTPS_64_2H EQU H'ED' ; 1: 64 _WDTPS_32_2H EQU H'EB' ; 1: 32 _WDTPS_16_2H EQU H'E9' ; 1: 16 _WDTPS_8_2H EQU H'E7' ; 1: 8 _WDTPS_4_2H EQU H'E5' ; 1: 4 _WDTPS_2_2H EQU H'E3' ; 1: 2 _WDTPS_1_2H EQU H'E1' ; 1: 1 ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'FF' ; MCLR enabled, RE3 input disabled _MCLRE_OFF_3H EQU H'7F' ; MCLR disabled, RE3 input enabled _PBAD_ANA_3H EQU H'FF' ; ADCON<3:0> resets to B'0000' _PBAD_DIG_3H EQU H'FD' ; ADCON<3:0> resets to B'0111' _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin function on RC1 _CCP2MX_OFF_3H EQU H'FE' ; CCP2 pin function on RB3 _CCP2MX_C1_3H EQU H'FF' ; CCP2 pin function on RC1 (alt defn) _CCP2MX_B3_3H EQU H'FE' ; CCP2 pin function on RB3 (alt defn) ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; DEBUGger enabled _DEBUG_OFF_4L EQU H'FF' ; DEBUGger disabled _LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled _LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP0_ON_5L EQU H'FE' ; Block 0 protected _CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable _CP1_ON_5L EQU H'FD' ; Block 1 protected _CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable _CP2_ON_5L EQU H'FB' ; Block 2 protected _CP2_OFF_5L EQU H'FF' ; Block 2 readable/ may be writable _CP3_ON_5L EQU H'F7' ; Block 3 protected _CP3_OFF_5L EQU H'FF' ; Block 3 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'BF' ; Boot Block protected _CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'7F' ; Data EE memory protected _CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT0_ON_6L EQU H'FE' ; Block 0 write protected _WRT0_OFF_6L EQU H'FF' ; Block 0 writable _WRT1_ON_6L EQU H'FD' ; Block 1 write protected _WRT1_OFF_6L EQU H'FF' ; Block 1 writable _WRT2_ON_6L EQU H'FB' ; Block 2 write protected _WRT2_OFF_6L EQU H'FF' ; Block 2 writable _WRT3_ON_6L EQU H'F7' ; Block 3 write protected _WRT3_OFF_6L EQU H'FF' ; Block 3 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'DF' ; Config registers write protected _WRTC_OFF_6H EQU H'FF' ; Config registers writable _WRTB_ON_6H EQU H'BF' ; Boot block write protected _WRTB_OFF_6H EQU H'FF' ; Boot block writable _WRTD_ON_6H EQU H'7F' ; Data EE write protected _WRTD_OFF_6H EQU H'FF' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR0_ON_7L EQU H'FE' ; Block 0 protected _EBTR0_OFF_7L EQU H'FF' ; Block 0 readable _EBTR1_ON_7L EQU H'FD' ; Block 1 protected _EBTR1_OFF_7L EQU H'FF' ; Block 1 readable _EBTR2_ON_7L EQU H'FB' ; Block 2 protected _EBTR2_OFF_7L EQU H'FF' ; Block 2 readable _EBTR3_ON_7L EQU H'F7' ; Block 3 protected _EBTR3_OFF_7L EQU H'FF' ; Block 3 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'BF' ; Boot block read protected _EBTRB_OFF_7H EQU H'FF' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p18f26j50.inc0000644000175000017500000016631011156521301013404 00000000000000 LIST ;========================================================================== ; MPASM PIC18F26J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F26J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F26J50 ; 2. LIST directive in the source file ; LIST P=PIC18F26J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F26J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F5F' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c923.inc0000644000175000017500000002633611156313161013154 00000000000000 LIST ; P16C923.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C923 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C923 ; 2. LIST directive in the source file ; LIST P=PIC16C923 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 09/13/01 Added the SSPSTAT bits CKE and SMP ;1.02 04/23/00 Added LCD controller bits ;1.01 05/12/97 Corrected ports F and G addresses ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C923 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' PORTF EQU H'0107' PORTG EQU H'0108' LCDSE EQU H'010D' LCDPS EQU H'010E' LCDCON EQU H'010F' LCDD00 EQU H'0110' LCDD01 EQU H'0111' LCDD02 EQU H'0112' LCDD03 EQU H'0113' LCDD04 EQU H'0114' LCDD05 EQU H'0115' LCDD06 EQU H'0116' LCDD07 EQU H'0117' LCDD08 EQU H'0118' LCDD09 EQU H'0119' LCDD10 EQU H'011A' LCDD11 EQU H'011B' LCDD12 EQU H'011C' LCDD13 EQU H'011D' LCDD14 EQU H'011E' LCDD15 EQU H'011F' TRISF EQU H'0187' TRISG EQU H'0188' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- LCDIF EQU H'0007' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- LCDIE EQU H'0007' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- LCDSE Bits --------------------------------------------------------- SE29 EQU H'0007' SE27 EQU H'0006' SE20 EQU H'0005' SE16 EQU H'0004' SE12 EQU H'0003' SE9 EQU H'0002' SE5 EQU H'0001' SE0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' VGEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'0D', H'18'-H'1F' __BADRAM H'8D', H'8F'-H'91', H'95'-H'9F' __BADRAM H'105', H'109', H'10C', H'120'-H'16F' __BADRAM H'185', H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f6620.inc0000644000175000017500000011006611156313161013233 00000000000000 LIST ; P18F6620.INC Standard Header File, Version .1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F6620 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F6620 ; 2. LIST directive in the source file ; LIST P=PIC18F6620 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ; 1.09 10/12/04 Added SPBRG, TXREG, TXSTA and RCSTA src ; 1.08 09/26/02 Include both names SWDTE and SWDTEN pas ; 1.07 11/16/2001 Changed CVREF_CVRCON => CVRSS, ADEN => ADDEN pas ; 1.06 10/23/01 Corrected CONFIG bits/registers, LVDCON bits tr/pas ; 1.05 10/08/01 Corrected names of T2CON and T4CON bits ; (TOUTPS3 => T2OUTPS3 and T4OUTPS3, etc.) pas ; 1.04 10/03/01 Changed T0CON bit 3 name from T0PS3 to PSA. pas ; 1.03 10/01/01 Added definitions of the CCP4, CCP5, TMR4, and ; USART2 registers (0x0F6B to 0x0F78); corrected names ; of INTCON3 bits (i.e., INT2P => INT2IP). pas ; 1.02 09/18/01 Some bits have identical names in the data sheet; ; for instance, CCP2 in PORTB and CCP2 in PORTC. ; The assembler does not allow multiple definitions of ; the same name, however. So I postfixed these names ; with the name of the register to make them ; unique. (Now we have CCP2_PORTB and CCP2_PORTC). pas ; 1.01 09/14/01 Preliminary release tr ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6620 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution #define DDRF TRISF ; PIC17Cxxx SFR substitution #define DDRG TRISG ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' CCPR3H EQU H'0FB9' CCPR3L EQU H'0FB8' CCP3CON EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' RCREG1 EQU H'0FAE' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' EEADRH EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TMR4 EQU H'0F78' PR4 EQU H'0F77' T4CON EQU H'0F76' CCPR4H EQU H'0F75' CCPR4L EQU H'0F74' CCP4CON EQU H'0F73' CCPR5H EQU H'0F72' CCPR5L EQU H'0F71' CCP5CON EQU H'0F70' SPBRG2 EQU H'0F6F' RCREG2 EQU H'0F6E' TXREG2 EQU H'0F6D' TXSTA2 EQU H'0F6C' RCSTA2 EQU H'0F6B' ;----- STKPTR Bits -------------------------------------------------------- STKOVF EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' INTEDG3 EQU H'0003' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF INT3P EQU H'0001' RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT3IE EQU H'0005' INT2IE EQU H'0004' INT1IE EQU H'0003' INT3IF EQU H'0002' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- T2OUTPS3 EQU H'0006' T2OUTPS2 EQU H'0005' T2OUTPS1 EQU H'0004' T2OUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DCCP1X EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DCCP1Y EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DCCP2X EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCP2Y EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- DCCP3X EQU H'0005' DCCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- CCP4CON Bits ------------------------------------------------------- DCCP4X EQU H'0005' DCCP4Y EQU H'0004' CCP4M3 EQU H'0003' CCP4M2 EQU H'0002' CCP4M1 EQU H'0001' CCP4M0 EQU H'0000' ;----- CCP5CON Bits ------------------------------------------------------- DCCP5X EQU H'0005' DCCP5Y EQU H'0004' CCP5M3 EQU H'0003' CCP5M2 EQU H'0002' CCP5M1 EQU H'0001' CCP5M0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVRSS EQU H'0004' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT_CMCON EQU H'0007' C1OUT_CMCON EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- T4CON Bits --------------------------------------------------------- T4OUTPS3 EQU H'0006' T4OUTPS2 EQU H'0005' T4OUTPS1 EQU H'0004' T4OUTPS0 EQU H'0003' TMR4ON EQU H'0002' T4CKPS1 EQU H'0001' T4CKPS0 EQU H'0000' ;----- TXSTA, TXSTA1 and TXSTA2 Bits -------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA, RCSTA1 and RCSTA2 Bits -------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR3 Bits ---------------------------------------------------------- RC2IP EQU H'0005' TX2IP EQU H'0004' TMR4IP EQU H'0003' CCP5IP EQU H'0002' CCP4IP EQU H'0001' CCP3IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- RC2IF EQU H'0005' TX2IF EQU H'0004' TMR4IF EQU H'0003' CCP5IF EQU H'0002' CCP4IF EQU H'0001' CCP3IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- RC2IE EQU H'0005' TX2IE EQU H'0004' TMR4IE EQU H'0003' CCP5IE EQU H'0002' CCP4IE EQU H'0001' CCP3IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' RC1IP EQU H'0005' TX1IP EQU H'0004' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' RC1IF EQU H'0005' TX1IF EQU H'0004' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' RC1IE EQU H'0005' TX1IE EQU H'0004' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- MEMCON Bits -------------------------------------------------------- EBDIS EQU H'0007' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 INT3 EQU 3 RB4 EQU 4 KBI0 EQU 4 RB5 EQU 5 KBI1 EQU 5 PGM EQU 5 RB6 EQU 6 KBI2 EQU 6 PGC EQU 6 RB7 EQU 7 KBI3 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T13CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 RE1 EQU 1 WR EQU 1 RE2 EQU 2 CS EQU 2 RE3 EQU 3 RE4 EQU 4 RE5 EQU 5 RE6 EQU 6 RE7 EQU 7 CCP2C EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 C2OUT EQU 1 RF2 EQU 2 AN7 EQU 2 C1OUT EQU 2 RF3 EQU 3 AN8 EQU 3 RF4 EQU 4 AN9 EQU 4 RF5 EQU 5 AN10 EQU 5 CVREF EQU 5 RF6 EQU 6 AN11 EQU 6 RF7 EQU 7 SS EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 CCP3 EQU 0 RG1 EQU 1 TX2 EQU 1 CK2 EQU 1 RG2 EQU 2 RX2 EQU 2 DT2 EQU 2 RG3 EQU 3 CCP4 EQU 3 RG4 EQU 4 CCP5 EQU 4 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'F00'-H'F6A' __BADRAM H'F79'-H'F7F' __BADRAM H'F9B',H'FB6',H'FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disabled ; CCP2MUX = ON Enabled ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3L Options _MC_MODE_3L EQU H'FF' ; Processor Mode Select bits _MP_MODE_3L EQU H'FE' _MPB_MODE_3L EQU H'FD' _XMC_MODE_3L EQU H'FC' _WAIT_ON_3L EQU H'7F' ; External Bus Data Wait Enable _WAIT_OFF_3L EQU H'FF' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' _CP4_ON_5L EQU H'EF' _CP4_OFF_5L EQU H'FF' _CP5_ON_5L EQU H'DF' _CP5_OFF_5L EQU H'FF' _CP6_ON_5L EQU H'BF' _CP6_OFF_5L EQU H'FF' _CP7_ON_5L EQU H'7F' _CP7_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' _WRT4_ON_6L EQU H'EF' _WRT4_OFF_6L EQU H'FF' _WRT5_ON_6L EQU H'DF' _WRT5_OFF_6L EQU H'FF' _WRT6_ON_6L EQU H'BF' _WRT6_OFF_6L EQU H'FF' _WRT7_ON_6L EQU H'7F' _WRT7_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' _EBTR4_ON_7L EQU H'EF' _EBTR4_OFF_7L EQU H'FF' _EBTR5_ON_7L EQU H'DF' _EBTR5_OFF_7L EQU H'FF' _EBTR6_ON_7L EQU H'BF' _EBTR6_OFF_7L EQU H'FF' _EBTR7_ON_7L EQU H'7F' _EBTR7_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3L ; __CONFIG _CONFIG3L, _WAIT_OFF_3L & _MC_MODE_3L ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L & _CP4_OFF_5L & _CP5_OFF_5L & _CP6_OFF_5L & _CP7_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L & _WRT4_OFF_6L & _WRT5_OFF_6L & _WRT6_OFF_6L & _WRT7_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L & _EBTR4_OFF_7L & _EBTR5_OFF_7L & _EBTR6_OFF_7L & _EBTR7_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p16cr65.inc0000644000175000017500000002677511156313161013262 00000000000000 LIST ; P16CR65.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR65 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR65 ; 2. LIST directive in the source file ; LIST P=PIC16CR65 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/27/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR65 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f8410.inc0000644000175000017500000013507211156521301013233 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8410 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8410 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8410 ; 2. LIST directive in the source file ; LIST P=PIC18F8410 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8410 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DCCP3Y EQU H'0004' DCCP3X EQU H'0005' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F70'-H'0F7D' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; PM = EM Extended Microcontroller mode ; PM = MPB Microprocessor with Boot Block mode ; PM = MP Microprocessor mode ; PM = MC Microcontroller mode ; ; External Bus Data Width Select bit: ; BW = 8 8-bit External Bus Data Width ; BW = 16 16-bit External Bus Data Width ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) ; WAIT = OFF Wait selections unavailable, device will not wait ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block code-protected ; CP = OFF Program memory block not code-protected ; ; Table Read Protection bit: ; EBTR = ON Internal program memory block protected from table reads executed from external memory block ; EBTR = OFF Internal program memory block not protected from table reads executed from external memory block ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG7L 30000Ch ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG7L EQU H'30000C' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _PM_EM_3L EQU H'FC' ; Extended Microcontroller mode _PM_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _PM_MP_3L EQU H'FE' ; Microprocessor mode _PM_MC_3L EQU H'FF' ; Microcontroller mode _BW_8_3L EQU H'BF' ; 8-bit External Bus Data Width _BW_16_3L EQU H'FF' ; 16-bit External Bus Data Width _WAIT_ON_3L EQU H'7F' ; Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) _WAIT_OFF_3L EQU H'FF' ; Wait selections unavailable, device will not wait ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block code-protected _CP_OFF_5L EQU H'FF' ; Program memory block not code-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR_ON_7L EQU H'FE' ; Internal program memory block protected from table reads executed from external memory block _EBTR_OFF_7L EQU H'FF' ; Internal program memory block not protected from table reads executed from external memory block _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c74b.inc0000644000175000017500000003070011156313161013221 00000000000000 LIST ; P16C74B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C74B microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C74B ; 2. LIST directive in the source file ; LIST P=PIC16C74B ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/17/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C74B MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16hv616.inc0000644000175000017500000004024011156521301013331 00000000000000 LIST ; P16HV616.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; Based on P16F616.INC ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16HV616 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16HV616 ; 2. LIST directive in the source file ; LIST P=PIC16HV616 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 09/12/05 Original ;1.01 12/04/06 Added WPU, BOR and IOC aliases ;1.02 12/06/06 Added FVREN bit to VRCON ;1.03 01/15/07 Added PORTA, PORTC, TRISA & TRISC bits ;1.04 04/16/07 Added ADCON1 bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16HV616 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' PWM1CON EQU H'0016' ECCPAS EQU H'0017' VRCON EQU H'0019' CM1CON0 EQU H'001A' CM2CON0 EQU H'001B' CM2CON1 EQU H'001C' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' SRCON EQU H'0099' SRCON0 EQU H'0099' SRCON1 EQU H'009A' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- PORTC Bits --------------------------------------------------------- RC5 EQU H'0005' RC4 EQU H'0004' RC3 EQU H'0003' RC2 EQU H'0002' RC1 EQU H'0001' RC0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- VRCON Bits ------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' FVREN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1ACS EQU H'0004' C1HYS EQU H'0003' C2HYS EQU H'0002' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISC Bits -------------------------------------------------------- TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- WPU Bits --------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- SRCON0 Bits ------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' SRCLKEN EQU H'0000' ;----- SRCON1 Bits ------------------------------------------------------- SRCS1 EQU H'0007' SRCS0 EQU H'0006' ;----- ADCON1 Bits ------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'18', H'1D' __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'93'-H'94', H'97'-H'98', H'9B'-H'9D', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOD_ON EQU H'3FFF' _BOR_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOR_NSLEEP EQU H'3EFF' _BOD_OFF EQU H'3CFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f24k20.inc0000644000175000017500000012477311156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F24K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F24K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F24K20 ; 2. LIST directive in the source file ; LIST P=PIC18F24K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F24K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' P1C EQU H'0001' P1B EQU H'0002' P1D EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16hv785.inc0000644000175000017500000004276711156521301013360 00000000000000 LIST ; P16HV785.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; Based on P16F785.INC ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16HV785 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16HV785 ; 2. LIST directive in the source file ; LIST P=PIC16HV785 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 03/26/04 Original ;1.10 07/12/04 Updated for changes to REFCON and VRCON ;1.20 08/26/04 Updated for changes from BOD to BOR ;1.30 09/23/04 Corrected addresses for OPA1CON and OPA2CON ;1.40 10/25/04 Added WPUA3 bit to WPUA register ; Deleted OVRLP bit from PWMCON1 register ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16HV785 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' WDTCON EQU H'0018' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' ANSEL0 EQU H'0091' PR2 EQU H'0092' ANSEL1 EQU H'0093' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' REFCON EQU H'0098' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' PWMCON1 EQU H'0110' PWMCON0 EQU H'0111' PWMCLK EQU H'0112' PWMPH1 EQU H'0113' PWMPH2 EQU H'0114' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' OPA1CON EQU H'011C' OPA2CON EQU H'011D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CCP1IF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' OSFIF EQU H'0002' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CCP1IE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' OSFIE EQU H'0002' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBODEN EQU H'0004' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits or ANSEL0 Bits ------------------------------------------ ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSEL1 Bits -------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA3 EQU H'0003' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- BGST EQU H'0005' VRBB EQU H'0004' VREN EQU H'0003' VROE EQU H'0002' CVROE EQU H'0001' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- PWMCON1 Bits -------------------------------------------------------- COMOD1 EQU H'0006' COMOD0 EQU H'0005' CMDLY4 EQU H'0004' CMDLY3 EQU H'0003' CMDLY2 EQU H'0002' CMDLY1 EQU H'0001' CMDLY0 EQU H'0000' ;----- PWMCON0 Bits -------------------------------------------------------- PRSEN EQU H'0007' PASEN EQU H'0006' BLANK2 EQU H'0005' BLANK1 EQU H'0004' SYNC1 EQU H'0003' SYNC0 EQU H'0002' PH2EN EQU H'0001' PH1EN EQU H'0000' ;----- PWMCLK Bits -------------------------------------------------------- PWMASE EQU H'0007' PWMP1 EQU H'0006' PWMP0 EQU H'0005' PER4 EQU H'0004' PER3 EQU H'0003' PER2 EQU H'0002' PER1 EQU H'0001' PER0 EQU H'0000' ;----- PWMPH1 Bits & PWMPH2 Bits ------------------------------------------ POL EQU H'0007' C2EN EQU H'0006' C1EN EQU H'0005' PH4 EQU H'0004' PH3 EQU H'0003' PH2 EQU H'0002' PH1 EQU H'0001' PH0 EQU H'0000' ;----- CM1CON0 Bits -------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1SP EQU H'0003' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits -------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2SP EQU H'0003' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits -------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- OPA1CON Bits & OPA2CON Bits ----------------------------------------- OPAON EQU H'0007' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'0D', H'16'-H'17', H'19'-H'1D' __BADRAM H'88'-H'89', H'8D', H'94', H'97', H'C0'-H'EF' __BADRAM H'108'-H'109', H'10C'-H'10F', H'115'-H'118', H'11E'-H'16F' __BADRAM H'188'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBOREN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18lf44j50.inc0000644000175000017500000017226211156521302013564 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF44J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF44J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF44J50 ; 2. LIST directive in the source file ; LIST P=PIC18LF44J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF44J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region: ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18c658.inc0000644000175000017500000014357211156313161013165 00000000000000 LIST ; P18C658.INC Standard Header File, Version 0.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C658 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C658 ; 2. LIST directive in the source file ; LIST P=PIC18C658 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ; Rev: Date: Details: Who: ; 0.01 15 May 2000 Modified from 958 dj ; 0.02 06 Jun 2000 Fixed typos fn ; 0.03 11 Oct 2000 Matched register, configuration defs with nr ; PIC18CXX8 datasheet, fixed RXM1EIDH ; address mismatch ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C658 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' ;RESERVED_0FA7 EQU H'0FA7' ;RESERVED_0FA6 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;TRISJ EQU H'0F9A' ;TRISH EQU H'0F99' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;DDRJ EQU H'0F9A' ;DDRH EQU H'0F99' DDRG EQU H'0F98' DDRF EQU H'0F97' DDRE EQU H'0F96' DDRD EQU H'0F95' DDRC EQU H'0F94' DDRB EQU H'0F93' DDRA EQU H'0F92' ;LATJ EQU H'0F91' ;LATH EQU H'0F90' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;PORTJ EQU H'0F88' ;PORTH EQU H'0F87' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;TRISK EQU H'0F7F' ;DDRK EQU H'0F7F' ;LATK EQU H'0F7E' ;PORTK EQU H'0F7D' ;TRISL EQU H'0F7C' ;DDRL EQU H'0F7C' ;LATL EQU H'0F7B' ;PORTL EQU H'0F7A' ;RESERVED_0F79 EQU H'0F79' ;RESERVED_0F78 EQU H'0F78' ;RESERVED_0F77 EQU H'0F77' TXERRCNT EQU H'0F76' RXERRCNT EQU H'0F75' COMSTAT EQU H'0F74' CIOCON EQU H'0F73' BRGCON3 EQU H'0F72' BRGCON2 EQU H'0F71' BRGCON1 EQU H'0F70' CANCON EQU H'0F6F' CANSTAT EQU H'0F6E' RXB0D7 EQU H'0F6D' RXB0D6 EQU H'0F6C' RXB0D5 EQU H'0F6B' RXB0D4 EQU H'0F6A' RXB0D3 EQU H'0F69' RXB0D2 EQU H'0F68' RXB0D1 EQU H'0F67' RXB0D0 EQU H'0F66' RXB0DLC EQU H'0F65' RXB0EIDL EQU H'0F64' RXB0EIDH EQU H'0F63' RXB0SIDL EQU H'0F62' RXB0SIDH EQU H'0F61' RXB0CON EQU H'0F60' ;RESERVED_0F5F EQU H'0F5F' CANSTAT_RO1 EQU H'0F5E' ;CANSTAT is repeated RXB1D7 EQU H'0F5D' RXB1D6 EQU H'0F5C' RXB1D5 EQU H'0F5B' RXB1D4 EQU H'0F5A' RXB1D3 EQU H'0F59' RXB1D2 EQU H'0F58' RXB1D1 EQU H'0F57' RXB1D0 EQU H'0F56' RXB1DLC EQU H'0F55' RXB1EIDL EQU H'0F54' RXB1EIDH EQU H'0F53' RXB1SIDL EQU H'0F52' RXB1SIDH EQU H'0F51' RXB1CON EQU H'0F50' ;RESERVED_0F4F EQU H'0F4F' CANSTAT_RO2 EQU H'0F4E' ;CANSTAT is repeated TXB0D7 EQU H'0F4D' TXB0D6 EQU H'0F4C' TXB0D5 EQU H'0F4B' TXB0D4 EQU H'0F4A' TXB0D3 EQU H'0F49' TXB0D2 EQU H'0F48' TXB0D1 EQU H'0F47' TXB0D0 EQU H'0F46' TXB0DLC EQU H'0F45' TXB0EIDL EQU H'0F44' TXB0EIDH EQU H'0F43' TXB0SIDL EQU H'0F42' TXB0SIDH EQU H'0F41' TXB0CON EQU H'0F40' ;RESERVED_0F3F EQU H'0F3F' CANSTAT_RO3 EQU H'0F3E' ;CANSTAT is repeated TXB1D7 EQU H'0F3D' TXB1D6 EQU H'0F3C' TXB1D5 EQU H'0F3B' TXB1D4 EQU H'0F3A' TXB1D3 EQU H'0F39' TXB1D2 EQU H'0F38' TXB1D1 EQU H'0F37' TXB1D0 EQU H'0F36' TXB1DLC EQU H'0F35' TXB1EIDL EQU H'0F34' TXB1EIDH EQU H'0F33' TXB1SIDL EQU H'0F32' TXB1SIDH EQU H'0F31' TXB1CON EQU H'0F30' ;RESERVED_0F2F EQU H'0F2F' CANSTAT_RO4 EQU H'0F2E' ;CANSTAT is repeated TXB2D7 EQU H'0F2D' TXB2D6 EQU H'0F2C' TXB2D5 EQU H'0F2B' TXB2D4 EQU H'0F2A' TXB2D3 EQU H'0F29' TXB2D2 EQU H'0F28' TXB2D1 EQU H'0F27' TXB2D0 EQU H'0F26' TXB2DLC EQU H'0F25' TXB2EIDL EQU H'0F24' TXB2EIDH EQU H'0F23' TXB2SIDL EQU H'0F22' TXB2SIDH EQU H'0F21' TXB2CON EQU H'0F20' RXM1EIDL EQU H'0F1F' RXM1EIDH EQU H'0F1E' RXM1SIDL EQU H'0F1D' RXM1SIDH EQU H'0F1C' RXM0EIDL EQU H'0F1B' RXM0EIDH EQU H'0F1A' RXM0SIDL EQU H'0F19' RXM0SIDH EQU H'0F18' RXF5EIDL EQU H'0F17' RXF5EIDH EQU H'0F16' RXF5SIDL EQU H'0F15' RXF5SIDH EQU H'0F14' RXF4EIDL EQU H'0F13' RXF4EIDH EQU H'0F12' RXF4SIDL EQU H'0F11' RXF4SIDH EQU H'0F10' RXF3EIDL EQU H'0F0F' RXF3EIDH EQU H'0F0E' RXF3SIDL EQU H'0F0D' RXF3SIDH EQU H'0F0C' RXF2EIDL EQU H'0F0B' RXF2EIDH EQU H'0F0A' RXF2SIDL EQU H'0F09' RXF2SIDH EQU H'0F08' RXF1EIDL EQU H'0F07' RXF1EIDH EQU H'0F06' RXF1SIDL EQU H'0F05' RXF1SIDH EQU H'0F04' RXF0EIDL EQU H'0F03' RXF0EIDH EQU H'0F02' RXF0SIDL EQU H'0F01' RXF0SIDH EQU H'0F00' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' STKPTR4 EQU H'0004' STKPTR3 EQU H'0003' STKPTR2 EQU H'0002' STKPTR1 EQU H'0001' STKPTR0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' INTEDG3 EQU h'0003' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF INT3P EQU H'0001' RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT3IE EQU H'0005' INT3E EQU H'0005' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT3IF EQU H'0002' INT3F EQU H'0002' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_IPEN EQU H'0007' LWRT EQU H'0006' NOT_LWRT EQU H'0006' RI EQU H'0004' NOT_RI EQU H'0004' TO EQU H'0003' NOT_TO EQU H'0003' PD EQU H'0002' NOT_PD EQU H'0002' POR EQU H'0001' NOT_POR EQU H'0001' BOR EQU H'0000' NOT_BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCPX EQU H'0005' DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- VRCON Bits ------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CMCON Bits ------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' T3SYNC EQU H'0002' NOT_T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- IPR3 Bits ------------------------------------------------------- IRXIP EQU H'0007' WAKIP EQU H'0006' ERRIP EQU H'0005' TXB2IP EQU H'0004' TXB1IP EQU H'0003' TXB0IP EQU H'0002' RXB1IP EQU H'0001' RXB0IP EQU H'0000' ;----- PIR3 Bits ------------------------------------------------------- IRXIF EQU H'0007' WAKIF EQU H'0006' ERRIF EQU H'0005' TXB2IF EQU H'0004' TXB1IF EQU H'0003' TXB0IF EQU H'0002' RXB1IF EQU H'0001' RXB0IF EQU H'0000' ;----- PIE3 Bits ------------------------------------------------------- IRXIE EQU H'0007' WAKIE EQU H'0006' ERRIE EQU H'0005' TXB2IE EQU H'0004' TXB1IE EQU H'0003' TXB0IE EQU H'0002' RXB1IE EQU H'0001' RXB0IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- MEMCON Bits ---------------------------------------------------------- EBDIS EQU H'0007' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;----- TXERRCNT Bits ---------------------------------------------------------- TEC7 EQU H'0007' TEC6 EQU H'0006' TEC5 EQU H'0005' TEC4 EQU H'0004' TEC3 EQU H'0003' TEC2 EQU H'0002' TEC1 EQU H'0001' TEC0 EQU H'0000' ;----- RXERRCNT Bits ---------------------------------------------------------- REC7 EQU H'0007' REC6 EQU H'0006' REC5 EQU H'0005' REC4 EQU H'0004' REC3 EQU H'0003' REC2 EQU H'0002' REC1 EQU H'0001' REC0 EQU H'0000' ;----- COMSTAT Bits ---------------------------------------------------------- RXB0OVFL EQU H'0007' RXB1OVFL EQU H'0006' TXBO EQU H'0005' TXBP EQU H'0004' RXBP EQU H'0003' TXWARN EQU H'0002' RXWARN EQU H'0001' EWARN EQU H'0000' ;----- TXBxDLC ---------------------------------------------------------- TXRTR EQU H'0006' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DCL0 EQU H'0000' ;----- CIOCON Bits ---------------------------------------------------------- TX1SRC EQU H'0007' TX1EN EQU H'0006' ENDRHI EQU H'0005' CANCAP EQU H'0004' ;----- BRGCON1 Bits ---------------------------------------------------------- SJW1 EQU H'0007' SJW0 EQU H'0006' BRP5 EQU H'0005' BRP4 EQU H'0004' BRP3 EQU H'0003' BRP2 EQU H'0002' BRP1 EQU H'0001' BRP0 EQU H'0000' ;----- BRGCON2 Bits ---------------------------------------------------------- SEG2PHTS EQU H'0007' SAM EQU H'0006' SEG1PH2 EQU H'0005' SEG1PH1 EQU H'0004' SEG1PH0 EQU H'0003' PRSEG2 EQU H'0002' PRSEG1 EQU H'0001' PRSEG0 EQU H'0000' ;----- BRGCON3 Bits ---------------------------------------------------------- WAKFIL EQU H'0006' SEG2PH2 EQU H'0002' SEG2PH1 EQU H'0001' SEG2PH0 EQU H'0000' ;----- CANCON Bits ---------------------------------------------------------- REQOP2 EQU H'0007' REQOP1 EQU H'0006' REQOP0 EQU H'0005' ABAT EQU H'0004' WIN2 EQU H'0003' WIN1 EQU H'0002' WIN0 EQU H'0001' ;----- CANSTAT Bits ---------------------------------------------------------- OPMODE2 EQU H'0007' OPMODE1 EQU H'0006' OPMODE0 EQU H'0005' ICODE2 EQU H'0003' ICODE1 EQU H'0002' ICODE0 EQU H'0001' ;----- RXFxSIDL Bits ---------------------------------------------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' EXIDE EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXB0D7 Bits ---------------------------------------------------------- RB0D77 EQU H'0007' RB0D76 EQU H'0006' RB0D75 EQU H'0005' RB0D74 EQU H'0004' RB0D73 EQU H'0003' RB0D72 EQU H'0002' RB0D71 EQU H'0001' RB0D70 EQU H'0000' ;----- RXB0D6 Bits ---------------------------------------------------------- RB0D67 EQU H'0007' RB0D66 EQU H'0006' RB0D65 EQU H'0005' RB0D64 EQU H'0004' RB0D63 EQU H'0003' RB0D62 EQU H'0002' RB0D61 EQU H'0001' RB0D60 EQU H'0000' ;----- RXB0D5 Bits ---------------------------------------------------------- RB0D57 EQU H'0007' RB0D56 EQU H'0006' RB0D55 EQU H'0005' RB0D54 EQU H'0004' RB0D53 EQU H'0003' RB0D52 EQU H'0002' RB0D51 EQU H'0001' RB0D50 EQU H'0000' ;----- RXB0D4 Bits ---------------------------------------------------------- RB0D47 EQU H'0007' RB0D46 EQU H'0006' RB0D45 EQU H'0005' RB0D44 EQU H'0004' RB0D43 EQU H'0003' RB0D42 EQU H'0002' RB0D41 EQU H'0001' RB0D40 EQU H'0000' ;----- RXB0D3 Bits ---------------------------------------------------------- RB0D37 EQU H'0007' RB0D36 EQU H'0006' RB0D35 EQU H'0005' RB0D34 EQU H'0004' RB0D33 EQU H'0003' RB0D32 EQU H'0002' RB0D31 EQU H'0001' RB0D30 EQU H'0000' ;----- RXB0D2 Bits ---------------------------------------------------------- RB0D27 EQU H'0007' RB0D26 EQU H'0006' RB0D25 EQU H'0005' RB0D24 EQU H'0004' RB0D23 EQU H'0003' RB0D22 EQU H'0002' RB0D21 EQU H'0001' RB0D20 EQU H'0000' ;----- RXB0D1 Bits ---------------------------------------------------------- RB0D17 EQU H'0007' RB0D16 EQU H'0006' RB0D15 EQU H'0005' RB0D14 EQU H'0004' RB0D13 EQU H'0003' RB0D12 EQU H'0002' RB0D11 EQU H'0001' RB0D10 EQU H'0000' ;----- RXB0D0 Bits ---------------------------------------------------------- RB0D07 EQU H'0007' RB0D06 EQU H'0006' RB0D05 EQU H'0005' RB0D04 EQU H'0004' RB0D03 EQU H'0003' RB0D02 EQU H'0002' RB0D01 EQU H'0001' RB0D00 EQU H'0000' ;----- RXB1D7 Bits ---------------------------------------------------------- RXB1D77 EQU H'0007' RXB1D76 EQU H'0006' RXB1D75 EQU H'0005' RXB1D74 EQU H'0004' RXB1D73 EQU H'0003' RXB1D72 EQU H'0002' RXB1D71 EQU H'0001' RXB1D70 EQU H'0000' ;----- RXB1D6 Bits ---------------------------------------------------------- RXB1D67 EQU H'0007' RXB1D66 EQU H'0006' RXB1D65 EQU H'0005' RXB1D64 EQU H'0004' RXB1D63 EQU H'0003' RXB1D62 EQU H'0002' RXB1D61 EQU H'0001' RXB1D60 EQU H'0000' ;----- RXB1D5 Bits ---------------------------------------------------------- RXB1D57 EQU H'0007' RXB1D56 EQU H'0006' RXB1D55 EQU H'0005' RXB1D54 EQU H'0004' RXB1D53 EQU H'0003' RXB1D52 EQU H'0002' RXB1D51 EQU H'0001' RXB1D50 EQU H'0000' ;----- RXB1D4 Bits ---------------------------------------------------------- RXB1D47 EQU H'0007' RXB1D46 EQU H'0006' RXB1D45 EQU H'0005' RXB1D44 EQU H'0004' RXB1D43 EQU H'0003' RXB1D42 EQU H'0002' RXB1D41 EQU H'0001' RXB1D40 EQU H'0000' ;----- RXB1D3 Bits ---------------------------------------------------------- RXB1D37 EQU H'0007' RXB1D36 EQU H'0006' RXB1D35 EQU H'0005' RXB1D34 EQU H'0004' RXB1D33 EQU H'0003' RXB1D32 EQU H'0002' RXB1D31 EQU H'0001' RXB1D30 EQU H'0000' ;----- RXB1D2 Bits ---------------------------------------------------------- RXB1D27 EQU H'0007' RXB1D26 EQU H'0006' RXB1D25 EQU H'0005' RXB1D24 EQU H'0004' RXB1D23 EQU H'0003' RXB1D22 EQU H'0002' RXB1D21 EQU H'0001' RXB1D20 EQU H'0000' ;----- RXB1D1 Bits ---------------------------------------------------------- RXB1D17 EQU H'0007' RXB1D16 EQU H'0006' RXB1D15 EQU H'0005' RXB1D14 EQU H'0004' RXB1D13 EQU H'0003' RXB1D12 EQU H'0002' RXB1D11 EQU H'0001' RXB1D10 EQU H'0000' ;----- RXB1D0 Bits ---------------------------------------------------------- RXB1D07 EQU H'0007' RXB1D06 EQU H'0006' RXB1D05 EQU H'0005' RXB1D04 EQU H'0004' RXB1D03 EQU H'0003' RXB1D02 EQU H'0002' RXB1D01 EQU H'0001' RXB1D00 EQU H'0000' ;----- TXB2D7 Bits ---------------------------------------------------------- TXB2D77 EQU H'0007' TXB2D76 EQU H'0006' TXB2D75 EQU H'0005' TXB2D74 EQU H'0004' TXB2D73 EQU H'0003' TXB2D72 EQU H'0002' TXB2D71 EQU H'0001' TXB2D70 EQU H'0000' ;----- TXB2D6 Bits ---------------------------------------------------------- TXB2D67 EQU H'0007' TXB2D66 EQU H'0006' TXB2D65 EQU H'0005' TXB2D64 EQU H'0004' TXB2D63 EQU H'0003' TXB2D62 EQU H'0002' TXB2D61 EQU H'0001' TXB2D60 EQU H'0000' ;----- TXB2D5 Bits ---------------------------------------------------------- TXB2D57 EQU H'0007' TXB2D56 EQU H'0006' TXB2D55 EQU H'0005' TXB2D54 EQU H'0004' TXB2D53 EQU H'0003' TXB2D52 EQU H'0002' TXB2D51 EQU H'0001' TXB2D50 EQU H'0000' ;----- TXB2D4 Bits ---------------------------------------------------------- TXB2D47 EQU H'0007' TXB2D46 EQU H'0006' TXB2D45 EQU H'0005' TXB2D44 EQU H'0004' TXB2D43 EQU H'0003' TXB2D42 EQU H'0002' TXB2D41 EQU H'0001' TXB2D40 EQU H'0000' ;----- TXB2D3 Bits ---------------------------------------------------------- TXB2D37 EQU H'0007' TXB2D36 EQU H'0006' TXB2D35 EQU H'0005' TXB2D34 EQU H'0004' TXB2D33 EQU H'0003' TXB2D32 EQU H'0002' TXB2D31 EQU H'0001' TXB2D30 EQU H'0000' ;----- TXB2D2 Bits ---------------------------------------------------------- TXB2D27 EQU H'0007' TXB2D26 EQU H'0006' TXB2D25 EQU H'0005' TXB2D24 EQU H'0004' TXB2D23 EQU H'0003' TXB2D22 EQU H'0002' TXB2D21 EQU H'0001' TXB2D20 EQU H'0000' ;----- TXB2D1 Bits ---------------------------------------------------------- TXB2D17 EQU H'0007' TXB2D16 EQU H'0006' TXB2D15 EQU H'0005' TXB2D14 EQU H'0004' TXB2D13 EQU H'0003' TXB2D12 EQU H'0002' TXB2D11 EQU H'0001' TXB2D10 EQU H'0000' ;----- TXB2D0 Bits ---------------------------------------------------------- TXB2D07 EQU H'0007' TXB2D06 EQU H'0006' TXB2D05 EQU H'0005' TXB2D04 EQU H'0004' TXB2D03 EQU H'0003' TXB2D02 EQU H'0002' TXB2D01 EQU H'0001' TXB2D00 EQU H'0000' ;----- TXB1D7 Bits ---------------------------------------------------------- TXB1D77 EQU H'0007' TXB1D76 EQU H'0006' TXB1D75 EQU H'0005' TXB1D74 EQU H'0004' TXB1D73 EQU H'0003' TXB1D72 EQU H'0002' TXB1D71 EQU H'0001' TXB1D70 EQU H'0000' ;----- TXB1D6 Bits ---------------------------------------------------------- TXB1D67 EQU H'0007' TXB1D66 EQU H'0006' TXB1D65 EQU H'0005' TXB1D64 EQU H'0004' TXB1D63 EQU H'0003' TXB1D62 EQU H'0002' TXB1D61 EQU H'0001' TXB1D60 EQU H'0000' ;----- TXB1D5 Bits ---------------------------------------------------------- TXB1D57 EQU H'0007' TXB1D56 EQU H'0006' TXB1D55 EQU H'0005' TXB1D54 EQU H'0004' TXB1D53 EQU H'0003' TXB1D52 EQU H'0002' TXB1D51 EQU H'0001' TXB1D50 EQU H'0000' ;----- TXB1D4 Bits ---------------------------------------------------------- TXB1D47 EQU H'0007' TXB1D46 EQU H'0006' TXB1D45 EQU H'0005' TXB1D44 EQU H'0004' TXB1D43 EQU H'0003' TXB1D42 EQU H'0002' TXB1D41 EQU H'0001' TXB1D40 EQU H'0000' ;----- TXB1D3 Bits ---------------------------------------------------------- TXB1D37 EQU H'0007' TXB1D36 EQU H'0006' TXB1D35 EQU H'0005' TXB1D34 EQU H'0004' TXB1D33 EQU H'0003' TXB1D32 EQU H'0002' TXB1D31 EQU H'0001' TXB1D30 EQU H'0000' ;----- TXB1D2 Bits ---------------------------------------------------------- TXB1D27 EQU H'0007' TXB1D26 EQU H'0006' TXB1D25 EQU H'0005' TXB1D24 EQU H'0004' TBB1D23 EQU H'0003' TXB1D22 EQU H'0002' TXB1D21 EQU H'0001' TXB1D20 EQU H'0000' ;----- TXB1D1 Bits ---------------------------------------------------------- TXB1D17 EQU H'0007' TXB1D16 EQU H'0006' TXB1D15 EQU H'0005' TXB1D14 EQU H'0004' TXB1D13 EQU H'0003' TXB1D12 EQU H'0002' TXB1D11 EQU H'0001' TXB1D10 EQU H'0000' ;----- TXB1D0 Bits ---------------------------------------------------------- TXB1D07 EQU H'0007' TXB1D06 EQU H'0006' TXB1D05 EQU H'0005' TXB1D04 EQU H'0004' TXB1D03 EQU H'0003' TXB1D02 EQU H'0002' TXB1D01 EQU H'0001' TXB1D00 EQU H'0000' ;----- TXB0D7 Bits ---------------------------------------------------------- TXB0D77 EQU H'0007' TXB0D76 EQU H'0006' TXB0D75 EQU H'0005' TXB0D74 EQU H'0004' TXB0D73 EQU H'0003' TXB0D72 EQU H'0002' TXB0D71 EQU H'0001' TXB0D70 EQU H'0000' ;----- TXB0D6 Bits ---------------------------------------------------------- TXB0D67 EQU H'0007' TXB0D66 EQU H'0006' TXB0D65 EQU H'0005' TXB0D64 EQU H'0004' TXB0D63 EQU H'0003' TXB0D62 EQU H'0002' TXB0D61 EQU H'0001' TXB0D60 EQU H'0000' ;----- TXB0D5 Bits ---------------------------------------------------------- TXB0D57 EQU H'0007' TXB0D56 EQU H'0006' TXB0D55 EQU H'0005' TXB0D54 EQU H'0004' TXB0D53 EQU H'0003' TXB0D52 EQU H'0002' TXB0D51 EQU H'0001' TXB0D50 EQU H'0000' ;----- TXB0D4 Bits ---------------------------------------------------------- TXB0D47 EQU H'0007' TXB0D46 EQU H'0006' TXB0D45 EQU H'0005' TXB0D44 EQU H'0004' TXB0D43 EQU H'0003' TXB0D42 EQU H'0002' TXB0D41 EQU H'0001' TXB0D40 EQU H'0000' ;----- TXB0D3 Bits ---------------------------------------------------------- TXB0D37 EQU H'0007' TXB0D36 EQU H'0006' TXB0D35 EQU H'0005' TXB0D34 EQU H'0004' TXB0D33 EQU H'0003' TXB0D32 EQU H'0002' TXB0D31 EQU H'0001' TXB0D30 EQU H'0000' ;----- TXB0D2 Bits ---------------------------------------------------------- TXB0D27 EQU H'0007' TXB0D26 EQU H'0006' TXB0D25 EQU H'0005' TXB0D24 EQU H'0004' TXB0D23 EQU H'0003' TXB0D22 EQU H'0002' TXB0D21 EQU H'0001' TXB0D20 EQU H'0000' ;----- TXB0D1 Bits ---------------------------------------------------------- TXB0D17 EQU H'0007' TXB0D16 EQU H'0006' TXB0D15 EQU H'0005' TXB0D14 EQU H'0004' TXB0D13 EQU H'0003' TXB0D12 EQU H'0002' TXB0D11 EQU H'0001' TXB0D10 EQU H'0000' ;----- TXB0D0 Bits ---------------------------------------------------------- TXB0D07 EQU H'0007' TXB0D06 EQU H'0006' TXB0D05 EQU H'0005' TXB0D04 EQU H'0004' TXB0D03 EQU H'0003' TXB0D02 EQU H'0002' TXB0D01 EQU H'0001' TXB0D00 EQU H'0000' ;----- RXB0DLC and TXB0DLC Bits ---------------------------------------------------------- RXRTR EQU H'0006' RESB1 EQU H'0005' RESBO EQU H'0004' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DLC0 EQU H'0000' ;----- RXB0EIDL and RXB1EIDL Bits ---------------------------------------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXB0EIDH, RXFnEIDH, and RXMnEIDH Bits ---------------------------------------------------------- EID15 EQU H'0007' EID14 EQU H'0006' EID13 EQU H'0005' EID12 EQU H'0004' EID11 EQU H'0003' EID10 EQU H'0002' EID9 EQU H'0001' EID8 EQU H'0000' ;----- RXB0EIDL and TXB0EIDL Bits ---------------------------------------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXB0SIDL, RXFnSIDL, and RXMnSIDL Bits ---------------------------------------------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' SRR EQU H'0004' EXID EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXB0SIDH, RXFnSIDH, RXMnSIDH Bits ---------------------------------------------------------- SID10 EQU H'0007' SID9 EQU H'0006' SID8 EQU H'0005' SID7 EQU H'0004' SID6 EQU H'0003' SID5 EQU H'0002' SID4 EQU H'0001' SID3 EQU H'0001' ;----- RXB0CON Bits ---------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' RX0DBEN EQU H'0002' JTOFF EQU H'0001' FILHIT0 EQU H'0000' ;----- RXB1CON Bits ---------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' FILHIT2 EQU H'0002' FILHIT1 EQU H'0001' ;----- TXB0CON Bits ---------------------------------------------------------- TXABT EQU H'0006' TXLARB EQU H'0005' TXERR EQU H'0004' TXREQ EQU H'0003' TXPRI1 EQU H'0001' TXPRI0 EQU H'0000' ;----- TXBnSIDL Bits ---------------------------------------------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' EXIDE EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLK0 EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 INT3 EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 ALE EQU 0 AN5 EQU 0 RE1 EQU 1 OE EQU 1 RE2 EQU 2 WRL EQU 2 RE3 EQU 3 WRH EQU 3 RE4 EQU 4 RE5 EQU 5 RE6 EQU 6 RE7 EQU 7 CCP2 EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 RF2 EQU 2 AN7 EQU 2 RF3 EQU 3 AN8 EQU 3 RF4 EQU 4 AN9 EQU 4 RF5 EQU 5 AN10 EQU 5 RF6 EQU 6 AN11 EQU 6 RF7 EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 CANTX1 EQU 0 RG1 EQU 1 CANTX2 EQU 1 RG2 EQU 2 CANRX EQU 2 RG3 EQU 3 RG4 EQU 4 ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM H'5FF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Code Protect: ; CP = ON Enabled ; CP = OFF Disabled ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 0 300000h ; CONFIG1H = Configuration Byte 1 300001h ; CONFIG2L = Configuration Byte 3 300002h ; CONFIG2H = Configuration Byte 4 300003h ; CONFIG3L = Configuration Byte 5 300004h ; CONFIG3H = Configuration Byte 6 300005h ; CONFIG4L = Configuration Byte 7 300006h ; CONFIG4H = Configuration Byte 8 300007h ; ;========================================================================== ; ;Configuration Byte 0 Options _CP_ON_0 EQU H'00' ; Code Protect enable _CP_OFF_0 EQU H'FF' ;Configuration Byte 1 Options _OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1 EQU H'FF' _LP_OSC_1 EQU H'F8' ; Oscillator type _XT_OSC_1 EQU H'F9' _HS_OSC_1 EQU H'FA' _RC_OSC_1 EQU H'FB' _EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1 EQU H'FE' ; HS PLL _RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options _BOR_ON_2 EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2 EQU H'FD' _PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable _PWRT_ON_2 EQU H'FE' _BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2 EQU H'FB' ; 2.7v _BORV_42_2 EQU H'F7' ; 4.2v _BORV_45_2 EQU H'F3' ; 4.5v ;Configuration Byte 3 Options _WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_3 EQU H'FE' _WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_3 EQU H'FD' _WDTPS_32_3 EQU H'FB' _WDTPS_16_3 EQU H'F9' _WDTPS_8_3 EQU H'F7' _WDTPS_4_3 EQU H'F5' _WDTPS_2_3 EQU H'F3' _WDTPS_1_3 EQU H'F1' ;Configuration Byte 6 Options _STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_6 EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG0 EQU H'300000' _CONFIG1 EQU H'300001' _CONFIG2 EQU H'300002' _CONFIG3 EQU H'300003' _CONFIG4 EQU H'300004' _CONFIG5 EQU H'300005' _CONFIG6 EQU H'300006' _CONFIG7 EQU H'300007' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 0 ; __CONFIG _CONFIG0, _CP_OFF_0 ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1 ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2 ;Program Configuration Register 3 ; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3 ;Program Configuration Register 6 ; __CONFIG _CONFIG6, _STVR_ON_6 ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p12c509a.inc0000644000175000017500000001012511156313161013276 00000000000000 LIST ; P12C509A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12C509A and PIC12CR509A microcontrollers. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12C509A or ; C:\ MPASM MYFILE.ASM /P12CR509A ; 2. LIST directive in the source file ; LIST P=12C509A or ; LIST P=12CR509A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/28/97 Initial Release ;1.10 06/12/02 Verification now includes the PIC12CR509A (pas) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12C509A IFNDEF __12CR509A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' OSCFST EQU H'0003' CAL1 EQU H'0003' OSCSLW EQU H'0002' CAL0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f4525.inc0000644000175000017500000011413211156521302013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4525 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4525 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4525 ; 2. LIST directive in the source file ; LIST P=PIC18F4525 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4525 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCPAS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' DEBUG EQU H'0FD4' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCPAS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO6 EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO6 RC-OSC2 as RA6 ; OSC = INTIO67 INTRC-OSC2 as RA6, OSC1 as RA7 ; OSC = INTIO7 INTRC-OSC2 as Clock Out, OSC1 as RA7 ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Osc. Switch Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON SBOREN Enabled ; BOREN = NOSLP Enabled except Sleep, SBOREN Disabled ; BOREN = SBORDIS Enabled, SBOREN Disabled ; ; Brown-out Voltage: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; T1 Oscillator Enable: ; LPT1OSC = OFF Disabled ; LPT1OSC = ON Enabled ; ; PORTB A/D Enable: ; PBADEN = OFF PORTB<4:0> digital on Reset ; PBADEN = ON PORTB<4:0> analog on Reset ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; XINST Enable: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO6_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO6_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_INTIO67_1H EQU H'F8' ; INTRC-OSC2 as RA6, OSC1 as RA7 _OSC_INTIO7_1H EQU H'F9' ; INTRC-OSC2 as Clock Out, OSC1 as RA7 _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'F9' ; Disabled _BOREN_ON_2L EQU H'FB' ; SBOREN Enabled _BOREN_NOSLP_2L EQU H'FD' ; Enabled except Sleep, SBOREN Disabled _BOREN_SBORDIS_2L EQU H'FF' ; Enabled, SBOREN Disabled _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _LPT1OSC_OFF_3H EQU H'FB' ; Disabled _LPT1OSC_ON_3H EQU H'FF' ; Enabled _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> digital on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> analog on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Disabled _XINST_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f13k22.inc0000644000175000017500000012025511156521301013376 00000000000000 LIST ;========================================================================== ; MPASM PIC18F13K22 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F13K22 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F13K22 ; 2. LIST directive in the source file ; LIST P=PIC18F13K22 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F13K22 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' APFCON EQU H'0F75' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' VREFCON0 EQU H'0FBA' VREFCON1 EQU H'0FBB' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- C1SEL EQU H'0000' T0CKISEL EQU H'0001' INT2SEL EQU H'0002' SRQSEL EQU H'0003' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA0 EQU H'0000' WPUA1 EQU H'0001' WPUA2 EQU H'0002' WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA2 EQU H'0002' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0100'-H'0F3F' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F74' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 512W boot block size ; BBSIZ = ON 1kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 512W boot block size _BBSIZ_ON_4L EQU H'FF' ; 1kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c712.inc0000644000175000017500000002003011156313161013131 00000000000000 LIST ; P16C712.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C712 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C712 ; 2. LIST directive in the source file ; LIST P=PIC16C712 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 25 Jan 1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C712 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' DATACCP EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISCCP EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- DATACCP Bits -------------------------------------------------------- DCCP EQU H'0002' DT1CK EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISCCP Bits -------------------------------------------------------- TCCP EQU H'0002' TT1CK EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'13'-H'14', H'18'-H'1D' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'93'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p12ce673.inc0000644000175000017500000001420711156313161013311 00000000000000 LIST ; P12CE673.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12CE673 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12CE673 ; 2. LIST directive in the source file ; LIST P=PIC12CE673 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Original release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12CE673 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'008F' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- OSCCAL Bits -------------------------------------------------------- CAL3 EQU H'0007' CAL2 EQU H'0006' CAL1 EQU H'0005' CAL0 EQU H'0004' CALFST EQU H'0003' CALSLW EQU H'0002' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D'-H'1D' __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3F7F' _CP_ALL EQU H'009F' _CP_75 EQU H'15BF' _CP_50 EQU H'2ADF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _INTRC_OSC EQU H'3FFC' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC EQU H'3FFE' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18f6493.inc0000644000175000017500000016620411156521301013245 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6493 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6493 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6493 ; 2. LIST directive in the source file ; LIST P=PIC18F6493 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6493 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16lf723.inc0000644000175000017500000005003211156521301013314 00000000000000 LIST ; P16LF723.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16LF723 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16LF723 ; 2. LIST directive in the source file ; LIST P=PIC16LF723 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/25/07 Initial template ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF723 MESSG "Processor-header file mismatch. Verify selected processor." #define __16LF723 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'08' __BADRAM H'88' __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'110'-H'11F', H'130'-H'16F' __BADRAM H'187'-H'189', H'18D'-H'18F' __BADRAM H'190'-H'1EF' LIST gputils-0.13.7/header/p16c62a.inc0000644000175000017500000002071711156313161013224 00000000000000 LIST ; P16C62A.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C62A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C62A ; 2. LIST directive in the source file ; LIST P=PIC16C62A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C62A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1F' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91',H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p17c756a.inc0000644000175000017500000004500411156313161013313 00000000000000 LIST ; P17C756A.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C756A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C756A ; 2. LIST directive in the source file ; LIST P=PIC17C756A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/01/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C756A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' BANK4 EQU H'0004' BANK5 EQU H'0005' BANK6 EQU H'0006' BANK7 EQU H'0007' GPR_BANK0 EQU H'0000' GPR_BANK1 EQU H'0008' GPR_BANK2 EQU H'0010' GPR_BANK3 EQU H'0018' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' ;----- Bank 0 ------------------------------------------------------------- PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCSTA1 EQU H'0013' RCREG EQU H'0014' ; Backward compatibility only RCREG1 EQU H'0014' TXSTA EQU H'0015' ; Backward compatibility only TXSTA1 EQU H'0015' TXREG EQU H'0016' ; Backward compatibility only TXREG1 EQU H'0016' SPBRG EQU H'0017' ; Backward compatibility only SPBRG1 EQU H'0017' ;----- Bank 1 ------------------------------------------------------------- DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' ; Backward compatibility only PIR1 EQU H'0116' PIE EQU H'0117' ; Backward compatibility only PIE1 EQU H'0117' ;----- Bank 2 ------------------------------------------------------------- TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' ;----- Bank 3 ------------------------------------------------------------- PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- Bank 4 ------------------------------------------------------------- PIR2 EQU H'0410' PIE2 EQU H'0411' RCSTA2 EQU H'0413' RCREG2 EQU H'0414' TXSTA2 EQU H'0415' TXREG2 EQU H'0416' SPBRG2 EQU H'0417' ;----- Bank 5 ------------------------------------------------------------- DDRF EQU H'0510' PORTF EQU H'0511' DDRG EQU H'0512' PORTG EQU H'0513' ADCON0 EQU H'0514' ADCON1 EQU H'0515' ADRESL EQU H'0516' ADRESH EQU H'0517' ;----- Bank 6 ------------------------------------------------------------- SSPADD EQU H'0610' SSPCON1 EQU H'0611' SSPCON2 EQU H'0612' SSPSTAT EQU H'0613' SSPBUF EQU H'0614' ;----- Bank 7 ------------------------------------------------------------- PW3DCL EQU H'0710' PW3DCH EQU H'0711' CA3L EQU H'0712' CA3H EQU H'0713' CA4L EQU H'0714' CA4H EQU H'0715' TCON3 EQU H'0716' ;----- Unbanked ----------------------------------------------------------- PRODL EQU H'0018' PL EQU H'0018' ; Backward compatibility only PRODH EQU H'0019' PH EQU H'0019' ; Backward compatibility only ;----- Special Function Register Bit Definitions -------------------------- ; ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' ; Backward compatibility only TX1IF EQU H'0001' RCIF EQU H'0000' ; Backward compatibility only RC1IF EQU H'0000' ;----- PIE1 Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' ; Backward compatibility only TX1IE EQU H'0001' RCIE EQU H'0000' ; Backward compatibility only RC1IE EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' ;----- RCSTA1 and 2 Bits -------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' ; Backward compatibility only T0PS2 EQU H'0003' PS2 EQU H'0003' ; Backward compatibility only T0PS1 EQU H'0002' PS1 EQU H'0002' ; Backward compatibility only T0PS0 EQU H'0001' PS0 EQU H'0001' ; Backward compatibility only ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- SSPIF EQU H'0007' BCLIF EQU H'0006' ADIF EQU H'0005' CA4IF EQU H'0003' CA3IF EQU H'0002' TX2IF EQU H'0001' RC2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- SSPIE EQU H'0007' BCLIE EQU H'0006' ADIE EQU H'0005' CA4IE EQU H'0003' CA3IE EQU H'0002' TX2IE EQU H'0001' RC2IE EQU H'0000' ;----- TXSTA1 and 2 Bits -------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0007' CHS2 EQU H'0006' CHS1 EQU H'0005' CHS0 EQU H'0004' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' ADFM EQU H'0005' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- SSPCON1 Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' AKSTAT EQU H'0006' ACKDT EQU H'0005' AKDT EQU H'0005' ACKEN EQU H'0004' AKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' NOT_A EQU H'0005' D_A EQU H'0005' P EQU H'0004' S EQU H'0003' R EQU H'0002' NOT_W EQU H'0002' R_W EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TCON3 Bits --------------------------------------------------------- CA4OVF EQU H'0006' CA3OVF EQU H'0005' CA4ED1 EQU H'0004' CA4ED0 EQU H'0003' CA3ED1 EQU H'0002' CA3ED0 EQU H'0001' PWM3ON EQU H'0000' ;----- PW2DCL Bit --------------------------------------------------------- TM2PW2 EQU H'0005' ;----- PW3DCL Bit --------------------------------------------------------- TM2PW3 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'8FF' __BADRAM H'118'-H'11F', H'218'-H'21F', H'318'-H'31F' __BADRAM H'412', H'418'-H'4FF' __BADRAM H'518'-H'5FF' __BADRAM H'615'-H'6FF' __BADRAM H'717'-H'7FF' __BADRAM H'814'-H'8FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _BODEN_OFF EQU H'BFFF' _BODEN_ON EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _WDT_0 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p18f67j60.inc0000644000175000017500000013431211156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F67J60 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F67J60 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F67J60 ; 2. LIST directive in the source file ; LIST P=PIC18F67J60 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F67J60 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2 EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' CCP3 EQU H'0001' CCP4 EQU H'0002' ECCP3 EQU H'0001' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG4 EQU H'0004' CCP5 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0F62'-H'0F66' __BADRAM H'0F6B'-H'0F6F' __BADRAM H'0F7C'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f85j10.inc0000644000175000017500000014201311156521301013377 00000000000000 LIST ;========================================================================== ; MPASM PIC18F85J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F85J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F85J10 ; 2. LIST directive in the source file ; LIST P=PIC18F85J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F85J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode, 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode, 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode, 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16lf722.inc0000644000175000017500000005004211156521301013314 00000000000000 LIST ; P16LF722.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16LF722 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16LF722 ; 2. LIST directive in the source file ; LIST P=PIC16LF722 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/25/07 Initial template ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF722 MESSG "Processor-header file mismatch. Verify selected processor." #define __16LF722 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'08' __BADRAM H'88' __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'C0'-H'EF' __BADRAM H'105'-H'107' __BADRAM H'110'-H'16F' __BADRAM H'187'-H'189', H'18D'-H'18F' __BADRAM H'190'-H'1EF' LIST gputils-0.13.7/header/p16f72.inc0000644000175000017500000002443711156313161013072 00000000000000 LIST ; P16F72.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F72 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F72 ; 2. LIST directive in the source file ; LIST P=PIC16F72 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 03/22/02 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F72 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADCON1 EQU H'009F' PMDATL EQU H'010C' PMADRL EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' TMR0IE EQU H'0005' ; Backward compatibility only T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' ; Backward compatibility only T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'0D', H'18'-H'1D' __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18D'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOREN_ON EQU H'3FFF' _BODEN_ON EQU H'3FFF' ; Backward compatibility only _BOREN_OFF EQU H'3FBF' _BODEN_OFF EQU H'3FBF' ; Backward compatibility only _CP_ALL EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTEN_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _PWRTEN_ON EQU H'3FF7' _PWRTE_ON EQU H'3FF7' ; Backward compatibility only _WDTEN_ON EQU H'3FFF' _WDTEN_OFF EQU H'3FFB' _WDT_ON EQU H'3FFF' ; Backward compatibility only _WDT_OFF EQU H'3FFB' ; Backward compatibility only _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f66j90.inc0000644000175000017500000015446711156521301013426 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J90 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J90 ; 2. LIST directive in the source file ; LIST P=PIC18F66J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PADCFG1 EQU H'0F54' CTMUICON EQU H'0F55' CTMUCONL EQU H'0F56' CTMUCONH EQU H'0F57' ALRMVALL EQU H'0F58' ALRMVALH EQU H'0F59' ALRMRPT EQU H'0F5A' ALRMCFG EQU H'0F5B' RTCVALL EQU H'0F5C' RTCVALH EQU H'0F5D' RTCCAL EQU H'0F5E' RTCCFG EQU H'0F5F' RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' ECCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' ECCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' TRISF EQU H'0F97' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PADCFG1 Bits ----------------------------------------------------- RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- LCDDATA6 Bits ----------------------------------------------------- S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' SEG32COM1 EQU H'0000' ;----- LCDDATA12 Bits ----------------------------------------------------- S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' SEG32COM2 EQU H'0000' ;----- LCDDATA18 Bits ----------------------------------------------------- S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' SEG00COM3 EQU H'0000' SEG01COM3 EQU H'0001' SEG02COM3 EQU H'0002' SEG03COM3 EQU H'0003' SEG04COM3 EQU H'0004' SEG05COM3 EQU H'0005' SEG06COM3 EQU H'0006' SEG07COM3 EQU H'0007' S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' SEG32COM3 EQU H'0000' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' TOCKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' CTED1 EQU H'0002' CTED2 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' CTPLS EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' CVREF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' TX2 EQU H'0001' RX2 EQU H'0002' RTCC EQU H'0004' VLCAP1 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' CCP1IE EQU H'0001' CCP2IE EQU H'0002' CTMUIE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' CCP1IF EQU H'0001' CCP2IF EQU H'0002' CTMUIF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' CCP1IP EQU H'0001' CCP2IP EQU H'0002' CTMUIP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SEGEN32 EQU H'0000' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- TRIGSEL EQU H'0007' PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM_RCON EQU H'0005' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- MODE13 EQU H'0002' CPEN EQU H'0006' CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- IOFS EQU H'0002' OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F6B' __BADRAM H'0F71' __BADRAM H'0F77' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FBA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled-Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Oscillator Selection bits: ; OSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; OSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; OSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; OSC = INTOSCPLLO INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 ; OSC = HS HS oscillator ; OSC = HSPLL HS oscillator, PLL enabled ; OSC = EC EC Oscillator with clock out on RA6 ; OSC = ECPLL EC Oscillator with PLL ; ; Secondary Clock Source T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = ON Timer1 oscillator configured for low-power operation ; LPT1OSC = OFF Timer1 oscillator configured for higher power operation ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Reference Clock Select bit: ; RTCSOSC = INTOSCREF RTCC uses INTOSC/INTRC as reference clock ; RTCSOSC = T1OSCREF RTCC uses T1OSC/T1CKI as reference clock ; ; CCP2 MUX: ; CCP2MX = ALTERNATE RE7 / RB3 ; CCP2MX = DEFAULT RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c771.inc0000644000175000017500000003012511156313161013144 00000000000000 LIST ; P16C771.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C771 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C771 ; 2. LIST directive in the source file ; LIST P=PIC16C771 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 14Sep1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C771 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' P1DEL EQU H'0097' REFCON EQU H'009B' LVDCON EQU H'009C' ANSEL EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' PMDATL EQU H'010C' PMADRL EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- LVDIF EQU H'0007' BCLIF EQU H'0003' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- PWM1M1 EQU H'0007' PWM1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- LVDIE EQU H'0007' BCLIE EQU H'0003' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- VRHEN EQU H'0007' VRLEN EQU H'0006' VRHOEN EQU H'0005' VRLOEN EQU H'0004' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'18'-H'1D' __BADRAM H'87'-H'89' __BADRAM H'8F'-H'90', H'98'-H'9A' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CFF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _MCLRE_OFF EQU H'3FDF' _MCLRE_ON EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FFB' _HS_OSC EQU H'3FFA' _XT_OSC EQU H'3FF9' _LP_OSC EQU H'3FF8' LIST gputils-0.13.7/header/p16f616.inc0000644000175000017500000004020511156521301013142 00000000000000 LIST ; P16F616.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F616 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F616 ; 2. LIST directive in the source file ; LIST P=PIC16F616 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 09/12/05 Original ;1.01 12/04/06 Added WPU, BOR and IOC aliases ;1.02 12/06/06 Added FVREN bit to VRCON ;1.03 01/15/07 Added PORTA, PORTC, TRISA & TRISC bits ;1.04 04/16/07 Added ADCON1 bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F616 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' PWM1CON EQU H'0016' ECCPAS EQU H'0017' VRCON EQU H'0019' CM1CON0 EQU H'001A' CM2CON0 EQU H'001B' CM2CON1 EQU H'001C' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' SRCON EQU H'0099' SRCON0 EQU H'0099' SRCON1 EQU H'009A' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- PORTC Bits --------------------------------------------------------- RC5 EQU H'0005' RC4 EQU H'0004' RC3 EQU H'0003' RC2 EQU H'0002' RC1 EQU H'0001' RC0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- VRCON Bits ------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' FVREN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1ACS EQU H'0004' C1HYS EQU H'0003' C2HYS EQU H'0002' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISC Bits -------------------------------------------------------- TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- WPU Bits --------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- SRCON0 Bits ------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' SRCLKEN EQU H'0000' ;----- SRCON1 Bits ------------------------------------------------------- SRCS1 EQU H'0007' SRCS0 EQU H'0006' ;----- ADCON1 Bits ------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'18', H'1D' __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'93'-H'94', H'97'-H'98', H'9B'-H'9D', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOD_ON EQU H'3FFF' _BOR_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOR_NSLEEP EQU H'3EFF' _BOD_OFF EQU H'3CFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16c74a.inc0000644000175000017500000003064011156313161013223 00000000000000 LIST ; P16C74A.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C74A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C74A ; 2. LIST directive in the source file ; LIST P=PIC16C74A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C74A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f4682.inc0000644000175000017500000043000711156521301013236 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4682 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4682 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4682 ; 2. LIST directive in the source file ; LIST P=PIC18F4682 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4682 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' ECCP1CON EQU H'0FBA' ECCPR1 EQU H'0FBB' ECCPR1L EQU H'0FBB' ECCPR1H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF_PORTA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' C1INB EQU H'0000' C1INA EQU H'0001' C2INB EQU H'0002' C2INA EQU H'0003' P1A EQU H'0004' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ECCP1 EQU H'0004' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- ECCP1IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- ECCP1IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- ECCP1IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF_CVRCON EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- ECCP1M0 EQU H'0000' ECCP1M1 EQU H'0001' ECCP1M2 EQU H'0002' ECCP1M3 EQU H'0003' EDC1B0 EQU H'0004' EDC1B1 EQU H'0005' EPWM1M0 EQU H'0006' EPWM1M1 EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; BackGround Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size Select Bits: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot Block (000000-0007FFh) write-protected ; WRTB = OFF Boot Block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot Block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4331.inc0000644000175000017500000012557111156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4331 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4331 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4331 ; 2. LIST directive in the source file ; LIST P=PIC18F4331 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4331 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- DFLTCON EQU H'0F60' CAP3CON EQU H'0F61' CAP2CON EQU H'0F62' CAP1CON EQU H'0F63' CAP3BUFL EQU H'0F64' MAXCNTL EQU H'0F64' CAP3BUFH EQU H'0F65' MAXCNTH EQU H'0F65' CAP2BUFL EQU H'0F66' POSCNTL EQU H'0F66' CAP2BUFH EQU H'0F67' POSCNTH EQU H'0F67' CAP1BUFL EQU H'0F68' VELRL EQU H'0F68' CAP1BUFH EQU H'0F69' VELRH EQU H'0F69' OVDCONS EQU H'0F6A' OVDCOND EQU H'0F6B' FLTCONFIG EQU H'0F6C' DTCON EQU H'0F6D' PWMCON1 EQU H'0F6E' PWMCON0 EQU H'0F6F' SEVTCMPH EQU H'0F70' SEVTCMPL EQU H'0F71' PDC3H EQU H'0F72' PDC3L EQU H'0F73' PDC2H EQU H'0F74' PDC2L EQU H'0F75' PDC1H EQU H'0F76' PDC1L EQU H'0F77' PDC0H EQU H'0F78' PDC0L EQU H'0F79' PTPERH EQU H'0F7A' PTPERL EQU H'0F7B' PTMRH EQU H'0F7C' PTMRL EQU H'0F7D' PTCON1 EQU H'0F7E' PTCON0 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' TMR5L EQU H'0F87' TMR5H EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' PR5L EQU H'0F90' PR5H EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' ADCHS EQU H'0F99' ADCON3 EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' BAUDCON EQU H'0FAA' BAUDCTL EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' QEICON EQU H'0FB6' T5CON EQU H'0FB7' ANSEL0 EQU H'0FB8' ANSEL1 EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- DFLTCON Bits ----------------------------------------------------- FLTCK0 EQU H'0000' FLTCK1 EQU H'0001' FLTCK2 EQU H'0002' FLT1EN EQU H'0003' FLT2EN EQU H'0004' FLT3EN EQU H'0005' FLT4EN EQU H'0006' ;----- CAP3CON Bits ----------------------------------------------------- CAP3M0 EQU H'0000' CAP3M1 EQU H'0001' CAP3M2 EQU H'0002' CAP3M3 EQU H'0003' CAP3TMR EQU H'0005' CAP3REN EQU H'0006' ;----- CAP2CON Bits ----------------------------------------------------- CAP2M0 EQU H'0000' CAP2M1 EQU H'0001' CAP2M2 EQU H'0002' CAP2M3 EQU H'0003' CAP2TMR EQU H'0005' CAP2REN EQU H'0006' ;----- CAP1CON Bits ----------------------------------------------------- CAP1M0 EQU H'0000' CAP1M1 EQU H'0001' CAP1M2 EQU H'0002' CAP1M3 EQU H'0003' CAP1TMR EQU H'0005' CAP1REN EQU H'0006' ;----- OVDCONS Bits ----------------------------------------------------- POUT0 EQU H'0000' POUT1 EQU H'0001' POUT2 EQU H'0002' POUT3 EQU H'0003' POUT4 EQU H'0004' POUT5 EQU H'0005' POUT6 EQU H'0006' POUT7 EQU H'0007' ;----- OVDCOND Bits ----------------------------------------------------- POVD0 EQU H'0000' POVD1 EQU H'0001' POVD2 EQU H'0002' POVD3 EQU H'0003' POVD4 EQU H'0004' POVD5 EQU H'0005' POVD6 EQU H'0006' POVD7 EQU H'0007' ;----- FLTCONFIG Bits ----------------------------------------------------- FLTAEN EQU H'0000' FLTAMOD EQU H'0001' FLTAS EQU H'0002' FLTCON EQU H'0003' FLTBEN EQU H'0004' FLTBMOD EQU H'0005' FLTBS EQU H'0006' ;----- DTCON Bits ----------------------------------------------------- DT0 EQU H'0000' DT1 EQU H'0001' DT2 EQU H'0002' DT3 EQU H'0003' DT4 EQU H'0004' DT5 EQU H'0005' DTPS0 EQU H'0006' DTPS1 EQU H'0007' DTA0 EQU H'0000' DTA1 EQU H'0001' DTA2 EQU H'0002' DTA3 EQU H'0003' DTA4 EQU H'0004' DTA5 EQU H'0005' DTAPS0 EQU H'0006' DTAPS1 EQU H'0007' ;----- PWMCON1 Bits ----------------------------------------------------- OSYNC EQU H'0000' UDIS EQU H'0001' SEVTDIR EQU H'0003' SEVOPS0 EQU H'0004' SEVOPS1 EQU H'0005' SEVOPS2 EQU H'0006' SEVOPS3 EQU H'0007' ;----- PWMCON0 Bits ----------------------------------------------------- PMOD0 EQU H'0000' PMOD1 EQU H'0001' PMOD2 EQU H'0002' PMOD3 EQU H'0003' PWMEN0 EQU H'0004' PWMEN1 EQU H'0005' PWMEN2 EQU H'0006' ;----- PTCON1 Bits ----------------------------------------------------- PTDIR EQU H'0006' PTEN EQU H'0007' ;----- PTCON0 Bits ----------------------------------------------------- PTMOD0 EQU H'0000' PTMOD1 EQU H'0001' PTCKPS0 EQU H'0002' PTCKPS1 EQU H'0003' PTOPS0 EQU H'0004' PTOPS1 EQU H'0005' PTOPS2 EQU H'0006' PTOPS3 EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' INT0 EQU H'0003' INT1 EQU H'0004' INT2 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' T0CKI EQU H'0003' SDA EQU H'0004' SCK EQU H'0005' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' NOT_FLTA EQU H'0001' NOT_FLTB EQU H'0002' T5CKI EQU H'0003' SDI EQU H'0004' SCL EQU H'0005' NOT_SS EQU H'0006' SDO EQU H'0007' FLTA EQU H'0001' FLTB EQU H'0002' SS EQU H'0006' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' NOT_MCLR EQU H'0003' MCLR EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- ADCHS Bits ----------------------------------------------------- GASEL0 EQU H'0000' GASEL1 EQU H'0001' GCSEL0 EQU H'0002' GCSEL1 EQU H'0003' GBSEL0 EQU H'0004' GBSEL1 EQU H'0005' GDSEL0 EQU H'0006' GDSEL1 EQU H'0007' SASEL0 EQU H'0000' SASEL1 EQU H'0001' SCSEL0 EQU H'0002' SCSEL1 EQU H'0003' SBSEL0 EQU H'0004' SBSEL1 EQU H'0005' SDSEL0 EQU H'0006' SDSEL1 EQU H'0007' ;----- ADCON3 Bits ----------------------------------------------------- SSRC0 EQU H'0000' SSRC1 EQU H'0001' SSRC2 EQU H'0002' SSRC3 EQU H'0003' SSRC4 EQU H'0004' ADRS0 EQU H'0006' ADRS1 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TBIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TBIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LVDIE EQU H'0002' EEIE EQU H'0004' OSFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LVDIF EQU H'0002' EEIF EQU H'0004' OSFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' LVDIP EQU H'0002' EEIP EQU H'0004' OSFIP EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR5IE EQU H'0000' IC1IE EQU H'0001' IC2QEIE EQU H'0002' IC3DRIE EQU H'0003' PTIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- TMR5IF EQU H'0000' IC1IF EQU H'0001' IC2QEIF EQU H'0002' IC3DRIF EQU H'0003' PTIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- TMR5IP EQU H'0000' IC1IP EQU H'0001' IC2QEIP EQU H'0002' IC3DRIP EQU H'0003' PTIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- QEICON Bits ----------------------------------------------------- PDEC0 EQU H'0000' PDEC1 EQU H'0001' QEIM0 EQU H'0002' QEIM1 EQU H'0003' QEIM2 EQU H'0004' UP_DOWN EQU H'0005' ; ERROR is a reserved word ; ERROR EQU H'0006' VELM EQU H'0007' UP EQU H'0005' DOWN EQU H'0005' NOT_DOWN EQU H'0005' NOT_VELM EQU H'0007' ;----- T5CON Bits ----------------------------------------------------- TMR5ON EQU H'0000' TMR5CS EQU H'0001' T5SYNC EQU H'0002' T5PS0 EQU H'0003' T5PS1 EQU H'0004' T5MOD EQU H'0005' RESEN EQU H'0006' T5SEN EQU H'0007' NOT_T5SYNC EQU H'0002' NOT_RESEN EQU H'0006' ;----- ANSEL0 Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSEL1 Bits ----------------------------------------------------- ANS8 EQU H'0000' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ACQT3 EQU H'0006' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- ADPNT0 EQU H'0000' ADPNT1 EQU H'0001' BFOVFL EQU H'0002' BFEMT EQU H'0003' FIFOEN EQU H'0004' VCFG0 EQU H'0006' VCFG1 EQU H'0007' FFOVFL EQU H'0002' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' ACMOD0 EQU H'0002' ACMOD1 EQU H'0003' ACSCH EQU H'0004' ACONV EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDT0 EQU H'0001' WDT1 EQU H'0002' WDT2 EQU H'0003' WDT3 EQU H'0004' WDT4 EQU H'0005' WDT5 EQU H'0006' WDT6 EQU H'0007' WDTW EQU H'0007' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F5F' __BADRAM H'0F85'-H'0F86' __BADRAM H'0F8E'-H'0F8F' __BADRAM H'0F97'-H'0F98' __BADRAM H'0F9C' __BADRAM H'0FB1'-H'0FB5' __BADRAM H'0FC5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC2 External RC, RA6 is CLKOUT ; OSC = EC EC, RA6 is CLKOUT ; OSC = ECIO EC, RA6 is I/O ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO External RC, RA6 is I/O ; OSC = IRCIO Internal RC, RA6 & RA7 are I/O ; OSC = IRC Internal RC, RA6 is CLKOUT, RA7 is I/O ; OSC = RC1 External RC, RA6 is CLKOUT ; OSC = RC External RC, RA6 is CLKOUT ; ; Fail-Safe Clock Monitor Enable: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal/External Switch-Over: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Power-up Timer: ; PWRTEN = ON Enabled ; PWRTEN = OFF Disabled ; ; Brown-out Reset: ; BOREN = OFF Disabled ; BOREN = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDTEN = OFF Disabled ; WDTEN = ON Enabled ; ; Watchdog Timer Enable Window: ; WINEN = ON Enabled ; WINEN = OFF Disabled ; ; Watchdog Postscaler: ; WDPS = 1 1:1 ; WDPS = 2 1:2 ; WDPS = 4 1:4 ; WDPS = 8 1:8 ; WDPS = 16 1:16 ; WDPS = 32 1:32 ; WDPS = 64 1:64 ; WDPS = 128 1:128 ; WDPS = 256 1:256 ; WDPS = 512 1:512 ; WDPS = 1024 1:1024 ; WDPS = 2048 1:2048 ; WDPS = 4096 1:4096 ; WDPS = 8192 1:8192 ; WDPS = 16384 1:16384 ; WDPS = 32768 1:32768 ; ; Timer1 Oscillator MUX: ; T1OSCMX = OFF Active ; T1OSCMX = ON Inactive ; ; High-Side Transistors Polarity: ; HPOL = LOW Active low ; HPOL = HIGH Active high ; ; Low-Side Transistors Polarity: ; LPOL = LOW Active low ; LPOL = HIGH Active high ; ; PWM output pins Reset state control: ; PWMPIN = ON Enabled ; PWMPIN = OFF Disabled ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; External clock MUX bit: ; EXCLKMX = RD0 Multiplexed with RD0 ; EXCLKMX = RC3 Multiplexed with RC3 ; ; PWM4 MUX bit: ; PWM4MX = RD5 Multiplexed with RD5 ; PWM4MX = RB5 Multiplexed with RB5 ; ; SSP I/O MUX bit: ; SSPMX = RD1 SDO output is multiplexed with RD1 ; SSPMX = RC7 SD0 output is multiplexed with RC7 ; ; FLTA MUX bit: ; FLTAMX = RD4 Multiplexed with RD4 ; FLTAMX = RC1 Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC2_1H EQU H'F3' ; External RC, RA6 is CLKOUT _OSC_EC_1H EQU H'F4' ; EC, RA6 is CLKOUT _OSC_ECIO_1H EQU H'F5' ; EC, RA6 is I/O _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; External RC, RA6 is I/O _OSC_IRCIO_1H EQU H'F8' ; Internal RC, RA6 & RA7 are I/O _OSC_IRC_1H EQU H'F9' ; Internal RC, RA6 is CLKOUT, RA7 is I/O _OSC_RC1_1H EQU H'FB' ; External RC, RA6 is CLKOUT _OSC_RC_1H EQU H'FF' ; External RC, RA6 is CLKOUT _FCMEN_OFF_1H EQU H'BF' ; Disabled _FCMEN_ON_1H EQU H'FF' ; Enabled _IESO_OFF_1H EQU H'7F' ; Disabled _IESO_ON_1H EQU H'FF' ; Enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; Enabled _PWRTEN_OFF_2L EQU H'FF' ; Disabled _BOREN_OFF_2L EQU H'FD' ; Disabled _BOREN_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; Disabled _WDTEN_ON_2H EQU H'FF' ; Enabled _WINEN_ON_2H EQU H'DF' ; Enabled _WINEN_OFF_2H EQU H'FF' ; Disabled _WDPS_1_2H EQU H'E1' ; 1:1 _WDPS_2_2H EQU H'E3' ; 1:2 _WDPS_4_2H EQU H'E5' ; 1:4 _WDPS_8_2H EQU H'E7' ; 1:8 _WDPS_16_2H EQU H'E9' ; 1:16 _WDPS_32_2H EQU H'EB' ; 1:32 _WDPS_64_2H EQU H'ED' ; 1:64 _WDPS_128_2H EQU H'EF' ; 1:128 _WDPS_256_2H EQU H'F1' ; 1:256 _WDPS_512_2H EQU H'F3' ; 1:512 _WDPS_1024_2H EQU H'F5' ; 1:1024 _WDPS_2048_2H EQU H'F7' ; 1:2048 _WDPS_4096_2H EQU H'F9' ; 1:4096 _WDPS_8192_2H EQU H'FB' ; 1:8192 _WDPS_16384_2H EQU H'FD' ; 1:16384 _WDPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _T1OSCMX_OFF_3L EQU H'DF' ; Active _T1OSCMX_ON_3L EQU H'FF' ; Inactive _HPOL_LOW_3L EQU H'EF' ; Active low _HPOL_HIGH_3L EQU H'FF' ; Active high _LPOL_LOW_3L EQU H'F7' ; Active low _LPOL_HIGH_3L EQU H'FF' ; Active high _PWMPIN_ON_3L EQU H'FB' ; Enabled _PWMPIN_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _EXCLKMX_RD0_3H EQU H'EF' ; Multiplexed with RD0 _EXCLKMX_RC3_3H EQU H'FF' ; Multiplexed with RC3 _PWM4MX_RD5_3H EQU H'F7' ; Multiplexed with RD5 _PWM4MX_RB5_3H EQU H'FF' ; Multiplexed with RB5 _SSPMX_RD1_3H EQU H'FB' ; SDO output is multiplexed with RD1 _SSPMX_RC7_3H EQU H'FF' ; SD0 output is multiplexed with RC7 _FLTAMX_RD4_3H EQU H'FE' ; Multiplexed with RD4 _FLTAMX_RC1_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Disabled _STVREN_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c621.inc0000644000175000017500000001355611156313161013147 00000000000000 LIST ; P16C621.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C621 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C621 ; 2. LIST directive in the source file ; LIST P=PIC16C621 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C621 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'9F' __BADRAM H'07'-H'09', H'0D'-H'01E', H'70'-H'7F' __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_50 EQU H'15DF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18c452.inc0000644000175000017500000006220511156313161013146 00000000000000 LIST ; P18C452.INC Standard Header File, Version 0.12 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C452 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C452 ; 2. LIST directive in the source file ; LIST P=PIC18C452 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.02 25 Nov 98 Preliminary Release drj ;0.03 07 Dec 98 Added compatibility #defines drj ;0.04 10 Dec 98 Added bits defs and new config jt ;0.05 14 Dec 98 Incorporated ko comments dj ;0.06 12 Jan 99 Changed config bits dj ;0.07 13 Jan 99 Changed BODEN to BOREN dj ;0.08 1 Apr 99 Added TRIS aliases ;0.09 17 Jun 99 Clean up ;0.10 23 Sep 99 Compatibility with PIC18Cxx2 Data Sheet (Rev B) ; and Added I/O Pin definitions mp ;0.11 29 Jun 00 Added support for Device ID/Revision & ID locations rr ;0.12 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C452 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' ;RESERVED_0FA7 EQU H'0FA7' ;RESERVED_0FA6 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' LWRT EQU H'0006' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- IPR2 Bits ---------------------------------------------------------- BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 AN5 EQU 0 RE1 EQU 1 WR EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 AN7 EQU 2 ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM H'5FF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Code Protect: ; CP = ON Enabled ; CP = OFF Disabled ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 0 300000h ; CONFIG1H = Configuration Byte 1 300001h ; CONFIG2L = Configuration Byte 3 300002h ; CONFIG2H = Configuration Byte 4 300003h ; CONFIG3L = Configuration Byte 5 300004h ; CONFIG3H = Configuration Byte 6 300005h ; CONFIG4L = Configuration Byte 7 300006h ; CONFIG4H = Configuration Byte 8 300007h ; ;========================================================================== ; ;Configuration Byte 0 Options _CP_ON_0 EQU H'00' ; Code Protect enable _CP_OFF_0 EQU H'FF' ;Configuration Byte 1 Options _OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1 EQU H'FF' _LP_OSC_1 EQU H'F8' ; Oscillator type _XT_OSC_1 EQU H'F9' _HS_OSC_1 EQU H'FA' _RC_OSC_1 EQU H'FB' _EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1 EQU H'FE' ; HS PLL _RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options _BOR_ON_2 EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2 EQU H'FD' _PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable _PWRT_ON_2 EQU H'FE' _BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2 EQU H'FB' ; 2.7v _BORV_42_2 EQU H'F7' ; 4.2v _BORV_45_2 EQU H'F3' ; 4.5v ;Configuration Byte 3 Options _WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_3 EQU H'FE' _WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_3 EQU H'FD' _WDTPS_32_3 EQU H'FB' _WDTPS_16_3 EQU H'F9' _WDTPS_8_3 EQU H'F7' _WDTPS_4_3 EQU H'F5' _WDTPS_2_3 EQU H'F3' _WDTPS_1_3 EQU H'F1' ;Configuration Byte 5 Options _CCP2MX_ON_5 EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_5 EQU H'FE' ;Configuration Byte 6 Options _STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_6 EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG0 EQU H'300000' _CONFIG1 EQU H'300001' _CONFIG2 EQU H'300002' _CONFIG3 EQU H'300003' _CONFIG4 EQU H'300004' _CONFIG5 EQU H'300005' _CONFIG6 EQU H'300006' _CONFIG7 EQU H'300007' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 0 ; __CONFIG _CONFIG0, _CP_OFF_0 ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1 ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2 ;Program Configuration Register 3 ; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3 ;Program Configuration Register 5 ;__CONFIG _CONFIG5, _CCP2MX_ON_5 ;Program Configuration Register 6 ; __CONFIG _CONFIG6, _STVR_ON_6 ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16f887.inc0000644000175000017500000005602011156521301013156 00000000000000 LIST ; P16F887.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F887 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F887 ; 2. LIST directive in the source file ; LIST P=PIC16F887 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ; ;1.00 11/18/05 Original ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F887 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' MSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' VRCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' PWM1CON EQU H'009B' ECCPAS EQU H'009C' PSTRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' CM1CON0 EQU H'0107' CM2CON0 EQU H'0108' CM2CON1 EQU H'0109' EEDATA EQU H'010C' EEDAT EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' SRCON EQU H'0185' BAUDCTL EQU H'0187' ANSEL EQU H'0188' ANSELH EQU H'0189' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' BCLIF EQU H'0003' ULPWUIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GIV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' CCP1X EQU H'0005' ; Backward compatibility only DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' ; Backward compatibility only DC2B1 EQU H'0005' CCP2Y EQU H'0004' ; Backward compatibility only DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' BCLIE EQU H'0003' ULPWUIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- IOCB Bits ---------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' C1RSEL EQU H'0005' C2RSEL EQU H'0004' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' FVREN EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS13 EQU H'0005' ANS12 EQU H'0004' ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word1 ------------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'2FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word2 ------------------------------------------------ _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _BOR21V EQU H'3EFF' _BOR40V EQU H'3FFF' LIST gputils-0.13.7/header/p18f2439.inc0000644000175000017500000006473411156521301013246 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2439 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2439 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2439 ; 2. LIST directive in the source file ; LIST P=PIC18F2439 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2439 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' CLK0 EQU H'0006' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2 EQU H'0001' CCP1 EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCPX EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0002' CHS0 EQU H'0003' CHS1 EQU H'0004' CHS2 EQU H'0005' ADCS0 EQU H'0006' ADCS1 EQU H'0007' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' TMR0IP EQU H'0002' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0280'-H'0F7F' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB4'-H'0FB9' __BADRAM H'0FC0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F8' ; LP _OSC_XT_1H EQU H'F9' ; XT _OSC_HS_1H EQU H'FA' ; HS _OSC_RC_1H EQU H'FB' ; RC _OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6 ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_25_2L EQU H'FF' ; 2.5V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'F1' ; 1:1 _WDTPS_2_2H EQU H'F3' ; 1:2 _WDTPS_4_2H EQU H'F5' ; 1:4 _WDTPS_8_2H EQU H'F7' ; 1:8 _WDTPS_16_2H EQU H'F9' ; 1:16 _WDTPS_32_2H EQU H'FB' ; 1:32 _WDTPS_64_2H EQU H'FD' ; 1:64 _WDTPS_128_2H EQU H'FF' ; 1:128 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f442.inc0000644000175000017500000007224111156313161013151 00000000000000 LIST ; P18F442.INC Standard Header File, Version 1.4 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F442 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F442 ; 2. LIST directive in the source file ; LIST P=PIC18F442 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;1.0 03/23/01 Modified C442 for F442 tr ;1.1 08/01/01 Added EECON1 bits, corrected code protect config bit inserts ;1.2 09/17/01 Corrected MAXRAM,BADRAM tr ;1.3 10/23/01 Corrected CONFIG bits/registers tr/pas ;1.4 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F442 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR2 Bits ---------------------------------------------------------- EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 AN5 EQU 0 RE1 EQU 1 WR EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 AN7 EQU 2 ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'300'-H'F7F' __BADRAM H'F85'-H'F88' __BADRAM H'F8E'-H'F91' __BADRAM H'F97'-H'F9C' __BADRAM H'FA3'-H'FA5' __BADRAM H'FAA' __BADRAM H'FB4'-H'FB9' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p16f636.inc0000644000175000017500000002574111156521301013154 00000000000000 LIST ; P16F636.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F636 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F636 ; 2. LIST directive in the source file ; LIST P=PIC16F636 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 12/07/03 Original ;1.10 04/19/04 Update to match first release datasheet --kjd ;1.20 06/07/04 Update and correct badram definitions --kjd ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F636 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ ;Bank 0 INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' WDTCON EQU H'0018' CMCON0 EQU H'0019' CMCON1 EQU H'001A' ;Bank 1 OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' LVDCON EQU H'0094' WPUDA EQU H'0095' IOCA EQU H'0096' WDA EQU H'0097' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ;Bank 2 CRCON EQU H'0110' CRDAT0 EQU H'0111' CRDAT1 EQU H'0112' CRDAT2 EQU H'0113' CRDAT3 EQU H'0114' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' LVDIF EQU H'0006' CRIF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' OSFIF EQU H'0002' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' LVDIE EQU H'0006' CRIE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' OSFIE EQU H'0002' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBODEN EQU H'0004' NOT_WUR EQU H'0003' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits ---------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CRCON Bits -------------------------------------------------------- GO EQU H'0007' ENC_DEC EQU H'0006' CRREG1 EQU H'0001' CRREG0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDA Bits ----------------------------------------------------------- WDA5 EQU H'0005' WDA4 EQU H'0004' WDA2 EQU H'0002' WDA1 EQU H'0001' WDA0 EQU H'0000' ;----- WPUDA Bits ----------------------------------------------------------- WPUDA5 EQU H'0005' WPUDA4 EQU H'0004' WPUDA2 EQU H'0002' WPUDA1 EQU H'0001' WPUDA0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F' __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF' __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186' __BADRAM H'188'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _WUREN_ON EQU H'2FFF' _WUREN_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16c711.inc0000644000175000017500000001250511156313161013140 00000000000000 LIST ; P16C711.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C711 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C711 ; 2. LIST directive in the source file ; LIST P=PIC16C711 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C711 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ADCON0 EQU H'0008' ADRES EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PCON EQU H'0087' ADCON1 EQU H'0088' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADIF EQU H'0001' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' ADIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'CF' __BADRAM H'07', H'50'-H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ON EQU H'004F' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f45j10.inc0000644000175000017500000010214411156521301013374 00000000000000 LIST ;========================================================================== ; MPASM PIC18F45J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F45J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F45J10 ; 2. LIST directive in the source file ; LIST P=PIC18F45J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F45J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' SSP2CON2 EQU H'0F85' SSP2CON1 EQU H'0F86' SSP2STAT EQU H'0F87' SSP2ADD EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' SSP2BUF EQU H'0F8E' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' SPBRGH EQU H'0FB0' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' VREFM EQU H'0002' VREFP EQU H'0003' SS1 EQU H'0005' CVREF EQU H'0002' C2OUT_PORTA EQU H'0005' NOT_SS1 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0006' PGD EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' T0CKI EQU H'0005' FLT0 EQU H'0000' C1OUT_PORTB EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' SCL EQU H'0003' SDA EQU H'0004' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' SCK2 EQU H'0000' SDI2 EQU H'0001' SDO2 EQU H'0002' SS2 EQU H'0003' NOT_SS2 EQU H'0003' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' T0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F7F' __BADRAM H'0F8F'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB1'-H'0FB3' __BADRAM H'0FB9' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; CCP2 MUX bit: ; CCP2MX = ALTERNATE CCP2 is multiplexed with RB3 ; CCP2MX = DEFAULT CCP2 is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c781.inc0000644000175000017500000002674111156313161013156 00000000000000 LIST ; P16C782.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C782 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C782 ; 2. LIST directive in the source file ; LIST P=PIC16C782 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 16May2001 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C781 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' WPUB EQU H'0095' IOCB EQU H'0096' REFCON EQU H'009B' LVDCON EQU H'009C' ANSEL EQU H'009D' ADCON1 EQU H'009F' PMDATL EQU H'010C' PMADRL EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' CALCON EQU H'0110' PSMCCON0 EQU H'0111' PSMCCON1 EQU H'0112' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' OPACON EQU H'011C' DAC EQU H'011E' DACON0 EQU H'011F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- LVDIF EQU H'0007' ADIF EQU H'0006' C2IF EQU H'0005' C1IF EQU H'0004' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- LVDIE EQU H'0007' ADIE EQU H'0006' C2IE EQU H'0005' C1IE EQU H'0004' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- WDTON EQU H'0004' OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- VREFEN EQU H'0003' VREFOE EQU H'0002' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- CALCON Bits -------------------------------------------------------- CAL EQU H'0007' CALERR EQU H'0006' CALREF EQU H'0005' ;----- PSMCCON0 Bits ------------------------------------------------------ SMCCL1 EQU H'0007' SMCCL0 EQU H'0006' MINDC1 EQU H'0005' MINDC0 EQU H'0004' MAXDC1 EQU H'0003' MAXDC0 EQU H'0002' DC1 EQU H'0001' DC0 EQU H'0000' ;----- PSMCCON1 Bits ------------------------------------------------------ SMCON EQU H'0007' S1APOL EQU H'0006' S1BPOL EQU H'0005' SCEN EQU H'0003' SMCOM EQU H'0002' PWM EQU H'0001' PSM EQU H'0001' NOT_PSM EQU H'0001' SMCCS EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------ C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1SP EQU H'0003' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------ C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2SP EQU H'0003' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------ MC1OUT EQU H'0007' MC2OUT EQU H'0006' C2SYNC EQU H'0000' ;----- OPACON Bits ------------------------------------------------------- OPAON EQU H'0007' CMPEN EQU H'0006' GBWP EQU H'0000' ;----- DACON Bits -------------------------------------------------------- DAON EQU H'0007' DAOE EQU H'0006' DARS1 EQU H'0001' DARS0 EQU H'0000' ;----- PMCON1 Bits ------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'0D', H'11'-H'1D' __BADRAM H'87'-H'89', H'8D' __BADRAM H'8F'-H'94', H'97'-H'9A', H'9E', H'C0'-H'EF' __BADRAM H'105', H'107'-H'109', H'113'-H'118' __BADRAM H'11D', H'120'-H'16F' __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CFF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _MCLRE_OFF EQU H'3FDF' _MCLRE_ON EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FFB' _HS_OSC EQU H'3FFA' _XT_OSC EQU H'3FF9' _LP_OSC EQU H'3FF8' LIST gputils-0.13.7/header/p18f86j65.inc0000644000175000017500000014701611156521301013422 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J65 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J65 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J65 ; 2. LIST directive in the source file ; LIST P=PIC18F86J65 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J65 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RJPU EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2_PORTC EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2_PORTE EQU H'0007' ECCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' ECCP3 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ4 EQU H'0004' RJ5 EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ4 EQU H'0004' LATJ5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ4 EQU H'0004' RJ5 EQU H'0005' ;----- TRISJ Bits ----------------------------------------------------- TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0F62'-H'0F66' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ; ECCP MUX bit: ; ECCPMX = OFF ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = ON ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = OFF ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) ; CCP2MX = ON ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f66j60.inc0000644000175000017500000013431211156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J60 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J60 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J60 ; 2. LIST directive in the source file ; LIST P=PIC18F66J60 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J60 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2 EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' CCP3 EQU H'0001' CCP4 EQU H'0002' ECCP3 EQU H'0001' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG4 EQU H'0004' CCP5 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0F62'-H'0F66' __BADRAM H'0F6B'-H'0F6F' __BADRAM H'0F7C'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p17c42.inc0000644000175000017500000002505111156313161013056 00000000000000 LIST ; P17C42.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C42 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C42 ; 2. LIST directive in the source file ; LIST P=PIC17C42 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 07/15/96 Corrected MAXRAM ;1.02 06/28/96 Corrected MAXRAM, BADRAM, and registers in upper banks ;1.01 04/10/96 Added _WDT_OFF value, PSx values ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C42 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCREG EQU H'0014' TXSTA EQU H'0015' TXREG EQU H'0016' SPBRG EQU H'0017' ; PRODL EQU H'0018' ; not on the 17C42 ; PRODH EQU H'0019' ; not on the 17C42 DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' PIE EQU H'0117' TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' NOT_PD EQU H'0002' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIE Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' RCIE EQU H'0000' ;----- PIR Bits ----------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' RCIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' T0CKI EQU H'0001' INT EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' T0PS2 EQU H'0003' PS2 EQU H'0003' T0PS1 EQU H'0002' PS1 EQU H'0002' T0PS0 EQU H'0001' PS0 EQU H'0001' ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3FF' __BADRAM H'118'-H'1FF', H'218'-H'2FF', H'318'-H'3FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'FFAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p18c442.inc0000644000175000017500000006220511156313161013145 00000000000000 LIST ; P18C442.INC Standard Header File, Version 0.12 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C442 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C442 ; 2. LIST directive in the source file ; LIST P=PIC18C442 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.02 25 Nov 98 Preliminary Release drj ;0.03 07 Dec 98 Added compatibility #defines drj ;0.04 10 Dec 98 Added bits defs and new config jt ;0.05 14 Dec 98 Incorporated ko comments dj ;0.06 12 Jan 99 Changed config bits dj ;0.07 13 Jan 99 Changed BODEN to BOREN dj ;0.08 1 Apr 99 Added TRIS aliases ;0.09 17 Jun 99 Clean up ;0.10 23 Sep 99 Compatibility with PIC18Cxx2 Data Sheet (Rev B) ; and Added I/O Pin definitions mp ;0.11 29 Jun 00 Added support for Device ID/Revision & ID locations rr ;0.12 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C442 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' ;RESERVED_0FA7 EQU H'0FA7' ;RESERVED_0FA6 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' LWRT EQU H'0006' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- IPR2 Bits ---------------------------------------------------------- BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 AN5 EQU 0 RE1 EQU 1 WR EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 AN7 EQU 2 ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM H'1FF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Code Protect: ; CP = ON Enabled ; CP = OFF Disabled ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 0 300000h ; CONFIG1H = Configuration Byte 1 300001h ; CONFIG2L = Configuration Byte 3 300002h ; CONFIG2H = Configuration Byte 4 300003h ; CONFIG3L = Configuration Byte 5 300004h ; CONFIG3H = Configuration Byte 6 300005h ; CONFIG4L = Configuration Byte 7 300006h ; CONFIG4H = Configuration Byte 8 300007h ; ;========================================================================== ; ;Configuration Byte 0 Options _CP_ON_0 EQU H'00' ; Code Protect enable _CP_OFF_0 EQU H'FF' ;Configuration Byte 1 Options _OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1 EQU H'FF' _LP_OSC_1 EQU H'F8' ; Oscillator type _XT_OSC_1 EQU H'F9' _HS_OSC_1 EQU H'FA' _RC_OSC_1 EQU H'FB' _EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1 EQU H'FE' ; HS PLL _RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options _BOR_ON_2 EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2 EQU H'FD' _PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable _PWRT_ON_2 EQU H'FE' _BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2 EQU H'FB' ; 2.7v _BORV_42_2 EQU H'F7' ; 4.2v _BORV_45_2 EQU H'F3' ; 4.5v ;Configuration Byte 3 Options _WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_3 EQU H'FE' _WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_3 EQU H'FD' _WDTPS_32_3 EQU H'FB' _WDTPS_16_3 EQU H'F9' _WDTPS_8_3 EQU H'F7' _WDTPS_4_3 EQU H'F5' _WDTPS_2_3 EQU H'F3' _WDTPS_1_3 EQU H'F1' ;Configuration Byte 5 Options _CCP2MX_ON_5 EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_5 EQU H'FE' ;Configuration Byte 6 Options _STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_6 EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG0 EQU H'300000' _CONFIG1 EQU H'300001' _CONFIG2 EQU H'300002' _CONFIG3 EQU H'300003' _CONFIG4 EQU H'300004' _CONFIG5 EQU H'300005' _CONFIG6 EQU H'300006' _CONFIG7 EQU H'300007' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 0 ; __CONFIG _CONFIG0, _CP_OFF_0 ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1 ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2 ;Program Configuration Register 3 ; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3 ;Program Configuration Register 5 ;__CONFIG _CONFIG5, _CCP2MX_ON_5 ;Program Configuration Register 6 ; __CONFIG _CONFIG6, _STVR_ON_6 ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p18f86j10.inc0000644000175000017500000014201611156521301013403 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J10 ; 2. LIST directive in the source file ; LIST P=PIC18F86J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f8627.inc0000644000175000017500000021376711156521301013255 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8627 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8627 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8627 ; 2. LIST directive in the source file ; LIST P=PIC18F8627 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8627 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ECCP2_PORTB EQU H'0003' P2A_PORTB EQU H'0003' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C_PORTE EQU H'0003' P3B_PORTE EQU H'0004' P1C_PORTE EQU H'0005' P1B_PORTE EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' P3C_PORTH EQU H'0004' P3B_PORTH EQU H'0005' P1C_PORTH EQU H'0006' P1B_PORTH EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; Address Bus Width Select bits: ; ADDRBW = ADDR8BIT 8-bit Address Bus ; ADDRBW = ADDR12BIT 12-bit Address Bus ; ADDRBW = ADDR16BIT 16-bit Address Bus ; ADDRBW = ADDR20BIT 20-bit Address Bus ; ; Data Bus Width Select bit: ; DATABW = DATA8BIT 8-bit External Bus mode ; DATABW = DATA16BIT 16-bit External Bus mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits ; WAIT = OFF Wait selections are unavailable for table reads and table writes ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; ECCP MUX bit: ; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively ; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively ; ; CCP2 MUX bit: ; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _ADDRBW_ADDR8BIT_3L EQU H'CF' ; 8-bit Address Bus _ADDRBW_ADDR12BIT_3L EQU H'DF' ; 12-bit Address Bus _ADDRBW_ADDR16BIT_3L EQU H'EF' ; 16-bit Address Bus _ADDRBW_ADDR20BIT_3L EQU H'FF' ; 20-bit Address Bus _DATABW_DATA8BIT_3L EQU H'BF' ; 8-bit External Bus mode _DATABW_DATA16BIT_3L EQU H'FF' ; 16-bit External Bus mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits _WAIT_OFF_3L EQU H'FF' ; Wait selections are unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _ECCPMX_PORTH_3H EQU H'FD' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively _ECCPMX_PORTE_3H EQU H'FF' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively _CCP2MX_PORTBE_3H EQU H'FE' ; ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18lf26j11.inc0000644000175000017500000014440511156521301013556 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF26J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF26J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF26J11 ; 2. LIST directive in the source file ; LIST P=PIC18LF26J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF26J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ULPWU EQU H'0000' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F65' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f526.inc0000644000175000017500000001577111156521301013154 00000000000000 LIST ; P16F526.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; PIC16F526 A1 Silicon Only (10/09/07) ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16F526 ; 2. LIST directive in the source file ; LIST P=16F526 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 4/23/07 Initial Release ;1.50 10/09/07 Release for the PIC16F526 Silicon Revision A1. ; ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F526 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' CM1CON0 EQU H'0008' ADCON0 EQU H'0009' ADRES EQU H'000A' CM2CON0 EQU H'000B' VRCON EQU H'000C' EECON EQU H'0021' EEDATA EQU H'0025' EEADR EQU H'0026' ;----- EECON ------------------------------------------------------------- FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- RBWUF EQU H'0007' CWUF EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- VRCON0 Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1OUT EQU H'0007' NOT_C1OUTEN EQU H'0006' C1POL EQU H'0005' NOT_C1T0CS EQU H'0004' C1ON EQU H'0003' C1NREF EQU H'0002' C1PREF EQU H'0001' NOT_C1WU EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2OUT EQU H'0007' NOT_C2OUTEN EQU H'0006' C2POL EQU H'0005' C2PREF2 EQU H'0004' C2ON EQU H'0003' C2NREF EQU H'0002' C2PREF1 EQU H'0001' NOT_C2WU EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- ADRES Bits -------------------------------------------------------- ADRES7 EQU H'0007' ADRES6 EQU H'0006' ADRES5 EQU H'0005' ADRES4 EQU H'0004' ADRES3 EQU H'0003' ADRES2 EQU H'0002' ADRES1 EQU H'0001' ADRES0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBWU EQU H'0007' NOT_RBPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPDF_OFF EQU H'0FFF' _CPDF_ON EQU H'0F7F' _IOSCFS_8MHz EQU H'0FFF' _IOSCFS_4MHz EQU H'0FBF' _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FDF' _CP_ON EQU H'0FEF' _CP_OFF EQU H'0FFF' _WDTE_ON EQU H'0FFF' _WDTE_OFF EQU H'0FF7' _LP_OSC EQU H'0FF8' _XT_OSC EQU H'0FF9' _HS_OSC EQU H'0FFA' _EC_OSC EQU H'0FFB' _IntRC_OSC_RB4 EQU H'0FFC' _IntRC_OSC_CLKOUT EQU H'0FFD' _ExtRC_OSC_RB4 EQU H'0FFE' _ExtRC_OSC_CLKOUT EQU H'0FFF' LIST gputils-0.13.7/header/pmcv18a.inc0000644000175000017500000000651711156521301013420 00000000000000 LIST ; PMCV18A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the MCV18A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PMCV18A ; 2. LIST directive in the source file ; LIST P=MCV18A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 1/3/2008 First revision. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __MCV18A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- PA2 EQU H'0007' PA1 EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _HS_OSC EQU H'0FFE' _RC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f458.inc0000644000175000017500000014622211156521301013156 00000000000000 LIST ; P18F458.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F458 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F458 ; 2. LIST directive in the source file ; LIST P=PIC18F458 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.90 15 May 2001 Preliminary Release dzb ;0.99 29 June2001 Rev 1 dzb ;1.00 29 Oct.2001 Corrections & Additions cjh ;1.10 25 Jun 2002 Added CFGS as EECON1 bit 6 name pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F458 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' ECCPR1H EQU H'0FBC' ECCPR1L EQU H'0FBB' ECCP1CON EQU H'0FBA' ECCP1DEL EQU H'0FB7' ECCPAS EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TXERRCNT EQU H'0F76' RXERRCNT EQU H'0F75' COMSTAT EQU H'0F74' CIOCON EQU H'0F73' BRGCON3 EQU H'0F72' BRGCON2 EQU H'0F71' BRGCON1 EQU H'0F70' CANCON EQU H'0F6F' CANSTAT EQU H'0F6E' RXB0D7 EQU H'0F6D' RXB0D6 EQU H'0F6C' RXB0D5 EQU H'0F6B' RXB0D4 EQU H'0F6A' RXB0D3 EQU H'0F69' RXB0D2 EQU H'0F68' RXB0D1 EQU H'0F67' RXB0D0 EQU H'0F66' RXB0DLC EQU H'0F65' RXB0EIDL EQU H'0F64' RXB0EIDH EQU H'0F63' RXB0SIDL EQU H'0F62' RXB0SIDH EQU H'0F61' RXB0CON EQU H'0F60' CANSTATRO1 EQU H'0F5E' RXB1D7 EQU H'0F5D' RXB1D6 EQU H'0F5C' RXB1D5 EQU H'0F5B' RXB1D4 EQU H'0F5A' RXB1D3 EQU H'0F59' RXB1D2 EQU H'0F58' RXB1D1 EQU H'0F57' RXB1D0 EQU H'0F56' RXB1DLC EQU H'0F55' RXB1EIDL EQU H'0F54' RXB1EIDH EQU H'0F53' RXB1SIDL EQU H'0F52' RXB1SIDH EQU H'0F51' RXB1CON EQU H'0F50' CANSTATRO2 EQU H'0F4E' TXB0D7 EQU H'0F4D' TXB0D6 EQU H'0F4C' TXB0D5 EQU H'0F4B' TXB0D4 EQU H'0F4A' TXB0D3 EQU H'0F49' TXB0D2 EQU H'0F48' TXB0D1 EQU H'0F47' TXB0D0 EQU H'0F46' TXB0DLC EQU H'0F45' TXB0EIDL EQU H'0F44' TXB0EIDH EQU H'0F43' TXB0SIDL EQU H'0F42' TXB0SIDH EQU H'0F41' TXB0CON EQU H'0F40' CANSTATRO3 EQU H'0F3E' TXB1D7 EQU H'0F3D' TXB1D6 EQU H'0F3C' TXB1D5 EQU H'0F3B' TXB1D4 EQU H'0F3A' TXB1D3 EQU H'0F39' TXB1D2 EQU H'0F38' TXB1D1 EQU H'0F37' TXB1D0 EQU H'0F36' TXB1DLC EQU H'0F35' TXB1EIDL EQU H'0F34' TXB1EIDH EQU H'0F33' TXB1SIDL EQU H'0F32' TXB1SIDH EQU H'0F31' TXB1CON EQU H'0F30' CANSTATRO4 EQU H'0F2E' TXB2D7 EQU H'0F2D' TXB2D6 EQU H'0F2C' TXB2D5 EQU H'0F2B' TXB2D4 EQU H'0F2A' TXB2D3 EQU H'0F29' TXB2D2 EQU H'0F28' TXB2D1 EQU H'0F27' TXB2D0 EQU H'0F26' TXB2DLC EQU H'0F25' TXB2EIDL EQU H'0F24' TXB2EIDH EQU H'0F23' TXB2SIDL EQU H'0F22' TXB2SIDH EQU H'0F21' TXB2CON EQU H'0F20' RXM1EIDL EQU H'0F1F' RXM1EIDH EQU H'0F1E' RXM1SIDL EQU H'0F1D' RXM1SIDH EQU H'0F1C' RXM0EIDL EQU H'0F1B' RXM0EIDH EQU H'0F1A' RXM0SIDL EQU H'0F19' RXM0SIDH EQU H'0F18' RXF5EIDL EQU H'0F17' RXF5EIDH EQU H'0F16' RXF5SIDL EQU H'0F15' RXF5SIDH EQU H'0F14' RXF4EIDL EQU H'0F13' RXF4EIDH EQU H'0F12' RXF4SIDL EQU H'0F11' RXF4SIDH EQU H'0F10' RXF3EIDL EQU H'0F0F' RXF3EIDH EQU H'0F0E' RXF3SIDL EQU H'0F0D' RXF3SIDH EQU H'0F0C' RXF2EIDL EQU H'0F0B' RXF2EIDH EQU H'0F0A' RXF2SIDL EQU H'0F09' RXF2SIDH EQU H'0F08' RXF1EIDL EQU H'0F07' RXF1EIDH EQU H'0F06' RXF1SIDL EQU H'0F05' RXF1SIDH EQU H'0F04' RXF0EIDL EQU H'0F03' RXF0EIDH EQU H'0F02' RXF0SIDL EQU H'0F01' RXF0SIDH EQU H'0F00' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' SP4 EQU H'0004' SP3 EQU H'0003' SP2 EQU H'0002' SP1 EQU H'0001' SP0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IVRST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ECCP1CON Bits ------------------------------------------------------ EPWM1M1 EQU H'0007' EPWM1M0 EQU H'0006' EDC2B1 EQU H'0005' EDC2B0 EQU H'0004' ECCP1M3 EQU H'0003' ECCP1M2 EQU H'0002' ECCP1M1 EQU H'0001' ECCP1M0 EQU H'0000' ;----- ECCP1DEL Bits ----------------------------------------------------- EPDC0 EQU H'0000' EPDC1 EQU H'0001' EPDC2 EQU H'0002' EPDC3 EQU H'0003' EPDC4 EQU H'0004' EPDC5 EQU H'0005' EPDC6 EQU H'0006' EPDC7 EQU H'0007' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' ; For backward compatibility CVRR EQU H'0005' CVRSS EQU H'0004' ; For backward compatibility CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' ; For backward compatibility C2INV EQU H'0005' C1INV EQU H'0004' ; For backward compatibility CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3ECCP1 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' EEFS EQU H'0006' ; Backward compatibility only CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR3 Bits ---------------------------------------------------------- IRXIP EQU H'0007' WAKIP EQU H'0006' ERRIP EQU H'0005' TXB2IP EQU H'0004' TXB1IP EQU H'0003' TXB0IP EQU H'0002' RXB1IP EQU H'0001' RXB0IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- IRXIF EQU H'0007' WAKIF EQU H'0006' ERRIF EQU H'0005' TXB2IF EQU H'0004' TXB1IF EQU H'0003' TXB0IF EQU H'0002' RXB1IF EQU H'0001' RXB0IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- IRXIE EQU H'0007' WAKIE EQU H'0006' ERRIE EQU H'0005' TXB2IE EQU H'0004' TXB1IE EQU H'0003' TXB0IE EQU H'0002' RXB1IE EQU H'0001' RXB0IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' ECCP1IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' ECCP1IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' ECCP1IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- COMSTAT Bits --------------------------------------------------------- RX1OVFL EQU H'0007' RXB0OVFL EQU H'0007' RX2OVFL EQU H'0006' RXB1OVFL EQU H'0006' TXBO EQU H'0005' TXBP EQU H'0004' RXBP EQU H'0003' TXWARN EQU H'0002' RXWARN EQU H'0001' EWARN EQU H'0000' ;----- CIOCON Bits ----------------------------------------------------------- ENDRHI EQU H'0005' CANCAP EQU H'0004' ;----- BRGCON3 Bits ---------------------------------------------------------- WAKFIL EQU H'0006' SEG2PH2 EQU H'0002' SEG2PH1 EQU H'0001' SEG2PH0 EQU H'0000' ;----- BRGCON2 Bits ----------------------------------------------------------- SEG2PHTS EQU H'0007' SAM EQU H'0006' SEG1PH2 EQU H'0005' SEG1PH1 EQU H'0004' SEG1PH0 EQU H'0003' PRSEG2 EQU H'0002' PRSEG1 EQU H'0001' PRSEG0 EQU H'0000' ;----- BRGCON1 Bits ------------------------------------------------------------ SJW1 EQU H'0007' SJW0 EQU H'0006' BRP5 EQU H'0005' BRP4 EQU H'0004' BRP3 EQU H'0003' BRP2 EQU H'0002' BRP1 EQU H'0001' BRP0 EQU H'0000' ;----- CANCON Bits ------------------------------------------------------------- REQOP2 EQU H'0007' REQOP1 EQU H'0006' REQOP0 EQU H'0005' ABAT EQU H'0004' WIN2 EQU H'0003' WIN1 EQU H'0002' WIN0 EQU H'0001' ;----- CANSTAT Bits ----------------------------------------------------------- OPMODE2 EQU H'0007' OPMODE1 EQU H'0006' OPMODE0 EQU H'0005' ICODE2 EQU H'0003' ICODE1 EQU H'0002' ICODE0 EQU H'0001' ;----- RXBnCON Bits ----------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' RXB0DBEN EQU H'0002' FILHIT2 EQU H'0002' JTOFF EQU H'0001' FILHIT1 EQU H'0001' FILHIT0 EQU H'0000' ;----- TXBnCON Bits ---------------------------------------------------------- TXABT EQU H'0006' TXLARB EQU H'0005' TXERR EQU H'0004' TXREQ EQU H'0003' TXPRI1 EQU H'0001' TXPRI0 EQU H'0000' ;----- TXERRCNT Bits ---------------------------------------------------------- TEC7 EQU H'0007' TEC6 EQU H'0006' TEC5 EQU H'0005' TEC4 EQU H'0004' TEC3 EQU H'0003' TEC2 EQU H'0002' TEC1 EQU H'0001' TEC0 EQU H'0000' ;----- RXERRCNT Bits ---------------------------------------------------------- REC7 EQU H'0007' REC6 EQU H'0006' REC5 EQU H'0005' REC4 EQU H'0004' REC3 EQU H'0003' REC2 EQU H'0002' REC1 EQU H'0001' REC0 EQU H'0000' ;----- RXBnDLC and TXBnDLC Bits ----------------------------------------------- RXRTR EQU H'0006' TXRTR EQU H'0006' RESB1 EQU H'0005' RESB0 EQU H'0004' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DLC0 EQU H'0000' ;----- RXBnEIDL, RXFnEIDL, RXMnEIDL, and TXBnEIDL Bits ------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXBnEIDH, RXFnEIDH, RXMnEIDH, and TXBnEIDH Bits ------------------------- EID15 EQU H'0007' EID14 EQU H'0006' EID13 EQU H'0005' EID12 EQU H'0004' EID11 EQU H'0003' EID10 EQU H'0002' EID9 EQU H'0001' EID8 EQU H'0000' ;----- RXBnSIDL, RXFnSIDL, RXMnSIDL, and TXBnSIDL Bits ---------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' SRR EQU H'0004' EXID EQU H'0003' EXIDE EQU H'0003' EXIDEN EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXBnSIDH, RXFnSIDH, RXMnSIDH, and TXBnSIDH Bits ---------------------- SID10 EQU H'0007' SID9 EQU H'0006' SID8 EQU H'0005' SID7 EQU H'0004' SID6 EQU H'0003' SID5 EQU H'0002' SID4 EQU H'0001' SID3 EQU H'0001' ;----- RXB0D7 Bits ---------------------------------------------------------- RB0D77 EQU H'0007' RB0D76 EQU H'0006' RB0D75 EQU H'0005' RB0D74 EQU H'0004' RB0D73 EQU H'0003' RB0D72 EQU H'0002' RB0D71 EQU H'0001' RB0D70 EQU H'0000' ;----- RXB0D6 Bits ---------------------------------------------------------- RB0D67 EQU H'0007' RB0D66 EQU H'0006' RB0D65 EQU H'0005' RB0D64 EQU H'0004' RB0D63 EQU H'0003' RB0D62 EQU H'0002' RB0D61 EQU H'0001' RB0D60 EQU H'0000' ;----- RXB0D5 Bits ---------------------------------------------------------- RB0D57 EQU H'0007' RB0D56 EQU H'0006' RB0D55 EQU H'0005' RB0D54 EQU H'0004' RB0D53 EQU H'0003' RB0D52 EQU H'0002' RB0D51 EQU H'0001' RB0D50 EQU H'0000' ;----- RXB0D4 Bits ---------------------------------------------------------- RB0D47 EQU H'0007' RB0D46 EQU H'0006' RB0D45 EQU H'0005' RB0D44 EQU H'0004' RB0D43 EQU H'0003' RB0D42 EQU H'0002' RB0D41 EQU H'0001' RB0D40 EQU H'0000' ;----- RXB0D3 Bits ---------------------------------------------------------- RB0D37 EQU H'0007' RB0D36 EQU H'0006' RB0D35 EQU H'0005' RB0D34 EQU H'0004' RB0D33 EQU H'0003' RB0D32 EQU H'0002' RB0D31 EQU H'0001' RB0D30 EQU H'0000' ;----- RXB0D2 Bits ---------------------------------------------------------- RB0D27 EQU H'0007' RB0D26 EQU H'0006' RB0D25 EQU H'0005' RB0D24 EQU H'0004' RB0D23 EQU H'0003' RB0D22 EQU H'0002' RB0D21 EQU H'0001' RB0D20 EQU H'0000' ;----- RXB0D1 Bits ---------------------------------------------------------- RB0D17 EQU H'0007' RB0D16 EQU H'0006' RB0D15 EQU H'0005' RB0D14 EQU H'0004' RB0D13 EQU H'0003' RB0D12 EQU H'0002' RB0D11 EQU H'0001' RB0D10 EQU H'0000' ;----- RXB0D0 Bits ---------------------------------------------------------- RB0D07 EQU H'0007' RB0D06 EQU H'0006' RB0D05 EQU H'0005' RB0D04 EQU H'0004' RB0D03 EQU H'0003' RB0D02 EQU H'0002' RB0D01 EQU H'0001' RB0D00 EQU H'0000' ;----- RXB1D7 Bits ---------------------------------------------------------- RXB1D77 EQU H'0007' RXB1D76 EQU H'0006' RXB1D75 EQU H'0005' RXB1D74 EQU H'0004' RXB1D73 EQU H'0003' RXB1D72 EQU H'0002' RXB1D71 EQU H'0001' RXB1D70 EQU H'0000' ;----- RXB1D6 Bits ---------------------------------------------------------- RXB1D67 EQU H'0007' RXB1D66 EQU H'0006' RXB1D65 EQU H'0005' RXB1D64 EQU H'0004' RXB1D63 EQU H'0003' RXB1D62 EQU H'0002' RXB1D61 EQU H'0001' RXB1D60 EQU H'0000' ;----- RXB1D5 Bits ---------------------------------------------------------- RXB1D57 EQU H'0007' RXB1D56 EQU H'0006' RXB1D55 EQU H'0005' RXB1D54 EQU H'0004' RXB1D53 EQU H'0003' RXB1D52 EQU H'0002' RXB1D51 EQU H'0001' RXB1D50 EQU H'0000' ;----- RXB1D4 Bits ---------------------------------------------------------- RXB1D47 EQU H'0007' RXB1D46 EQU H'0006' RXB1D45 EQU H'0005' RXB1D44 EQU H'0004' RXB1D43 EQU H'0003' RXB1D42 EQU H'0002' RXB1D41 EQU H'0001' RXB1D40 EQU H'0000' ;----- RXB1D3 Bits ---------------------------------------------------------- RXB1D37 EQU H'0007' RXB1D36 EQU H'0006' RXB1D35 EQU H'0005' RXB1D34 EQU H'0004' RXB1D33 EQU H'0003' RXB1D32 EQU H'0002' RXB1D31 EQU H'0001' RXB1D30 EQU H'0000' ;----- RXB1D2 Bits ---------------------------------------------------------- RXB1D27 EQU H'0007' RXB1D26 EQU H'0006' RXB1D25 EQU H'0005' RXB1D24 EQU H'0004' RXB1D23 EQU H'0003' RXB1D22 EQU H'0002' RXB1D21 EQU H'0001' RXB1D20 EQU H'0000' ;----- RXB1D1 Bits ---------------------------------------------------------- RXB1D17 EQU H'0007' RXB1D16 EQU H'0006' RXB1D15 EQU H'0005' RXB1D14 EQU H'0004' RXB1D13 EQU H'0003' RXB1D12 EQU H'0002' RXB1D11 EQU H'0001' RXB1D10 EQU H'0000' ;----- RXB1D0 Bits ---------------------------------------------------------- RXB1D07 EQU H'0007' RXB1D06 EQU H'0006' RXB1D05 EQU H'0005' RXB1D04 EQU H'0004' RXB1D03 EQU H'0003' RXB1D02 EQU H'0002' RXB1D01 EQU H'0001' RXB1D00 EQU H'0000' ;----- TXB2D7 Bits ---------------------------------------------------------- TXB2D77 EQU H'0007' TXB2D76 EQU H'0006' TXB2D75 EQU H'0005' TXB2D74 EQU H'0004' TXB2D73 EQU H'0003' TXB2D72 EQU H'0002' TXB2D71 EQU H'0001' TXB2D70 EQU H'0000' ;----- TXB2D6 Bits ---------------------------------------------------------- TXB2D67 EQU H'0007' TXB2D66 EQU H'0006' TXB2D65 EQU H'0005' TXB2D64 EQU H'0004' TXB2D63 EQU H'0003' TXB2D62 EQU H'0002' TXB2D61 EQU H'0001' TXB2D60 EQU H'0000' ;----- TXB2D5 Bits ---------------------------------------------------------- TXB2D57 EQU H'0007' TXB2D56 EQU H'0006' TXB2D55 EQU H'0005' TXB2D54 EQU H'0004' TXB2D53 EQU H'0003' TXB2D52 EQU H'0002' TXB2D51 EQU H'0001' TXB2D50 EQU H'0000' ;----- TXB2D4 Bits ---------------------------------------------------------- TXB2D47 EQU H'0007' TXB2D46 EQU H'0006' TXB2D45 EQU H'0005' TXB2D44 EQU H'0004' TXB2D43 EQU H'0003' TXB2D42 EQU H'0002' TXB2D41 EQU H'0001' TXB2D40 EQU H'0000' ;----- TXB2D3 Bits ---------------------------------------------------------- TXB2D37 EQU H'0007' TXB2D36 EQU H'0006' TXB2D35 EQU H'0005' TXB2D34 EQU H'0004' TXB2D33 EQU H'0003' TXB2D32 EQU H'0002' TXB2D31 EQU H'0001' TXB2D30 EQU H'0000' ;----- TXB2D2 Bits ---------------------------------------------------------- TXB2D27 EQU H'0007' TXB2D26 EQU H'0006' TXB2D25 EQU H'0005' TXB2D24 EQU H'0004' TXB2D23 EQU H'0003' TXB2D22 EQU H'0002' TXB2D21 EQU H'0001' TXB2D20 EQU H'0000' ;----- TXB2D1 Bits ---------------------------------------------------------- TXB2D17 EQU H'0007' TXB2D16 EQU H'0006' TXB2D15 EQU H'0005' TXB2D14 EQU H'0004' TXB2D13 EQU H'0003' TXB2D12 EQU H'0002' TXB2D11 EQU H'0001' TXB2D10 EQU H'0000' ;----- TXB2D0 Bits ---------------------------------------------------------- TXB2D07 EQU H'0007' TXB2D06 EQU H'0006' TXB2D05 EQU H'0005' TXB2D04 EQU H'0004' TXB2D03 EQU H'0003' TXB2D02 EQU H'0002' TXB2D01 EQU H'0001' TXB2D00 EQU H'0000' ;----- TXB1D7 Bits ---------------------------------------------------------- TXB1D77 EQU H'0007' TXB1D76 EQU H'0006' TXB1D75 EQU H'0005' TXB1D74 EQU H'0004' TXB1D73 EQU H'0003' TXB1D72 EQU H'0002' TXB1D71 EQU H'0001' TXB1D70 EQU H'0000' ;----- TXB1D6 Bits ---------------------------------------------------------- TXB1D67 EQU H'0007' TXB1D66 EQU H'0006' TXB1D65 EQU H'0005' TXB1D64 EQU H'0004' TXB1D63 EQU H'0003' TXB1D62 EQU H'0002' TXB1D61 EQU H'0001' TXB1D60 EQU H'0000' ;----- TXB1D5 Bits ---------------------------------------------------------- TXB1D57 EQU H'0007' TXB1D56 EQU H'0006' TXB1D55 EQU H'0005' TXB1D54 EQU H'0004' TXB1D53 EQU H'0003' TXB1D52 EQU H'0002' TXB1D51 EQU H'0001' TXB1D50 EQU H'0000' ;----- TXB1D4 Bits ---------------------------------------------------------- TXB1D47 EQU H'0007' TXB1D46 EQU H'0006' TXB1D45 EQU H'0005' TXB1D44 EQU H'0004' TXB1D43 EQU H'0003' TXB1D42 EQU H'0002' TXB1D41 EQU H'0001' TXB1D40 EQU H'0000' ;----- TXB1D3 Bits ---------------------------------------------------------- TXB1D37 EQU H'0007' TXB1D36 EQU H'0006' TXB1D35 EQU H'0005' TXB1D34 EQU H'0004' TXB1D33 EQU H'0003' TXB1D32 EQU H'0002' TXB1D31 EQU H'0001' TXB1D30 EQU H'0000' ;----- TXB1D2 Bits ---------------------------------------------------------- TXB1D27 EQU H'0007' TXB1D26 EQU H'0006' TXB1D25 EQU H'0005' TXB1D24 EQU H'0004' TBB1D23 EQU H'0003' TXB1D22 EQU H'0002' TXB1D21 EQU H'0001' TXB1D20 EQU H'0000' ;----- TXB1D1 Bits ---------------------------------------------------------- TXB1D17 EQU H'0007' TXB1D16 EQU H'0006' TXB1D15 EQU H'0005' TXB1D14 EQU H'0004' TXB1D13 EQU H'0003' TXB1D12 EQU H'0002' TXB1D11 EQU H'0001' TXB1D10 EQU H'0000' ;----- TXB1D0 Bits ---------------------------------------------------------- TXB1D07 EQU H'0007' TXB1D06 EQU H'0006' TXB1D05 EQU H'0005' TXB1D04 EQU H'0004' TXB1D03 EQU H'0003' TXB1D02 EQU H'0002' TXB1D01 EQU H'0001' TXB1D00 EQU H'0000' ;----- TXB0D7 Bits ---------------------------------------------------------- TXB0D77 EQU H'0007' TXB0D76 EQU H'0006' TXB0D75 EQU H'0005' TXB0D74 EQU H'0004' TXB0D73 EQU H'0003' TXB0D72 EQU H'0002' TXB0D71 EQU H'0001' TXB0D70 EQU H'0000' ;----- TXB0D6 Bits ---------------------------------------------------------- TXB0D67 EQU H'0007' TXB0D66 EQU H'0006' TXB0D65 EQU H'0005' TXB0D64 EQU H'0004' TXB0D63 EQU H'0003' TXB0D62 EQU H'0002' TXB0D61 EQU H'0001' TXB0D60 EQU H'0000' ;----- TXB0D5 Bits ---------------------------------------------------------- TXB0D57 EQU H'0007' TXB0D56 EQU H'0006' TXB0D55 EQU H'0005' TXB0D54 EQU H'0004' TXB0D53 EQU H'0003' TXB0D52 EQU H'0002' TXB0D51 EQU H'0001' TXB0D50 EQU H'0000' ;----- TXB0D4 Bits ---------------------------------------------------------- TXB0D47 EQU H'0007' TXB0D46 EQU H'0006' TXB0D45 EQU H'0005' TXB0D44 EQU H'0004' TXB0D43 EQU H'0003' TXB0D42 EQU H'0002' TXB0D41 EQU H'0001' TXB0D40 EQU H'0000' ;----- TXB0D3 Bits ---------------------------------------------------------- TXB0D37 EQU H'0007' TXB0D36 EQU H'0006' TXB0D35 EQU H'0005' TXB0D34 EQU H'0004' TXB0D33 EQU H'0003' TXB0D32 EQU H'0002' TXB0D31 EQU H'0001' TXB0D30 EQU H'0000' ;----- TXB0D2 Bits ---------------------------------------------------------- TXB0D27 EQU H'0007' TXB0D26 EQU H'0006' TXB0D25 EQU H'0005' TXB0D24 EQU H'0004' TXB0D23 EQU H'0003' TXB0D22 EQU H'0002' TXB0D21 EQU H'0001' TXB0D20 EQU H'0000' ;----- TXB0D1 Bits ---------------------------------------------------------- TXB0D17 EQU H'0007' TXB0D16 EQU H'0006' TXB0D15 EQU H'0005' TXB0D14 EQU H'0004' TXB0D13 EQU H'0003' TXB0D12 EQU H'0002' TXB0D11 EQU H'0001' TXB0D10 EQU H'0000' ;----- TXB0D0 Bits ---------------------------------------------------------- TXB0D07 EQU H'0007' TXB0D06 EQU H'0006' TXB0D05 EQU H'0005' TXB0D04 EQU H'0004' TXB0D03 EQU H'0003' TXB0D02 EQU H'0002' TXB0D01 EQU H'0001' TXB0D00 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 CVREF EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 NOT_SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 CANTX EQU 2 RB3 EQU 3 CANRX EQU 3 RB4 EQU 4 RB5 EQU 5 PGM EQU 5 RB6 EQU 6 PGC EQU 6 RB7 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 C1INP EQU 0 RD1 EQU 1 PSP1 EQU 1 C1INM EQU 1 RD2 EQU 2 PSP2 EQU 2 C2INP EQU 2 RD3 EQU 3 PSP3 EQU 3 C2INM EQU 3 RD4 EQU 4 PSP4 EQU 4 ECCP1 EQU 4 P1A EQU 4 RD5 EQU 5 PSP5 EQU 5 P1B EQU 5 RD6 EQU 6 PSP6 EQU 6 P1C EQU 6 RD7 EQU 7 PSP7 EQU 7 P1D EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 NOT_RD EQU 0 AN5 EQU 0 RE1 EQU 1 ;WR EQU 1 *** Already defined by EECON.WR, also bit 1 NOT_WR EQU 1 AN6 EQU 1 RE2 EQU 2 CS EQU 2 NOT_CS EQU 2 AN7 EQU 2 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'600'-H'EFF' __BADRAM H'FD4',H'FC0',H'FB9',H'FB8',H'FAA',H'F97'-H'F9C' __BADRAM H'F8E'-H'F91',H'F85'-H'F88', H'F79'-H'F7F',H'F77' __BADRAM H'F5F',H'F4F',H'F3F',H'F2F' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000Ah ; CONFIG6H = Configuration Byte 6H 30000Bh ; CONFIG7L = Configuration Byte 7L 30000Ch ; CONFIG7H = Configuration Byte 7H 30000Dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_25_2L EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled _LVP_ON_4L EQU H'FF' ; Enableda _LVP_OFF_4L EQU H'FB' ; Disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;Configuration Byte 6H Options _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as _BOR_ON_2L). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_25_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16f689.inc0000644000175000017500000005020011156521301013150 00000000000000 LIST ; P16F689.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F689 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F689 ; 2. LIST directive in the source file ; LIST P=PIC16F689 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/12/04 Original ;2.00 04/21/05 Modified names to match released datasheet ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F689 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' SSPBUF EQU H'0013' SSPCON EQU H'0014' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPADD EQU H'0093' MSK EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' WDTCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' BAUDCTL EQU H'009B' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDAT EQU H'010C' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' WPUB EQU H'0115' IOCB EQU H'0116' VRCON EQU H'0118' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' ANSEL EQU H'011E' ANSELH EQU H'011F' EECON1 EQU H'018C' EECON2 EQU H'018D' SRCON EQU H'019E' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RABIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RABIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- SSPCON Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION Bits -------------------------------------------------------- NOT_RABPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TRISB7 EQU H'0007' TRISB6 EQU H'0006' TRISB5 EQU H'0005' TRISB4 EQU H'0004' ;----- TRISC Bits -------------------------------------------------------- TRISC7 EQU H'0007' TRISC6 EQU H'0006' TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits -------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' SENB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' ;----- IOCB Bits --------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'11'-H'12', H'15'-H'17', H'1B'-H'1D' __BADRAM H'88'-H'89', H'91'-H'92', H'9C'-H'9D' __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D' __BADRAM H'188'-H'189', H'18E'-H'19D', H'19F'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f8493.inc0000644000175000017500000017646211156521301013256 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8493 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8493 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8493 ; 2. LIST directive in the source file ; LIST P=PIC18F8493 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8493 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDSE4 EQU H'0F5E' LCDSE5 EQU H'0F5F' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG32 EQU H'0000' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F7D' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/ps810.inc0000644000175000017500000004602511156313161013015 00000000000000 NOLIST ; Based on PS500.INC, and PS810 DOS - WK 10/29/04 LIST ; PS810.INC Standard Header File, Version 0.1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PS810 Fuel Gage. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PS810 ; 2. LIST directive in the source file ; LIST P=PS810 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 01 Nov 2004 Initial release WK ; ; Verify Processor ; ;======================================================================= IFNDEF __PS810 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution ; #define DDRC TRISC ; PIC17Cxxx SFR substitution ; #define DDRD TRISD ; PIC17Cxxx SFR substitution ; #define DDRE TRISE ; PIC17Cxxx SFR substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' ; reserved H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved H'0FD4' OSCCON EQU H'0FD3' ; reserved H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' ; reserved H'0FCF' TMR1 EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' ; reserved H'0FCB' T2CON EQU H'0FCA' ASIBUF EQU H'0FC9' ASIADD EQU H'0FC8' ASISTAT EQU H'0FC7' ASICON1 EQU H'0FC6' ASICON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' ; reserved H'0FBF' ; reserved H'0FBE' ; reserved H'0FBD' ; reserved H'0FBC' ; reserved H'0FBB' ; reserved H'0FBA' ; reserved H'0FB9' ; reserved H'0FB8' ; reserved H'0FB7' ; reserved H'0FB6' ; reserved H'0FB5' CMCON EQU H'0FB4' ; reserved H'0FB3' TMR3 EQU H'0FB2' T3CON EQU H'0FB1' ; reserved H'0FB0' ; reserved H'0FAF' ; reserved H'0FAE' ; reserved H'0FAD' ; reserved H'0FAC' ; reserved H'0FAB' ; reserved H'0FAA' ; reserved H'0FA9' ; reserved H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved H'0FB5' ; reserved H'0FB4' ; reserved H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' BGCAL EQU H'0F9C' OSCCAL EQU H'0F9B' REFCAL EQU H'0F9A' ; reserved H'0F99' ; reserved H'0F98' ; reserved H'0F97' ; reserved H'0F96' ; reserved H'0F95' ; reserved H'0F94' TRISB EQU H'0F93' ; reserved H'0F92' PDPB EQU H'0F91' ; reserved H'0F90' ; reserved H'0F8F' ; reserved H'0F8E' ; reserved H'0F8D' ; reserved H'0F8C' ; reserved H'0F8B' LATB EQU H'0F8A' ; reserved H'0F89' ; reserved H'0F88' ; reserved H'0F87' ; reserved H'0F86' ; reserved H'0F85' ; reserved H'0F84' ; reserved H'0F83' ; reserved H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' ;For backward compatibilty STKOVF EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0E EQU H'0004' INT0IE EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' ; For backward compatibility INT0F EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0RD16 EQU H'0005' T0PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' OSTS EQU H'0003' SCS2 EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' GPB EQU H'0006' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ T1ON EQU H'0007' T1PSA EQU H'0003' T1PS2 EQU H'0002' T1PS1 EQU H'0001' T1PS0 EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ T2ON EQU H'0007' T2PSA EQU H'0003' T2PS2 EQU H'0002' T2PS1 EQU H'0001' T2PS0 EQU H'0000' ;----- ASISTAT Bits ------------------------------------------------------- ASIOV EQU H'0007' D_A EQU H'0006' R_W EQU H'0005' PF EQU H'0004' SF EQU H'0003' RSF EQU H'0002' SRF EQU H'0001' BF EQU H'0000' ;----- ASICON1 Bits -------------------------------------------------------- ASIMOD1 EQU H'0007' ASIMOD2 EQU H'0006' PIE EQU H'0004' SIE EQU H'0003' RSIE EQU H'0002' SRIE EQU H'0001' BIE EQU H'0000' ;----- ASICON2 Bits -------------------------------------------------------- TP EQU H'0007' SLWRT EQU H'0006' BBM EQU H'0006' AEN EQU H'0005' BBMPS2 EQU H'0005' GCEN EQU H'0004' BBMPS1 EQU H'0004' NACK EQU H'0003' BBMPS0 EQU H'0003' CKEN EQU H'0002' SPSPS2 EQU H'0002' BACS EQU H'0001' SPSPS1 EQU H'0001' AACS EQU H'0000' SPSPS0 EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCOV EQU H'0007' SIZE2 EQU H'0006' SIZE1 EQU H'0005' SIZE0 EQU H'0004' ;----- ADCON2 Bits ----------------------------------------------------- C340 EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CMCON bits ------------------------------------------------------ CWTST EQU H'0007' CWVI EQU H'0004' CWVEN EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ T3ON EQU H'0007' T3PSA EQU H'0003' T3PS2 EQU H'0002' T3PS1 EQU H'0001' T3PS0 EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' COMA EQU H'0005' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' ;----- IPR2 Bits ------------------------------------------------------- CMIP EQU H'0006' AOFIP EQU H'0003' TMR3IP EQU H'0001' ;----- PIR2 Bits ------------------------------------------------------- CMIF EQU H'0006' AOFIF EQU H'0003' TMR3IF EQU H'0001' ;----- PIE2 Bits ------------------------------------------------------- CMIE EQU H'0006' AOFIE EQU H'0003' TMR3IE EQU H'0001' ;----- IPR1 Bits ------------------------------------------------------- ADIP EQU H'0006' ASIIP EQU H'0003' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- ADIF EQU H'0006' ASIIF EQU H'0003' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- ADIE EQU H'0006' ASIIE EQU H'0003' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- BGCAL Bits ------------------------------------------------------- BGTC3 EQU H'0003' BGTC2 EQU H'0002' BGTC1 EQU H'0001' BGTC0 EQU H'0000' ;----- OSCCAL Bits ---------------------------------------------------- REXT EQU H'0007' OSC6 EQU H'0006' OSC5 EQU H'0005' OSC4 EQU H'0004' OSC3 EQU H'0003' OSC2 EQU H'0002' OSC1 EQU H'0001' OSC0 EQU H'0000' ;----- WDTCON Bits ------------------------------------------------------- SWDTEN EQU H'0000' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA5 EQU 5 MCLR EQU 5 INT0 EQU 5 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 SCL EQU 0 RB1 EQU 1 SDA EQU 1 SPS EQU 1 RB2 EQU 2 RB3 EQU 3 RB4 EQU 4 RB5 EQU 5 VC2 EQU 5 RB6 EQU 6 NTC EQU 6 PGC EQU 6 RB7 EQU 7 PGD EQU 7 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'200'-H'DFF' __BADRAM H'E40'-H'F7F' __BADRAM H'F82'-H'F89',H'F8B'-H'F90',H'F92' __BADRAM H'F94'-H'F99',H'FA3'-H'FA5',H'FA8'-H'FB0' __BADRAM H'FB3',H'FB5'-H'FBF',H'FCB', H'FCF' __BADRAM H'FD2',H'FF0' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _CONFIG8L EQU H'30000E' ; To use the Configuration Bits, place the following lines in your ; source code in the following format, and change the configuration ; value to the desired setting (such as WDT_OFF to WDT_ON). These are ; currently commented out here and each __CONFIG line should have the ; preceding semicolon removed when pasted into your source code. ; __CONFIG _CONFIG1L, 0x00 ; __CONFIG _CONFIG1H, 0x00 ; __CONFIG _CONFIG2L, 0x00 ; __CONFIG _CONFIG2H, _WDT_ON_2H ; __CONFIG _CONFIG3L, 0x00 ; __CONFIG _CONFIG3H, _MCLRE_ON_3H ; __CONFIG _CONFIG4L, _BKBUG_OFF_4L | _STVR_ON_4L ; __CONFIG _CONFIG4H, 0x00 ; __CONFIG _CONFIG5L, _CP01_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H ; __CONFIG _CONFIG6L, _WRT01_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H | _WRTB_OFF_6H ; __CONFIG _CONFIG7L, _EBTR01_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ; __CONFIG _CONFIG8L, 0x01 ;Configuration Byte 2H Options _WDT_ON_2H EQU H'01' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'00' ; Watch Dog Timer disabled ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'80' ; MCLR enabled, RA5 input disabled _MCLRE_OFF_3H EQU H'00' ; MCLR disabled, RA5 input enabled ;Configuration Byte 4L Options _BKBUG_ON_4L EQU H'00' ; BacKground deBUGger enabled _BKBUG_OFF_4L EQU H'80' ; BacKground deBUGger disabled _STVR_ON_4L EQU H'01' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'00' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP01_ON_5L EQU H'00' ; Blocks 0 & 1 protected _CP01_OFF_5L EQU H'01' ; Blocks 0 & 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'00' ; Boot Block protected _CPB_OFF_5H EQU H'40' ; Boot Block readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT01_ON_6L EQU H'00' ; Block 0 & 1 write protected _WRT01_OFF_6L EQU H'01' ; Block 0 & 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'00' ; Config registers write protected _WRTC_OFF_6H EQU H'20' ; Config registers writable _WRTB_ON_6H EQU H'00' ; Boot block write protected _WRTB_OFF_6H EQU H'40' ; Boot block writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR01_ON_7L EQU H'00' ; Block 0 & 1 protected _EBTR01_OFF_7L EQU H'01' ; Block 0 & 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'00' ; Boot block read protected _EBTRB_OFF_7H EQU H'40' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p18f2515.inc0000644000175000017500000011421111156521301013223 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2515 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2515 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2515 ; 2. LIST directive in the source file ; LIST P=PIC18F2515 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2515 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' DAD5 EQU H'0005' DAD6 EQU H'0006' DAD7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f737.inc0000644000175000017500000004636411156313161013165 00000000000000 LIST ; P16F737.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F737 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F737 ; 2. LIST directive in the source file ; LIST P=PIC16F737 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/05/03 Initial Release ;1.01 10/21/03 Made changes to Program Memory register names. ;1.02 04/07/04 Added INT0IE & INT0IF bit names. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F737 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' CCPR3L EQU H'0095' CCPR3H EQU H'0096' CCP3CON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON2 EQU H'009B' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LVDCON EQU H'0109' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' INT0IE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' CMIF EQU H'0006' LVDIF EQU H'0005' BCLIF EQU H'0003' CCP3IF EQU H'0001' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE3 EQU H'0003' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' CMIE EQU H'0006' LVDIE EQU H'0005' BCLIE EQU H'0003' CCP3IE EQU H'0001' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- CCP3X EQU H'0005' CCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON2 Bits --------------------------------------------------------- ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08' __BADRAM H'88', H'9A' __BADRAM H'107'-H'108' __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;Configuration Byte 1 Options _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP2_RC1 EQU H'3FFF' _CCP2_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _VBOR_2_0 EQU H'3FFF' _VBOR_2_7 EQU H'3F7F' _VBOR_4_2 EQU H'3EFF' _VBOR_4_5 EQU H'3E7F' _BOREN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _BOREN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' ;Configuration Byte 2 Options _BORSEN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _BORSEN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3FFD' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'3FFE' ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ALL). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF LIST gputils-0.13.7/header/coff.inc0000644000175000017500000001106411156313161013052 00000000000000 list ; coff.inc - gputils header file nolist ; Copyright (C) 2004 Craig Franklin ; ; Redistribution and use in source and binary forms, with or without ; modification, are permitted provided that the following conditions are met: ; ; 1. Redistributions of source code must retain the above copyright notice, ; this list of conditions and the following disclaimer. ; 2. Redistributions in binary form must reproduce the above copyright notice, ; this list of conditions and the following disclaimer in the ; documentation and/or other materials provided with the distribution. ; 3. The name of the author may not be used to endorse or promote products ; derived from this software without specific prior written permission. ; ; THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR ; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES ; OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ; NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; ; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ; WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR ; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ; ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ; Size of a symbol, use for creating auxiliary entries. #define SYMBOL_SIZE 18 ; Symbol section numbers #define N_DEBUG -2 #define N_ABS -1 #define N_UNDEF 0 #define N_SCNUM ; Basic symbol types #define T_NULL 0 ; null #define T_VOID 1 ; void #define T_CHAR 2 ; character #define T_SHORT 3 ; short integer #define T_INT 4 ; integer #define T_LONG 5 ; long integer #define T_FLOAT 6 ; floating point #define T_DOUBLE 7 ; double length floating point #define T_STRUCT 8 ; structure #define T_UNION 9 ; union #define T_ENUM 10 ; enumeration #define T_MOE 11 ; member of enumeration #define T_UCHAR 12 ; unsigned character #define T_USHORT 13 ; unsigned short #define T_UINT 14 ; unsigned integer #define T_ULONG 15 ; unsigned long #define T_LNGDBL 16 ; long double floating point #define T_SLONG 17 ; short long #define T_USLONG 18 ; unsigned short long ; Derived types #define DT_NON 0 ; no derived type #define DT_PTR 1 ; pointer #define DT_FCN 2 ; function #define DT_ARY 3 ; array ; Storage classes #define C_EFCN 0xff ; physical end of function #define C_NULL 0 ; null #define C_AUTO 1 ; automatic variable #define C_EXT 2 ; external symbol #define C_STAT 3 ; static #define C_REG 4 ; register variable #define C_EXTDEF 5 ; external definition #define C_LABEL 6 ; label #define C_ULABEL 7 ; undefined label #define C_MOS 8 ; member of structure #define C_ARG 9 ; function argument #define C_STRTAG 10 ; structure tag #define C_MOU 11 ; member of union #define C_UNTAG 12 ; union tag #define C_TPDEF 13 ; type definition #define C_USTATIC 14 ; undefined static #define C_ENTAG 15 ; enumeration tag #define C_MOE 16 ; member of enumeration #define C_REGPARM 17 ; register parameter #define C_FIELD 18 ; bit field #define C_AUTOARG 19 ; auto argument #define C_LASTENT 20 ; dummy entry (end of block) #define C_BLOCK 100 ; ".bb" or ".eb" #define C_FCN 101 ; ".bf" or ".ef" #define C_EOS 102 ; end of structure #define C_FILE 103 ; file name #define C_LINE 104 ; line number reformatted as symbol table entry #define C_ALIAS 105 ; duplicate tag #define C_HIDDEN 106 ; ext symbol in dmert public lib #define C_EOF 107 ; end of file #define C_LIST 108 ; absoulte listing on or off #define C_SECTION 109 ; section ; Begin Function Code .bf macro .def ".bf", type = T_NULL, class = C_FCN endm ; End Function .ef macro .def ".ef", type = T_NULL, class = C_FCN endm ; Begin Basic Block .bb macro .def ".bb", type = T_NULL, class = C_BLOCK endm ; End of Basic Block .eb macro .def ".eb", type = T_NULL, class = C_BLOCK endm ; Assertion .assert macro x .direct "a", x endm ; Simulator Command .sim macro x .direct "e", x endm ; Printf Command .print macro x .direct "f", x endm ; Log Command .log macro x .direct "l", x endm list gputils-0.13.7/header/p18f84j90.inc0000644000175000017500000016532011156521302013415 00000000000000 LIST ;========================================================================== ; MPASM PIC18F84J90 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F84J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F84J90 ; 2. LIST directive in the source file ; LIST P=PIC18F84J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F84J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA5 EQU H'0F6B' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA11 EQU H'0F71' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA17 EQU H'0F77' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' LCDDATA23 EQU H'0F7D' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDSE5 EQU H'0FBA' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP1 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' MODE13 EQU H'0002' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' CPEN EQU H'0006' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f66j65.inc0000644000175000017500000013431211156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J65 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J65 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J65 ; 2. LIST directive in the source file ; LIST P=PIC18F66J65 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J65 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2 EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' CCP3 EQU H'0001' CCP4 EQU H'0002' ECCP3 EQU H'0001' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG4 EQU H'0004' CCP5 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0F62'-H'0F66' __BADRAM H'0F6B'-H'0F6F' __BADRAM H'0F7C'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p12f508.inc0000644000175000017500000000751211156313161013145 00000000000000 LIST ; P12F508.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F508 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12F508 ; 2. LIST directive in the source file ; LIST P=12F508 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/09/03 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F508 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16c73b.inc0000644000175000017500000002752311156313161013231 00000000000000 LIST ; P16C73B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C73B microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C73B ; 2. LIST directive in the source file ; LIST P=PIC16C73B ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17/12/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C73B MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f874a.inc0000644000175000017500000003761311156313161013325 00000000000000 LIST ; P16F874A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F877A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F874A ; 2. LIST directive in the source file ; LIST P=PIC16F874A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 11/17/05 Added the INTCON bits TMR0IE and TMR0IF and the ADCON1 bit ADCS2. ;1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. ;1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE ;1.00 04/19/01 Initial Release (BD - generated from PIC16F877A.inc) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F874A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _CPD_OFF EQU H'3FFF' _CPD_ON EQU H'3EFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _RC_OSC EQU H'3FFF' _HS_OSC EQU H'3FFE' _XT_OSC EQU H'3FFD' _LP_OSC EQU H'3FFC' LIST gputils-0.13.7/header/p16f506.inc0000644000175000017500000001602611156313161013147 00000000000000 LIST ; P16F506.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F506 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16F506 ; 2. LIST directive in the source file ; LIST P=16F506 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/13/04 Initial Release ;1.01 13/15/04 Added EC osc mode, COrrected CP on ;1.02 07/14/05 Updated Comparator names, comparator register bit names, and Oscillator fuse options ;1.03 08/26/05 Added port bit names ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F506 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' CM1CON0 EQU H'0008' ADCON0 EQU H'0009' ADRES EQU H'000A' CM2CON0 EQU H'000B' VRCON EQU H'000C' ;----- STATUS Bits -------------------------------------------------------- RBWUF EQU H'0007' CWUF EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBWU EQU H'0007' NOT_RBPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;----- CM1CON0 Bits -------------------------------------------------------- C1OUT EQU H'0007' NOT_C1OUTEN EQU H'0006' C1POL EQU H'0005' NOT_C1T0CS EQU H'0004' C1ON EQU H'0003' C1NREF EQU H'0002' C1PREF EQU H'0001' NOT_C1WU EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- CM2CON0 Bits -------------------------------------------------------- C2OUT EQU H'0007' NOT_C2OUTEN EQU H'0006' C2POL EQU H'0005' C2PREF2 EQU H'0004' C2ON EQU H'0003' C2NREF EQU H'0002' C2PREF1 EQU H'0001' NOT_C2WU EQU H'0000' ;----- VRCON Bits -------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- PORTB Bits -------------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' ;----- PORTC Bits -------------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _IOSCFS_ON EQU H'0FFF' _IOSCFS_OFF EQU H'0FBF' _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FDF' _CP_ON EQU H'0FEF' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FF7' _LP_OSC EQU H'0FF8' _XT_OSC EQU H'0FF9' _HS_OSC EQU H'0FFA' _EC_OSC EQU H'0FFB' _IntRC_OSC_RB4EN EQU H'0FFC' _IntRC_OSC_CLKOUTEN EQU H'0FFD' _ExtRC_OSC_RB4EN EQU H'0FFE' _ExtRC_OSC_CLKOUTEN EQU H'0FFF' LIST gputils-0.13.7/header/p12f510.inc0000644000175000017500000001265711156313161013144 00000000000000 LIST ; P12F510.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F510 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12F510 ; 2. LIST directive in the source file ; LIST P=12F510 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/13/04 Initial Release ;1.01 07/13/05 Updated comparator names and fuse section ;1.02 08/26/05 Added port bit names ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F510 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' CM1CON0 EQU H'0007' ADCON0 EQU H'0008' ADRES EQU H'0009' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' CWUF EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;----- CM1CON0 Bits -------------------------------------------------------- C1OUT EQU H'0007' NOT_C1OUTEN EQU H'0006' C1POL EQU H'0005' NOT_C1T0CS EQU H'0004' C1ON EQU H'0003' C1NREF EQU H'0002' C1PREF EQU H'0001' NOT_C1WU EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' GP4 EQU H'0004' GP5 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _IOSCFS_ON EQU H'0FFF' _IOSCFS_OFF EQU H'0FDF' _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16f874.inc0000644000175000017500000003517211156313161013162 00000000000000 LIST ; P16F874.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F874 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F874 ; 2. LIST directive in the source file ; LIST P=PIC16F874 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.12 01/12/00 Changed some bit names, a register name, configuration bits ; to match datasheet (DS30292B) ;1.11 10/18/98 Changes to file registers to match updated DOS ;1.10 08/17/98 Fixed typo in processor name, RCSTA and ADCON1 ;1.00 08/07/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F874 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'0FCF' _CP_HALF EQU H'1FDF' _CP_UPPER_256 EQU H'2FEF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f873a.inc0000644000175000017500000003636411156313161013326 00000000000000 LIST ; P16F873A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F877A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F873A ; 2. LIST directive in the source file ; LIST P=PIC16F873A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 11/17/05 Added the INTCON bits TMR0IE and TMR0IF and the ADCON1 bit ADCS2. ;1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. ;1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE ;1.00 04/19/01 Initial Release (BD - generated from PIC16F877a.inc) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F873A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _CPD_OFF EQU H'3FFF' _CPD_ON EQU H'3EFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _RC_OSC EQU H'3FFF' _HS_OSC EQU H'3FFE' _XT_OSC EQU H'3FFD' _LP_OSC EQU H'3FFC' LIST gputils-0.13.7/header/p16c77.inc0000644000175000017500000003107711156313161013072 00000000000000 LIST ; P16C77.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C77 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C77 ; 2. LIST directive in the source file ; LIST P=PIC16C77 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/13/96 Initial Release ;1.01 12/18/96 Modified per review ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C77 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'10F' __BADRAM H'185', H'187'-H'189', H'18C'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f747.inc0000644000175000017500000004632711156313161013165 00000000000000 LIST ; P16F747.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F747 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F747 ; 2. LIST directive in the source file ; LIST P=PIC16F747 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/05/03 Initial Release ;1.01 10/21/03 Made changes to Program Memory register names. ;1.02 04/07/04 Added INT0IE & INT0IF bit names. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F747 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' CCPR3L EQU H'0095' CCPR3H EQU H'0096' CCP3CON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON2 EQU H'009B' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LVDCON EQU H'0109' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' INT0IE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' CMIF EQU H'0006' LVDIF EQU H'0005' BCLIF EQU H'0003' CCP3IF EQU H'0001' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE3 EQU H'0003' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' CMIE EQU H'0006' LVDIE EQU H'0005' BCLIE EQU H'0003' CCP3IE EQU H'0001' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- CCP3X EQU H'0005' CCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON2 Bits --------------------------------------------------------- ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'9A' __BADRAM H'107'-H'108' __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;Configuration Byte 1 Options _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP2_RC1 EQU H'3FFF' _CCP2_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _VBOR_2_0 EQU H'3FFF' _VBOR_2_7 EQU H'3F7F' _VBOR_4_2 EQU H'3EFF' _VBOR_4_5 EQU H'3E7F' _BOREN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _BOREN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BORSEN (CONFIG2) _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' ;Configuration Byte 2 Options _BORSEN_1 EQU H'3FFF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _BORSEN_0 EQU H'3FBF' ;MUST BE CONFIGURED IN CONJUCTION W/ BOREN (CONFIG1) _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3FFD' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'3FFE' ;**** Brown-out Reset configurations **** (Refer to the 16F7x7 Data Sheet for more details) ;BOREN_1 & BORSEN_1 = BOR enabled and always on ;BOREN_1 & BORSEN_0 = BOR enabled during operation and disabled during sleep by hardware ;BOREN_0 & BORSEN_1 = BOR controlled by software bit SBOREN (PCON,2) ;BOREN_0 & BORSEN_0 = BOR disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ALL). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _CP_OFF & _CCP2_RC1 & _DEBUG_OFF & _VBOR_2_0 & BOREN_1 & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BORSEN_1 & _IESO_OFF & _FCMEN_OFF LIST gputils-0.13.7/header/p18f25j50.inc0000644000175000017500000016235111156521301013404 00000000000000 LIST ;========================================================================== ; MPASM PIC18F25J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F25J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F25J50 ; 2. LIST directive in the source file ; LIST P=PIC18F25J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F25J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F5F' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select : ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/mcp250xx.inc0000644000175000017500000005452611156313161013535 00000000000000 LIST ; MCP250XX.INC Standard Header File, Version 2.00 Microchip Technology, Inc. NOLIST ; This header file is used to define the configuration for MCP250XX devices. ; To use this header file, include it in the beginning of a source file. Use ; the various macros below to select the configuration options. Then at the end ; of the source file, invoke the macro GENERATE. ;******************************************************************************* ;CHANGE HISTORY ;9/13/01 PKR Version 0.20 ;- Added a "DEVICE" macro to select between mixed signal (MCP2505x) and digital ; only (MCP2502x) devices. ;- Fixed "RECEIVE_BUFFERS" and "TRANSMIT_BUFFERS" macro. Extended IDs were not ; being configured correctly. ; ;10/29/01 PKR Version 0.30 ;- Corrected the DATA directives in the "GENERATE" macro to place bytes in the ; proper order. Bytes were incorrectly swapped in the resulting HEX file. ; ;11/14/01 PKR Version 1.00 ;- Initial release ; ;06/25/02 PKR Version 2.00 ;- Added the ability to configure the Configuration Word ;******************************************************************************* ; Quick Reference ; ; CAN Configuration Macros ; DEVICE SET_DEVICE ; RECEIVE_BUFFERS MASK, MID, FILTER0, F0ID, FILTER1, F1ID ; TRANSMIT_BUFFERS TXB0, TXB0ID, TXB1, TXB1ID, TXB2, TXB2ID ; CAN_BIT_TIMING BRP, SJW, PS1, PS2, PROP, SP, P2S, WF ; CAN_MODE MACRO MODE, PUMODE, TXID1MSG, ERROR_RECOVERY, TX_ON_ERROR, SLEEPMODE, MSGTYPE, PWM_POR, LOTOSLEEP ; SCHEDULED_TRANSMISSION MODE, INFO, MULTIPLIER, FREQUENCY ; ; Peripheral Configuration Macros ; CLOCK_OUT MODE, PRESCALER ; IO_DIRECTION B6, B5, B4, B3, B2, B1, B0 ; IO_LATCH B6, B5, B4, B3, B2, B1, B0 ; IO_FUNCTION B3, B2, B1, B0 ; IO_XMIT_ON_CHANGE B7, B6, B5, B4, B3, B2, B1, B0 ; IO_WEAK_PULLUPS MODE ; PWM1 TMRON, PRESCALER, PERIOD, DUTY_CYCLE ; PWM2 TMRON, PRESCALER, PERIOD, DUTY_CYCLE ; ADC_SETUP MODE, SEQ_DELAY, CLOCK_SOURCE, VREF_POS, VREF_NEG, TIME ; ADC_COMPARES CHANNEL0, CHANNEL1, CHANNEL2, CHANNEL3 ; ; User Defined Configuration Macros ; SET_USER# VALUE ; ; Generate Configuration Information - REQUIRED! ; GENERATE LIST P=EEPROM16, M=0x100 NOEXPAND ;******************************************************************************* ; __config ; ; Configuration bits ; ; Reset Setting & Osc Setting ; Example: __config _RST_ON & _HS_OSC ; _RST_ON EQU H'3FFF' _RST_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFF' ;******************************************************************************* ;******************************************************************************* ; Initialize configuration words ;******************************************************************************* ;******************************************************************************* IOINTEN SET H'FF' IOINTPO SET H'FF' GPLAT SET H'FF' RES_03 SET H'FF' OPTREG1 SET H'FF' T1CON SET H'FF' T2CON SET H'FF' PR1 SET H'FF' PR2 SET H'FF' PWM1DCH SET H'FF' PWM2DCH SET H'FF' CNF1 SET H'FF' CNF2 SET H'FF' CNF3 SET H'FF' ADCON0 SET H'FF' ADCON1 SET H'FF' STCON SET H'FF' OPTREG2 SET H'FF' RES_12 SET H'FF' RES_13 SET H'FF' RXMSIDH SET H'FF' RXMSIDL SET H'FF' RXMEID8 SET H'FF' RXMEID0 SET H'FF' RXF0SIDH SET H'FF' RXF0SIDL SET H'FF' RXF0EID8 SET H'FF' RXF0EID0 SET H'FF' RXF1SIDH SET H'FF' RXF1SIDL SET H'FF' RXF1EID8 SET H'FF' RXF1EID0 SET H'FF' TXID0SIDH SET H'FF' TXID0SIDL SET H'FF' TXID0EID8 SET H'FF' TXID0EID0 SET H'FF' TXID1SIDH SET H'FF' TXID1SIDL SET H'FF' TXID1EID8 SET H'FF' TXID1EID0 SET H'FF' TXID2SIDH SET H'FF' TXID2SIDL SET H'FF' TXID2EID8 SET H'FF' TXID2EID0 SET H'FF' ADCMP3H SET H'FF' ADCMP3L SET H'FF' ADCMP2H SET H'FF' ADCMP2L SET H'FF' ADCMP1H SET H'FF' ADCMP1L SET H'FF' ADCMP0H SET H'FF' ADCMP0L SET H'FF' GPDDR SET H'FF' USER0 SET H'FF' USER1 SET H'FF' USER2 SET H'FF' USER3 SET H'FF' USER4 SET H'FF' USER5 SET H'FF' USER6 SET H'FF' USER7 SET H'FF' USER8 SET H'FF' USER9 SET H'FF' USERA SET H'FF' USERB SET H'FF' USERC SET H'FF' USERD SET H'FF' USERE SET H'FF' USERF SET H'FF' CRCSUM SET H'FF' ;******************************************************************************* ;******************************************************************************* ; Internal values ;******************************************************************************* ;******************************************************************************* ADC_FOSC_2 EQU 0x00 ADC_FOSC_8 EQU 0x40 ADC_FOSC_32 EQU 0x80 ADC_FRC EQU 0xC0 ADC_RESULT EQU 0x40 ANALOG EQU 0 CLK_FOSC EQU 0x00 CLK_FOSC_2 EQU 0x10 CLK_FOSC_4 EQU 0x20 CLK_FOSC_8 EQU 0x30 CMD_ACK EQU 0x80 DIGITAL EQU 1 DISABLED EQU 0 ENABLED EQU 1 ERR_RECVRY_LO EQU 0x40 ERR_RECVRY_NORM EQU 0 EXTENDED EQU 1 EXTERNAL EQU 1 INPUT EQU 1 IO_FALL EQU 1 IO_RISE EQU 3 LISTEN_ONLY EQU 0x04 LO_TO_SLEEP_EN EQU 0x02 LO_TO_SLEEP_DIS EQU 0 MCP2502X EQU 0 MCP2505X EQU 1 MSG_TYPE_DATA EQU 0x08 MSG_TYPE_RTR EQU 0 NO_TX_ON_ERR EQU 0 NONE EQU 0x00 NORMAL EQU 0x00 OUTPUT EQU 0 PHASE1_AND_IPT EQU 0x00 PHASE2 EQU 0x80 PWRUP_LO EQU 0 PWRUP_NORM EQU 0x01 PWM_POR_DEF EQU 0x04 PWM_POR_UNCH EQU 0 RX_OVRFLW EQU 0 SLEEP_DIS EQU 0 SLEEP_EN EQU 0x10 STANDARD EQU 0 TIMES_1 EQU 0x00 TIMES_3 EQU 0x40 TOSC32 EQU 0x00 TOSC64 EQU 0x10 TOSC128 EQU 0x20 TOSC256 EQU 0x30 TOSC512 EQU 0x40 TOSC1024 EQU 0x50 TOSC2048 EQU 0x60 TOSC4096 EQU 0x70 TX_ON_ERR EQU 0x20 VDD EQU 0 VSS EQU 0 X1_64TOSC EQU 0x00 X2_64TOSC EQU 0x01 X4_64TOSC EQU 0x02 X8_64TOSC EQU 0x03 X1_4096TOSC EQU 0x00 X16_4096TOSC EQU 0x10 X256_4096TOSC EQU 0x20 X4096_4096TOSC EQU 0x30 DEVICE_NUM SET 0 ;******************************************************************************* ;******************************************************************************* ; Configuration Macros ;******************************************************************************* ;******************************************************************************* ;******************************************************************************* ; DEVICE ; ; Call this macro to set the device for mixed signal (MCP2505X) ; or digital only (MCP2502X). ; ; SET_DEVICE enter MCP2505X or MCP2502X DEVICE MACRO SET_DEVICE DEVICE_NUM SET SET_DEVICE ENDM ;******************************************************************************* ; RECEIVE_BUFFERS ; ; Call this macro to set up the receive buffers. Macro paramaters are: ; ; MASK message identifier [eleven (max 7FFh) or twenty nine bits (max 1FFFFFFF)] ; MID enter STANDARD or EXTENDED ; FILTER0 message identifier [eleven (max 7FFh) or twenty nine bits (max 1FFFFFFF)] ; F0ID enter STANDARD or EXTENDED ; FILTER1 message identifier [eleven (max 7FFh) or twenty nine bits (max 1FFFFFFF)] ; F1ID enter STANDARD or EXTENDED RECEIVE_BUFFERS MACRO MASK, MID, FILTER0, F0ID, FILTER1, F1ID IF MID == STANDARD RXMSIDH SET MASK >> 3 RXMSIDL SET ((MASK & 0x07) << 5) + 3 ELSE RXMSIDH SET (MASK >> 0x15) & 0xFF RXMSIDL SET 0x08 + (((MASK >> 0x0D) & 0xE0) | ((MASK >> 0x10) & 0x03)) RXMEID8 SET (MASK >> 8) & 0xFF RXMEID0 SET MASK & 0xFF ENDIF IF F0ID == STANDARD RXF0SIDH SET FILTER0 >> 3 RXF0SIDL SET ((FILTER0 & 0x07) << 5) + 3 ELSE RXF0SIDH SET (FILTER0 >> 0x15) & 0xFF RXF0SIDL SET 0x08 + (((FILTER0 >> 0x0D) & 0xE0) | ((FILTER0 >> 0x10) & 0x03)) RXF0EID8 SET (FILTER0 >> 8) & 0xFF RXF0EID0 SET FILTER0 & 0xFF ENDIF IF F1ID == STANDARD RXF1SIDH SET FILTER1 >> 3 RXF1SIDL SET ((FILTER1 & 0x07) << 5) + 3 ELSE RXF1SIDH SET (FILTER1 >> 0x15) & 0xFF RXF1SIDL SET 0x08 + (((FILTER1 >> 0x0D) & 0xE0) | ((FILTER1 >> 0x10) & 0x03)) RXF1EID8 SET (FILTER1 >> 8) & 0xFF RXF1EID0 SET FILTER1 & 0xFF ENDIF ENDM ;******************************************************************************* ; TRANSMIT_BUFFERS ; ; Call this macro to set up the transmit buffers. Macro parameters are: ; ; TXB0 message identifier [eleven (max 7FFh) or twenty nine bits (max 1FFFFFFF)] ; TXB0ID enter STANDARD or EXTENDED ; TXB1 message identifier [eleven (max 7FFh) or twenty nine bits (max 1FFFFFFF)] ; TXB1ID enter STANDARD or EXTENDED ; TXB2 message identifier [eleven (max 7FFh) or twenty nine bits (max 1FFFFFFF)] ; TXB2ID enter STANDARD or EXTENDED TRANSMIT_BUFFERS MACRO TXB0, TXB0ID, TXB1, TXB1ID, TXB2, TXB2ID IF TXB0ID == STANDARD TXID0SIDH SET TXB0 >> 3 TXID0SIDL SET ((TXB0 & 0x07) << 5) + 3 ELSE TXID0SIDH SET (TXB0 >> 0x15) & 0xFF TXID0SIDL SET 0x08 + (((TXB0 >> 0x0D) & 0xE0) | ((TXB0 >> 0x10) & 0x03)) TXID0EID8 SET (TXB0 >> 8) & 0xFF TXID0EID0 SET TXB0 & 0xFF ENDIF IF TXB1ID == STANDARD TXID1SIDH SET TXB1 >> 3 TXID1SIDL SET ((TXB1 & 0x07) << 5) + 3 ELSE TXID1SIDH SET (TXB1 >> 0x15) & 0xFF TXID1SIDL SET 0x08 + (((TXB1 >> 0x0D) & 0xE0) | ((TXB1 >> 0x10) & 0x03)) TXID1EID8 SET (TXB1 >> 8) & 0xFF TXID1EID0 SET TXB1 & 0xFF ENDIF IF TXB2ID == STANDARD TXID2SIDH SET TXB2 >> 3 TXID2SIDL SET ((TXB2 & 0x07) << 5) + 3 ELSE TXID2SIDH SET (TXB2 >> 0x15) & 0xFF TXID2SIDL SET 0x08 + (((TXB2 >> 0x0D) & 0xE0) | ((TXB2 >> 0x10) & 0x03)) TXID2EID8 SET (TXB2 >> 8) & 0xFF TXID2EID0 SET TXB2 & 0xFF ENDIF ENDM ;******************************************************************************* ; CAN_BIT_TIMING ; ; Call this macro to set up the CAN bit timing. Macro parameters are: ; ; BRP Baud Rate Prescaler enter a value from 0 to 0x3F ; SJW Synchronized Jump Width enter a value from 1 to 4 ; PS1 Phase 1 Segment Width enter a value from 1 to 8 ; PS2 Phase 2 Segment Width enter a value from 2 to 8 ; PROP Propagation Width enter a value from 1 to 8 ; SP Sample Point enter TIMES_3 or TIMES_1 ; P2S Phase 2 Source enter PHASE2 or PHASE1_IPT ; WF Wake-up Filter enter ENABLED or DISABLED CAN_BIT_TIMING MACRO BRP, SJW, PS1, PS2, PROP, SP, P2S, WF CNF1 SET ((SJW-1) << 6) + BRP CNF2 SET P2S + (SP << 6) + ((PS1-1) << 3) + (PROP-1) CNF3 SET (WF << 6) + (PS2-1) ENDM ;******************************************************************************* ; CAN_MODE ; ; Call this macro to set up the initial CAN mode. Macro parameters are: ; ; MODE enter NORMAL or LISTEN_ONLY ; PUMODE enter PWRUP_NORM or PWRUP_LO ; TXID1MSG enter CMD_ACK or RX_OVRFLW ; ERROR_RECOVERY enter ERR_RECVRY_LO or ERR_RECVRY_NORM ; TX_ON_ERROR enter TX_ON_ERR or NO_TX_ON_ERR ; SLEEPMODE enter SLEEP_EN or SLEEP_DIS ; MSGTYPE enter MSG_TYPE_DATA or MSG_TYPE_RTR ; PWM_POR enter PWM_POR_DEF OR PWM_POR_UNCH ; LOTOSLEEP enter LO_TO_SLEEP_EN OR LO_TO_SLEEP_DIS CAN_MODE MACRO MODE, PUMODE, TXID1MSG, ERROR_RECOVERY, TX_ON_ERROR, SLEEPMODE, MSGTYPE, PWM_POR, LOTOSLEEP TEMP SET PUMODE | TXID1MSG | ERROR_RECOVERY | TX_ON_ERROR OPTREG2 SET TEMP | SLEEPMODE | MSGTYPE | PWM_POR | LOTOSLEEP OPTREG1 SET (OPTREG1 & 0xF3) | MODE ENDM ;******************************************************************************* ; SCHEDULED_TRANSMISSION ; ; Call this macro to set up scheduled transmission. Macro parameters are: ; ; MODE enter ENABLED or DISABLED ; INFO enter NONE or ADC_RESULT ; MULTIPLIER enter a value from 1 to 0x10 ; FREQUENCY enter X1_4096TOSC, X16_4096TOSC, X256_4096TOSC, or ; X4096_4096TOSC SCHEDULED_TRANSMISSION MACRO MODE, INFO, MULTIPLIER, FREQUENCY STCON SET (MODE << 7) + INFO + FREQUENCY + (MULTIPLIER-1) ENDM ;******************************************************************************* ; CLOCK_OUT ; ; Call this macro to configure the Clock Out Function. Macro parameters are: ; ; MODE enter ENABLED or DISABLED ; PRESCALER enter CLK_FOSC, CLK_FOSC_2, CLK_FOSC_4, or CLK_FOSC_8 CLOCK_OUT MACRO MODE, PRESCALER IF MODE == 0 OPTREG1 SET (OPTREG1 & 0x8F) | (0x40 + PRESCALER) ELSE OPTREG1 SET (OPTREG1 & 0x8F) | PRESCALER ENDIF ENDM ;******************************************************************************* ; IO_DIRECTION ; ; Call this macro to set up the I/O direction for the digital I/O's. ; Macro parameters are: ; ; B6 enter INPUT or OUTPUT for pin GP6 ; B5 enter INPUT or OUTPUT for pin GP5 ; B4 enter INPUT or OUTPUT for pin GP4 ; B3 enter INPUT or OUTPUT for pin GP3 ; B2 enter INPUT or OUTPUT for pin GP2 ; B1 enter INPUT or OUTPUT for pin GP1 ; B0 enter INPUT or OUTPUT for pin GP0 IO_DIRECTION MACRO B6, B5, B4, B3, B2, B1, B0 TEMP SET (((((B6 << 1) + B5) << 1) + B4) << 1) + B3 GPDDR SET (((((TEMP << 1) + B2) << 1) + B1) << 1) + B0 ENDM ;******************************************************************************* ; IO_LATCH ; ; Call this macro to set the latch values for the digital I/O's. Macro ; parameters are: ; ; B6 enter 0 or 1 for pin GP6 ; B5 enter 0 or 1 for pin GP5 ; B4 enter 0 or 1 for pin GP4 ; B3 enter 0 or 1 for pin GP3 ; B2 enter 0 or 1 for pin GP2 ; B1 enter 0 or 1 for pin GP1 ; B0 enter 0 or 1 for pin GP0 IO_LATCH MACRO B6, B5, B4, B3, B2, B1, B0 TEMP SET (((((B6 << 1) + B5) << 1) + B4) << 1) + B3 GPLAT SET (((((TEMP << 1) + B2) << 1) + B1) << 1) + B0 ENDM ;******************************************************************************* ; IO_FUNCTION ; ; Call this macro to set the pin function to analog or digital. Macro ; parameters are: ; ; B3 enter ANALOG or DIGITAL for pin AN3 ; B2 enter ANALOG or DIGITAL for pin AN2 ; B1 enter ANALOG or DIGITAL for pin AN1 ; B0 enter ANALOG or DIGITAL for pin AN0 IO_FUNCTION MACRO B3, B2, B1, B0 IF DEVICE_NUM == MCP2502X ADCON1 SET 0x0F ELSE ADCON1 SET (ADCON1 & 0xF0) | (((((B3 << 1) + B2) << 1) + B1) << 1) + B0 ENDIF ENDM ;******************************************************************************* ; IO_XMIT_ON_CHANGE ; ; Call this macro to set the Transmit on Change for each pin. Macro parameters ; are: ; ; B7 enter DISABLE, IO_RISE, or IO_FALL for pin GP7 ; B6 enter DISABLE, IO_RISE, or IO_FALL for pin GP6 ; B5 enter DISABLE, IO_RISE, or IO_FALL for pin GP5 ; B4 enter DISABLE, IO_RISE, or IO_FALL for pin GP4 ; B3 enter DISABLE, IO_RISE, or IO_FALL for pin GP3 ; B2 enter DISABLE, IO_RISE, or IO_FALL for pin GP2 ; B1 enter DISABLE, IO_RISE, or IO_FALL for pin GP1 ; B0 enter DISABLE, IO_RISE, or IO_FALL for pin GP0 IO_XMIT_ON_CHANGE MACRO B7, B6, B5, B4, B3, B2, B1, B0 TEMP SET ((((((B7&1) << 1) + (B6&1)) << 1) + (B5&1)) << 1) + (B4&1) IOINTEN SET (((((((TEMP << 1) + (B3&1)) << 1) + (B2&1)) << 1) + (B1&1)) << 1) + (B0&1) TEMP SET ((((((B7&2) <<1) + (B6&2)) << 1) + (B5&2)) << 1) + (B4&2) IOINTPO SET (((((((TEMP << 1) + (B3&2)) << 1) + (B2&2)) << 1) + (B1&2)) << 1) + (B0&2) ENDM ;******************************************************************************* ; IO_WEAK_PULLUPS ; ; Call this macro to configure weak pull-ups. Macro parameters are: ; ; MODE enter ENABLED or DISABLED IO_WEAK_PULLUPS MACRO MODE IF MODE == 0 OPTREG1 SET (OPTREG1 & 0x7F) | 0x80 ELSE OPTREG1 SET (OPTREG1 & 0x7F) ENDIF ENDM ;******************************************************************************* ; PWM1 ; ; Call this macro to configure PWM1. Macro parameters are: ; ; TMRON enter ENABLED or DISABLED ; PRESCALER Timer Prescaler; enter 1, 4, or 0x10 ; PERIOD PWM Period; enter a value from 0 to 0xFF ; DUTY_CYCLE PWM Duty Cycle; enter a value from 0 to 0x3FF PWM1 MACRO TMRON, PRESCALER, PERIOD, DUTY_CYCLE IF PRESCALER == 0x10 TEMP SET 0x20 ELSE IF PRESCALER == 4 TEMP SET 0x10 ELSE TEMP SET 0x00 ENDIF ENDIF T1CON SET (TMRON << 7) | TEMP | (DUTY_CYCLE & 0x03) PR1 SET PERIOD PWM1DCH SET DUTY_CYCLE >> 2 ENDM ;******************************************************************************* ; PWM2 ; ; Call this macro to configure PWM2. Macro parameters are: ; ; TMRON enter ENABLED or DISABLED ; PRESCALER Timer Prescaler; enter 1, 4, or 0x10 ; PERIOD PWM Period; enter a value from 0 to 0xFF ; DUTY_CYCLE PWM Duty Cycle; enter a value from 0 to 0x3FF PWM2 MACRO TMRON, PRESCALER, PERIOD, DUTY_CYCLE IF PRESCALER == 0x10 TEMP SET 0x20 ELSE IF PRESCALER == 4 TEMP SET 0x10 ELSE TEMP SET 0x00 ENDIF ENDIF T2CON SET (TMRON << 7) | TEMP | (DUTY_CYCLE & 0x03) PR2 SET PERIOD PWM2DCH SET DUTY_CYCLE >> 2 ENDM ;******************************************************************************* ; ADC_SETUP ; ; Call this macro to set up the ADC. Macro parameters are: ; ; MODE enter ENABLED or DISABLED ; SEQ_DELAY Minimum Sequence Delay; enter TOSC32, TOSC64, TOSC128, ; TOSC256, TOSC512, TOSC1024, TOSC2048, or TOSC4096 ; CLOCK_SOURCE Clock Source; enter ADC_FOSC_2, ADC_FOSC_8, ADC_FOSC_32, ; or ADC_FRC ; VREF_POS Vref+ Source; enter VDD or EXTERNAL ; VREF_NEG Vref- Source; enter VSS or EXTERNAL ; TIME Acquisition Time; enter X1_64TOSC, X2_64TOSC, X4_64TOSC, ; or X8_64TOSC ; ; Note: Be sure to call the macro IO_FUNCTION to configure the pins as ; analog or digital. ADC_SETUP MACRO MODE, SEQ_DELAY, CLOCK_SOURCE, VREF_POS, VREF_NEG, TIME IF DEVICE_NUM == MCP2502X ADCON0 SET 0x00 ADCON1 SET 0x0F OPTREG1 SET (OPTREG1 & 0xFC) ELSE ADCON0 SET (MODE << 7) + SEQ_DELAY TEMP SET CLOCK_SOURCE + (VREF_NEG << 5) + (VREF_POS << 4) ADCON1 SET (ADCON1 & 0x0F) | TEMP OPTREG1 SET (OPTREG1 & 0xFC) | TIME ENDIF ENDM ;******************************************************************************* ; ADC_COMPARES ; ; Call this macro to set up the ADC compare values. Macro parameters are: ; ; CHANNEL0 enter a value from 0 to 0x3FF ; CHANNEL1 enter a value from 0 to 0x3FF ; CHANNEL2 enter a value from 0 to 0x3FF ; CHANNEL3 enter a value from 0 to 0x3FF ADC_COMPARES MACRO CHANNEL0, CHANNEL1, CHANNEL2, CHANNEL3 IF DEVICE_NUM == MCP2502X ADCMP0L SET 0x00 ADCMP0H SET 0x00 ADCMP1L SET 0x00 ADCMP1H SET 0x00 ADCMP2L SET 0x00 ADCMP2H SET 0x00 ADCMP3L SET 0x00 ADCMP3H SET 0x00 ELSE ;IF DEVICE_NUM == MCP2505X ADCMP0L SET (CHANNEL0 & 0x003) << 6 ADCMP0H SET (CHANNEL0 & 0x3FC) >> 2 ADCMP1L SET (CHANNEL1 & 0x003) << 6 ADCMP1H SET (CHANNEL1 & 0x3FC) >> 2 ADCMP2L SET (CHANNEL2 & 0x003) << 6 ADCMP2H SET (CHANNEL2 & 0x3FC) >> 2 ADCMP3L SET (CHANNEL3 & 0x003) << 6 ADCMP3H SET (CHANNEL3 & 0x3FC) >> 2 ENDIF ENDM ;******************************************************************************* ; SET_USER# ; ; Call these macros to set the user data values. Macro parameters are: ; ; VALUE enter a value from 0 to 0xFF SET_USER0 MACRO VALUE USER0 SET VALUE ENDM SET_USER1 MACRO VALUE USER1 SET VALUE ENDM SET_USER2 MACRO VALUE USER2 SET VALUE ENDM SET_USER3 MACRO VALUE USER3 SET VALUE ENDM SET_USER4 MACRO VALUE USER4 SET VALUE ENDM SET_USER5 MACRO VALUE USER5 SET VALUE ENDM SET_USER6 MACRO VALUE USER6 SET VALUE ENDM SET_USER7 MACRO VALUE USER7 SET VALUE ENDM SET_USER8 MACRO VALUE USER8 SET VALUE ENDM SET_USER9 MACRO VALUE USER9 SET VALUE ENDM SET_USERA MACRO VALUE USERA SET VALUE ENDM SET_USERB MACRO VALUE USERB SET VALUE ENDM SET_USERC MACRO VALUE USERC SET VALUE ENDM SET_USERD MACRO VALUE USERD SET VALUE ENDM SET_USERE MACRO VALUE USERE SET VALUE ENDM SET_USERF MACRO VALUE USERF SET VALUE ENDM ;******************************************************************************* ; GENERATE ; ; Call this macro after using all of the other macros to configure the device. ; This macro will actually generate the hex file output to configure the ; device using a Device Programmer. This macro has no parameters. GENERATE MACRO TEMP SET IOINTEN + IOINTPO + GPLAT + RES_03 + OPTREG1 + T1CON TEMP SET TEMP + T2CON + PR1 + PR2 + PWM1DCH + PWM2DCH + CNF1 TEMP SET TEMP + CNF2 + CNF3 + ADCON0 + ADCON1 + STCON + OPTREG2 TEMP SET TEMP + RES_12 + RES_13 + RXMSIDH + RXMSIDL + RXMEID8 TEMP SET TEMP + RXMEID0 + RXF0SIDH + RXF0SIDL + RXF0EID8 + RXF0EID0 TEMP SET TEMP + RXF1SIDH + RXF1SIDL + RXF1EID8 + RXF1EID0 + TXID0SIDH TEMP SET TEMP + TXID0SIDL + TXID0EID8 + TXID0EID0 + TXID1SIDH TEMP SET TEMP + TXID1SIDL + TXID1EID8 + TXID1EID0 + TXID2SIDH TEMP SET TEMP + TXID2SIDL + TXID2EID8 + TXID2EID0 + ADCMP3H + ADCMP3L TEMP SET TEMP + ADCMP2H + ADCMP2L + ADCMP1H + ADCMP1L + ADCMP0H + ADCMP0L TEMP SET TEMP + GPDDR + USER0 + USER1 + USER2 + USER3 + USER4 + USER5 TEMP SET TEMP + USER6 + USER7 + USER8 + USER9 + USERA + USERB + USERC TEMP SET TEMP + USERD + USERE + USERF CRCSUM SET (-TEMP) & 0xFF ; EXPAND DATA 0x34 | ((IOINTEN & 0xFF) << 8) DATA 0x34 | ((IOINTPO & 0xFF) << 8) DATA 0x34 | ((GPLAT & 0xFF) << 8) DATA 0x34 | ((RES_03 & 0xFF) << 8) DATA 0x34 | ((OPTREG1 & 0xFF) << 8) DATA 0x34 | ((T1CON & 0xFF) << 8) DATA 0x34 | ((T2CON & 0xFF) << 8) DATA 0x34 | ((PR1 & 0xFF) << 8) DATA 0x34 | ((PR2 & 0xFF) << 8) DATA 0x34 | ((PWM1DCH & 0xFF) << 8) DATA 0x34 | ((PWM2DCH & 0xFF) << 8) DATA 0x34 | ((CNF1 & 0xFF) << 8) DATA 0x34 | ((CNF2 & 0xFF) << 8) DATA 0x34 | ((CNF3 & 0xFF) << 8) DATA 0x34 | ((ADCON0 & 0xFF) << 8) DATA 0x34 | ((ADCON1 & 0xFF) << 8) DATA 0x34 | ((STCON & 0xFF) << 8) DATA 0x34 | ((OPTREG2 & 0xFF) << 8) DATA 0x34 | ((RES_12 & 0xFF) << 8) DATA 0x34 | ((RES_13 & 0xFF) << 8) DATA 0x34 | ((RXMSIDH & 0xFF) << 8) DATA 0x34 | ((RXMSIDL & 0xFF) << 8) DATA 0x34 | ((RXMEID8 & 0xFF) << 8) DATA 0x34 | ((RXMEID0 & 0xFF) << 8) DATA 0x34 | ((RXF0SIDH & 0xFF) << 8) DATA 0x34 | ((RXF0SIDL & 0xFF) << 8) DATA 0x34 | ((RXF0EID8 & 0xFF) << 8) DATA 0x34 | ((RXF0EID0 & 0xFF) << 8) DATA 0x34 | ((RXF1SIDH & 0xFF) << 8) DATA 0x34 | ((RXF1SIDL & 0xFF) << 8) DATA 0x34 | ((RXF1EID8 & 0xFF) << 8) DATA 0x34 | ((RXF1EID0 & 0xFF) << 8) DATA 0x34 | ((TXID0SIDH & 0xFF) << 8) DATA 0x34 | ((TXID0SIDL & 0xFF) << 8) DATA 0x34 | ((TXID0EID8 & 0xFF) << 8) DATA 0x34 | ((TXID0EID0 & 0xFF) << 8) DATA 0x34 | ((TXID1SIDH & 0xFF) << 8) DATA 0x34 | ((TXID1SIDL & 0xFF) << 8) DATA 0x34 | ((TXID1EID8 & 0xFF) << 8) DATA 0x34 | ((TXID1EID0 & 0xFF) << 8) DATA 0x34 | ((TXID2SIDH & 0xFF) << 8) DATA 0x34 | ((TXID2SIDL & 0xFF) << 8) DATA 0x34 | ((TXID2EID8 & 0xFF) << 8) DATA 0x34 | ((TXID2EID0 & 0xFF) << 8) DATA 0x34 | ((ADCMP3H & 0xFF) << 8) DATA 0x34 | ((ADCMP3L & 0xFF) << 8) DATA 0x34 | ((ADCMP2H & 0xFF) << 8) DATA 0x34 | ((ADCMP2L & 0xFF) << 8) DATA 0x34 | ((ADCMP1H & 0xFF) << 8) DATA 0x34 | ((ADCMP1L & 0xFF) << 8) DATA 0x34 | ((ADCMP0H & 0xFF) << 8) DATA 0x34 | ((ADCMP0L & 0xFF) << 8) DATA 0x34 | ((GPDDR & 0xFF) << 8) DATA 0x34 | ((USER0 & 0xFF) << 8) DATA 0x34 | ((USER1 & 0xFF) << 8) DATA 0x34 | ((USER2 & 0xFF) << 8) DATA 0x34 | ((USER3 & 0xFF) << 8) DATA 0x34 | ((USER4 & 0xFF) << 8) DATA 0x34 | ((USER5 & 0xFF) << 8) DATA 0x34 | ((USER6 & 0xFF) << 8) DATA 0x34 | ((USER7 & 0xFF) << 8) DATA 0x34 | ((USER8 & 0xFF) << 8) DATA 0x34 | ((USER9 & 0xFF) << 8) DATA 0x34 | ((USERA & 0xFF) << 8) DATA 0x34 | ((USERB & 0xFF) << 8) DATA 0x34 | ((USERC & 0xFF) << 8) DATA 0x34 | ((USERD & 0xFF) << 8) DATA 0x34 | ((USERE & 0xFF) << 8) DATA 0x34 | ((USERF & 0xFF) << 8) DATA 0x34 | ((CRCSUM & 0xFF) << 8) ENDM LIST gputils-0.13.7/header/p16f76.inc0000644000175000017500000003024211156313161013065 00000000000000 LIST ; P16F76.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F76 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F76 ; 2. LIST directive in the source file ; LIST P=PIC16F76 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 00/00/00 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F76 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'88'-H'89' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f44j50.inc0000644000175000017500000017442111156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F44J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F44J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F44J50 ; 2. LIST directive in the source file ; LIST P=PIC18F44J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F44J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select : ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/rf509ag.inc0000644000175000017500000000773311156313161013322 00000000000000 LIST ; RF509AG.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the rfPIC12C509AG microcontroller. These names are taken to ; match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /p=RF509AG ; 2. LIST directive in the source file ; LIST P=RF509AG ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 09/18/01 Shortened processor name to RF509AG for COD format (pas) ;1.00 08/31/01 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __RF509AG MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' OSCFST EQU H'0003' CAL1 EQU H'0003' OSCSLW EQU H'0002' CAL0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p18f96j60.inc0000644000175000017500000016427511156521301013424 00000000000000 LIST ;========================================================================== ; MPASM PIC18F96J60 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F96J60 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F96J60 ; 2. LIST directive in the source file ; LIST P=PIC18F96J60 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F96J60 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RJPU EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ECCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2_PORTC EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ECCP2_PORTE EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' RG6 EQU H'0006' RG7 EQU H'0007' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' ECCP3 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' LATG6 EQU H'0006' LATG7 EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' RG6 EQU H'0006' RG7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' TRISG6 EQU H'0006' TRISG7 EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled and selected by MEMCON<5:4> ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-Bit Data Width mode ; BW = 16 16-Bit Data Width mode ; ; External Memory Bus Configuration bits: ; MODE = XM20 Extended Microcontroller mode, 20-Bit Address mode ; MODE = XM16 Extended Microcontroller mode,16-Bit Address mode ; MODE = XM12 Extended Microcontroller mode,12-Bit Address mode ; MODE = MM Microcontroller mode, external bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled; address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled; address on external bus is offset to start at 000000h ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ; ECCP MUX bit: ; ECCPMX = OFF ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = ON ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = OFF ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) ; CCP2MX = ON ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16cr64.inc0000644000175000017500000002200311156313161013235 00000000000000 LIST ; P16CR64.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CR64 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CR64 ; 2. LIST directive in the source file ; LIST P=PIC16CR64 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CR64 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'0D', H'18'-H'1F', H'8D', H'8F'-H'91', H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18lf25j50.inc0000644000175000017500000016021311156521301013553 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF25J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF25J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF25J50 ; 2. LIST directive in the source file ; LIST P=PIC18LF25J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF25J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F5F' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18c601.inc0000644000175000017500000005760511156521301013147 00000000000000 LIST ; P18C601.INC Standard Header File, Version 0.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C601 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C601 ; 2. LIST directive in the source file ; LIST P=PIC18C601 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ; Rev: Date: Details: Who: ; 0.01 11 Oct 2000 Original nr ; 0.02 09 May 2001 Added Configuration bits nr ; 0.03 13 Jun 2001 Fixed RAM map and changed config bit labels MG ; 0.04 22 Jun 2001 Fixed OSCCON bits nr ; 0.05 27 Jun 2001 Fixed LVDCON, IPR2, PIR2, PIE2 bits nr ; 0.06 22 Oct 2001 Added __MAXROM / __BADROM directive for bad ; ROM between external memory and boot ram pas ; 0.07 12 Mar 2008 Added SWDPS0, SWDPS1, and SWDPS2 src ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C601 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' CSEL2 EQU H'0FA7' CSELIO EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;TRISJ EQU H'0F9A' ;TRISH EQU H'0F99' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;DDRJ EQU H'0F9A' ;DDRH EQU H'0F99' DDRG EQU H'0F98' DDRF EQU H'0F97' DDRE EQU H'0F96' DDRD EQU H'0F95' DDRC EQU H'0F94' DDRB EQU H'0F93' DDRA EQU H'0F92' ;LATJ EQU H'0F91' ;LATH EQU H'0F90' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;PORTJ EQU H'0F88' ;PORTH EQU H'0F87' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' STKPTR4 EQU H'0004' STKPTR3 EQU H'0003' STKPTR2 EQU H'0002' STKPTR1 EQU H'0001' STKPTR0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- LOCK EQU H'0003' PLLEN EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- WDPS2 EQU H'0003' SWDPS2 EQU H'0003' WDPS1 EQU H'0002' SWDPS1 EQU H'0002' WDPS0 EQU H'0001' SWDPS0 EQU H'0001' SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_IPEN EQU H'0007' RI EQU H'0004' NOT_RI EQU H'0004' TO EQU H'0003' NOT_TO EQU H'0003' PD EQU H'0002' NOT_PD EQU H'0002' POR EQU H'0001' NOT_POR EQU H'0001' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCPX EQU H'0005' DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' T3SYNC EQU H'0002' NOT_T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits --------------------------------------------------------- CMLK1 EQU H'0001' CMLK0 EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- MEMCON Bits ---------------------------------------------------------- EBDIS EQU H'0007' PGRM EQU H'0006' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFN EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2 EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 AD0 EQU 0 RD1 EQU 1 AD1 EQU 1 RD2 EQU 2 AD2 EQU 2 RD3 EQU 3 AD3 EQU 3 RD4 EQU 4 AD4 EQU 4 RD5 EQU 5 AD5 EQU 5 RD6 EQU 6 AD6 EQU 6 RD7 EQU 7 AD7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 AD8 EQU 0 RE1 EQU 1 AD9 EQU 1 RE2 EQU 2 AD10 EQU 2 RE3 EQU 3 AD11 EQU 3 RE4 EQU 4 AD12 EQU 4 RE5 EQU 5 AD13 EQU 5 RE6 EQU 6 AD14 EQU 6 RE7 EQU 7 AD15 EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 RF2 EQU 2 AN7 EQU 2 RF3 EQU 3 CSIO EQU 3 RF4 EQU 4 AD16 EQU 4 RF5 EQU 5 CS1 EQU 5 RF6 EQU 6 LB EQU 6 RF7 EQU 7 UB EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 ALE EQU 0 RG1 EQU 1 OE EQU 1 RG2 EQU 2 WRL EQU 2 RG3 EQU 3 WRH EQU 3 RG4 EQU 4 BA0 EQU 4 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'400'-H'F7F', H'F9B', H'FA3'-H'FA5' __BADRAM H'FA8'-H'FAA', H'FB4'-H'FB9', H'FD4' ;========================================================================== ; ; ROM Definition ; ;========================================================================== __MAXROM H'1FFFFF' __BADROM H'40000' - H'1FFDFF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = EC EC Oscillator ; OSC = HS HS Oscillator ; OSC = RC RC Oscillator ; ; Power-up Timer: ; PWRT = ON Enable ; PWRT = OFF Disable ; ; External Bus Data Width: ; BW = 8 8-bit External Bus mode ; BW = 16 16-bit External Bus mode ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Timer Postscale Selection: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Full/Underflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG4L = Configuration Byte 4L 300006h ; ;========================================================================== ;Configuration Byte 1H Options _RC_OSC_1H EQU H'FF' _HS_OSC_1H EQU H'FE' ; Default mode. 4x PLL enabled in S/W _EC_OSC_1H EQU H'FD' ; External Clock w/OSC2 output divide by 4 _LP_OSC_1H EQU H'FC' ; Oscillator type ;Configuration Byte 2L Options _BW_16_BIT_2L EQU H'FF' ; Default bus width _BW_8_BIT_2L EQU H'BF' ; _PWRT_OFF_2L EQU H'FF' ; Disable Power-up Timer _PWRT_ON_2L EQU H'FE' ; Enable Power-up Timer ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as _HS_OSC_1H). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program _CONFIG1H ; __CONFIG _CONFIG1H, _RC_OSC_1H ;Program _CONFIG2L ; __CONFIG _CONFIG2L, _BW_16_BIT_2L & _PWRT_OFF_2L ;Program _CONFIG2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program _CONFIG4L ; __CONFIG _CONFIG4L, _STVR_ON_4L ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p18f4685.inc0000644000175000017500000043217611156521301013252 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4685 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4685 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4685 ; 2. LIST directive in the source file ; LIST P=PIC18F4685 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4685 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' ECCP1CON EQU H'0FBA' ECCPR1 EQU H'0FBB' ECCPR1L EQU H'0FBB' ECCPR1H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF_PORTA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' C1INB EQU H'0000' C1INA EQU H'0001' C2INB EQU H'0002' C2INA EQU H'0003' P1A EQU H'0004' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ECCP1 EQU H'0004' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- ECCP1IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- ECCP1IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- ECCP1IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF_CVRCON EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- ECCP1M0 EQU H'0000' ECCP1M1 EQU H'0001' ECCP1M2 EQU H'0002' ECCP1M3 EQU H'0003' EDC1B0 EQU H'0004' EDC1B1 EQU H'0005' EPWM1M0 EQU H'0006' EPWM1M1 EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; BackGround Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size Select Bits: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot Block (000000-0007FFh) write-protected ; WRTB = OFF Boot Block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot Block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f627.inc0000644000175000017500000002413011156313161013146 00000000000000 LIST ; P16F627.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F627 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F627 ; 2. LIST directive in the source file ; LIST P=PIC16F627 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 13 Sept 2001 Added _DATA_CP_ON and _DATA_CP_OFF ;1.00 10 Feb 1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F627 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' CMIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits --------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' CMIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' NOT_BOD EQU H'0000' ;----- TXSTA Bits ---------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'03FF' _CP_75 EQU H'17FF' _CP_50 EQU H'2BFF' _CP_OFF EQU H'3FFF' _DATA_CP_ON EQU H'3EFF' _DATA_CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FEF' _LP_OSC EQU H'3FEC' _XT_OSC EQU H'3FED' _HS_OSC EQU H'3FEE' LIST gputils-0.13.7/header/p18f13k50.inc0000644000175000017500000013415411156521301013402 00000000000000 LIST ;========================================================================== ; MPASM PIC18F13K50 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F13K50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F13K50 ; 2. LIST directive in the source file ; LIST P=PIC18F13K50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F13K50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UEP0 EQU H'0F53' UEP1 EQU H'0F54' UEP2 EQU H'0F55' UEP3 EQU H'0F56' UEP4 EQU H'0F57' UEP5 EQU H'0F58' UEP6 EQU H'0F59' UEP7 EQU H'0F5A' UEIE EQU H'0F5B' UADDR EQU H'0F5C' UFRML EQU H'0F5D' UFRMH EQU H'0F5E' UEIR EQU H'0F5F' UIE EQU H'0F60' UCFG EQU H'0F61' UIR EQU H'0F62' USTAT EQU H'0F63' UCON EQU H'0F64' SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' REFCON0 EQU H'0FBA' VREFCON0 EQU H'0FBA' REFCON1 EQU H'0FBB' VREFCON1 EQU H'0FBB' REFCON2 EQU H'0FBC' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UPUEN EQU H'0004' UTEYE EQU H'0007' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' USBIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' USBIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' USBIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- REFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- REFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- REFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0100'-H'01FF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F65'-H'0F67' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F75' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; CPU System Clock Selection bit: ; CPUDIV = NOCLKDIV No CPU System Clock divide ; CPUDIV = CLKDIV2 CPU System Clock divided by 2 ; CPUDIV = CLKDIV3 CPU System Clock divided by 3 ; CPUDIV = CLKDIV4 CPU System Clock divided by 4 ; ; USB Clock Selection bit: ; USBDIV = OFF USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide ; USBDIV = ON USB clock comes from the OSC1/OSC2 divided by 2 ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 512W boot block size ; BBSIZ = ON 1kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _CPUDIV_NOCLKDIV_1L EQU H'E7' ; No CPU System Clock divide _CPUDIV_CLKDIV2_1L EQU H'EF' ; CPU System Clock divided by 2 _CPUDIV_CLKDIV3_1L EQU H'F7' ; CPU System Clock divided by 3 _CPUDIV_CLKDIV4_1L EQU H'FF' ; CPU System Clock divided by 4 _USBDIV_OFF_1L EQU H'DF' ; USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide _USBDIV_ON_1L EQU H'FF' ; USB clock comes from the OSC1/OSC2 divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 512W boot block size _BBSIZ_ON_4L EQU H'FF' ; 1kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p12c508a.inc0000644000175000017500000000761411156313161013306 00000000000000 LIST ; P12C508A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12C508A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12C508A ; 2. LIST directive in the source file ; LIST P=12C508A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/28/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12C508A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' OSCFST EQU H'0003' CAL1 EQU H'0003' OSCSLW EQU H'0002' CAL0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16f886.inc0000644000175000017500000005546111156521301013165 00000000000000 LIST ; P16F886.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F886 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F886 ; 2. LIST directive in the source file ; LIST P=PIC16F886 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ; ;1.00 11/18/05 Original ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F886 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' MSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' VRCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' PWM1CON EQU H'009B' ECCPAS EQU H'009C' PSTRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' CM1CON0 EQU H'0107' CM2CON0 EQU H'0108' CM2CON1 EQU H'0109' EEDATA EQU H'010C' EEDAT EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' SRCON EQU H'0185' BAUDCTL EQU H'0187' ANSEL EQU H'0188' ANSELH EQU H'0189' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' BCLIF EQU H'0003' ULPWUIF EQU H'0002' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GIV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' CCP1X EQU H'0005' ; Backward compatibility only DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' ; Backward compatibility only DC2B1 EQU H'0005' CCP2Y EQU H'0004' ; Backward compatibility only DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' BCLIE EQU H'0003' ULPWUIE EQU H'0002' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- IOCB Bits ---------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' C1RSEL EQU H'0005' C2RSEL EQU H'0004' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' FVREN EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS13 EQU H'0005' ANS12 EQU H'0004' ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word1 ------------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'2FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word2 ------------------------------------------------ _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _BOR21V EQU H'3EFF' _BOR40V EQU H'3FFF' LIST gputils-0.13.7/header/p17c44.inc0000644000175000017500000002517611156313161013070 00000000000000 LIST ; P17C44.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C44 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C44 ; 2. LIST directive in the source file ; LIST P=PIC17C44 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.04 03/14/97 Corrected configuration bits value for protected ; microcontroller mode ;1.03 07/15/96 Corrected MAXRAM ;1.02 06/28/96 Corrected MAXRAM, BADRAM, and registers in upper banks ;1.01 04/10/96 Added _WDT_OFF value, PSx values, fixed MAXRAM value ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C44 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCREG EQU H'0014' TXSTA EQU H'0015' TXREG EQU H'0016' SPBRG EQU H'0017' PRODL EQU H'0018' PRODH EQU H'0019' DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' PIE EQU H'0117' TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' NOT_PD EQU H'0002' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIE Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' RCIE EQU H'0000' ;----- PIR Bits ----------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' RCIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' T0CKI EQU H'0001' INT EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' T0PS2 EQU H'0003' PS2 EQU H'0003' T0PS1 EQU H'0002' PS1 EQU H'0002' T0PS0 EQU H'0001' PS0 EQU H'0001' ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3FF' __BADRAM H'118'-H'11F', H'218'-H'2FF', H'318'-H'3FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p16c622.inc0000644000175000017500000001357511156313161013151 00000000000000 LIST ; P16C622.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C622 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C622 ; 2. LIST directive in the source file ; LIST P=PIC16C622 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C622 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'07'-H'09', H'0D'-H'1E', H'87'-H'89', H'8D', H'8F'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f688.inc0000644000175000017500000003332711156521301013162 00000000000000 LIST ; P16F688.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F688 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F688 ; 2. LIST directive in the source file ; LIST P=PIC16F688 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 07/28/03 Original ;1.01 09/02/03 Modified to match datasheet ;1.02 09/19/03 Changed CMCON1 from 0x20 to 0x1A (pas) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F688 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' BAUDCTL EQU H'0011' SPBRGH EQU H'0012' SPBRG EQU H'0013' RCREG EQU H'0014' TXREG EQU H'0015' TXSTA EQU H'0016' RCSTA EQU H'0017' WDTCON EQU H'0018' CMCON0 EQU H'0019' CMCON1 EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' EEDATH EQU H'0097' EEADRH EQU H'0098' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' OSFIF EQU H'0002' TXIF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- BAUDCTL Bits -------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- TXSTA Bits -------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits -------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- COMCON0 Bits ------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- COMCON1 Bits ------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' OSFIE EQU H'0002' TXIE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBODEN EQU H'0004' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D' __BADRAM H'86', H'88'-H'89', H'8D', H'92'-H'94' __BADRAM H'106', H'108'-H'109', H'10C'-H'11F' __BADRAM H'186', H'188'-H'189', H'18C'-H'18D', H'190'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/Makefile.sh0000755000175000017500000000156211156521301013515 00000000000000#!/bin/sh # generate Makefile.am from the directory contents MAKE_FILE=Makefile.am cat > $MAKE_FILE <<\_ACEOF ## This file was automatically generated by Makefile.sh pkgdatadir = @GPUTILS_HEADER_PATH@ HEADER_FILES =\ _ACEOF # compile the header check program rm -f header_check gcc -Wall -pedantic -g -O2 -I../include -o header_check header_check.c # count the number of items in the list let count=0 for x in *.inc do let count=count+1 done # output the file list let number=0 for x in *.inc do let number=number+1 echo "testing $x" ./header_check $x if [ $number -eq $count ]; then echo " $x" >> $MAKE_FILE else echo " $x \\" >> $MAKE_FILE fi done cat >> $MAKE_FILE <<\_ACEOF pkgdata_DATA = $(HEADER_FILES) EXTRA_DIST = $(HEADER_FILES) Makefile.sh header_check.c _ACEOF # clean up the temporary files rm -f header_check gputils-0.13.7/header/p18f8621.inc0000644000175000017500000015206611156521301013241 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8621 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8621 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8621 ; 2. LIST directive in the source file ; LIST P=PIC18F8621 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8621 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ECCP2DEL EQU H'0F67' PWM2CON EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' PWM3CON EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' PWM1CON EQU H'0F79' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' VPP EQU H'0005' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' CCP3Y EQU H'0004' CCP3X EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F00'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F9B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; OSC = ECIOPLL EC-OSC2 as RA6 and PLL ; OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL ; OSC = HSSWPLL HS with SW PLL ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Mode Selection: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait: ; WAIT = ON Enabled ; WAIT = OFF Disabled ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; ECCP MUX: ; ECCPMX = PORTH Multiplexed with RH7:4 ; ECCPMX = PORTE Multiplexed with RE6:3 ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 or RE7 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC-OSC2 as RA6 and PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC-OSC2 as RA6 and SW PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS with SW PLL _OSCS_ON_1H EQU H'DF' ; Enabled _OSCS_OFF_1H EQU H'FF' ; Disabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _WAIT_ON_3L EQU H'7F' ; Enabled _WAIT_OFF_3L EQU H'FF' ; Disabled ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _ECCPMX_PORTH_3H EQU H'FD' ; Multiplexed with RH7:4 _ECCPMX_PORTE_3H EQU H'FF' ; Multiplexed with RE6:3 _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 or RE7 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c5x.inc0000644000175000017500000002224611156521301013164 00000000000000 LIST ; P16C5X.INC Standard Header File, Version 4.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the 16C5X microcontrollers. These names are taken to match ; the data sheets as closely as possible. The microcontrollers included ; in this file are: ; 16C52 ; 16C54 ; 16CR54 ; 16C54A ; 16CR54A ; 16C54B ; 16CR54B ; 16C54C ; 16CR54C ; 16C55 ; 16C55A ; 16C56 ; 16C56A ; 16CR56A ; 16C57 ; 16CR57A ; 16CR57B ; 16C57C ; 16CR57C ; 16C58A ; 16CR58A ; 16C58B ; 16CR58B ; There is one group of symbols that is valid for all microcontrollers. ; Each microcontroller in this family also has its own section of special ; symbols. Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16C54A ; 2. LIST directive in the source file ; LIST P=16C54A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;4.12 12/02/02 Added 16CR57C ;4.11 01/18/99 Added 54C, 55A, 57C for interim release ;4.10 08/18/98 Added new processor for MPASM v2.16 ;4.00 06/05/97 Added new processors for MPASM v2.00 ;3.30 07/16/96 Aligned processors with MPASM v1.40 ;3.20 04/09/96 Added 16C54B, 16CR56B, 16C58B ;3.10 12/14/95 Added 16C52 ;3.01 11/29/95 Removed 16CR55 ;3.00 10/16/95 Added new processors for MPASM v1.30 ;2.04 07/26/95 Reformatted for readability ;2.03 06/21/95 Removed leading spaces ;========================================================================== ; ; Generic Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- PA2 EQU H'0007' PA1 EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; Processor-dependent Definitions ; ;========================================================================== IFDEF __16C52 __MAXRAM H'01F' #define __CONFIG_2 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C54 __MAXRAM H'01F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR54 __MAXRAM H'01F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C54A __MAXRAM H'01F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR54A __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C54B __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C54C __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR54B __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR54C __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C55 ; Register Files PORTC EQU H'0007' __MAXRAM H'01F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C55A ; Register Files PORTC EQU H'0007' __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C56 __MAXRAM H'01F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C56A __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR56A __MAXRAM H'01F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C57 ; Register Files PORTC EQU H'0007' __MAXRAM H'07F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C57C ; Register Files PORTC EQU H'0007' __MAXRAM H'07F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR57A ; Register Files PORTC EQU H'0007' __MAXRAM H'07F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR57B ; Register Files PORTC EQU H'0007' __MAXRAM H'07F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR57C ; Register Files PORTC EQU H'0007' __MAXRAM H'07F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C58A __MAXRAM H'07F' #define __CONFIG_0 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR58A __MAXRAM H'07F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16C58B __MAXRAM H'07F' #define __CONFIG_1 ENDIF ;-------------------------------------------------------------------------- IFDEF __16CR58B __MAXRAM H'07F' #define __CONFIG_1 ENDIF ;========================================================================== ; ; Configuration Bits ; ;========================================================================== IFDEF __CONFIG_0 _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _HS_OSC EQU H'0FFE' _RC_OSC EQU H'0FFF' #undefine __CONFIG_0 ENDIF IFDEF __CONFIG_1 _CP_ON EQU H'0007' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _HS_OSC EQU H'0FFE' _RC_OSC EQU H'0FFF' #undefine __CONFIG_1 ENDIF IFDEF __CONFIG_2 _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _XT_OSC EQU H'0FFD' _RC_OSC EQU H'0FFF' #undefine __CONFIG_2 ENDIF LIST gputils-0.13.7/header/p16c557.inc0000644000175000017500000001113311156313161013144 00000000000000 LIST ; P16C557.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C557 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /p=16C557 ; 2. LIST directive in the source file ; LIST P=16C557 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 08/29/01 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C557 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PCON EQU H'008E' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08'-H'09', H'0C'-H'1F' __BADRAM H'88'-H'89', H'8C'-H'8D', H'8F'-H'9F', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f86j90.inc0000644000175000017500000017207411156521301013422 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J90 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J90 ; 2. LIST directive in the source file ; LIST P=PIC18F86J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PADCFG1 EQU H'0F54' CTMUICON EQU H'0F55' CTMUCONL EQU H'0F56' CTMUCONH EQU H'0F57' ALRMVALL EQU H'0F58' ALRMVALH EQU H'0F59' ALRMRPT EQU H'0F5A' ALRMCFG EQU H'0F5B' RTCVALL EQU H'0F5C' RTCVALH EQU H'0F5D' RTCCAL EQU H'0F5E' RTCCFG EQU H'0F5F' RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' ECCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' ECCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA5 EQU H'0F6B' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA11 EQU H'0F71' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA17 EQU H'0F77' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' LCDDATA23 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' TRISF EQU H'0F97' TRISG EQU H'0F98' TRISH EQU H'0F99' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDSE5 EQU H'0FBA' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PADCFG1 Bits ----------------------------------------------------- RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' SEG00COM3 EQU H'0000' SEG01COM3 EQU H'0001' SEG02COM3 EQU H'0002' SEG03COM3 EQU H'0003' SEG04COM3 EQU H'0004' SEG05COM3 EQU H'0005' SEG06COM3 EQU H'0006' SEG07COM3 EQU H'0007' S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' TOCKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' CTED1 EQU H'0002' CTED2 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' CTPLS EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' CVREF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' TX2 EQU H'0001' RX2 EQU H'0002' RTCC EQU H'0004' VLCAP1 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' CCP1IE EQU H'0001' CCP2IE EQU H'0002' CTMUIE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' CCP1IF EQU H'0001' CCP2IF EQU H'0002' CTMUIF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' CCP1IP EQU H'0001' CCP2IP EQU H'0002' CTMUIP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- TRIGSEL EQU H'0007' PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM_RCON EQU H'0005' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- MODE13 EQU H'0002' CPEN EQU H'0006' CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- IOFS EQU H'0002' OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled-Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Oscillator Selection bits: ; OSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; OSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; OSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; OSC = INTOSCPLLO INTOSC with PLL enabled, CLKOUT on RA6 and port function on RA7 ; OSC = HS HS oscillator ; OSC = HSPLL HS oscillator, PLL enabled ; OSC = EC EC Oscillator with clock out on RA6 ; OSC = ECPLL EC Oscillator with PLL ; ; Secondary Clock Source T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = ON Timer1 oscillator configured for low-power operation ; LPT1OSC = OFF Timer1 oscillator configured for higher power operation ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Reference Clock Select bit: ; RTCSOSC = INTOSCREF RTCC uses INTOSC/INTRC as reference clock ; RTCSOSC = T1OSCREF RTCC uses T1OSC/T1CKI as reference clock ; ; CCP2 MUX: ; CCP2MX = ALTERNATE RE7 / RB3 ; CCP2MX = DEFAULT RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/memory.inc0000644000175000017500000002073611156313161013453 00000000000000 LIST ; MEMORY.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines the maximum byte address for memory devices. ; To use MPASM to generate memory device data, select either EEPROM8 or ; EEPROM16 as the "processor". Use the DATA directive to generate the ; data for the device. All mathematical, text substitution, symbol, and ; macro support is available for generating the data. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PEEPROM8 ; or ; C:\ MPASM MYFILE.ASM /PEEPROM16 ; 2. LIST directive in the source file ; LIST P=EEPROM8 ; or ; LIST P=EEPROM16 ; 3. Processor Type entry in the MPASM full-screen interface ; The default byte size for a memory device is 256 bytes. To modify this, ; use the symbols defined in the file in the LIST M=??? directive. For ; example: ; LIST P=EEPROM8 ; INCLUDE "MEMORY.INC" ; LIST M=_24LCS21 ; Note that case sensitivity is enforced by default. ;========================================================================== ; ; Revision History ; ; Rev: Date: Reason: ; 1.02 03/25/99 Added new devices ; 1.01 12/16/96 Added new devices ; 1.00 07/18/96 Initial release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFDEF __EEPROM8 #define __IS_MEMORY ENDIF IFDEF __EEPROM16 #define __IS_MEMORY ENDIF IFNDEF __IS_MEMORY MESSG "Processor-header file mismatch. Verify selected processor." ELSE #undefine __IS_MEMORY ENDIF ;========================================================================== ; ; 2-Wire Bus Protocol ; ;========================================================================== ;-------------------------------------------------------------------------- ; ; AA Series ; ;-------------------------------------------------------------------------- #define _24AA00 H'000F' #define _24AA01 H'007F' #define _24AA02 H'00FF' #define _24AA04 H'01FF' #define _24AA08 H'03FF' #define _24AA16 H'07FF' #define _24AA32 H'0FFF' #define _24AA32A H'0FFF' #define _24AA64 H'1FFF' #define _24AA128 H'3FFF' #define _24AA256 H'7FFF' #define _24AA164 H'07FF' #define _24AA174 H'07FF' ;-------------------------------------------------------------------------- ; ; C-Series ; ;-------------------------------------------------------------------------- #define _24C00 H'000F' #define _24C01A H'007F' #define _24C01B H'007F' #define _24C01C H'007F' #define _24C02A H'00FF' #define _24C02B H'00FF' #define _24C02C H'00FF' #define _24C04A H'01FF' #define _24C08B H'03FF' #define _24C16B H'07FF' #define _24C32 H'0FFF' #define _24C32A H'0FFF' #define _85C72 H'007F' #define _85C82 H'00FF' #define _85C92 H'01FF' ;-------------------------------------------------------------------------- ; ; FC Series ; ;-------------------------------------------------------------------------- #define _24FC16 H'07FF' #define _24FC32 H'0FFF' ;-------------------------------------------------------------------------- ; ; Low-Voltage LC Series ; ;-------------------------------------------------------------------------- #define _24LC00 H'000F' #define _24LC01B H'007F' #define _24LC02B H'00FF' #define _24LC04B H'01FF' #define _24LC08B H'03FF' #define _24LC16B H'07FF' #define _24LC32 H'0FFF' #define _24LC32A H'0FFF' #define _24LC64 H'1FFF' #define _24LC128 H'3FFF' #define _24LC256 H'7FFF' #define _24LC164 H'07FF' #define _24LC174 H'07FF' ;-------------------------------------------------------------------------- ; ; Smart Card Devices ; ;-------------------------------------------------------------------------- #define _24C01SC H'007F' #define _24C02SC H'00FF' #define _24LC32ASC H'0FFF' #define _24LC64SC H'1FFF' #define _24LC128SC H'3FFF' #define _24LC256SC H'7FFF' ;-------------------------------------------------------------------------- ; ; Smart Serial (tm) Family ; ;-------------------------------------------------------------------------- #define _24C65 H'1FFF' #define _24LC65 H'1FFF' #define _24AA65 H'1FFF' #define _24FC65 H'1FFF' ;-------------------------------------------------------------------------- ; ; VESA (tm) / DDC (tm) ; ;-------------------------------------------------------------------------- #define _24LC21 H'007F' #define _24LC21A H'007F' #define _24LCS21 H'007F' #define _24LCS21A H'007F' #define _24LC41A H'01FF' ;-------------------------------------------------------------------------- ; ; SPD DIMM ; ;-------------------------------------------------------------------------- #define _24LC024 H'00FF' #define _24LC025 H'00FF' #define _24LCS52 H'00FF' #define _24LCS61 H'007F' #define _24LCS62 H'00FF' ;========================================================================== ; ; 3-Wire/4-Wire Bus Protocol ; ;========================================================================== ;-------------------------------------------------------------------------- ; ; G.I. ; ;-------------------------------------------------------------------------- #define _59C11 H'007F' ;-------------------------------------------------------------------------- ; ; AA Series ; ;-------------------------------------------------------------------------- #define _93AA46 H'007F' #define _93AA56 H'00FF' #define _93AA66 H'01FF' #define _93AA76 H'03FF' #define _93AA86 H'07FF' ;-------------------------------------------------------------------------- ; ; C-Series ; ;-------------------------------------------------------------------------- #define _93C06 H'001F' #define _93C46 H'007F' #define _93C76 H'03FF' #define _93C86 H'07FF' ;-------------------------------------------------------------------------- ; ; Low-Voltage LC Series ; ;-------------------------------------------------------------------------- #define _93LC46 H'007F' #define _93LC46A H'007F' #define _93LC46B H'007F' #define _93LC56 H'00FF' #define _93LC56A H'00FF' #define _93LC56B H'00FF' #define _93LC66 H'01FF' #define _93LC66A H'01FF' #define _93LC66B H'01FF' #define _93LC76 H'03FF' #define _93LC86 H'07FF' ;-------------------------------------------------------------------------- ; ; Secure LCS-Series ; ;-------------------------------------------------------------------------- #define _93LCS56 H'00FF' #define _93LCS66 H'01FF' ;========================================================================== ; ; SPI Protocol ; ;========================================================================== ;-------------------------------------------------------------------------- ; ; AA Series ; ;-------------------------------------------------------------------------- #define _25AA040 H'01FF' #define _25AA080 H'03FF' #define _25AA160 H'07FF' #define _25AA640 H'1FFF' #define _25AA128 H'3FFF' #define _25AA256 H'7FFF' ;-------------------------------------------------------------------------- ; ; C-Series ; ;-------------------------------------------------------------------------- #define _25C040 H'01FF' #define _25C080 H'03FF' #define _25C160 H'07FF' #define _25C320 H'0FFF' ;-------------------------------------------------------------------------- ; ; Low-Voltage LC Series ; ;-------------------------------------------------------------------------- #define _25LC040 H'01FF' #define _25LC080 H'03FF' #define _25LC160 H'07FF' #define _25LC320 H'0FFF' #define _25LC640 H'1FFF' #define _25LC128 H'3FFF' #define _25LC256 H'7FFF' LIST gputils-0.13.7/header/p17c762.inc0000644000175000017500000004552611156313161013160 00000000000000 LIST ; P17C762.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C762 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C762 ; 2. LIST directive in the source file ; LIST P=PIC17C762 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/01/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C762 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' BANK4 EQU H'0004' BANK5 EQU H'0005' BANK6 EQU H'0006' BANK7 EQU H'0007' BANK8 EQU H'0008' ; added 5/2/01 BD - Apps GPR_BANK0 EQU H'0000' GPR_BANK1 EQU H'0008' GPR_BANK2 EQU H'0010' GPR_BANK3 EQU H'0018' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' ;----- Bank 0 ------------------------------------------------------------- PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCSTA1 EQU H'0013' RCREG EQU H'0014' ; Backward compatibility only RCREG1 EQU H'0014' TXSTA EQU H'0015' ; Backward compatibility only TXSTA1 EQU H'0015' TXREG EQU H'0016' ; Backward compatibility only TXREG1 EQU H'0016' SPBRG EQU H'0017' ; Backward compatibility only SPBRG1 EQU H'0017' ;----- Bank 1 ------------------------------------------------------------- DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' ; Backward compatibility only PIR1 EQU H'0116' PIE EQU H'0117' ; Backward compatibility only PIE1 EQU H'0117' ;----- Bank 2 ------------------------------------------------------------- TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' ;----- Bank 3 ------------------------------------------------------------- PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- Bank 4 ------------------------------------------------------------- PIR2 EQU H'0410' PIE2 EQU H'0411' RCSTA2 EQU H'0413' RCREG2 EQU H'0414' TXSTA2 EQU H'0415' TXREG2 EQU H'0416' SPBRG2 EQU H'0417' ;----- Bank 5 ------------------------------------------------------------- DDRF EQU H'0510' PORTF EQU H'0511' DDRG EQU H'0512' PORTG EQU H'0513' ADCON0 EQU H'0514' ADCON1 EQU H'0515' ADRESL EQU H'0516' ADRESH EQU H'0517' ;----- Bank 6 ------------------------------------------------------------- SSPADD EQU H'0610' SSPCON1 EQU H'0611' SSPCON2 EQU H'0612' SSPSTAT EQU H'0613' SSPBUF EQU H'0614' ;----- Bank 7 ------------------------------------------------------------- PW3DCL EQU H'0710' PW3DCH EQU H'0711' CA3L EQU H'0712' CA3H EQU H'0713' CA4L EQU H'0714' CA4H EQU H'0715' TCON3 EQU H'0716' ;----- Bank 8 ------------------------------------------------------------- DDRH EQU H'0810' PORTH EQU H'0811' DDRJ EQU H'0812' PORTJ EQU H'0813' ;----- Unbanked ----------------------------------------------------------- PRODL EQU H'0018' PL EQU H'0018' ; Backward compatibility only PRODH EQU H'0019' PH EQU H'0019' ; Backward compatibility only ;----- Special Function Register Bit Definitions -------------------------- ; ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' ; Backward compatibility only TX1IF EQU H'0001' RCIF EQU H'0000' ; Backward compatibility only RC1IF EQU H'0000' ;----- PIE1 Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' ; Backward compatibility only TX1IE EQU H'0001' RCIE EQU H'0000' ; Backward compatibility only RC1IE EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' ;----- RCSTA1 and 2 Bits -------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' ; Backward compatibility only T0PS2 EQU H'0003' PS2 EQU H'0003' ; Backward compatibility only T0PS1 EQU H'0002' PS1 EQU H'0002' ; Backward compatibility only T0PS0 EQU H'0001' PS0 EQU H'0001' ; Backward compatibility only ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- SSPIF EQU H'0007' BCLIF EQU H'0006' ADIF EQU H'0005' CA4IF EQU H'0003' CA3IF EQU H'0002' TX2IF EQU H'0001' RC2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- SSPIE EQU H'0007' BCLIE EQU H'0006' ADIE EQU H'0005' CA4IE EQU H'0003' CA3IE EQU H'0002' TX2IE EQU H'0001' RC2IE EQU H'0000' ;----- TXSTA1 and 2 Bits -------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0007' CHS2 EQU H'0006' CHS1 EQU H'0005' CHS0 EQU H'0004' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' ADFM EQU H'0005' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- SSPCON1 Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' AKSTAT EQU H'0006' ACKDT EQU H'0005' AKDT EQU H'0005' ACKEN EQU H'0004' AKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' NOT_A EQU H'0005' D_A EQU H'0005' P EQU H'0004' S EQU H'0003' R EQU H'0002' NOT_W EQU H'0002' R_W EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TCON3 Bits --------------------------------------------------------- CA4OVF EQU H'0006' CA3OVF EQU H'0005' CA4ED1 EQU H'0004' CA4ED0 EQU H'0003' CA3ED1 EQU H'0002' CA3ED0 EQU H'0001' PWM3ON EQU H'0000' ;----- PW2DCL Bit --------------------------------------------------------- TM2PW2 EQU H'0005' ;----- PW3DCL Bit --------------------------------------------------------- TM2PW3 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'8FF' __BADRAM H'118'-H'11F', H'218'-H'21F', H'318'-H'31F' __BADRAM H'412', H'418'-H'4FF' __BADRAM H'518'-H'5FF' __BADRAM H'615'-H'6FF' __BADRAM H'717'-H'7FF' __BADRAM H'814'-H'8FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _BODEN_OFF EQU H'BFFF' _BODEN_ON EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _WDT_0 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p16f876a.inc0000644000175000017500000003634411156313161013327 00000000000000 LIST ; P16F876A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F877A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F876A ; 2. LIST directive in the source file ; LIST P=PIC16F876A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 11/17/05 Added the INTCON bits TMR0IE and TMR0IF and the ADCON1 bit ADCS2. ;1.02 05/28/02 Corrected values for _CP_ALL and _CP_OFF in Configuration Bits section. ;1.01 10/03/01 Added the PIR2 bit CMIF and the PIE2 bit CMIE ;1.00 04/19/01 Initial Release (BD - generated from PIC16F877.inc) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F876A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON EQU H'009C' CVRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A'-H'9B' __BADRAM H'105', H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_OFF EQU H'3FFF' ; No prog memmory write protection _WRT_256 EQU H'3DFF' ; First 256 prog memmory write protected _WRT_1FOURTH EQU H'3BFF' ; First quarter prog memmory write protected _WRT_HALF EQU H'39FF' ; First half memmory write protected _CPD_OFF EQU H'3FFF' _CPD_ON EQU H'3EFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _RC_OSC EQU H'3FFF' _HS_OSC EQU H'3FFE' _XT_OSC EQU H'3FFD' _LP_OSC EQU H'3FFC' LIST gputils-0.13.7/header/Makefile.am0000644000175000017500000001516511156521301013501 00000000000000## This file was automatically generated by Makefile.sh pkgdatadir = @GPUTILS_HEADER_PATH@ HEADER_FILES =\ coff.inc \ mcp250xx.inc \ memory.inc \ migrate.inc \ p10f200.inc \ p10f202.inc \ p10f204.inc \ p10f206.inc \ p10f220.inc \ p10f222.inc \ p12c508a.inc \ p12c508.inc \ p12c509a.inc \ p12c509.inc \ p12c671.inc \ p12c672.inc \ p12ce518.inc \ p12ce519.inc \ p12ce673.inc \ p12ce674.inc \ p12f508.inc \ p12f509.inc \ p12f510.inc \ p12f519.inc \ p12f609.inc \ p12f615.inc \ p12f629.inc \ p12f635.inc \ p12f675.inc \ p12f683.inc \ p12hv609.inc \ p12hv615.inc \ p14000.inc \ p16c432.inc \ p16c433.inc \ p16c505.inc \ p16c554.inc \ p16c557.inc \ p16c558.inc \ p16c5x.inc \ p16c61.inc \ p16c620a.inc \ p16c620.inc \ p16c621a.inc \ p16c621.inc \ p16c622a.inc \ p16c622.inc \ p16c62a.inc \ p16c62b.inc \ p16c62.inc \ p16c63a.inc \ p16c63.inc \ p16c642.inc \ p16c64a.inc \ p16c64.inc \ p16c65a.inc \ p16c65b.inc \ p16c65.inc \ p16c662.inc \ p16c66.inc \ p16c67.inc \ p16c710.inc \ p16c711.inc \ p16c712.inc \ p16c715.inc \ p16c716.inc \ p16c717.inc \ p16c71.inc \ p16c72a.inc \ p16c72.inc \ p16c73a.inc \ p16c73b.inc \ p16c73.inc \ p16c745.inc \ p16c74a.inc \ p16c74b.inc \ p16c74.inc \ p16c765.inc \ p16c76.inc \ p16c770.inc \ p16c771.inc \ p16c773.inc \ p16c774.inc \ p16c77.inc \ p16c781.inc \ p16c782.inc \ p16c84.inc \ p16c923.inc \ p16c924.inc \ p16c925.inc \ p16c926.inc \ p16ce623.inc \ p16ce624.inc \ p16ce625.inc \ p16cr62.inc \ p16cr63.inc \ p16cr64.inc \ p16cr65.inc \ p16cr72.inc \ p16cr83.inc \ p16cr84.inc \ p16f1933.inc \ p16f1934.inc \ p16f1936.inc \ p16f1937.inc \ p16f505.inc \ p16f506.inc \ p16f526.inc \ p16f5x.inc \ p16f610.inc \ p16f616.inc \ p16f627a.inc \ p16f627.inc \ p16f628a.inc \ p16f628.inc \ p16f630.inc \ p16f631.inc \ p16f636.inc \ p16f639.inc \ p16f648a.inc \ p16f676.inc \ p16f677.inc \ p16f684.inc \ p16f685.inc \ p16f687.inc \ p16f688.inc \ p16f689.inc \ p16f690.inc \ p16f716.inc \ p16f722.inc \ p16f723.inc \ p16f724.inc \ p16f726.inc \ p16f727.inc \ p16f72.inc \ p16f737.inc \ p16f73.inc \ p16f747.inc \ p16f74.inc \ p16f767.inc \ p16f76.inc \ p16f777.inc \ p16f77.inc \ p16f785.inc \ p16f818.inc \ p16f819.inc \ p16f83.inc \ p16f84a.inc \ p16f84.inc \ p16f870.inc \ p16f871.inc \ p16f872.inc \ p16f873a.inc \ p16f873.inc \ p16f874a.inc \ p16f874.inc \ p16f876a.inc \ p16f876.inc \ p16f877a.inc \ p16f877.inc \ p16f87.inc \ p16f882.inc \ p16f883.inc \ p16f884.inc \ p16f886.inc \ p16f887.inc \ p16f88.inc \ p16f913.inc \ p16f914.inc \ p16f916.inc \ p16f917.inc \ p16f946.inc \ p16hv540.inc \ p16hv610.inc \ p16hv616.inc \ p16hv785.inc \ p16lf1933.inc \ p16lf1934.inc \ p16lf1936.inc \ p16lf1937.inc \ p16lf722.inc \ p16lf723.inc \ p16lf724.inc \ p16lf726.inc \ p16lf727.inc \ p17c42a.inc \ p17c42.inc \ p17c43.inc \ p17c44.inc \ p17c752.inc \ p17c756a.inc \ p17c756.inc \ p17c762.inc \ p17c766.inc \ p17cr42.inc \ p17cr43.inc \ p18c242.inc \ p18c252.inc \ p18c442.inc \ p18c452.inc \ p18c601.inc \ p18c658.inc \ p18c801.inc \ p18c858.inc \ p18cxxx.inc \ p18f1220.inc \ p18f1230.inc \ p18f1320.inc \ p18f1330.inc \ p18f13k22.inc \ p18f13k50.inc \ p18f14k22.inc \ p18f14k50.inc \ p18f2220.inc \ p18f2221.inc \ p18f2320.inc \ p18f2321.inc \ p18f2331.inc \ p18f23k20.inc \ p18f2410.inc \ p18f2420.inc \ p18f2423.inc \ p18f242.inc \ p18f2431.inc \ p18f2439.inc \ p18f2450.inc \ p18f2455.inc \ p18f2458.inc \ p18f2480.inc \ p18f248.inc \ p18f24j10.inc \ p18f24j11.inc \ p18f24j50.inc \ p18f24k20.inc \ p18f2510.inc \ p18f2515.inc \ p18f2520.inc \ p18f2523.inc \ p18f2525.inc \ p18f252.inc \ p18f2539.inc \ p18f2550.inc \ p18f2553.inc \ p18f2580.inc \ p18f2585.inc \ p18f258.inc \ p18f25j10.inc \ p18f25j11.inc \ p18f25j50.inc \ p18f25k20.inc \ p18f2610.inc \ p18f2620.inc \ p18f2680.inc \ p18f2682.inc \ p18f2685.inc \ p18f26j11.inc \ p18f26j50.inc \ p18f26k20.inc \ p18f4220.inc \ p18f4221.inc \ p18f4320.inc \ p18f4321.inc \ p18f4331.inc \ p18f43k20.inc \ p18f4410.inc \ p18f4420.inc \ p18f4423.inc \ p18f442.inc \ p18f4431.inc \ p18f4439.inc \ p18f4450.inc \ p18f4455.inc \ p18f4458.inc \ p18f4480.inc \ p18f448.inc \ p18f44j10.inc \ p18f44j11.inc \ p18f44j50.inc \ p18f44k20.inc \ p18f4510.inc \ p18f4515.inc \ p18f4520.inc \ p18f4523.inc \ p18f4525.inc \ p18f452.inc \ p18f4539.inc \ p18f4550.inc \ p18f4553.inc \ p18f4580.inc \ p18f4585.inc \ p18f458.inc \ p18f45j10.inc \ p18f45j11.inc \ p18f45j50.inc \ p18f45k20.inc \ p18f4610.inc \ p18f4620.inc \ p18f4680.inc \ p18f4682.inc \ p18f4685.inc \ p18f46j11.inc \ p18f46j50.inc \ p18f46k20.inc \ p18f6310.inc \ p18f6390.inc \ p18f6393.inc \ p18f63j11.inc \ p18f63j90.inc \ p18f6410.inc \ p18f6490.inc \ p18f6493.inc \ p18f64j11.inc \ p18f64j90.inc \ p18f6520.inc \ p18f6525.inc \ p18f6527.inc \ p18f6585.inc \ p18f65j10.inc \ p18f65j11.inc \ p18f65j15.inc \ p18f65j50.inc \ p18f65j90.inc \ p18f6620.inc \ p18f6621.inc \ p18f6622.inc \ p18f6627.inc \ p18f6628.inc \ p18f6680.inc \ p18f66j10.inc \ p18f66j11.inc \ p18f66j15.inc \ p18f66j16.inc \ p18f66j50.inc \ p18f66j55.inc \ p18f66j60.inc \ p18f66j65.inc \ p18f66j90.inc \ p18f6720.inc \ p18f6722.inc \ p18f6723.inc \ p18f67j10.inc \ p18f67j11.inc \ p18f67j50.inc \ p18f67j60.inc \ p18f67j90.inc \ p18f8310.inc \ p18f8390.inc \ p18f8393.inc \ p18f83j11.inc \ p18f83j90.inc \ p18f8410.inc \ p18f8490.inc \ p18f8493.inc \ p18f84j11.inc \ p18f84j90.inc \ p18f8520.inc \ p18f8525.inc \ p18f8527.inc \ p18f8585.inc \ p18f85j10.inc \ p18f85j11.inc \ p18f85j15.inc \ p18f85j50.inc \ p18f85j90.inc \ p18f8620.inc \ p18f8621.inc \ p18f8622.inc \ p18f8627.inc \ p18f8628.inc \ p18f8680.inc \ p18f86j10.inc \ p18f86j11.inc \ p18f86j15.inc \ p18f86j16.inc \ p18f86j50.inc \ p18f86j55.inc \ p18f86j60.inc \ p18f86j65.inc \ p18f86j90.inc \ p18f8720.inc \ p18f8722.inc \ p18f8723.inc \ p18f87j10.inc \ p18f87j11.inc \ p18f87j50.inc \ p18f87j60.inc \ p18f87j90.inc \ p18f96j60.inc \ p18f96j65.inc \ p18f97j60.inc \ p18lf13k22.inc \ p18lf13k50.inc \ p18lf14k22.inc \ p18lf14k50.inc \ p18lf24j11.inc \ p18lf24j50.inc \ p18lf25j11.inc \ p18lf25j50.inc \ p18lf26j11.inc \ p18lf26j50.inc \ p18lf44j11.inc \ p18lf44j50.inc \ p18lf45j11.inc \ p18lf45j50.inc \ p18lf46j11.inc \ p18lf46j50.inc \ p18macro.inc \ pmcv08a.inc \ pmcv14a.inc \ pmcv18a.inc \ pmcv28a.inc \ ps500.inc \ ps810.inc \ rf509af.inc \ rf509ag.inc \ rf675f.inc \ rf675h.inc \ rf675k.inc pkgdata_DATA = $(HEADER_FILES) EXTRA_DIST = $(HEADER_FILES) Makefile.sh header_check.c gputils-0.13.7/header/p18f87j10.inc0000644000175000017500000014175511156521301013415 00000000000000 LIST ;========================================================================== ; MPASM PIC18F87J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F87J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F87J10 ; 2. LIST directive in the source file ; LIST P=PIC18F87J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F87J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f6520.inc0000644000175000017500000012126211156521301013227 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6520 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6520 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6520 ; 2. LIST directive in the source file ; LIST P=PIC18F6520 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6520 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2A EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DCCP3Y EQU H'0004' DCCP3X EQU H'0005' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F79'-H'0F7F' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9C' __BADRAM H'0FB6' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC-OSC2 as Clock Out ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Uses RE7 ; CCP2MUX = RE7 Uses RE7 ; CCP2MUX = ON Uses RC1 ; CCP2MUX = RC1 Uses RC1 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F8' ; LP _OSC_XT_1H EQU H'F9' ; XT _OSC_HS_1H EQU H'FA' ; HS _OSC_RC_1H EQU H'FB' ; RC-OSC2 as Clock Out _OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6 _OSCS_ON_1H EQU H'DF' ; Enabled _OSCS_OFF_1H EQU H'FF' ; Disabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_25_2L EQU H'FF' ; 2.5V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'F1' ; 1:1 _WDTPS_2_2H EQU H'F3' ; 1:2 _WDTPS_4_2H EQU H'F5' ; 1:4 _WDTPS_8_2H EQU H'F7' ; 1:8 _WDTPS_16_2H EQU H'F9' ; 1:16 _WDTPS_32_2H EQU H'FB' ; 1:32 _WDTPS_64_2H EQU H'FD' ; 1:64 _WDTPS_128_2H EQU H'FF' ; 1:128 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _CCP2MUX_OFF_3H EQU H'FE' ; Uses RE7 _CCP2MUX_RE7_3H EQU H'FE' ; Uses RE7 _CCP2MUX_ON_3H EQU H'FF' ; Uses RC1 _CCP2MUX_RC1_3H EQU H'FF' ; Uses RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f8393.inc0000644000175000017500000017646211156521301013255 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8393 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8393 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8393 ; 2. LIST directive in the source file ; LIST P=PIC18F8393 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8393 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDSE4 EQU H'0F5E' LCDSE5 EQU H'0F5F' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG32 EQU H'0000' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F7D' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f690.inc0000644000175000017500000005522411156521301013153 00000000000000 LIST ; P16F690.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F690 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F690 ; 2. LIST directive in the source file ; LIST P=PIC16F690 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/12/04 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F690 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' PWM1CON EQU H'001C' ECCPAS EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' SSPADD EQU H'0093' MSK EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' WDTCON EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' SPBRGH EQU H'009A' BAUDCTL EQU H'009B' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDAT EQU H'010C' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' WPUB EQU H'0115' IOCB EQU H'0116' VRCON EQU H'0118' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' ANSEL EQU H'011E' ANSELH EQU H'011F' EECON1 EQU H'018C' EECON2 EQU H'018D' PSTRCON EQU H'019D' SRCON EQU H'019E' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RABIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RABIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION Bits -------------------------------------------------------- NOT_RABPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TRISB7 EQU H'0007' TRISB6 EQU H'0006' TRISB5 EQU H'0005' TRISB4 EQU H'0004' ;----- TRISC Bits -------------------------------------------------------- TRISC7 EQU H'0007' TRISC6 EQU H'0006' TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits -------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' SENB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- SPBRG Bits ------------------------------------------------------- BRG7 EQU H'0007' BRG6 EQU H'0006' BRG5 EQU H'0005' BRG4 EQU H'0004' BRG3 EQU H'0003' BRG2 EQU H'0002' BRG1 EQU H'0001' BRG0 EQU H'0000' ;----- SPBRGH Bits ------------------------------------------------------- BRG15 EQU H'0007' BRG14 EQU H'0006' BRG13 EQU H'0005' BRG12 EQU H'0004' BRG11 EQU H'0003' BRG10 EQU H'0002' BRG9 EQU H'0001' BRG8 EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------- ABDOVF EQU H'0007' RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' ;----- IOCB Bits --------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ANSELH Bits -------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'1B' __BADRAM H'88'-H'89', H'91', H'9C'-H'9D' __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D' __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16f1937.inc0000644000175000017500000012527411156521301013243 00000000000000 LIST ;========================================================================== ; MPASM PIC16F1937 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16F1937 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16F1937 ; 2. LIST directive in the source file ; LIST P=PIC16F1937 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F1937 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTD EQU H'000F' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISD EQU H'008F' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATD EQU H'010F' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' ANSELD EQU H'018F' ANSELE EQU H'0190' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDSE2 EQU H'079A' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA2 EQU H'07A2' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA5 EQU H'07A5' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA8 EQU H'07A8' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' LCDDATA11 EQU H'07AB' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' CPSCH3 EQU H'0003' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- ANSELD Bits ----------------------------------------------------- ANSD0 EQU H'0000' ANSD1 EQU H'0001' ANSD2 EQU H'0002' ANSD3 EQU H'0003' ANSD4 EQU H'0004' ANSD5 EQU H'0005' ANSD6 EQU H'0006' ANSD7 EQU H'0007' ;----- ANSELE Bits ----------------------------------------------------- ANSE0 EQU H'0000' ANSE1 EQU H'0001' ANSE2 EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SEG16 EQU H'0000' SEG17 EQU H'0001' SEG18 EQU H'0002' SEG19 EQU H'0003' SEG20 EQU H'0004' SEG21 EQU H'0005' SEG22 EQU H'0006' SEG23 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA2 Bits ----------------------------------------------------- SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA8 Bits ----------------------------------------------------- SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E' __BADRAM H'0197'-H'0198' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0330'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079B'-H'079F' __BADRAM H'07AC'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _PWRTE_ON EQU H'FFDF' ; PWRT enabled _PWRTE_OFF EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _DEBUG_ON EQU H'EFFF' ; Background debugger is enabled _DEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p16c505.inc0000644000175000017500000001004711156313161013140 00000000000000 LIST ; P16C505.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C505 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16C505 ; 2. LIST directive in the source file ; LIST P=16C505 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 03/01/98 Initial Release ;1.10 13Aug2001 Fixed MAXRAM definition ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C505 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' ;----- STATUS Bits -------------------------------------------------------- RBWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBWU EQU H'0007' NOT_RBPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FDF' _CP_ON EQU H'002F' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FF7' _LP_OSC EQU H'0FF8' _XT_OSC EQU H'0FF9' _HS_OSC EQU H'0FFA' _IntRC_OSC_RB4EN EQU H'0FFC' _IntRC_OSC_CLKOUTEN EQU H'0FFD' _ExtRC_OSC_RB4EN EQU H'0FFE' _ExtRC_OSC_CLKOUTEN EQU H'0FFF' LIST gputils-0.13.7/header/p18f86j50.inc0000644000175000017500000020340511156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J50 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J50 ; 2. LIST directive in the source file ; LIST P=PIC18F86J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f258.inc0000644000175000017500000014317311156521301013156 00000000000000 LIST ; P18F258.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F258 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F258 ; 2. LIST directive in the source file ; LIST P=PIC18F258 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.90 15 May 2001 Preliminary Release dzb ;0.99 29 June2001 Rev 1 dzb ;1.00 29 Oct.2001 Corrections & Additions cjh ;1.10 25 Jun 2002 Addec CFGS as EECON1 bit 6 name pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F258 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' ECCPR1H EQU H'0FBC' ECCPR1L EQU H'0FBB' ECCP1CON EQU H'0FBA' ECCP1DEL EQU H'0FB7' ECCPAS EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TXERRCNT EQU H'0F76' RXERRCNT EQU H'0F75' COMSTAT EQU H'0F74' CIOCON EQU H'0F73' BRGCON3 EQU H'0F72' BRGCON2 EQU H'0F71' BRGCON1 EQU H'0F70' CANCON EQU H'0F6F' CANSTAT EQU H'0F6E' RXB0D7 EQU H'0F6D' RXB0D6 EQU H'0F6C' RXB0D5 EQU H'0F6B' RXB0D4 EQU H'0F6A' RXB0D3 EQU H'0F69' RXB0D2 EQU H'0F68' RXB0D1 EQU H'0F67' RXB0D0 EQU H'0F66' RXB0DLC EQU H'0F65' RXB0EIDL EQU H'0F64' RXB0EIDH EQU H'0F63' RXB0SIDL EQU H'0F62' RXB0SIDH EQU H'0F61' RXB0CON EQU H'0F60' CANSTATRO1 EQU H'0F5E' RXB1D7 EQU H'0F5D' RXB1D6 EQU H'0F5C' RXB1D5 EQU H'0F5B' RXB1D4 EQU H'0F5A' RXB1D3 EQU H'0F59' RXB1D2 EQU H'0F58' RXB1D1 EQU H'0F57' RXB1D0 EQU H'0F56' RXB1DLC EQU H'0F55' RXB1EIDL EQU H'0F54' RXB1EIDH EQU H'0F53' RXB1SIDL EQU H'0F52' RXB1SIDH EQU H'0F51' RXB1CON EQU H'0F50' CANSTATRO2 EQU H'0F4E' TXB0D7 EQU H'0F4D' TXB0D6 EQU H'0F4C' TXB0D5 EQU H'0F4B' TXB0D4 EQU H'0F4A' TXB0D3 EQU H'0F49' TXB0D2 EQU H'0F48' TXB0D1 EQU H'0F47' TXB0D0 EQU H'0F46' TXB0DLC EQU H'0F45' TXB0EIDL EQU H'0F44' TXB0EIDH EQU H'0F43' TXB0SIDL EQU H'0F42' TXB0SIDH EQU H'0F41' TXB0CON EQU H'0F40' CANSTATRO3 EQU H'0F3E' TXB1D7 EQU H'0F3D' TXB1D6 EQU H'0F3C' TXB1D5 EQU H'0F3B' TXB1D4 EQU H'0F3A' TXB1D3 EQU H'0F39' TXB1D2 EQU H'0F38' TXB1D1 EQU H'0F37' TXB1D0 EQU H'0F36' TXB1DLC EQU H'0F35' TXB1EIDL EQU H'0F34' TXB1EIDH EQU H'0F33' TXB1SIDL EQU H'0F32' TXB1SIDH EQU H'0F31' TXB1CON EQU H'0F30' CANSTATRO4 EQU H'0F2E' TXB2D7 EQU H'0F2D' TXB2D6 EQU H'0F2C' TXB2D5 EQU H'0F2B' TXB2D4 EQU H'0F2A' TXB2D3 EQU H'0F29' TXB2D2 EQU H'0F28' TXB2D1 EQU H'0F27' TXB2D0 EQU H'0F26' TXB2DLC EQU H'0F25' TXB2EIDL EQU H'0F24' TXB2EIDH EQU H'0F23' TXB2SIDL EQU H'0F22' TXB2SIDH EQU H'0F21' TXB2CON EQU H'0F20' RXM1EIDL EQU H'0F1F' RXM1EIDH EQU H'0F1E' RXM1SIDL EQU H'0F1D' RXM1SIDH EQU H'0F1C' RXM0EIDL EQU H'0F1B' RXM0EIDH EQU H'0F1A' RXM0SIDL EQU H'0F19' RXM0SIDH EQU H'0F18' RXF5EIDL EQU H'0F17' RXF5EIDH EQU H'0F16' RXF5SIDL EQU H'0F15' RXF5SIDH EQU H'0F14' RXF4EIDL EQU H'0F13' RXF4EIDH EQU H'0F12' RXF4SIDL EQU H'0F11' RXF4SIDH EQU H'0F10' RXF3EIDL EQU H'0F0F' RXF3EIDH EQU H'0F0E' RXF3SIDL EQU H'0F0D' RXF3SIDH EQU H'0F0C' RXF2EIDL EQU H'0F0B' RXF2EIDH EQU H'0F0A' RXF2SIDL EQU H'0F09' RXF2SIDH EQU H'0F08' RXF1EIDL EQU H'0F07' RXF1EIDH EQU H'0F06' RXF1SIDL EQU H'0F05' RXF1SIDH EQU H'0F04' RXF0EIDL EQU H'0F03' RXF0EIDH EQU H'0F02' RXF0SIDL EQU H'0F01' RXF0SIDH EQU H'0F00' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' SP4 EQU H'0004' SP3 EQU H'0003' SP2 EQU H'0002' SP1 EQU H'0001' SP0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IVRST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ECCP1CON Bits ------------------------------------------------------ EPWM1M1 EQU H'0007' EPWM1M0 EQU H'0006' EDC2B1 EQU H'0005' EDC2B0 EQU H'0004' ECCP1M3 EQU H'0003' ECCP1M2 EQU H'0002' ECCP1M1 EQU H'0001' ECCP1M0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' ; For backward compatibility CVRR EQU H'0005' CVRSS EQU H'0004' ; For backward compatibility CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' ; For backward compatibility C2INV EQU H'0005' C1INV EQU H'0004' ; For backward compatibility CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3ECCP1 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' EEFS EQU H'0006' ; Backward compatibility only CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR3 Bits ---------------------------------------------------------- IRXIP EQU H'0007' WAKIP EQU H'0006' ERRIP EQU H'0005' TXB2IP EQU H'0004' TXB1IP EQU H'0003' TXB0IP EQU H'0002' RXB1IP EQU H'0001' RXB0IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- IRXIF EQU H'0007' WAKIF EQU H'0006' ERRIF EQU H'0005' TXB2IF EQU H'0004' TXB1IF EQU H'0003' TXB0IF EQU H'0002' RXB1IF EQU H'0001' RXB0IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- IRXIE EQU H'0007' WAKIE EQU H'0006' ERRIE EQU H'0005' TXB2IE EQU H'0004' TXB1IE EQU H'0003' TXB0IE EQU H'0002' RXB1IE EQU H'0001' RXB0IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' ECCP1IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' ECCP1IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' ECCP1IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- COMSTAT Bits --------------------------------------------------------- RX1OVFL EQU H'0007' RXB0OVFL EQU H'0007' RX2OVFL EQU H'0006' RXB1OVFL EQU H'0006' TXBO EQU H'0005' TXBP EQU H'0004' RXBP EQU H'0003' TXWARN EQU H'0002' RXWARN EQU H'0001' EWARN EQU H'0000' ;----- CIOCON Bits ----------------------------------------------------------- ENDRHI EQU H'0005' CANCAP EQU H'0004' ;----- BRGCON3 Bits ---------------------------------------------------------- WAKFIL EQU H'0006' SEG2PH2 EQU H'0002' SEG2PH1 EQU H'0001' SEG2PH0 EQU H'0000' ;----- BRGCON2 Bits ----------------------------------------------------------- SEG2PHTS EQU H'0007' SAM EQU H'0006' SEG1PH2 EQU H'0005' SEG1PH1 EQU H'0004' SEG1PH0 EQU H'0003' PRSEG2 EQU H'0002' PRSEG1 EQU H'0001' PRSEG0 EQU H'0000' ;----- BRGCON1 Bits ------------------------------------------------------------ SJW1 EQU H'0007' SJW0 EQU H'0006' BRP5 EQU H'0005' BRP4 EQU H'0004' BRP3 EQU H'0003' BRP2 EQU H'0002' BRP1 EQU H'0001' BRP0 EQU H'0000' ;----- CANCON Bits ------------------------------------------------------------- REQOP2 EQU H'0007' REQOP1 EQU H'0006' REQOP0 EQU H'0005' ABAT EQU H'0004' WIN2 EQU H'0003' WIN1 EQU H'0002' WIN0 EQU H'0001' ;----- CANSTAT Bits ----------------------------------------------------------- OPMODE2 EQU H'0007' OPMODE1 EQU H'0006' OPMODE0 EQU H'0005' ICODE2 EQU H'0003' ICODE1 EQU H'0002' ICODE0 EQU H'0001' ;----- RXBnCON Bits ----------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' RXB0DBEN EQU H'0002' FILHIT2 EQU H'0002' JTOFF EQU H'0001' FILHIT1 EQU H'0001' FILHIT0 EQU H'0000' ;----- TXBnCON Bits ---------------------------------------------------------- TXABT EQU H'0006' TXLARB EQU H'0005' TXERR EQU H'0004' TXREQ EQU H'0003' TXPRI1 EQU H'0001' TXPRI0 EQU H'0000' ;----- TXERRCNT Bits ---------------------------------------------------------- TEC7 EQU H'0007' TEC6 EQU H'0006' TEC5 EQU H'0005' TEC4 EQU H'0004' TEC3 EQU H'0003' TEC2 EQU H'0002' TEC1 EQU H'0001' TEC0 EQU H'0000' ;----- RXERRCNT Bits ---------------------------------------------------------- REC7 EQU H'0007' REC6 EQU H'0006' REC5 EQU H'0005' REC4 EQU H'0004' REC3 EQU H'0003' REC2 EQU H'0002' REC1 EQU H'0001' REC0 EQU H'0000' ;----- RXBnDLC and TXBnDLC Bits ----------------------------------------------- RXRTR EQU H'0006' TXRTR EQU H'0006' RESB1 EQU H'0005' RESB0 EQU H'0004' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DLC0 EQU H'0000' ;----- RXBnEIDL, RXFnEIDL, RXMnEIDL, and TXBnEIDL Bits ------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXBnEIDH, RXFnEIDH, RXMnEIDH, and TXBnEIDH Bits ------------------------- EID15 EQU H'0007' EID14 EQU H'0006' EID13 EQU H'0005' EID12 EQU H'0004' EID11 EQU H'0003' EID10 EQU H'0002' EID9 EQU H'0001' EID8 EQU H'0000' ;----- RXBnSIDL, RXFnSIDL, RXMnSIDL, and TXBnSIDL Bits ---------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' SRR EQU H'0004' EXID EQU H'0003' EXIDE EQU H'0003' EXIDEN EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXBnSIDH, RXFnSIDH, RXMnSIDH, and TXBnSIDH Bits ---------------------- SID10 EQU H'0007' SID9 EQU H'0006' SID8 EQU H'0005' SID7 EQU H'0004' SID6 EQU H'0003' SID5 EQU H'0002' SID4 EQU H'0001' SID3 EQU H'0001' ;----- RXB0D7 Bits ---------------------------------------------------------- RB0D77 EQU H'0007' RB0D76 EQU H'0006' RB0D75 EQU H'0005' RB0D74 EQU H'0004' RB0D73 EQU H'0003' RB0D72 EQU H'0002' RB0D71 EQU H'0001' RB0D70 EQU H'0000' ;----- RXB0D6 Bits ---------------------------------------------------------- RB0D67 EQU H'0007' RB0D66 EQU H'0006' RB0D65 EQU H'0005' RB0D64 EQU H'0004' RB0D63 EQU H'0003' RB0D62 EQU H'0002' RB0D61 EQU H'0001' RB0D60 EQU H'0000' ;----- RXB0D5 Bits ---------------------------------------------------------- RB0D57 EQU H'0007' RB0D56 EQU H'0006' RB0D55 EQU H'0005' RB0D54 EQU H'0004' RB0D53 EQU H'0003' RB0D52 EQU H'0002' RB0D51 EQU H'0001' RB0D50 EQU H'0000' ;----- RXB0D4 Bits ---------------------------------------------------------- RB0D47 EQU H'0007' RB0D46 EQU H'0006' RB0D45 EQU H'0005' RB0D44 EQU H'0004' RB0D43 EQU H'0003' RB0D42 EQU H'0002' RB0D41 EQU H'0001' RB0D40 EQU H'0000' ;----- RXB0D3 Bits ---------------------------------------------------------- RB0D37 EQU H'0007' RB0D36 EQU H'0006' RB0D35 EQU H'0005' RB0D34 EQU H'0004' RB0D33 EQU H'0003' RB0D32 EQU H'0002' RB0D31 EQU H'0001' RB0D30 EQU H'0000' ;----- RXB0D2 Bits ---------------------------------------------------------- RB0D27 EQU H'0007' RB0D26 EQU H'0006' RB0D25 EQU H'0005' RB0D24 EQU H'0004' RB0D23 EQU H'0003' RB0D22 EQU H'0002' RB0D21 EQU H'0001' RB0D20 EQU H'0000' ;----- RXB0D1 Bits ---------------------------------------------------------- RB0D17 EQU H'0007' RB0D16 EQU H'0006' RB0D15 EQU H'0005' RB0D14 EQU H'0004' RB0D13 EQU H'0003' RB0D12 EQU H'0002' RB0D11 EQU H'0001' RB0D10 EQU H'0000' ;----- RXB0D0 Bits ---------------------------------------------------------- RB0D07 EQU H'0007' RB0D06 EQU H'0006' RB0D05 EQU H'0005' RB0D04 EQU H'0004' RB0D03 EQU H'0003' RB0D02 EQU H'0002' RB0D01 EQU H'0001' RB0D00 EQU H'0000' ;----- RXB1D7 Bits ---------------------------------------------------------- RXB1D77 EQU H'0007' RXB1D76 EQU H'0006' RXB1D75 EQU H'0005' RXB1D74 EQU H'0004' RXB1D73 EQU H'0003' RXB1D72 EQU H'0002' RXB1D71 EQU H'0001' RXB1D70 EQU H'0000' ;----- RXB1D6 Bits ---------------------------------------------------------- RXB1D67 EQU H'0007' RXB1D66 EQU H'0006' RXB1D65 EQU H'0005' RXB1D64 EQU H'0004' RXB1D63 EQU H'0003' RXB1D62 EQU H'0002' RXB1D61 EQU H'0001' RXB1D60 EQU H'0000' ;----- RXB1D5 Bits ---------------------------------------------------------- RXB1D57 EQU H'0007' RXB1D56 EQU H'0006' RXB1D55 EQU H'0005' RXB1D54 EQU H'0004' RXB1D53 EQU H'0003' RXB1D52 EQU H'0002' RXB1D51 EQU H'0001' RXB1D50 EQU H'0000' ;----- RXB1D4 Bits ---------------------------------------------------------- RXB1D47 EQU H'0007' RXB1D46 EQU H'0006' RXB1D45 EQU H'0005' RXB1D44 EQU H'0004' RXB1D43 EQU H'0003' RXB1D42 EQU H'0002' RXB1D41 EQU H'0001' RXB1D40 EQU H'0000' ;----- RXB1D3 Bits ---------------------------------------------------------- RXB1D37 EQU H'0007' RXB1D36 EQU H'0006' RXB1D35 EQU H'0005' RXB1D34 EQU H'0004' RXB1D33 EQU H'0003' RXB1D32 EQU H'0002' RXB1D31 EQU H'0001' RXB1D30 EQU H'0000' ;----- RXB1D2 Bits ---------------------------------------------------------- RXB1D27 EQU H'0007' RXB1D26 EQU H'0006' RXB1D25 EQU H'0005' RXB1D24 EQU H'0004' RXB1D23 EQU H'0003' RXB1D22 EQU H'0002' RXB1D21 EQU H'0001' RXB1D20 EQU H'0000' ;----- RXB1D1 Bits ---------------------------------------------------------- RXB1D17 EQU H'0007' RXB1D16 EQU H'0006' RXB1D15 EQU H'0005' RXB1D14 EQU H'0004' RXB1D13 EQU H'0003' RXB1D12 EQU H'0002' RXB1D11 EQU H'0001' RXB1D10 EQU H'0000' ;----- RXB1D0 Bits ---------------------------------------------------------- RXB1D07 EQU H'0007' RXB1D06 EQU H'0006' RXB1D05 EQU H'0005' RXB1D04 EQU H'0004' RXB1D03 EQU H'0003' RXB1D02 EQU H'0002' RXB1D01 EQU H'0001' RXB1D00 EQU H'0000' ;----- TXB2D7 Bits ---------------------------------------------------------- TXB2D77 EQU H'0007' TXB2D76 EQU H'0006' TXB2D75 EQU H'0005' TXB2D74 EQU H'0004' TXB2D73 EQU H'0003' TXB2D72 EQU H'0002' TXB2D71 EQU H'0001' TXB2D70 EQU H'0000' ;----- TXB2D6 Bits ---------------------------------------------------------- TXB2D67 EQU H'0007' TXB2D66 EQU H'0006' TXB2D65 EQU H'0005' TXB2D64 EQU H'0004' TXB2D63 EQU H'0003' TXB2D62 EQU H'0002' TXB2D61 EQU H'0001' TXB2D60 EQU H'0000' ;----- TXB2D5 Bits ---------------------------------------------------------- TXB2D57 EQU H'0007' TXB2D56 EQU H'0006' TXB2D55 EQU H'0005' TXB2D54 EQU H'0004' TXB2D53 EQU H'0003' TXB2D52 EQU H'0002' TXB2D51 EQU H'0001' TXB2D50 EQU H'0000' ;----- TXB2D4 Bits ---------------------------------------------------------- TXB2D47 EQU H'0007' TXB2D46 EQU H'0006' TXB2D45 EQU H'0005' TXB2D44 EQU H'0004' TXB2D43 EQU H'0003' TXB2D42 EQU H'0002' TXB2D41 EQU H'0001' TXB2D40 EQU H'0000' ;----- TXB2D3 Bits ---------------------------------------------------------- TXB2D37 EQU H'0007' TXB2D36 EQU H'0006' TXB2D35 EQU H'0005' TXB2D34 EQU H'0004' TXB2D33 EQU H'0003' TXB2D32 EQU H'0002' TXB2D31 EQU H'0001' TXB2D30 EQU H'0000' ;----- TXB2D2 Bits ---------------------------------------------------------- TXB2D27 EQU H'0007' TXB2D26 EQU H'0006' TXB2D25 EQU H'0005' TXB2D24 EQU H'0004' TXB2D23 EQU H'0003' TXB2D22 EQU H'0002' TXB2D21 EQU H'0001' TXB2D20 EQU H'0000' ;----- TXB2D1 Bits ---------------------------------------------------------- TXB2D17 EQU H'0007' TXB2D16 EQU H'0006' TXB2D15 EQU H'0005' TXB2D14 EQU H'0004' TXB2D13 EQU H'0003' TXB2D12 EQU H'0002' TXB2D11 EQU H'0001' TXB2D10 EQU H'0000' ;----- TXB2D0 Bits ---------------------------------------------------------- TXB2D07 EQU H'0007' TXB2D06 EQU H'0006' TXB2D05 EQU H'0005' TXB2D04 EQU H'0004' TXB2D03 EQU H'0003' TXB2D02 EQU H'0002' TXB2D01 EQU H'0001' TXB2D00 EQU H'0000' ;----- TXB1D7 Bits ---------------------------------------------------------- TXB1D77 EQU H'0007' TXB1D76 EQU H'0006' TXB1D75 EQU H'0005' TXB1D74 EQU H'0004' TXB1D73 EQU H'0003' TXB1D72 EQU H'0002' TXB1D71 EQU H'0001' TXB1D70 EQU H'0000' ;----- TXB1D6 Bits ---------------------------------------------------------- TXB1D67 EQU H'0007' TXB1D66 EQU H'0006' TXB1D65 EQU H'0005' TXB1D64 EQU H'0004' TXB1D63 EQU H'0003' TXB1D62 EQU H'0002' TXB1D61 EQU H'0001' TXB1D60 EQU H'0000' ;----- TXB1D5 Bits ---------------------------------------------------------- TXB1D57 EQU H'0007' TXB1D56 EQU H'0006' TXB1D55 EQU H'0005' TXB1D54 EQU H'0004' TXB1D53 EQU H'0003' TXB1D52 EQU H'0002' TXB1D51 EQU H'0001' TXB1D50 EQU H'0000' ;----- TXB1D4 Bits ---------------------------------------------------------- TXB1D47 EQU H'0007' TXB1D46 EQU H'0006' TXB1D45 EQU H'0005' TXB1D44 EQU H'0004' TXB1D43 EQU H'0003' TXB1D42 EQU H'0002' TXB1D41 EQU H'0001' TXB1D40 EQU H'0000' ;----- TXB1D3 Bits ---------------------------------------------------------- TXB1D37 EQU H'0007' TXB1D36 EQU H'0006' TXB1D35 EQU H'0005' TXB1D34 EQU H'0004' TXB1D33 EQU H'0003' TXB1D32 EQU H'0002' TXB1D31 EQU H'0001' TXB1D30 EQU H'0000' ;----- TXB1D2 Bits ---------------------------------------------------------- TXB1D27 EQU H'0007' TXB1D26 EQU H'0006' TXB1D25 EQU H'0005' TXB1D24 EQU H'0004' TBB1D23 EQU H'0003' TXB1D22 EQU H'0002' TXB1D21 EQU H'0001' TXB1D20 EQU H'0000' ;----- TXB1D1 Bits ---------------------------------------------------------- TXB1D17 EQU H'0007' TXB1D16 EQU H'0006' TXB1D15 EQU H'0005' TXB1D14 EQU H'0004' TXB1D13 EQU H'0003' TXB1D12 EQU H'0002' TXB1D11 EQU H'0001' TXB1D10 EQU H'0000' ;----- TXB1D0 Bits ---------------------------------------------------------- TXB1D07 EQU H'0007' TXB1D06 EQU H'0006' TXB1D05 EQU H'0005' TXB1D04 EQU H'0004' TXB1D03 EQU H'0003' TXB1D02 EQU H'0002' TXB1D01 EQU H'0001' TXB1D00 EQU H'0000' ;----- TXB0D7 Bits ---------------------------------------------------------- TXB0D77 EQU H'0007' TXB0D76 EQU H'0006' TXB0D75 EQU H'0005' TXB0D74 EQU H'0004' TXB0D73 EQU H'0003' TXB0D72 EQU H'0002' TXB0D71 EQU H'0001' TXB0D70 EQU H'0000' ;----- TXB0D6 Bits ---------------------------------------------------------- TXB0D67 EQU H'0007' TXB0D66 EQU H'0006' TXB0D65 EQU H'0005' TXB0D64 EQU H'0004' TXB0D63 EQU H'0003' TXB0D62 EQU H'0002' TXB0D61 EQU H'0001' TXB0D60 EQU H'0000' ;----- TXB0D5 Bits ---------------------------------------------------------- TXB0D57 EQU H'0007' TXB0D56 EQU H'0006' TXB0D55 EQU H'0005' TXB0D54 EQU H'0004' TXB0D53 EQU H'0003' TXB0D52 EQU H'0002' TXB0D51 EQU H'0001' TXB0D50 EQU H'0000' ;----- TXB0D4 Bits ---------------------------------------------------------- TXB0D47 EQU H'0007' TXB0D46 EQU H'0006' TXB0D45 EQU H'0005' TXB0D44 EQU H'0004' TXB0D43 EQU H'0003' TXB0D42 EQU H'0002' TXB0D41 EQU H'0001' TXB0D40 EQU H'0000' ;----- TXB0D3 Bits ---------------------------------------------------------- TXB0D37 EQU H'0007' TXB0D36 EQU H'0006' TXB0D35 EQU H'0005' TXB0D34 EQU H'0004' TXB0D33 EQU H'0003' TXB0D32 EQU H'0002' TXB0D31 EQU H'0001' TXB0D30 EQU H'0000' ;----- TXB0D2 Bits ---------------------------------------------------------- TXB0D27 EQU H'0007' TXB0D26 EQU H'0006' TXB0D25 EQU H'0005' TXB0D24 EQU H'0004' TXB0D23 EQU H'0003' TXB0D22 EQU H'0002' TXB0D21 EQU H'0001' TXB0D20 EQU H'0000' ;----- TXB0D1 Bits ---------------------------------------------------------- TXB0D17 EQU H'0007' TXB0D16 EQU H'0006' TXB0D15 EQU H'0005' TXB0D14 EQU H'0004' TXB0D13 EQU H'0003' TXB0D12 EQU H'0002' TXB0D11 EQU H'0001' TXB0D10 EQU H'0000' ;----- TXB0D0 Bits ---------------------------------------------------------- TXB0D07 EQU H'0007' TXB0D06 EQU H'0006' TXB0D05 EQU H'0005' TXB0D04 EQU H'0004' TXB0D03 EQU H'0003' TXB0D02 EQU H'0002' TXB0D01 EQU H'0001' TXB0D00 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 NOT_SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 CANTX EQU 2 RB3 EQU 3 CANRX EQU 3 RB4 EQU 4 RB5 EQU 5 PGM EQU 5 RB6 EQU 6 PGC EQU 6 RB7 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'600'-H'EFF' __BADRAM H'FD4',H'FC0',H'FB4'-H'FB9',H'FB0', H'FAA',H'F95'-H'F9C' __BADRAM H'F8C'-H'F91',H'F83'-H'F88', H'F79'-H'F7F',H'F77' __BADRAM H'F5F',H'F4F',H'F3F',H'F2F' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000Ah ; CONFIG6H = Configuration Byte 6H 30000Bh ; CONFIG7L = Configuration Byte 7L 30000Ch ; CONFIG7H = Configuration Byte 7H 30000Dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_25_2L EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled _LVP_ON_4L EQU H'FF' ; Enableda _LVP_OFF_4L EQU H'FB' ; Disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;Configuration Byte 6H Options _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as _BOR_ON_2L). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_25_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16lf726.inc0000644000175000017500000004773211156521301013334 00000000000000 LIST ; P16LF726.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16LF726 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16LF726 ; 2. LIST directive in the source file ; LIST P=PIC16LF726 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/25/07 Initial template ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF726 MESSG "Processor-header file mismatch. Verify selected processor." #define __16LF726 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'08' __BADRAM H'88' __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'187'-H'189', H'18D'-H'18F' LIST gputils-0.13.7/header/p18f6627.inc0000644000175000017500000017661511156521301013253 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6627 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6627 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6627 ; 2. LIST directive in the source file ; LIST P=PIC18F6627 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6627 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f44j10.inc0000644000175000017500000010214411156521301013373 00000000000000 LIST ;========================================================================== ; MPASM PIC18F44J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F44J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F44J10 ; 2. LIST directive in the source file ; LIST P=PIC18F44J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F44J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' SSP2CON2 EQU H'0F85' SSP2CON1 EQU H'0F86' SSP2STAT EQU H'0F87' SSP2ADD EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' SSP2BUF EQU H'0F8E' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' SPBRGH EQU H'0FB0' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' VREFM EQU H'0002' VREFP EQU H'0003' SS1 EQU H'0005' CVREF EQU H'0002' C2OUT_PORTA EQU H'0005' NOT_SS1 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0006' PGD EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' T0CKI EQU H'0005' FLT0 EQU H'0000' C1OUT_PORTB EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' SCL EQU H'0003' SDA EQU H'0004' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' SCK2 EQU H'0000' SDI2 EQU H'0001' SDO2 EQU H'0002' SS2 EQU H'0003' NOT_SS2 EQU H'0003' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' T0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F7F' __BADRAM H'0F8F'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB1'-H'0FB3' __BADRAM H'0FB9' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; CCP2 MUX bit: ; CCP2MX = ALTERNATE CCP2 is multiplexed with RB3 ; CCP2MX = DEFAULT CCP2 is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f4585.inc0000644000175000017500000042264511156521301013251 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4585 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4585 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4585 ; 2. LIST directive in the source file ; LIST P=PIC18F4585 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4585 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' ECCP1CON EQU H'0FBA' ECCPR1 EQU H'0FBB' ECCPR1L EQU H'0FBB' ECCPR1H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXBODBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXB0DBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF_PORTA EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' C1INB EQU H'0000' C1INA EQU H'0001' C2INB EQU H'0002' C2INA EQU H'0003' P1A EQU H'0004' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ECCP1 EQU H'0004' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- ECCP1IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- ECCP1IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- ECCP1IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF_CVRCON EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- ECCP1M0 EQU H'0000' ECCP1M1 EQU H'0001' ECCP1M2 EQU H'0002' ECCP1M3 EQU H'0003' EDC1B0 EQU H'0004' EDC1B1 EQU H'0005' EPWM1M0 EQU H'0006' EPWM1M1 EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f85j11.inc0000644000175000017500000013061711156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F85J11 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F85J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F85J11 ; 2. LIST directive in the source file ; LIST P=PIC18F85J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F85J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' TX2 EQU H'0001' RX2 EQU H'0002' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F6B'-H'0F7D' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB6'-H'0FBF' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode, 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode, 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode, 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 7FF8h ; CONFIG1H 7FF9h ; CONFIG2L 7FFAh ; CONFIG2H 7FFBh ; CONFIG3L 7FFCh ; CONFIG3H 7FFDh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'7FF8' _CONFIG1H EQU H'7FF9' _CONFIG2L EQU H'7FFA' _CONFIG2H EQU H'7FFB' _CONFIG3L EQU H'7FFC' _CONFIG3H EQU H'7FFD' ;----- CONFIG1L Options -------------------------------------------------- _DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled _STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled _WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit) _WDTEN_ON_1L EQU H'FF' ; WDT enabled ;----- CONFIG1H Options -------------------------------------------------- _CP0_ON_1H EQU H'FB' ; Program memory is code-protected _CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected ;----- CONFIG2L Options -------------------------------------------------- _IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled _FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled _FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00 _FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 _FOSC_HS_2L EQU H'FC' ; HS oscillator _FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control _FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2 _FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2 ;----- CONFIG2H Options -------------------------------------------------- _WDTPS_1_2H EQU H'F0' ; 1:1 _WDTPS_2_2H EQU H'F1' ; 1:2 _WDTPS_4_2H EQU H'F2' ; 1:4 _WDTPS_8_2H EQU H'F3' ; 1:8 _WDTPS_16_2H EQU H'F4' ; 1:16 _WDTPS_32_2H EQU H'F5' ; 1:32 _WDTPS_64_2H EQU H'F6' ; 1:64 _WDTPS_128_2H EQU H'F7' ; 1:128 _WDTPS_256_2H EQU H'F8' ; 1:256 _WDTPS_512_2H EQU H'F9' ; 1:512 _WDTPS_1024_2H EQU H'FA' ; 1:1024 _WDTPS_2048_2H EQU H'FB' ; 1:2048 _WDTPS_4096_2H EQU H'FC' ; 1:4096 _WDTPS_8192_2H EQU H'FD' ; 1:8192 _WDTPS_16384_2H EQU H'FE' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _WAIT_ON_3L EQU H'7F' ; Wait states for operations on external memory bus enabled _WAIT_OFF_3L EQU H'FF' ; Wait states for operations on external memory bus disabled _BW_8_3L EQU H'BF' ; 8-bit external bus mode _BW_16_3L EQU H'FF' ; 16-bit external bus mode _MODE_XM20_3L EQU H'CF' ; Extended Microcontroller mode, 20-bit Address mode _MODE_XM16_3L EQU H'DF' ; Extended Microcontroller mode, 16-bit Address mode _MODE_XM12_3L EQU H'EF' ; Extended Microcontroller mode, 12-bit Address mode _MODE_MM_3L EQU H'FF' ; Microcontroller mode - External bus disabled _EASHFT_OFF_3L EQU H'F7' ; Address shifting disabled, address on external bus reflects the PC value _EASHFT_ON_3L EQU H'FF' ; Address shifting enabled, address on external bus is offset to start at 000000h ;----- CONFIG3H Options -------------------------------------------------- _CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode _CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1 _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f45j50.inc0000644000175000017500000017640011156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F45J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F45J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F45J50 ; 2. LIST directive in the source file ; LIST P=PIC18F45J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F45J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p17cr43.inc0000644000175000017500000002507511156313161013247 00000000000000 LIST ; P17CR43.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17CR43 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17CR43 ; 2. LIST directive in the source file ; LIST P=PIC17CR43 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 03/14/97 Corrected configuration bits value for protected ; microcontroller mode ;1.02 07/15/96 Corrected MAXRAM ;1.01 06/28/96 Corrected MAXRAM, BADRAM, and registers in upper banks ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17CR43 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCREG EQU H'0014' TXSTA EQU H'0015' TXREG EQU H'0016' SPBRG EQU H'0017' PRODL EQU H'0018' PRODH EQU H'0019' DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' PIE EQU H'0117' TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' NOT_PD EQU H'0002' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIE Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' RCIE EQU H'0000' ;----- PIR Bits ----------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' RCIF EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' T0CKI EQU H'0001' INT EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' T0PS2 EQU H'0003' PS2 EQU H'0003' T0PS1 EQU H'0002' PS1 EQU H'0002' T0PS0 EQU H'0001' PS0 EQU H'0001' ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3FF' __BADRAM H'118'-H'11F', H'218'-H'2FF', H'318'-H'3FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p16f819.inc0000644000175000017500000002732511156313161013162 00000000000000 LIST ; P16F819.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F819 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F819 ; 2. LIST directive in the source file ; LIST P=PIC16F819 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 06/15/02 Initial Release ;1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F819 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' IOFS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'18'-H'1D' __BADRAM H'87'-H'89', H'91', H'95'-H'9D' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP1_RB2 EQU H'3FFF' _CCP1_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_ENABLE_OFF EQU H'3FFF' _WRT_ENABLE_512 EQU H'3DFF' _WRT_ENABLE_1024 EQU H'3BFF' _WRT_ENABLE_1536 EQU H'39FF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' LIST gputils-0.13.7/header/p18f8720.inc0000644000175000017500000011613711156313161013243 00000000000000 LIST ; P18F8720.INC Standard Header File, Version .1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F8720 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F8720 ; 2. LIST directive in the source file ; LIST P=PIC18F8720 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ; 1.09 10/12/04 Added SPBRG, TXREG, TXSTA and RCSTA src ; 1.08 09/26/02 Include both names SWDTE and SWDTEN pas ; 1.07 11/16/2001 Changed CVREF_CVRCON => CVRSS, ADEN => ADDEN pas ; 1.06 10/23/01 Corrected CONFIG bits/registers, LVDCON bits tr/pas ; 1.05 10/08/01 Corrected names of T2CON and T4CON bits ; (TOUTPS3 => T2OUTPS3 and T4OUTPS3, etc.) pas ; 1.04 10/03/01 Changed T0CON bit 3 name from T0PS3 to PSA. pas ; 1.03 10/01/01 Added definitions of the CCP4, CCP5, TMR4, and ; USART2 registers (0x0F6B to 0x0F78); corrected names ; of INTCON3 bits (i.e., INT2P => INT2IP). pas ; 1.02 09/18/01 Some bits have identical names in the data sheet; ; for instance, CCP2 in PORTB and CCP2 in PORTC. ; The assembler does not allow multiple definitions of ; the same name, however. So I postfixed these names ; with the name of the register to make them ; unique. (Now we have CCP2_PORTB and CCP2_PORTC). pas ; 1.01 09/14/01 Preliminary release tr ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8720 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution #define DDRF TRISF ; PIC17Cxxx SFR substitution #define DDRG TRISG ; PIC17Cxxx SFR substitution #define DDRH TRISH ; PIC17Cxxx SFR substitution #define DDRJ TRISJ ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' CCPR3H EQU H'0FB9' CCPR3L EQU H'0FB8' CCP3CON EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' RCREG1 EQU H'0FAE' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' EEADRH EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' TRISJ EQU H'0F9A' TRISH EQU H'0F99' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATJ EQU H'0F91' LATH EQU H'0F90' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTJ EQU H'0F88' PORTH EQU H'0F87' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TMR4 EQU H'0F78' PR4 EQU H'0F77' T4CON EQU H'0F76' CCPR4H EQU H'0F75' CCPR4L EQU H'0F74' CCP4CON EQU H'0F73' CCPR5H EQU H'0F72' CCPR5L EQU H'0F71' CCP5CON EQU H'0F70' SPBRG2 EQU H'0F6F' RCREG2 EQU H'0F6E' TXREG2 EQU H'0F6D' TXSTA2 EQU H'0F6C' RCSTA2 EQU H'0F6B' ;----- STKPTR Bits -------------------------------------------------------- STKOVF EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' INTEDG3 EQU H'0003' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF INT3P EQU H'0001' RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT3IE EQU H'0005' INT2IE EQU H'0004' INT1IE EQU H'0003' INT3IF EQU H'0002' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- T2OUTPS3 EQU H'0006' T2OUTPS2 EQU H'0005' T2OUTPS1 EQU H'0004' T2OUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DCCP1X EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DCCP1Y EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DCCP2X EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCP2Y EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- DCCP3X EQU H'0005' DCCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- CCP4CON Bits ------------------------------------------------------- DCCP4X EQU H'0005' DCCP4Y EQU H'0004' CCP4M3 EQU H'0003' CCP4M2 EQU H'0002' CCP4M1 EQU H'0001' CCP4M0 EQU H'0000' ;----- CCP5CON Bits ------------------------------------------------------- DCCP5X EQU H'0005' DCCP5Y EQU H'0004' CCP5M3 EQU H'0003' CCP5M2 EQU H'0002' CCP5M1 EQU H'0001' CCP5M0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVRSS EQU H'0004' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT_CMCON EQU H'0007' C1OUT_CMCON EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- T4CON Bits --------------------------------------------------------- T4OUTPS3 EQU H'0006' T4OUTPS2 EQU H'0005' T4OUTPS1 EQU H'0004' T4OUTPS0 EQU H'0003' TMR4ON EQU H'0002' T4CKPS1 EQU H'0001' T4CKPS0 EQU H'0000' ;----- TXSTA, TXSTA1 and TXSTA2 Bits -------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA, RCSTA1 and RCSTA2 Bits -------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR3 Bits ---------------------------------------------------------- RC2IP EQU H'0005' TX2IP EQU H'0004' TMR4IP EQU H'0003' CCP5IP EQU H'0002' CCP4IP EQU H'0001' CCP3IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- RC2IF EQU H'0005' TX2IF EQU H'0004' TMR4IF EQU H'0003' CCP5IF EQU H'0002' CCP4IF EQU H'0001' CCP3IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- RC2IE EQU H'0005' TX2IE EQU H'0004' TMR4IE EQU H'0003' CCP5IE EQU H'0002' CCP4IE EQU H'0001' CCP3IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' RC1IP EQU H'0005' TX1IP EQU H'0004' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' RC1IF EQU H'0005' TX1IF EQU H'0004' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' RC1IE EQU H'0005' TX1IE EQU H'0004' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- MEMCON Bits -------------------------------------------------------- EBDIS EQU H'0007' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 INT3 EQU 3 RB4 EQU 4 KBI0 EQU 4 RB5 EQU 5 KBI1 EQU 5 PGM EQU 5 RB6 EQU 6 KBI2 EQU 6 PGC EQU 6 RB7 EQU 7 KBI3 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T13CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 AD00 EQU 0 RD1 EQU 1 PSP1 EQU 1 AD01 EQU 1 RD2 EQU 2 PSP2 EQU 2 AD02 EQU 2 RD3 EQU 3 PSP3 EQU 3 AD03 EQU 3 RD4 EQU 4 PSP4 EQU 4 AD04 EQU 4 RD5 EQU 5 PSP5 EQU 5 AD05 EQU 5 RD6 EQU 6 PSP6 EQU 6 AD06 EQU 6 RD7 EQU 7 PSP7 EQU 7 AD07 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 AD08 EQU 0 RE1 EQU 1 WR EQU 1 AD09 EQU 1 RE2 EQU 2 CS EQU 2 AD10 EQU 2 RE3 EQU 3 AD11 EQU 3 RE4 EQU 4 AD12 EQU 4 RE5 EQU 5 AD13 EQU 5 RE6 EQU 6 AD14 EQU 6 RE7 EQU 7 AD15 EQU 7 CCP2C EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 C2OUT EQU 1 RF2 EQU 2 AN7 EQU 2 C1OUT EQU 2 RF3 EQU 3 AN8 EQU 3 RF4 EQU 4 AN9 EQU 4 RF5 EQU 5 AN10 EQU 5 CVREF_PORTF EQU 5 RF6 EQU 6 AN11 EQU 6 RF7 EQU 7 SS EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 CCP3 EQU 0 RG1 EQU 1 TX2 EQU 1 CK2 EQU 1 RG2 EQU 2 RX2 EQU 2 DT2 EQU 2 RG3 EQU 3 CCP4 EQU 3 RG4 EQU 4 CCP5 EQU 4 ;----- PORTH ------------------------------------------------------------------ RH0 EQU 0 AD16 EQU 0 RH1 EQU 1 AD17 EQU 1 RH2 EQU 2 AD18 EQU 2 RH3 EQU 3 AD19 EQU 3 RH4 EQU 4 AD12 EQU 4 RH5 EQU 5 AD13 EQU 5 RH6 EQU 6 AD14 EQU 6 RH7 EQU 7 AD15 EQU 7 ;----- PORTJ ------------------------------------------------------------------ RJ0 EQU 0 ALE EQU 0 RJ1 EQU 1 OE EQU 1 RJ2 EQU 2 WRL EQU 2 RJ3 EQU 3 WRH EQU 3 RJ4 EQU 4 BA0 EQU 4 RJ5 EQU 5 RJ6 EQU 6 LB EQU 6 RJ7 EQU 7 UB EQU 7 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'F00'-H'F6A' __BADRAM H'F79'-H'F7F' __BADRAM H'F9B',H'FB6',H'FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Processor Mode Selection: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait: ; WAIT = ON Enabled ; WAIT = OFF Disabled ; ; CCP2 MUX: ; CCP2MUX = OFF Disabled ; CCP2MUX = ON Enabled ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Code Protection Block 4: ; CP4 = ON Enabled ; CP4 = OFF Disabled ; ; Code Protection Block 5: ; CP5 = ON Enabled ; CP5 = OFF Disabled ; ; Code Protection Block 6: ; CP6 = ON Enabled ; CP6 = OFF Disabled ; ; Code Protection Block 7: ; CP7 = ON Enabled ; CP7 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Write Protection Block 4: ; WRT4 = ON Enabled ; WRT4 = OFF Disabled ; ; Write Protection Block 5: ; WRT5 = ON Enabled ; WRT5 = OFF Disabled ; ; Write Protection Block 6: ; WRT6 = ON Enabled ; WRT6 = OFF Disabled ; ; Write Protection Block 7: ; WRT7 = ON Enabled ; WRT7 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Table Read Protection Block 4: ; EBTR4 = ON Enabled ; EBTR4 = OFF Disabled ; ; Table Read Protection Block 5: ; EBTR5 = ON Enabled ; EBTR5 = OFF Disabled ; ; Table Read Protection Block 6: ; EBTR6 = ON Enabled ; EBTR6 = OFF Disabled ; ; Table Read Protection Block 7: ; EBTR7 = ON Enabled ; EBTR7 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3L Options _MC_MODE_3L EQU H'FF' ; Processor Mode Select bits _MP_MODE_3L EQU H'FE' _MPB_MODE_3L EQU H'FD' _XMC_MODE_3L EQU H'FC' _WAIT_ON_3L EQU H'7F' ; External Bus Data Wait Enable _WAIT_OFF_3L EQU H'FF' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' _CP4_ON_5L EQU H'EF' _CP4_OFF_5L EQU H'FF' _CP5_ON_5L EQU H'DF' _CP5_OFF_5L EQU H'FF' _CP6_ON_5L EQU H'BF' _CP6_OFF_5L EQU H'FF' _CP7_ON_5L EQU H'7F' _CP7_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' _WRT4_ON_6L EQU H'EF' _WRT4_OFF_6L EQU H'FF' _WRT5_ON_6L EQU H'DF' _WRT5_OFF_6L EQU H'FF' _WRT6_ON_6L EQU H'BF' _WRT6_OFF_6L EQU H'FF' _WRT7_ON_6L EQU H'7F' _WRT7_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' _EBTR4_ON_7L EQU H'EF' _EBTR4_OFF_7L EQU H'FF' _EBTR5_ON_7L EQU H'DF' _EBTR5_OFF_7L EQU H'FF' _EBTR6_ON_7L EQU H'BF' _EBTR6_OFF_7L EQU H'FF' _EBTR7_ON_7L EQU H'7F' _EBTR7_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3L ; __CONFIG _CONFIG3L, _WAIT_OFF_3L & _MC_MODE_3L ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L & _CP4_OFF_5L & _CP5_OFF_5L & _CP6_OFF_5L & _CP7_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L & _WRT4_OFF_6L & _WRT5_OFF_6L & _WRT6_OFF_6L & _WRT7_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L & _EBTR4_OFF_7L & _EBTR5_OFF_7L & _EBTR6_OFF_7L & _EBTR7_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p16f685.inc0000644000175000017500000004502311156521301013153 00000000000000 LIST ; P16F685.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F685 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F685 ; 2. LIST directive in the source file ; LIST P=PIC16F685 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 10/12/04 Original ;2.00 04/21/05 Modified file to match released datasheet ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F685 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' PWM1CON EQU H'001C' ECCPAS EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' WDTCON EQU H'0097' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDAT EQU H'010C' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' WPUB EQU H'0115' IOCB EQU H'0116' VRCON EQU H'0118' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' ANSEL EQU H'011E' ANSELH EQU H'011F' EECON1 EQU H'018C' EECON2 EQU H'018D' PSTRCON EQU H'019D' SRCON EQU H'019E' ;----- BANK 0 REGISTER DEFINITIONS ---------------------------------------- ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RABIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RABIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0002' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- BANK 1 REGISTER DEFINITIONS ---------------------------------------- ;----- OPTION Bits -------------------------------------------------------- NOT_RABPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISA Bits -------------------------------------------------------- TRISA5 EQU H'0005' TRISA4 EQU H'0004' TRISA3 EQU H'0003' TRISA2 EQU H'0002' TRISA1 EQU H'0001' TRISA0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TRISB7 EQU H'0007' TRISB6 EQU H'0006' TRISB5 EQU H'0005' TRISB4 EQU H'0004' ;----- TRISC Bits -------------------------------------------------------- TRISC7 EQU H'0007' TRISC6 EQU H'0006' TRISC5 EQU H'0005' TRISC4 EQU H'0004' TRISC3 EQU H'0003' TRISC2 EQU H'0002' TRISC1 EQU H'0001' TRISC0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0002' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- BANK 2 REGISTER DEFINITIONS ---------------------------------------- ;----- WPUB Bits ---------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' ;----- IOCB Bits --------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- VRCON Bits --------------------------------------------------------- C1VREN EQU H'0007' C2VREN EQU H'0006' VRR EQU H'0005' VP6EN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------- MC1OUT EQU H'0007' MC2OUT EQU H'0006' T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ANSELH Bits --------------------------------------------------------- ANS11 EQU H'0003' ANS10 EQU H'0002' ANS9 EQU H'0001' ANS8 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- BANK 3 REGISTER DEFINITIONS ---------------------------------------- ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- PSTRCON Bits -------------------------------------------------------- STRSYNC EQU H'0004' STRD EQU H'0003' STRC EQU H'0002' STRB EQU H'0001' STRA EQU H'0000' ;----- SRCON Bits ---------------------------------------------------------- SR1 EQU H'0007' SR0 EQU H'0006' C1SEN EQU H'0005' C2REN EQU H'0004' PULSS EQU H'0003' PULSR EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'13'-H'14', H'18'-H'1B' __BADRAM H'88'-H'89', H'91', H'93'-H'94', H'98'-H'9D' __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D' __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_SBODEN EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f6621.inc0000644000175000017500000014111511156521301013230 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6621 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6621 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6621 ; 2. LIST directive in the source file ; LIST P=PIC18F6621 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6621 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ECCP2DEL EQU H'0F67' PWM2CON EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' PWM3CON EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' PWM1CON EQU H'0F79' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1DC7 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' VPP EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' CCP3Y EQU H'0004' CCP3X EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F00'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; OSC = ECIOPLL EC-OSC2 as RA6 and PLL ; OSC = ECIOSWPLL EC-OSC2 as RA6 and SW PLL ; OSC = HSSWPLL HS with SW PLL ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 20 2.0V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; CCP2 MUX: ; CCP2MX = PORTBE Multiplexed with RB3 or RE7 ; CCP2MX = PORTC Multiplexed with RC1 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP _OSC_XT_1H EQU H'F1' ; XT _OSC_HS_1H EQU H'F2' ; HS _OSC_RC_1H EQU H'F3' ; RC _OSC_EC_1H EQU H'F4' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'F5' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'F7' ; RC-OSC2 as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC-OSC2 as RA6 and PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC-OSC2 as RA6 and SW PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS with SW PLL _OSCS_ON_1H EQU H'DF' ; Enabled _OSCS_OFF_1H EQU H'FF' ; Disabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_20_2L EQU H'FF' ; 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; Disabled _MCLRE_ON_3H EQU H'FF' ; Enabled _CCP2MX_PORTBE_3H EQU H'FE' ; Multiplexed with RB3 or RE7 _CCP2MX_PORTC_3H EQU H'FF' ; Multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled _CP3_ON_5L EQU H'F7' ; Enabled _CP3_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled _WRT3_ON_6L EQU H'F7' ; Enabled _WRT3_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled _EBTR3_ON_7L EQU H'F7' ; Enabled _EBTR3_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/rf675k.inc0000644000175000017500000002156311156313161013166 00000000000000 LIST ; RF675K.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the rfPIC12F675K microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PICRF675K ; 2. LIST directive in the source file ; LIST P=RF675K ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 02/19/03 Original -- copied from P12F675.INC (pas) ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __RF675K MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' WPU EQU H'0095' IOC EQU H'0096' IOCB EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 ------------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ANSEL -------------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p12f683.inc0000644000175000017500000003117111156521302013145 00000000000000 LIST ; P12F683.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F683 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F684 ; 2. LIST directive in the source file ; LIST P=PIC12F683 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 12/09/03 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F683 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' WDTCON EQU H'0018' CMCON0 EQU H'0019' CMCON1 EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEDAT EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits ----------------------------------------------------------- GP5 EQU H'0005' GP4 EQU H'0004' GP3 EQU H'0003' GP2 EQU H'0002' GP1 EQU H'0001' GP0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CCP1IF EQU H'0005' CMIF EQU H'0003' OSFIF EQU H'0002' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- COMCON0 Bits ------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- COMCON1 Bits ------------------------------------------------------- T1GSS EQU H'0001' CMSYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CCP1IE EQU H'0005' CMIE EQU H'0003' OSFIE EQU H'0002' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBODEN EQU H'0004' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D' __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTOSCIO EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRCIO EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p18f6310.inc0000644000175000017500000012175711156521301013235 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6310 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6310 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6310 ; 2. LIST directive in the source file ; LIST P=PIC18F6310 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6310 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2E EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DCCP3Y EQU H'0004' DCCP3X EQU H'0005' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F70'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block code-protected ; CP = OFF Program memory block not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG7L 30000Ch ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG7L EQU H'30000C' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block code-protected _CP_OFF_5L EQU H'FF' ; Program memory block not code-protected ;----- CONFIG7L Options -------------------------------------------------- _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18lf44j11.inc0000644000175000017500000015261511156521302013561 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF44J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF44J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF44J11 ; 2. LIST directive in the source file ; LIST P=PIC18LF44J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF44J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F60'-H'0F65' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/pmcv28a.inc0000644000175000017500000000655411156521301013422 00000000000000 LIST ; PMCV28A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the MCV28A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PMCV28A ; 2. LIST directive in the source file ; LIST P=MCV28A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 1/3/2008 First Revision ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __MCV28A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' ;----- STATUS Bits -------------------------------------------------------- PA2 EQU H'0007' PA1 EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'07F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _HS_OSC EQU H'0FFE' _RC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p12c508.inc0000644000175000017500000000740311156313161013141 00000000000000 LIST ; P12C508.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12C508 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12C508 ; 2. LIST directive in the source file ; LIST P=12C508 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.02 05/12/97 Correct STATUS and OPTION register bits ;1.01 08/21/96 Removed VCLMP fuse, corrected oscillators ;1.00 04/10/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12C508 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL0 EQU H'0004' CAL1 EQU H'0005' CAL2 EQU H'0006' CAL3 EQU H'0007' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16c65.inc0000644000175000017500000002650411156313161013066 00000000000000 LIST ; P16C65.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C65 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C65 ; 2. LIST directive in the source file ; LIST P=PIC16C65 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C65 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3F8F' _CP_75 EQU H'3F9F' _CP_50 EQU H'3FAF' _CP_OFF EQU H'3FBF' _PWRTE_ON EQU H'3FBF' _PWRTE_OFF EQU H'3FB7' _WDT_ON EQU H'3FBF' _WDT_OFF EQU H'3FBB' _LP_OSC EQU H'3FBC' _XT_OSC EQU H'3FBD' _HS_OSC EQU H'3FBE' _RC_OSC EQU H'3FBF' LIST gputils-0.13.7/header/p16f876.inc0000644000175000017500000003356411156313161013167 00000000000000 LIST ; P16F876.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F876 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F876 ; 2. LIST directive in the source file ; LIST P=PIC16F876 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.12 01/12/00 Changed some bit names, a register name, configuration bits ; to match datasheet (DS30292B) ;1.00 08/07/98 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F876 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09' __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A'-H'9D' __BADRAM H'105', H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'0FCF' _CP_HALF EQU H'1FDF' _CP_UPPER_256 EQU H'2FEF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c765.inc0000644000175000017500000003427111156313161013155 00000000000000 LIST ; P16C765.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C765 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C765 ; 2. LIST directive in the source file ; LIST P=PIC16C765 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 28 Sep 99 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C765 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' UIR EQU H'0190' UIE EQU H'0191' UEIR EQU H'0192' UEIE EQU H'0193' USTAT EQU H'0194' UCTRL EQU H'0195' UADDR EQU H'0196' USWSTAT EQU H'0197' UEP0 EQU H'0198' UEP1 EQU H'0199' UEP2 EQU H'019A' BD0OST EQU H'01A0' BD0OBC EQU H'01A1' BD0OAL EQU H'01A2' BD0IST EQU H'01A4' BD0IBC EQU H'01A5' BD0IAL EQU H'01A6' BD1OST EQU H'01A8' BD1OBC EQU H'01A9' BD1OAL EQU H'01AA' BD1IST EQU H'01AC' BD1IBC EQU H'01AD' BD1IAL EQU H'01AE' BD2OST EQU H'01B0' BD2OBC EQU H'01B1' BD2OAL EQU H'01B2' BD2IST EQU H'01B4' BD2IBC EQU H'01B5' BD2IAL EQU H'01B6' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' USBIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' USBIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- UIR/UIE Bits ----------------------------------------------------- STALL EQU H'0005' UIDLE EQU H'0004' TOK_DNE EQU H'0003' ACTIVITY EQU H'0002' UERR EQU H'0001' USB_RST EQU H'0000' ;----- UEIR/UEIE Bits ----------------------------------------------------- BTS_ERR EQU H'0007' OWN_ERR EQU H'0006' WRT_ERR EQU H'0005' BTO_ERR EQU H'0004' DFN8 EQU H'0003' CRC16 EQU H'0002' CRC5 EQU H'0001' PID_ERR EQU H'0000' ;----- USTAT Bits --------------------------------------------------------- ENDP1 EQU H'0004' ENDP0 EQU H'0003' IN EQU H'0002' ;----- UCTRL Bits --------------------------------------------------------- SE0 EQU H'0005' PKT_DIS EQU H'0004' DEV_ATT EQU H'0003' RESUME EQU H'0002' SUSPND EQU H'0001' ;----- UEPn Bits --------------------------------------------------------- EP_CTL_DIS EQU H'0003' EP_OUT_EN EQU H'0002' EP_IN_EN EQU H'0001' EP_STALL EQU H'0000' ;----- Buffer descriptor Bits --------------------------------------------- UOWN EQU H'0007' OWN EQU H'0007' DATA01 EQU H'0006' DTS EQU H'0003' BSTALL EQU H'0002' PID3 EQU H'0005' PID2 EQU H'0004' PID1 EQU H'0003' PID0 EQU H'0002' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'01FF' __BADRAM H'13', H'14', H'8F'-H'91' __BADRAM H'93'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F' __BADRAM H'1E0'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _HS_OSC EQU H'3FFC' _EC_OSC EQU H'3FFD' _H4_OSC EQU H'3FFE' _E4_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f66j10.inc0000644000175000017500000013047111156521301013403 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J10 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J10 ; 2. LIST directive in the source file ; LIST P=PIC18F66J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c715.inc0000644000175000017500000001366011156521301013144 00000000000000 LIST ; P16C715.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C715 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C715 ; 2. LIST directive in the source file ; LIST P=PIC16C715 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 05/12/97 Added values for Parity Enable configuration bits ;1.00 04/11/96 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C715 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_MPE EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'07'-H'09', H'0D'-H'1D' __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MPEEN_ON EQU H'3FFF' _MPEEN_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_50 EQU H'15DF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f2520.inc0000644000175000017500000012142311156521301013222 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2520 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2520 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2520 ; 2. LIST directive in the source file ; LIST P=PIC18F2520 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2520 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f871.inc0000644000175000017500000002711211156313161013152 00000000000000 LIST ; P16F871.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F871 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F871 ; 2. LIST directive in the source file ; LIST P=PIC16F871 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 08/07/98 Initial Release - cloned from 16F873 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F871 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' TXSTA EQU H'0098' SPBRG EQU H'0099' ADRESL EQU H'009E' ADCON1 EQU H'009F' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- EEIE EQU H'0004' ;----- PIR2 Bits ---------------------------------------------------------- EEIF EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'13'-H'14', H'1B'-H'1D' __BADRAM H'8F'-H'91', H'93'-H'97', H'9A'-H'9D', H'C0'-H'EF' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'19F', H'1C0'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'0FCF' _CP_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _DEBUG_OFF EQU H'3FFF' _WRT_ENABLE_ON EQU H'3FFF' _WRT_ENABLE_OFF EQU H'3DFF' _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f86j55.inc0000644000175000017500000020340511156521301013414 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J55 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J55 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J55 ; 2. LIST directive in the source file ; LIST P=PIC18F86J55 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J55 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c622a.inc0000644000175000017500000001361311156313161013303 00000000000000 LIST ; P16C622A.INC Standard Header File, Version 1.10 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C622A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C622A ; 2. LIST directive in the source file ; LIST P=PIC16C622A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 05/28/97 Initial Release ;1.10 16/08/99 Added unbanked RAM at 70-7F ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C622A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'07'-H'09', H'0D'-H'1E', H'87'-H'89', H'8D', H'8F'-H'9E' __BADRAM H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c84.inc0000644000175000017500000001127411156313161013065 00000000000000 LIST ; P16C84.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C84 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C84 ; 2. LIST directive in the source file ; LIST P=PIC16C84 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C84 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' EEDATA EQU H'0008' EEADR EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' EECON1 EQU H'0088' EECON2 EQU H'0089' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' EEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEIF EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'AF' __BADRAM H'07', H'30'-H'7F', H'87' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FFF' _PWRTE_OFF EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16lf1937.inc0000644000175000017500000012530111156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC16LF1937 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16LF1937 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16LF1937 ; 2. LIST directive in the source file ; LIST P=PIC16LF1937 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF1937 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTD EQU H'000F' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISD EQU H'008F' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATD EQU H'010F' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' ANSELD EQU H'018F' ANSELE EQU H'0190' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDSE2 EQU H'079A' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA2 EQU H'07A2' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA5 EQU H'07A5' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA8 EQU H'07A8' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' LCDDATA11 EQU H'07AB' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' CPSCH3 EQU H'0003' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- ANSELD Bits ----------------------------------------------------- ANSD0 EQU H'0000' ANSD1 EQU H'0001' ANSD2 EQU H'0002' ANSD3 EQU H'0003' ANSD4 EQU H'0004' ANSD5 EQU H'0005' ANSD6 EQU H'0006' ANSD7 EQU H'0007' ;----- ANSELE Bits ----------------------------------------------------- ANSE0 EQU H'0000' ANSE1 EQU H'0001' ANSE2 EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SEG16 EQU H'0000' SEG17 EQU H'0001' SEG18 EQU H'0002' SEG19 EQU H'0003' SEG20 EQU H'0004' SEG21 EQU H'0005' SEG22 EQU H'0006' SEG23 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA2 Bits ----------------------------------------------------- SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA8 Bits ----------------------------------------------------- SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E' __BADRAM H'0197'-H'0198' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0330'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079B'-H'079F' __BADRAM H'07AC'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _PWRTE_ON EQU H'FFDF' ; PWRT enabled _PWRTE_OFF EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _DEBUG_ON EQU H'EFFF' ; Background debugger is enabled _DEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p18lf14k50.inc0000644000175000017500000013411611156521301013555 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF14K50 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF14K50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF14K50 ; 2. LIST directive in the source file ; LIST P=PIC18LF14K50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF14K50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- UEP0 EQU H'0F53' UEP1 EQU H'0F54' UEP2 EQU H'0F55' UEP3 EQU H'0F56' UEP4 EQU H'0F57' UEP5 EQU H'0F58' UEP6 EQU H'0F59' UEP7 EQU H'0F5A' UEIE EQU H'0F5B' UADDR EQU H'0F5C' UFRML EQU H'0F5D' UFRMH EQU H'0F5E' UEIR EQU H'0F5F' UIE EQU H'0F60' UCFG EQU H'0F61' UIR EQU H'0F62' USTAT EQU H'0F63' UCON EQU H'0F64' SRCON0 EQU H'0F68' SRCON1 EQU H'0F69' CM2CON0 EQU H'0F6B' CM2CON1 EQU H'0F6C' CM1CON0 EQU H'0F6D' SSPMSK EQU H'0F6F' SLRCON EQU H'0F76' WPUA EQU H'0F77' WPUB EQU H'0F78' IOCA EQU H'0F79' IOCB EQU H'0F7A' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' REFCON0 EQU H'0FBA' VREFCON0 EQU H'0FBA' REFCON1 EQU H'0FBB' VREFCON1 EQU H'0FBB' REFCON2 EQU H'0FBC' VREFCON2 EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON2 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UPUEN EQU H'0004' UTEYE EQU H'0007' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C1SYNC EQU H'0001' C2HYS EQU H'0002' C1HYS EQU H'0003' C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' ;----- WPUA Bits ----------------------------------------------------- WPUA3 EQU H'0003' WPUA4 EQU H'0004' WPUA5 EQU H'0005' ;----- WPUB Bits ----------------------------------------------------- WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCA Bits ----------------------------------------------------- IOCA0 EQU H'0000' IOCA1 EQU H'0001' IOCA3 EQU H'0003' IOCA4 EQU H'0004' IOCA5 EQU H'0005' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN3 EQU H'0004' OSC2 EQU H'0004' OSC1 EQU H'0005' CLKOUT EQU H'0004' CLKIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' SDI EQU H'0004' RX EQU H'0005' SCL EQU H'0006' TX EQU H'0007' SDA EQU H'0004' ; DT is a reserved word ; DT EQU H'0005' SCK EQU H'0006' CK EQU H'0007' AN10 EQU H'0004' AN11 EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' AN4 EQU H'0000' AN5 EQU H'0001' AN6 EQU H'0002' AN7 EQU H'0003' AN8 EQU H'0006' AN9 EQU H'0007' C12INP EQU H'0000' C12IN1M EQU H'0001' C12IN2M EQU H'0002' C12IN3M EQU H'0003' C12OUT EQU H'0004' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0003' SRQ EQU H'0004' T0CKI EQU H'0005' T13CKI EQU H'0006' T1OSCO EQU H'0007' VREFP EQU H'0000' VREFM EQU H'0001' CVREF EQU H'0002' T1OSCI EQU H'0006' P1D EQU H'0002' P1C EQU H'0003' P1B EQU H'0004' P1A EQU H'0005' SS EQU H'0006' SDO EQU H'0007' CCP1 EQU H'0005' NOT_SS EQU H'0006' ;----- LATA Bits ----------------------------------------------------- LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' SPLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' USBIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' USBIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' USBIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- EEADR Bits ----------------------------------------------------- EEADR0 EQU H'0000' EEADR1 EQU H'0001' EEADR2 EQU H'0002' EEADR3 EQU H'0003' EEADR4 EQU H'0004' EEADR5 EQU H'0005' EEADR6 EQU H'0006' EEADR7 EQU H'0007' ;----- EEADRH Bits ----------------------------------------------------- EEADR8 EQU H'0000' EEADR9 EQU H'0001' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- REFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- TSRS EQU H'0002' TSEN EQU H'0003' FVR1S0 EQU H'0004' FVR1S1 EQU H'0005' FVR1ST EQU H'0006' FVR1EN EQU H'0007' ;----- REFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- REFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- NVCFG0 EQU H'0000' NVCFG1 EQU H'0001' PVCFG0 EQU H'0002' PVCFG1 EQU H'0003' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- OSCCON2 Bits ----------------------------------------------------- LFIOFS EQU H'0000' HFIOFL EQU H'0001' PRI_SD EQU H'0002' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RABIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RABPU EQU H'0007' NOT_RABPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RABIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RABIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F65'-H'0F67' __BADRAM H'0F6A' __BADRAM H'0F6E' __BADRAM H'0F70'-H'0F75' __BADRAM H'0F7B'-H'0F7D' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FB4'-H'0FB5' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; CPU System Clock Selection bit: ; CPUDIV = NOCLKDIV No CPU System Clock divide ; CPUDIV = CLKDIV2 CPU System Clock divided by 2 ; CPUDIV = CLKDIV3 CPU System Clock divided by 3 ; CPUDIV = CLKDIV4 CPU System Clock divided by 4 ; ; USB Clock Selection bit: ; USBDIV = OFF USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide ; USBDIV = ON USB clock comes from the OSC1/OSC2 divided by 2 ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = ERCCLKOUT External RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTH EC, CLKOUT function on OSC2 (high) ; FOSC = ECH EC (high) ; FOSC = ERC External RC oscillator ; FOSC = IRC Internal RC oscillator ; FOSC = IRCCLKOUT Internal RC oscillator, CLKOUT function on OSC2 ; FOSC = ECCLKOUTM EC, CLKOUT function on OSC2 (medium) ; FOSC = ECM EC (medium) ; FOSC = ECCLKOUTL EC, CLKOUT function on OSC2 (low) ; FOSC = ECL EC (low) ; ; 4 X PLL Enable bit: ; PLLEN = OFF PLL is under software control ; PLLEN = ON Oscillator multiplied by 4 ; ; Primary Clock Enable Bit: ; PCLKEN = OFF Primary clock is under software control ; PCLKEN = ON Primary clock enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRTEN = ON PWRT enabled ; PWRTEN = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 19 VBOR set to 1.9 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HFINTOSC Fast Start-up bit: ; HFOFST = OFF The system clock is held off until the HFINTOSC is stable. ; HFOFST = ON HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select Bit: ; BBSIZ = OFF 1kW boot block size ; BBSIZ = ON 2kW boot block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Code Protection bit: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers write-protected ; WRTC = OFF Configuration registers not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _CPUDIV_NOCLKDIV_1L EQU H'E7' ; No CPU System Clock divide _CPUDIV_CLKDIV2_1L EQU H'EF' ; CPU System Clock divided by 2 _CPUDIV_CLKDIV3_1L EQU H'F7' ; CPU System Clock divided by 3 _CPUDIV_CLKDIV4_1L EQU H'FF' ; CPU System Clock divided by 4 _USBDIV_OFF_1L EQU H'DF' ; USB Clock comes directly from the OSC1/OSC2 oscillator block; no divide _USBDIV_ON_1L EQU H'FF' ; USB clock comes from the OSC1/OSC2 divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high) _FOSC_ECH_1H EQU H'F5' ; EC (high) _FOSC_ERC_1H EQU H'F7' ; External RC oscillator _FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator _FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2 _FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium) _FOSC_ECM_1H EQU H'FB' ; EC (medium) _FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low) _FOSC_ECL_1H EQU H'FD' ; EC (low) _PLLEN_OFF_1H EQU H'EF' ; PLL is under software control _PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4 _PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control _PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRTEN_ON_2L EQU H'FE' ; PWRT enabled _PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize. ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size _BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p12ce674.inc0000644000175000017500000001420711156313161013312 00000000000000 LIST ; P12CE674.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12CE674 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12CE674 ; 2. LIST directive in the source file ; LIST P=PIC12CE674 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Original Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12CE674 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'008F' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- OSCCAL Bits -------------------------------------------------------- CAL3 EQU H'0007' CAL2 EQU H'0006' CAL1 EQU H'0005' CAL0 EQU H'0004' CALFST EQU H'0003' CALSLW EQU H'0002' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D'-H'1D' __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3F7F' _CP_ALL EQU H'009F' _CP_75 EQU H'15BF' _CP_50 EQU H'2ADF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _INTRC_OSC EQU H'3FFC' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC EQU H'3FFE' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p16c925.inc0000644000175000017500000003246311156313161013154 00000000000000 LIST ; P16C925.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C925 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C925 ; 2. LIST directive in the source file ; LIST P=PIC16C925 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/21/00 Initial Release ;1.01 02/27/01 Changes to reflect design changes to data memory map: ; 1.) Locations of PMDATA and PMCON1 swapped. ; 2.) Locations of PMDATH and PMADR swapped. ;1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected. ;1.03 03/06/01 RD bit in PMCON1 defined. ;1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01. ;1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04. ;1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C925 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ADRESL EQU H'009E' ADCON1 EQU H'009F' PORTF EQU H'0107' PORTG EQU H'0108' PMCON1 EQU H'010C' LCDSE EQU H'010D' LCDPS EQU H'010E' LCDCON EQU H'010F' LCDD00 EQU H'0110' LCDD01 EQU H'0111' LCDD02 EQU H'0112' LCDD03 EQU H'0113' LCDD04 EQU H'0114' LCDD05 EQU H'0115' LCDD06 EQU H'0116' LCDD07 EQU H'0117' LCDD08 EQU H'0118' LCDD09 EQU H'0119' LCDD10 EQU H'011A' LCDD11 EQU H'011B' LCDD12 EQU H'011C' LCDD13 EQU H'011D' LCDD14 EQU H'011E' LCDD15 EQU H'011F' TRISF EQU H'0187' TRISG EQU H'0188' PMDATA EQU H'018C' PMDATH EQU H'018D' PMADR EQU H'018E' PMADRH EQU H'018F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- LCDIF EQU H'0007' ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- LCDIE EQU H'0007' ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- LCDSE Bits --------------------------------------------------------- SE29 EQU H'0007' SE27 EQU H'0006' SE20 EQU H'0005' SE16 EQU H'0004' SE12 EQU H'0003' SE9 EQU H'0002' SE5 EQU H'0001' SE0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' BIAS EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'0D', H'18'-H'1D' __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D' __BADRAM H'105', H'109', H'120'-H'16F' __BADRAM H'185', H'189', H'190'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3FCF' _CP_75 EQU H'3FDF' _CP_50 EQU H'3FEF' _CP_OFF EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _BODEN_ON EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f63j11.inc0000644000175000017500000011570611156521301013405 00000000000000 LIST ;========================================================================== ; MPASM PIC18F63J11 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F63J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F63J11 ; 2. LIST directive in the source file ; LIST P=PIC18F63J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F63J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' REPU EQU H'0006' RDPU EQU H'0007' TX2 EQU H'0001' RX2 EQU H'0002' CK2 EQU H'0001' DT2 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F5F' __BADRAM H'0F6B'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB6'-H'0FBF' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 1FF8h ; CONFIG1H 1FF9h ; CONFIG2L 1FFAh ; CONFIG2H 1FFBh ; CONFIG3L 1FFCh ; CONFIG3H 1FFDh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'1FF8' _CONFIG1H EQU H'1FF9' _CONFIG2L EQU H'1FFA' _CONFIG2H EQU H'1FFB' _CONFIG3L EQU H'1FFC' _CONFIG3H EQU H'1FFD' ;----- CONFIG1L Options -------------------------------------------------- _DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled _STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled _WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit) _WDTEN_ON_1L EQU H'FF' ; WDT enabled ;----- CONFIG1H Options -------------------------------------------------- _CP0_ON_1H EQU H'FB' ; Program memory is code-protected _CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected ;----- CONFIG2L Options -------------------------------------------------- _IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled _FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled _FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00 _FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 _FOSC_HS_2L EQU H'FC' ; HS oscillator _FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control _FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2 _FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2 ;----- CONFIG2H Options -------------------------------------------------- _WDTPS_1_2H EQU H'F0' ; 1:1 _WDTPS_2_2H EQU H'F1' ; 1:2 _WDTPS_4_2H EQU H'F2' ; 1:4 _WDTPS_8_2H EQU H'F3' ; 1:8 _WDTPS_16_2H EQU H'F4' ; 1:16 _WDTPS_32_2H EQU H'F5' ; 1:32 _WDTPS_64_2H EQU H'F6' ; 1:64 _WDTPS_128_2H EQU H'F7' ; 1:128 _WDTPS_256_2H EQU H'F8' ; 1:256 _WDTPS_512_2H EQU H'F9' ; 1:512 _WDTPS_1024_2H EQU H'FA' ; 1:1024 _WDTPS_2048_2H EQU H'FB' ; 1:2048 _WDTPS_4096_2H EQU H'FC' ; 1:4096 _WDTPS_8192_2H EQU H'FD' ; 1:8192 _WDTPS_16384_2H EQU H'FE' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode _CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1 _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18c252.inc0000644000175000017500000006003211156313161013140 00000000000000 LIST ; P18C252.INC Standard Header File, Version 0.12 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C252 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C252 ; 2. LIST directive in the source file ; LIST P=PIC18C252 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: Who: ;0.02 25 Nov 98 Preliminary Release drj ;0.03 07 Dec 98 Added compatibility #defines drj ;0.04 10 Dec 98 Added bits defs and new config jt ;0.05 14 Dec 98 Incorporated ko comments dj ;0.06 12 Jan 99 Changed config bits dj ;0.07 13 Jan 99 Changed BODEN to BOREN dj ;0.08 1 Apr 99 Added TRIS aliases ;0.09 17 Jun 99 Clean up ;0.10 23 Sep 99 Compatibility with PIC18Cxx2 Data Sheet (Rev B) ; and Added I/O Pin definitions mp ;0.11 29 Jun 00 Added support for Device ID/Revision & ID locations rr ;0.12 09/26/02 Include both names SWDTE and SWDTEN pas ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C252 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ;RESERVED_0FC0 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' ;RESERVED_0FB0 EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' ;RESERVED_0FA7 EQU H'0FA7' ;RESERVED_0FA6 EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ;RESERVED_0F9C EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' ;RESERVED_0F9A EQU H'0F9A' ;RESERVED_0F99 EQU H'0F99' ;RESERVED_0F98 EQU H'0F98' ;RESERVED_0F97 EQU H'0F97' ;RESERVED_0F96 EQU H'0F96' ;RESERVED_0F95 EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ;RESERVED_0F91 EQU H'0F91' ;RESERVED_0F90 EQU H'0F90' ;RESERVED_0F8F EQU H'0F8F' ;RESERVED_0F8E EQU H'0F8E' ;RESERVED_0F8D EQU H'0F8D' ;RESERVED_0F8C EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ;RESERVED_0F88 EQU H'0F88' ;RESERVED_0F87 EQU H'0F87' ;RESERVED_0F86 EQU H'0F86' ;RESERVED_0F85 EQU H'0F85' ;RESERVED_0F84 EQU H'0F84' ;RESERVED_0F83 EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' LWRT EQU H'0006' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0006' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- IPR2 Bits ---------------------------------------------------------- BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM H'5FF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Code Protect: ; CP = ON Enabled ; CP = OFF Disabled ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disable (RB3) ; CCP2MUX = ON Enable (RC1) ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 0 300000h ; CONFIG1H = Configuration Byte 1 300001h ; CONFIG2L = Configuration Byte 3 300002h ; CONFIG2H = Configuration Byte 4 300003h ; CONFIG3L = Configuration Byte 5 300004h ; CONFIG3H = Configuration Byte 6 300005h ; CONFIG4L = Configuration Byte 7 300006h ; CONFIG4H = Configuration Byte 8 300007h ; ;========================================================================== ; ;Configuration Byte 0 Options _CP_ON_0 EQU H'00' ; Code Protect enable _CP_OFF_0 EQU H'FF' ;Configuration Byte 1 Options _OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1 EQU H'FF' _LP_OSC_1 EQU H'F8' ; Oscillator type _XT_OSC_1 EQU H'F9' _HS_OSC_1 EQU H'FA' _RC_OSC_1 EQU H'FB' _EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1 EQU H'FE' ; HS PLL _RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options _BOR_ON_2 EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2 EQU H'FD' _PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable _PWRT_ON_2 EQU H'FE' _BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2 EQU H'FB' ; 2.7v _BORV_42_2 EQU H'F7' ; 4.2v _BORV_45_2 EQU H'F3' ; 4.5v ;Configuration Byte 3 Options _WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_3 EQU H'FE' _WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_3 EQU H'FD' _WDTPS_32_3 EQU H'FB' _WDTPS_16_3 EQU H'F9' _WDTPS_8_3 EQU H'F7' _WDTPS_4_3 EQU H'F5' _WDTPS_2_3 EQU H'F3' _WDTPS_1_3 EQU H'F1' ;Configuration Byte 5 Options _CCP2MX_ON_5 EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_5 EQU H'FE' ;Configuration Byte 6 Options _STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_6 EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG0 EQU H'300000' _CONFIG1 EQU H'300001' _CONFIG2 EQU H'300002' _CONFIG3 EQU H'300003' _CONFIG4 EQU H'300004' _CONFIG5 EQU H'300005' _CONFIG6 EQU H'300006' _CONFIG7 EQU H'300007' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 0 ; __CONFIG _CONFIG0, _CP_OFF_0 ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1 ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2 ;Program Configuration Register 3 ; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3 ;Program Configuration Register 5 ;__CONFIG _CONFIG5, _CCP2MX_ON_5 ;Program Configuration Register 6 ; __CONFIG _CONFIG6, _STVR_ON_6 ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16f716.inc0000644000175000017500000002302611156313161013150 00000000000000 LIST ; P16F716.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F716 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F716 ; 2. LIST directive in the source file ; LIST P=PIC16F716 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 16 Apr 2003 Initial Release ;1.01 30 Apr 2003 Added references for backward compatibility to PIC16C716 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F716 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' DATACCP EQU H'0006' ; C712/C716 compatibility PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' PWM1CON EQU H'0018' ECCPAS EQU H'0019' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISCP EQU H'0086' ; C712/C716 compatibility PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- PORTB Bits -------------------------------------------------------- DCCP EQU H'0003' ; C712/C716 compatibility DT1CK EQU H'0001' ; C712/C716 compatibility ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISB Bits -------------------------------------------------------- TCCP EQU H'0003' TT1CK EQU H'0001' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ; C712/C716 compatibility NOT_BOD EQU H'0000' ; C712/C716 compatibility NOT_BOR EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1A'-H'1D' __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' ; C712/C716 compatibility _BODEN_OFF EQU H'3FBF' ; C712/C716 compatibility _BOREN_ON EQU H'3FFF' _BOREN_OFF EQU H'3FBF' _VBOR_25 EQU H'3F7F' _VBOR_40 EQU H'3FFF' _CP_ON EQU H'1FFF' _CP_ALL EQU H'1FFF' ; C712/C716 compatibility _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18lf26j50.inc0000644000175000017500000016415311156521301013563 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF26J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF26J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF26J50 ; 2. LIST directive in the source file ; LIST P=PIC18LF26J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF26J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F5F' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f724.inc0000644000175000017500000005122411156521301013145 00000000000000 LIST ; P16F724.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F724 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F724 ; 2. LIST directive in the source file ; LIST P=PIC16F724 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/09/06 Initial template ;0.02 10/25/07 Remove 120h-12Fh and 188h from BADRAM ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F724 MESSG "Processor-header file mismatch. Verify selected processor." #define __16F724 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' ANSELD EQU H'0188' ANSELE EQU H'0189' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- ANSELD Bits --------------------------------------------------------- ANSD7 EQU H'0007' ANSD6 EQU H'0006' ANSD5 EQU H'0005' ANSD4 EQU H'0004' ANSD3 EQU H'0003' ANSD2 EQU H'0002' ANSD1 EQU H'0001' ANSD0 EQU H'0000' ;----- ANSELE Bits --------------------------------------------------------- ANSE2 EQU H'0002' ANSE1 EQU H'0001' ANSE0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'110'-H'11F',H'130'-H'16F' __BADRAM H'187', H'18D'-H'18F' __BADRAM H'190'-H'1EF' LIST gputils-0.13.7/header/p18f2410.inc0000644000175000017500000011201011156521301013210 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2410 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2410 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2410 ; 2. LIST directive in the source file ; LIST P=PIC18F2410 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2410 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' DAD5 EQU H'0005' DAD6 EQU H'0006' DAD7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' FLTS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' IOFS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f86j15.inc0000644000175000017500000014175511156521301013421 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J15 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J15 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J15 ; 2. LIST directive in the source file ; LIST P=PIC18F86J15 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J15 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0004' PGC EQU H'0005' PGD EQU H'0006' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2 EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD00 EQU H'0000' AD01 EQU H'0001' AD02 EQU H'0002' AD03 EQU H'0003' AD04 EQU H'0004' AD05 EQU H'0005' AD06 EQU H'0006' AD07 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0003' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p12c672.inc0000644000175000017500000001436011156313161013143 00000000000000 LIST ; P12C672.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12C672 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C672 ; 2. LIST directive in the source file ; LIST P=PIC12C672 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 07/22/97 Corrected BADRAM ;1.02 05/12/97 Corrected configuration bits, RAM map ;1.01 12/18/96 Modified per review ;1.00 11/12/96 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12C672 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'008F' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- OSCCAL Bits -------------------------------------------------------- CAL3 EQU H'0007' CAL2 EQU H'0006' CAL1 EQU H'0005' CAL0 EQU H'0004' CALFST EQU H'0003' CALSLW EQU H'0002' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D'-H'1D' __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3F7F' _CP_ALL EQU H'009F' _CP_75 EQU H'15BF' _CP_50 EQU H'2ADF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _INTRC_OSC EQU H'3FFC' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC EQU H'3FFE' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18f86j60.inc0000644000175000017500000014701611156521301013415 00000000000000 LIST ;========================================================================== ; MPASM PIC18F86J60 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F86J60 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F86J60 ; 2. LIST directive in the source file ; LIST P=PIC18F86J60 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F86J60 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- MAADR5 EQU H'0E80' MAADR6 EQU H'0E81' MAADR3 EQU H'0E82' MAADR4 EQU H'0E83' MAADR1 EQU H'0E84' MAADR2 EQU H'0E85' MISTAT EQU H'0E8A' EFLOCON EQU H'0E97' EPAUS EQU H'0E98' EPAUSL EQU H'0E98' EPAUSH EQU H'0E99' MACON1 EQU H'0EA0' MACON3 EQU H'0EA2' MACON4 EQU H'0EA3' MABBIPG EQU H'0EA4' MAIPG EQU H'0EA6' MAIPGL EQU H'0EA6' MAIPGH EQU H'0EA7' MAMXFL EQU H'0EAA' MAMXFLL EQU H'0EAA' MAMXFLH EQU H'0EAB' MICMD EQU H'0EB2' MIREGADR EQU H'0EB4' MIWR EQU H'0EB6' MIWRL EQU H'0EB6' MIWRH EQU H'0EB7' MIRD EQU H'0EB8' MIRDL EQU H'0EB8' MIRDH EQU H'0EB9' EHT0 EQU H'0EC0' EHT1 EQU H'0EC1' EHT2 EQU H'0EC2' EHT3 EQU H'0EC3' EHT4 EQU H'0EC4' EHT5 EQU H'0EC5' EHT6 EQU H'0EC6' EHT7 EQU H'0EC7' EPMM0 EQU H'0EC8' EPMM1 EQU H'0EC9' EPMM2 EQU H'0ECA' EPMM3 EQU H'0ECB' EPMM4 EQU H'0ECC' EPMM5 EQU H'0ECD' EPMM6 EQU H'0ECE' EPMM7 EQU H'0ECF' EPMCS EQU H'0ED0' EPMCSL EQU H'0ED0' EPMCSH EQU H'0ED1' EPMO EQU H'0ED4' EPMOL EQU H'0ED4' EPMOH EQU H'0ED5' ERXFCON EQU H'0ED8' EPKTCNT EQU H'0ED9' EWRPT EQU H'0EE2' EWRPTL EQU H'0EE2' EWRPTH EQU H'0EE3' ETXST EQU H'0EE4' ETXSTL EQU H'0EE4' ETXSTH EQU H'0EE5' ETXND EQU H'0EE6' ETXNDL EQU H'0EE6' ETXNDH EQU H'0EE7' ERXST EQU H'0EE8' ERXSTL EQU H'0EE8' ERXSTH EQU H'0EE9' ERXND EQU H'0EEA' ERXNDL EQU H'0EEA' ERXNDH EQU H'0EEB' ERXRDPT EQU H'0EEC' ERXRDPTL EQU H'0EEC' ERXRDPTH EQU H'0EED' ERXWRPT EQU H'0EEE' ERXWRPTL EQU H'0EEE' ERXWRPTH EQU H'0EEF' EDMAST EQU H'0EF0' EDMASTL EQU H'0EF0' EDMASTH EQU H'0EF1' EDMAND EQU H'0EF2' EDMANDL EQU H'0EF2' EDMANDH EQU H'0EF3' EDMADST EQU H'0EF4' EDMADSTL EQU H'0EF4' EDMADSTH EQU H'0EF5' EDMACS EQU H'0EF6' EDMACSL EQU H'0EF6' EDMACSH EQU H'0EF7' EIE EQU H'0EFB' ESTAT EQU H'0EFD' ECON2 EQU H'0EFE' EIR EQU H'0F60' EDATA EQU H'0F61' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' ERDPT EQU H'0F7A' ERDPTL EQU H'0F7A' ERDPTH EQU H'0F7B' BAUDCON2 EQU H'0F7C' BAUDCTL2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' ECON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- MISTAT Bits ----------------------------------------------------- BUSY EQU H'0000' SCAN EQU H'0001' NVALID EQU H'0002' ;----- EFLOCON Bits ----------------------------------------------------- FCEN0 EQU H'0000' FCEN1 EQU H'0001' FULDPXS EQU H'0002' ;----- MACON1 Bits ----------------------------------------------------- MARXEN EQU H'0000' PASSALL EQU H'0001' RXPAUS EQU H'0002' TXPAUS EQU H'0003' ;----- MACON3 Bits ----------------------------------------------------- FULDPX EQU H'0000' FRMLNEN EQU H'0001' HFRMEN EQU H'0002' PHDREN EQU H'0003' TXCRCEN EQU H'0004' PADCFG0 EQU H'0005' PADCFG1 EQU H'0006' PADCFG2 EQU H'0007' PADCFG EQU H'0005' ;----- MACON4 Bits ----------------------------------------------------- DEFER EQU H'0006' ;----- MICMD Bits ----------------------------------------------------- MIIRD EQU H'0000' MIISCAN EQU H'0001' ;----- ERXFCON Bits ----------------------------------------------------- BCEN EQU H'0000' MCEN EQU H'0001' HTEN EQU H'0002' MPEN EQU H'0003' PMEN EQU H'0004' CRCEN EQU H'0005' ANDOR EQU H'0006' UCEN EQU H'0007' ;----- EIE Bits ----------------------------------------------------- RXERIE EQU H'0000' TXERIE EQU H'0001' TXIE_EIE EQU H'0003' LINKIE EQU H'0004' DMAIE EQU H'0005' PKTIE EQU H'0006' ;----- ESTAT Bits ----------------------------------------------------- PHYRDY EQU H'0000' TXABRT EQU H'0001' RXBUSY EQU H'0002' BUFER EQU H'0006' ;----- ECON2 Bits ----------------------------------------------------- ETHEN EQU H'0005' PKTDEC EQU H'0006' AUTOINC EQU H'0007' ;----- EIR Bits ----------------------------------------------------- RXERIF EQU H'0000' TXERIF EQU H'0001' TXIF_EIR EQU H'0003' LINKIF EQU H'0004' DMAIF EQU H'0005' PKTIF EQU H'0006' ;----- EDATA Bits ----------------------------------------------------- EDATA0 EQU H'0000' EDATA1 EQU H'0001' EDATA2 EQU H'0002' EDATA3 EQU H'0003' EDATA4 EQU H'0004' EDATA5 EQU H'0005' EDATA6 EQU H'0006' EDATA7 EQU H'0007' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' CCP5Y EQU H'0004' CCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' CCP4Y EQU H'0004' CCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RJPU EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' LEDA EQU H'0000' LEDB EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ECCP2_PORTC EQU H'0001' ECCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2_PORTE EQU H'0007' ECCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' NOT_SS EQU H'0007' SS1 EQU H'0007' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' ECCP3 EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ4 EQU H'0004' RJ5 EQU H'0005' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ4 EQU H'0004' LATJ5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ4 EQU H'0004' RJ5 EQU H'0005' ;----- TRISJ Bits ----------------------------------------------------- TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- PPRE EQU H'0004' PPST0 EQU H'0005' PLLEN EQU H'0006' PPST1 EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE_PIE1 EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF_PIR1 EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' BCLIE EQU H'0003' ETHIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' BCLIF EQU H'0003' ETHIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' BCLIP EQU H'0003' ETHIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' ADCAL EQU H'0007' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ADMSK EQU H'0001' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- ECON1 Bits ----------------------------------------------------- RXEN EQU H'0002' TXRTS EQU H'0003' CSUMEN EQU H'0004' DMAST EQU H'0005' RXRST EQU H'0006' TXRST EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0E86'-H'0E89' __BADRAM H'0E8B'-H'0E96' __BADRAM H'0E9A'-H'0E9F' __BADRAM H'0EA1' __BADRAM H'0EA5' __BADRAM H'0EA8'-H'0EA9' __BADRAM H'0EAC'-H'0EB1' __BADRAM H'0EB3' __BADRAM H'0EB5' __BADRAM H'0EBA'-H'0EBF' __BADRAM H'0ED2'-H'0ED3' __BADRAM H'0ED6'-H'0ED7' __BADRAM H'0EDA'-H'0EE1' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0EFC' __BADRAM H'0EFF'-H'0F5F' __BADRAM H'0F62'-H'0F66' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVR = OFF Reset on stack overflow/underflow disabled ; STVR = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on SWDTEN bit) ; WDT = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Ethernet LED Enable bit: ; ETHLED = OFF RA0/RA1 function as I/O regardless of Ethernet module status ; ETHLED = ON RA0/RA1 are multiplexed with LEDA/LEDB when Ethernet module is enabled and function as I/O when Ethernet is disabled ; ; ECCP MUX bit: ; ECCPMX = OFF ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = ON ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = OFF ECCP2/P2A is multiplexed with RE7 in Microcontroller mode (80-pin and 100-pin devices) or with RB3 in Extended Microcontroller mode (100-pin devices only) ; CCP2MX = ON ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f85j50.inc0000644000175000017500000020340511156521301013406 00000000000000 LIST ;========================================================================== ; MPASM PIC18F85J50 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F85J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F85J50 ; 2. LIST directive in the source file ; LIST P=PIC18F85J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F85J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F40' PMSTATL EQU H'0F40' PMSTATH EQU H'0F41' PMEL EQU H'0F42' PMEN EQU H'0F42' PMEH EQU H'0F43' PMDIN2 EQU H'0F44' PMDIN2L EQU H'0F44' PMDIN2H EQU H'0F45' PMDOUT2 EQU H'0F46' PMDOUT2L EQU H'0F46' PMDOUT2H EQU H'0F47' PMMODE EQU H'0F48' PMMODEL EQU H'0F48' PMMODEH EQU H'0F49' PMCON EQU H'0F4A' PMCONL EQU H'0F4A' PMCONH EQU H'0F4B' UEP0 EQU H'0F4C' UEP1 EQU H'0F4D' UEP2 EQU H'0F4E' UEP3 EQU H'0F4F' UEP4 EQU H'0F50' UEP5 EQU H'0F51' UEP6 EQU H'0F52' UEP7 EQU H'0F53' UEP8 EQU H'0F54' UEP9 EQU H'0F55' UEP10 EQU H'0F56' UEP11 EQU H'0F57' UEP12 EQU H'0F58' UEP13 EQU H'0F59' UEP14 EQU H'0F5A' UEP15 EQU H'0F5B' UIE EQU H'0F5C' UEIE EQU H'0F5D' UADDR EQU H'0F5E' UCFG EQU H'0F5F' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' MEMCON EQU H'0FCB' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' C2INA EQU H'0005' CLKO EQU H'0006' PMD5_PORTA EQU H'0004' PMD4_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' C2OUT EQU H'0005' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0_PORTD EQU H'0000' PMD1_PORTD EQU H'0001' PMD2_PORTD EQU H'0002' PMD3_PORTD EQU H'0003' PMD4_PORTD EQU H'0004' PMD5_PORTD EQU H'0005' PMD6_PORTD EQU H'0006' PMD7_PORTD EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' PMRD_PORTE EQU H'0000' PMWR_PORTE EQU H'0001' PMBE_PORTE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN7 EQU H'0002' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2INB EQU H'0002' C1INB EQU H'0005' C1INA EQU H'0006' C1OUT EQU H'0007' PMA5 EQU H'0002' PMD2_PORTF EQU H'0005' PMD1_PORTF EQU H'0006' PMD0_PORTF EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' RJPU EQU H'0005' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' PMD7_PORTH EQU H'0002' PMD6_PORTH EQU H'0003' PMD3_PORTH EQU H'0004' PMBE_PORTH EQU H'0005' PMRD_PORTH EQU H'0006' PMWR_PORTH EQU H'0007' C2INC EQU H'0004' C2IND EQU H'0005' C1INC EQU H'0006' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EDBIS EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 [CPU System clock/6] ; CPUDIV = OSC3_PLL3 [CPU System clock/3] ; CPUDIV = OSC2_PLL2 [CPU System clock/2] ; CPUDIV = OSC1 [No CPU System clock divide] ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7, INTOSCPLL used by USB ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7, INTOSCPLL used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL HS oscillator, PLL enabled, HSPLL used by USB ; FOSC = EC EC Oscillator with clock out on RA6, EC used by USB ; FOSC = ECPLL EC Oscillator with PLL , CLKOUT on RA6, ECPLL used by USB ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; External Bus Wait Enable bit: ; WAIT = ON Wait states for operations on external memory bus enabled ; WAIT = OFF Wait states for operations on external memory bus disabled ; ; Data Bus Width Select bit: ; BW = 8 8-bit external bus mode ; BW = 16 16-bit external bus mode ; ; Processor Mode Selection: ; MODE = XM20 Extended Microcontroller mode - 20-bit Address mode ; MODE = XM16 Extended Microcontroller mode - 16-bit Address mode ; MODE = XM12 Extended Microcontroller mode - 12-bit Address mode ; MODE = MM Microcontroller mode - External bus disabled ; ; External Address Bus Shift Enable bit: ; EASHFT = OFF Address shifting disabled, address on external bus reflects the PC value ; EASHFT = ON Address shifting enabled, address on external bus is offset to start at 000000h ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; PMP pin select: ; PMPMX = ALTERNATE PMP port pins not connected to EMB ; PMPMX = DEFAULT PMP port pins connected to EMB ; ; ECCPx MUX bit: ; ECCPMX = ALTERNATE ECCP1 outputs (P1B/P1C) are multiplexed with RH7 and RH6; ECCP3 outputs (P3B/P3C) are multiplexed with RH5 and RH4 ; ECCPMX = DEFAULT ECCP1 outputs (P1B/P1C) are multiplexed with RE6 and RE5; ECCP3 outputs (P3B/P3C) are multiplexed with RE4 and RE3 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16c782.inc0000644000175000017500000002674111156313161013157 00000000000000 LIST ; P16C782.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C782 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C782 ; 2. LIST directive in the source file ; LIST P=PIC16C782 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 16May2001 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C782 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' WPUB EQU H'0095' IOCB EQU H'0096' REFCON EQU H'009B' LVDCON EQU H'009C' ANSEL EQU H'009D' ADCON1 EQU H'009F' PMDATL EQU H'010C' PMADRL EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' CALCON EQU H'0110' PSMCCON0 EQU H'0111' PSMCCON1 EQU H'0112' CM1CON0 EQU H'0119' CM2CON0 EQU H'011A' CM2CON1 EQU H'011B' OPACON EQU H'011C' DAC EQU H'011E' DACON0 EQU H'011F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- LVDIF EQU H'0007' ADIF EQU H'0006' C2IF EQU H'0005' C1IF EQU H'0004' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- LVDIE EQU H'0007' ADIE EQU H'0006' C2IE EQU H'0005' C1IE EQU H'0004' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- WDTON EQU H'0004' OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- VREFEN EQU H'0003' VREFOE EQU H'0002' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- CALCON Bits -------------------------------------------------------- CAL EQU H'0007' CALERR EQU H'0006' CALREF EQU H'0005' ;----- PSMCCON0 Bits ------------------------------------------------------ SMCCL1 EQU H'0007' SMCCL0 EQU H'0006' MINDC1 EQU H'0005' MINDC0 EQU H'0004' MAXDC1 EQU H'0003' MAXDC0 EQU H'0002' DC1 EQU H'0001' DC0 EQU H'0000' ;----- PSMCCON1 Bits ------------------------------------------------------ SMCON EQU H'0007' S1APOL EQU H'0006' S1BPOL EQU H'0005' SCEN EQU H'0003' SMCOM EQU H'0002' PWM EQU H'0001' PSM EQU H'0001' NOT_PSM EQU H'0001' SMCCS EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------ C1ON EQU H'0007' C1OUT EQU H'0006' C1OE EQU H'0005' C1POL EQU H'0004' C1SP EQU H'0003' C1R EQU H'0002' C1CH1 EQU H'0001' C1CH0 EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------ C2ON EQU H'0007' C2OUT EQU H'0006' C2OE EQU H'0005' C2POL EQU H'0004' C2SP EQU H'0003' C2R EQU H'0002' C2CH1 EQU H'0001' C2CH0 EQU H'0000' ;----- CM2CON1 Bits ------------------------------------------------------ MC1OUT EQU H'0007' MC2OUT EQU H'0006' C2SYNC EQU H'0000' ;----- OPACON Bits ------------------------------------------------------- OPAON EQU H'0007' CMPEN EQU H'0006' GBWP EQU H'0000' ;----- DACON Bits -------------------------------------------------------- DAON EQU H'0007' DAOE EQU H'0006' DARS1 EQU H'0001' DARS0 EQU H'0000' ;----- PMCON1 Bits ------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'0D', H'11'-H'1D' __BADRAM H'87'-H'89', H'8D' __BADRAM H'8F'-H'94', H'97'-H'9A', H'9E', H'C0'-H'EF' __BADRAM H'105', H'107'-H'109', H'113'-H'118' __BADRAM H'11D', H'120'-H'16F' __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CFF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _MCLRE_OFF EQU H'3FDF' _MCLRE_ON EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FFB' _HS_OSC EQU H'3FFA' _XT_OSC EQU H'3FF9' _LP_OSC EQU H'3FF8' LIST gputils-0.13.7/header/Makefile.in0000644000175000017500000003766611156521301013524 00000000000000# Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ top_builddir = .. am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd INSTALL = @INSTALL@ install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = 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p16c61.inc \ p16c620a.inc \ p16c620.inc \ p16c621a.inc \ p16c621.inc \ p16c622a.inc \ p16c622.inc \ p16c62a.inc \ p16c62b.inc \ p16c62.inc \ p16c63a.inc \ p16c63.inc \ p16c642.inc \ p16c64a.inc \ p16c64.inc \ p16c65a.inc \ p16c65b.inc \ p16c65.inc \ p16c662.inc \ p16c66.inc \ p16c67.inc \ p16c710.inc \ p16c711.inc \ p16c712.inc \ p16c715.inc \ p16c716.inc \ p16c717.inc \ p16c71.inc \ p16c72a.inc \ p16c72.inc \ p16c73a.inc \ p16c73b.inc \ p16c73.inc \ p16c745.inc \ p16c74a.inc \ p16c74b.inc \ p16c74.inc \ p16c765.inc \ p16c76.inc \ p16c770.inc \ p16c771.inc \ p16c773.inc \ p16c774.inc \ p16c77.inc \ p16c781.inc \ p16c782.inc \ p16c84.inc \ p16c923.inc \ p16c924.inc \ p16c925.inc \ p16c926.inc \ p16ce623.inc \ p16ce624.inc \ p16ce625.inc \ p16cr62.inc \ p16cr63.inc \ p16cr64.inc \ p16cr65.inc \ p16cr72.inc \ p16cr83.inc \ p16cr84.inc \ p16f1933.inc \ p16f1934.inc \ p16f1936.inc \ p16f1937.inc \ p16f505.inc \ p16f506.inc \ p16f526.inc \ p16f5x.inc \ p16f610.inc \ p16f616.inc \ p16f627a.inc \ p16f627.inc \ p16f628a.inc \ p16f628.inc \ p16f630.inc \ p16f631.inc \ p16f636.inc \ p16f639.inc \ p16f648a.inc \ p16f676.inc \ p16f677.inc \ p16f684.inc \ p16f685.inc \ p16f687.inc \ p16f688.inc \ p16f689.inc \ p16f690.inc \ p16f716.inc \ p16f722.inc \ p16f723.inc \ p16f724.inc \ p16f726.inc \ p16f727.inc \ p16f72.inc \ p16f737.inc \ p16f73.inc \ p16f747.inc \ p16f74.inc \ p16f767.inc \ p16f76.inc \ p16f777.inc \ p16f77.inc \ p16f785.inc \ p16f818.inc \ p16f819.inc \ p16f83.inc \ p16f84a.inc \ p16f84.inc \ p16f870.inc \ p16f871.inc \ p16f872.inc \ p16f873a.inc \ p16f873.inc \ p16f874a.inc \ p16f874.inc \ p16f876a.inc \ p16f876.inc \ p16f877a.inc \ p16f877.inc \ p16f87.inc \ p16f882.inc \ p16f883.inc \ p16f884.inc \ p16f886.inc \ p16f887.inc \ p16f88.inc \ p16f913.inc \ p16f914.inc \ p16f916.inc \ p16f917.inc \ p16f946.inc \ p16hv540.inc \ p16hv610.inc \ p16hv616.inc \ p16hv785.inc \ p16lf1933.inc \ p16lf1934.inc \ p16lf1936.inc \ p16lf1937.inc \ p16lf722.inc \ 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html html-am info info-am \ install install-am install-data install-data-am install-exec \ install-exec-am install-info install-info-am install-man \ install-pkgdataDATA install-strip installcheck installcheck-am \ installdirs maintainer-clean maintainer-clean-generic \ mostlyclean mostlyclean-generic pdf pdf-am ps ps-am uninstall \ uninstall-am uninstall-info-am uninstall-pkgdataDATA # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: gputils-0.13.7/header/p18f1320.inc0000644000175000017500000007342411156521301013226 00000000000000 LIST ; P18F1320.INC Standard Header File, Version 1.0 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4320 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F1320 ; 2. LIST directive in the source file ; LIST P=PIC18F1320 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;======================================================================= ; ; Revision History ; ;======================================================================= ;Rev: Date: Details: Who: ;0.10 03 June 2002 Initial release GK ;0.11 09/26/02 Include both names SWDTE and SWDTEN pas ;0.21 21 Jan 2003 Changed _MCLRE_OFF_3H from 0xEF to 0x7F BD ; Changed _MCLRE_()_3H description from RE3 to RA5 ;0.22 23Jan2003 Added RCIO, ECIO, INTIO1, INTIO2 OSC modes BD ; Commented out RCIO6, ECIO6, INTIO7, INTIO67 ; Maintains compatability to 18F4320 ;0.23 29Jan2003 Changed from BAUDCTL:W4E to WUE BD ;0.24 04Feb2003 Changed ECCPAS EQU from H'0FB8' to H'0FB6' BD ;0.25 1 Oct 2003 Bit names changed BD ; LVVn to LVDLn IVRST to IRVST ; FSCMEN to FSCM ; Bit names removed - EPWM1M1,EPWM1M0,EDC1B1, ; EDC1B0,ECCP1M3,ECCP1M2,ECCP1M1,ECCP1M0, ; Removed redundant bit names ; RCIO6 use RCIO INTIO7 use INTIO1 ; ECIO6 use ECIO INTIO67 use INTIO2 ; BKBUG use DEBUG SWDTE use SWDTEN ; T0IE use TMR0IE INT0E use INT0IE ; T0IF use TMR0IF INT0F use INT0IE ; BGST use IRVST T1INSYNC use T1SYNC ; TXD8 use TX9D T3INSYNC use T3SYNC ; TX8_9 use TX9 NOT_TX8 use TX9 ; RC9 use RX9 NOT_RC8 use RX9 ; RC8_9 use RX9 RCD8 use RX9D ; INT2P use INT2IP INT1P use INT1IP ; INT2E use INT2IE INT1E use INT1IE ; INT2F use INT2IF INT1F use INT1IF ; FLTS use IOFS STKOVF use STKFUL ; Added equates for PIC16 Compatability ; ADRES, INTF, INTE, CCPnX, CCPnY ; General clean-up (removed some comments) ;======================================================================= ; ; Verify Processor ; ;======================================================================= IFNDEF __18F1320 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;======================================================================= ; 18Fxxx Family EQUates ;======================================================================= FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;======================================================================= ; 16Cxxx/17Cxxx Substitutions ;======================================================================= #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define ADRES ADRESH ; PIC16 SFR substitution #define INTE INT0IE ; PIC16 bit substitution #define INTF INT0IF ; PIC16 bit substitution #define CCP1X DC1B1 ; PIC16 bit substitution #define CCP1Y DC1B0 ; PIC16 bit substitution #define SCS SCS0 ; PIC18 bit substitution ;======================================================================= ; ; Register Definitions ; ;======================================================================= ;----- Register Files -------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ; reserved EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' ; reserved EQU H'0FC9' ; reserved EQU H'0FC8' ; reserved EQU H'0FC7' ; reserved EQU H'0FC6' ; reserved EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' ; reserved EQU H'0FBC' ; reserved EQU H'0FBB' ; reserved EQU H'0FBA' ; reserved EQU H'0FB9' ; reserved EQU H'0FB8' PWM1CON EQU H'0FB7' ECCPAS EQU H'0FB6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' SPBRGH EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' BAUDCTL EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' ; reserved EQU H'0FB5' ; reserved EQU H'0FB4' ; reserved EQU H'0FB3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' ; reserved EQU H'0F9C' OSCTUNE EQU H'0F9B' ; reserved EQU H'0F9A' ; reserved EQU H'0F99' ; reserved EQU H'0F98' ; reserved EQU H'0F97' ; reserved EQU H'0F96' ; reserved EQU H'0F95' ; reserved EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' ; reserved EQU H'0F91' ; reserved EQU H'0F90' ; reserved EQU H'0F8F' ; reserved EQU H'0F8E' ; reserved EQU H'0F8D' ; reserved EQU H'0F8C' ; reserved EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' ; reserved EQU H'0F88' ; reserved EQU H'0F87' ; reserved EQU H'0F86' ; reserved EQU H'0F85' ; reserved EQU H'0F84' ; reserved EQU H'0F83' ; reserved EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits ----------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' SP4 EQU H'0004' SP3 EQU H'0003' SP2 EQU H'0002' SP1 EQU H'0001' SP0 EQU H'0000' ;----- INTCON Bits ----------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' INT0IE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INT0IF EQU H'0001' RBIF EQU H'0000' ;----- INTCON2 Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' RBIP EQU H'0000' ;----- INTCON3 Bits ---------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT2IE EQU H'0004' INT1IE EQU H'0003' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits ----------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits ------------------------------------------------------ TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------ IDLEN EQU H'0007' IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ;----- RCON Bits ------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits ------------------------------------------------------ RD16 EQU H'0007' T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits ------------------------------------------------------ TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- ADCON0 Bits ----------------------------------------------------- VCFG1 EQU H'0007' VCFG0 EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- PCFG6 EQU H'0006' PCFG5 EQU H'0005' PCFG4 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADFM EQU H'0007' ACQT2 EQU H'0005' ACQT1 EQU H'0004' ACQT0 EQU H'0003' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ---------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON bits ---------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits ----------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- T3CON Bits ------------------------------------------------------ RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------ CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' SENDB EQU H'0003' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------ SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- BAUDCTL Bits ------------------------------------------------------ RCIDL EQU H'0006' SCKP EQU H'0004' BRG16 EQU H'0003' WUE EQU H'0001' ABDEN EQU H'0000' ;----- EECON1 Bits ----------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- IPR2 Bits ------------------------------------------------------- OSCFIP EQU H'0007' EEIP EQU H'0004' LVDIP EQU H'0002' TMR3IP EQU H'0001' ;----- PIR2 Bits ------------------------------------------------------- OSCFIF EQU H'0007' EEIF EQU H'0004' LVDIF EQU H'0002' TMR3IF EQU H'0001' ;----- PIE2 Bits ------------------------------------------------------- OSCFIE EQU H'0007' EEIE EQU H'0004' LVDIE EQU H'0002' TMR3IE EQU H'0001' ;----- IPR1 Bits ------------------------------------------------------- ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- OSCTUNE Bits ---------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;======================================================================= ; ; I/O Pin Name Definitions ; ;======================================================================= ;----- PORTA ----------------------------------------------------------- RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 LVDIN EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 RA7 EQU 7 OSC1 EQU 7 CLKI EQU 7 ;----- PORTB ----------------------------------------------------------- RB0 EQU 0 INT0 EQU 0 AN4 EQU 0 RB1 EQU 1 INT1 EQU 1 AN5 EQU 1 TX EQU 1 CK EQU 1 RB2 EQU 2 INT2 EQU 2 P1B EQU 2 RB3 EQU 3 CCP1 EQU 3 P1A EQU 3 RB4 EQU 4 KBI0 EQU 4 AN6 EQU 4 RX EQU 4 RB5 EQU 5 KBI1 EQU 5 PGM EQU 5 RB6 EQU 6 KBI2 EQU 6 PGC EQU 6 T1OSO EQU 6 T1CKI EQU 6 T13CKI EQU 6 P1C EQU 6 RB7 EQU 7 KBI3 EQU 7 T1OSI EQU 7 PGD EQU 7 P1D EQU 7 ;======================================================================= ; ; RAM Definition ; ;======================================================================= __MAXRAM H'FFF' __BADRAM H'100'-H'F7F' __BADRAM H'F82'-H'F88',H'F8B'-H'F91',H'F94'-H'F9A',H'F9C' __BADRAM H'FA3'-H'FA5',H'FB4'-H'FB5',H'FB8'-H'FBC' __BADRAM H'FC5'-H'FC9',H'FD4' ;======================================================================= ; ; ID Location Registers ; ; The following is an assignment of address values for all of the ; ID Location registers for the purpose of table reads and writes, ; and for device programming. _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ; To use the IDLOC registers, place the following lines in your source ; code in the following format, and change as desired. ; These lines are currently commented out here and each __IDLOCS line ; should have the preceding semicolon removed when pasted into your ; source code. ; ; should take the form of B'1111bbbb' or H'Fn' ; where b = user defined bit, or n = user defined nibble. ; Program IDLOC registers ; __IDLOCS _IDLOC0, ; __IDLOCS _IDLOC1, ; __IDLOCS _IDLOC2, ; __IDLOCS _IDLOC3, ; __IDLOCS _IDLOC4, ; __IDLOCS _IDLOC5, ; __IDLOCS _IDLOC6, ; __IDLOCS _IDLOC7, ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = EC External Clock on OSC1, OSC2 as FOSC/4 ; OSC = ECIO External Clock on OSC1, OSC2 as RA6 ; OSC = HSPLL HS + PLL ; OSC = RCIO External RC on OSC1, OSC2 as RA6 ; OSC = INTIO2 Internal RC, OSC1 as RA7, OSC2 as RA6 ; OSC = INTIO1 Internal RC, OSC1 as RA7, OSC2 as FOSC/4 ; OSC = RC External RC on OSC1, OSC2 as FOSC/4 ; ; Fail-Safe Clock Monitor: ; FSCM = OFF Fail-Safe Clock Monitor disabled ; FSCM = ON Fail-Safe Clock Monitor enabled ; ; Internal External Switch Over mode: ; IESO = OFF Internal External Switch Over mode disabled ; IESO = ON Internal External Switch Over mode enabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Enable: ; MCLRE = OFF Disabled ; MCLRE = ON Enabled ; ; Stack Full/Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;======================================================================= ; ; Configuration Bits ; ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads and writes, ; and for programming configuration words. _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ; To embed the Configuration Bits in your source code, paste the ; following lines into your source code in the following format, ; and change the configuration value to the desired setting (such ; as WDT_OFF to WDT_ON). ; These lines are commented out - each __CONFIG line should have the ; preceding semicolon (;) removed when pasted into your source code. ; __CONFIG _CONFIG1H, _IESO_ON_1H & _FSCM_OFF_1H & _RC_OSC_1H ; __CONFIG _CONFIG2L, _PWRT_ON_2L & _BOR_OFF_2L & _BORV_27_2L ; __CONFIG _CONFIG2H, _WDT_OFF_2H & _WDTPS_32K_2H ; __CONFIG _CONFIG3H, _MCLRE_ON_3H ; __CONFIG _CONFIG4L, _DEBUG_OFF_4L & _LVP_ON_4L & _STVR_ON_4L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L ; __CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;Configuration Byte 1H Options _IESO_ON_1H EQU H'FF' ; Internal External Oscillator Switch Over mode enabled _IESO_OFF_1H EQU H'7F' ; Internal External Oscillator Switch Over mode disabled _FSCM_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _FSCM_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _RC_OSC_1H EQU H'FF' ; External RC on OSC1, OSC2 as FOSC/4 _RCIO_OSC_1H EQU H'F7' ; External RC on OSC1, OSC2 as RA6 _LP_OSC_1H EQU H'F0' ; LP Oscillator _XT_OSC_1H EQU H'F1' ; XT Oscillator _HS_OSC_1H EQU H'F2' ; HS Oscillator _HSPLL_OSC_1H EQU H'F6' ; HS + PLL _EC_OSC_1H EQU H'F4' ; External Clock on OSC1, OSC2 as FOSC/4 _ECIO_OSC_1H EQU H'F5' ; External Clock on OSC1, OSC2 as RA6 _INTIO1_OSC_1H EQU H'F9' ; Internal RC, OSC1 as RA7, OSC2 as FOSC/4 _INTIO2_OSC_1H EQU H'F8' ; Internal RC, OSC1 as RA7, OSC2 as RA6 ;Configuration Byte 2L Options _BORV_27_2L EQU H'FB' ; BOR Voltage - 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _PWRT_OFF_2L EQU H'FF' ; Power-up Timer disabled _PWRT_ON_2L EQU H'FE' ; Power-up Timer enabled ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enabled _WDT_OFF_2H EQU H'FE' ; Watch Dog Timer disabled _WDTPS_32K_2H EQU H'FF' ; 1:32,768 WDT Postscaler ratio _WDTPS_16K_2H EQU H'FD' ; 1:16,384 _WDTPS_8K_2H EQU H'FB' ; 1: 8,192 _WDTPS_4K_2H EQU H'F9' ; 1: 4,096 _WDTPS_2K_2H EQU H'F7' ; 1: 2,048 _WDTPS_1K_2H EQU H'F5' ; 1: 1,024 _WDTPS_512_2H EQU H'F3' ; 1: 512 _WDTPS_256_2H EQU H'F1' ; 1: 256 _WDTPS_128_2H EQU H'EF' ; 1: 128 _WDTPS_64_2H EQU H'ED' ; 1: 64 _WDTPS_32_2H EQU H'EB' ; 1: 32 _WDTPS_16_2H EQU H'E9' ; 1: 16 _WDTPS_8_2H EQU H'E7' ; 1: 8 _WDTPS_4_2H EQU H'E5' ; 1: 4 _WDTPS_2_2H EQU H'E3' ; 1: 2 _WDTPS_1_2H EQU H'E1' ; 1: 1 ;Configuration Byte 3H Options _MCLRE_ON_3H EQU H'FF' ; MCLR enabled, RA5 input disabled _MCLRE_OFF_3H EQU H'7F' ; MCLR disabled, RA5 input enabled ;Configuration Byte 4L Options _DEBUG_ON_4L EQU H'7F' ; BacKground deBUGger enabled _DEBUG_OFF_4L EQU H'FF' ; BacKground deBUGger disabled _LVP_ON_4L EQU H'FF' ; Low Voltage Prgramming enabled _LVP_OFF_4L EQU H'FB' ; Low Voltage Prgramming disabled _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enabled _STVR_OFF_4L EQU H'FE' ; Stack over/underflow Reset disabled ;Configuration Byte 5L Options ; Protect program memory blocks from programmer reads and writes (see Config Byte 6L) _CP0_ON_5L EQU H'FE' ; Block 0 protected _CP0_OFF_5L EQU H'FF' ; Block 0 readable/ may be writable _CP1_ON_5L EQU H'FD' ; Block 1 protected _CP1_OFF_5L EQU H'FF' ; Block 1 readable/ may be writable ;Configuration Byte 5H Options ; Protect blocks from programmer reads and writes (see Config Byte 6H) _CPB_ON_5H EQU H'BF' ; Boot Block protected _CPB_OFF_5H EQU H'FF' ; Boot Block readable / may be writable _CPD_ON_5H EQU H'7F' ; Data EE memory protected _CPD_OFF_5H EQU H'FF' ; Data EE memory readable / may be writable ;Configuration Byte 6L Options ; Protect program memory blocks from table writes and programmer writes _WRT0_ON_6L EQU H'FE' ; Block 0 write protected _WRT0_OFF_6L EQU H'FF' ; Block 0 writable _WRT1_ON_6L EQU H'FD' ; Block 1 write protected _WRT1_OFF_6L EQU H'FF' ; Block 1 writable ;Configuration Byte 6H Options ; Protect blocks from table writes and programmer writes _WRTC_ON_6H EQU H'DF' ; Config registers write protected _WRTC_OFF_6H EQU H'FF' ; Config registers writable _WRTB_ON_6H EQU H'BF' ; Boot block write protected _WRTB_OFF_6H EQU H'FF' ; Boot block writable _WRTD_ON_6H EQU H'7F' ; Data EE write protected _WRTD_OFF_6H EQU H'FF' ; Data EE writable ;Configuration Byte 7L Options ; Protect program memory blocks from table reads executed from other blocks _EBTR0_ON_7L EQU H'FE' ; Block 0 protected _EBTR0_OFF_7L EQU H'FF' ; Block 0 readable _EBTR1_ON_7L EQU H'FD' ; Block 1 protected _EBTR1_OFF_7L EQU H'FF' ; Block 1 readable ;Configuration Byte 7H Options ; Protect block from table reads executed in other blocks _EBTRB_ON_7H EQU H'BF' ; Boot block read protected _EBTRB_OFF_7H EQU H'FF' ; Boot block readable ;======================================================================= ; ; Device ID registers ; ; The following is an assignment of address values for the Device ID ; registers for the purpose of table reads. _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ; Device ID registers hold device ID and revision number and are ; read-only ; ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ; ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;======================================================================= LIST gputils-0.13.7/header/p16f726.inc0000644000175000017500000004776711156521301013170 00000000000000 LIST ; P16F726.INC Standard Header File, Version 2.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F726 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F726 ; 2. LIST directive in the source file ; LIST P=PIC16F726 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;0.01 10/09/06 Initial template ;0.02 10/25/07 Add 189h to BADRAM ;1.00 11/06/07 Version 1.00 (no changes) ;1.01 11/27/07 Remove 108h-109h (CPSCON0 and CPSCON1) from BADRAM ;2.00 12/18/07 Flatten include files not to include one master file ;2.01 01/31/08 Correct swapped definitions of VCAP_RA5 and VCAP_RA6 ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F726 MESSG "Processor-header file mismatch. Verify selected processor." #define __16F726 ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' T1GCON EQU H'008F' OSCCON EQU H'0090' OSCTUNE EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPMSK EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' TXSTA EQU H'0098' SPBRG EQU H'0099' APFCON EQU H'009C' FVRCON EQU H'009D' ADCON1 EQU H'009F' CPSCON0 EQU H'0108' CPSCON1 EQU H'0109' PMDATL EQU H'010C' PMDATA EQU H'010C' ; Backward compatibility only PMADRL EQU H'010D' PMADR EQU H'010D' ; Backward compatibility only PMDATH EQU H'010E' PMADRH EQU H'010F' ANSELA EQU H'0185' ANSELB EQU H'0186' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' IOCIE EQU H'0003' ;; USE IOCIE instead of RBIE to be generic T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' IOCIF EQU H'0000' ;; USE IOCIF instead of RBIF to be generic ;----- PIR1 Bits ---------------------------------------------------------- TMR1GIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1CS1 EQU H'0007' TMR1CS0 EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1X EQU H'0005' ; Backward compatibility only CCP1Y EQU H'0004' ; Backward compatibility only CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' DC2B0 EQU H'0004' CCP2X EQU H'0005' ; Backward compatibility only CCP2Y EQU H'0004' ; Backward compatibility only CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- TMR1GIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' ;; Backwards Compatability only NOT_BOR EQU H'0000' ;----- T1GCON Bits ---------------------------------------------------------- TMR1GE EQU H'0007' T1GPOL EQU H'0006' T1GTM EQU H'0005' T1GSPM EQU H'0004' T1G_NOT_DONE EQU H'0003' T1GGO_DONE EQU H'0003' T1GGO EQU H'0003' T1GVAL EQU H'0002' T1GSS1 EQU H'0001' T1GSS0 EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF1 EQU H'0005' IRCF0 EQU H'0004' ICSL EQU H'0003' ICSS EQU H'0002' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' ; Backward Compatability only WPU6 EQU H'0006' ; Backward Compatability only WPU5 EQU H'0005' ; Backward Compatability only WPU4 EQU H'0004' ; Backward Compatability only WPU3 EQU H'0003' ; Backward Compatability only WPU2 EQU H'0002' ; Backward Compatability only WPU1 EQU H'0001' ; Backward Compatability only WPU0 EQU H'0000' ; Backward Compatability only ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' ; Backward Compatability only IOC6 EQU H'0006' ; Backward Compatability only IOC5 EQU H'0005' ; Backward Compatability only IOC4 EQU H'0004' ; Backward Compatability only IOC3 EQU H'0003' ; Backward Compatability only IOC2 EQU H'0002' ; Backward Compatability only IOC1 EQU H'0001' ; Backward Compatability only IOC0 EQU H'0000' ; Backward Compatability only ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- APFCON Bits --------------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' ;----- FVRCON Bits -------------------------------------------------------- FVRST EQU H'0007' FVREN EQU H'0006' ADFVR1 EQU H'0001' ADFVR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ADREF1 EQU H'0001' ADREF0 EQU H'0000' ;----- CPSCON0 Bits --------------------------------------------------------- CPSON EQU H'0007' CPSRNG1 EQU H'0003' CPSRNG0 EQU H'0002' CPSOUT EQU H'0001' T0XCS EQU H'0000' ;----- CPSCON1 Bits --------------------------------------------------------- CPSCH3 EQU H'0003' CPSCH2 EQU H'0002' CPSCH1 EQU H'0001' CPSCH0 EQU H'0000' ;----- ANSELA Bits --------------------------------------------------------- ANSA5 EQU H'0005' ANSA4 EQU H'0004' ANSA3 EQU H'0003' ANSA2 EQU H'0002' ANSA1 EQU H'0001' ANSA0 EQU H'0000' ;----- ANSELB Bits --------------------------------------------------------- ANSB5 EQU H'0005' ANSB4 EQU H'0004' ANSB3 EQU H'0003' ANSB2 EQU H'0002' ANSB1 EQU H'0001' ANSB0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' PMRD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;----- Configuration Word 1 Bits ------------------------------------------ _DEBUG_ON EQU H'1FFF' _DEBUG_OFF EQU H'3FFF' _PLL_EN EQU H'3FFF' _PLL_DIS EQU H'2FFF' _BORV_1_9 EQU H'3FFF' _BORV_2_5 EQU H'3BFF' _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3DFF' _BOR_OFF EQU H'3CFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLR_EN EQU H'3FFF' _MCLRE_ON EQU H'3FFF' ; Backward compatibility only _MCLR_DIS EQU H'3FDF' _MCLRE_OFF EQU H'3FDF' ; Backward compatibility only _PWRT_EN EQU H'3FEF' _PWRTE_ON EQU H'3FEF' ; Backward compatibility only _PWRT_DIS EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' ; Backward compatibility only _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' ;----- Configuration Word 2 Bits ------------------------------------------ _VCAP_DIS EQU H'3FFF' _VCAP_RA6 EQU H'3FEF' _VCAP_RA5 EQU H'3FDF' _VCAP_RA0 EQU H'3FCF' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __BADRAM H'08' __BADRAM H'88' __BADRAM H'97', H'9A'-H'9B', H'9E' __BADRAM H'105'-H'107' __BADRAM H'187'-H'189', H'18D'-H'18F' LIST gputils-0.13.7/header/p16c662.inc0000644000175000017500000001442211156313161013145 00000000000000 LIST ; P16C662.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C662 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C662 ; 2. LIST directive in the source file ; LIST P=PIC16C662 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/12/96 Initial Release ;1.01 12/18/96 Modified per review ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C662 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- MPEEN EQU H'0007' NOT_PER EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'0D'-H'1E', H'8D', H'8F'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MPEEN_ON EQU H'3FFF' _MPEEN_OFF EQU H'3F7F' LIST gputils-0.13.7/header/p12f675.inc0000644000175000017500000002333711156521301013152 00000000000000 LIST ; P12F675.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F675 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12F675 ; 2. LIST directive in the source file ; LIST P=PIC12F675 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.04 07/01/02 Updated configuration bit names ;1.03 05/10/02 Corrected ADCON0 register, added IOC register ;1.02 02/28/02 Updated per datasheet ;1.01 01/31/02 Updated per datasheet ;1.00 08/24/01 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F675 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' CMCON EQU H'0019' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'0090' WPU EQU H'0095' IOC EQU H'0096' IOCB EQU H'0096' VRCON EQU H'0099' EEDATA EQU H'009A' EEDAT EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CMIF EQU H'0003' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- COMCON Bits -------------------------------------------------------- COUT EQU H'0006' CINV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CMIE EQU H'0003' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL5 EQU H'0007' CAL4 EQU H'0006' CAL3 EQU H'0005' CAL2 EQU H'0004' CAL1 EQU H'0003' CAL0 EQU H'0002' ;----- IOCB Bits -------------------------------------------------------- IOCB5 EQU H'0005' IOCB4 EQU H'0004' IOCB3 EQU H'0003' IOCB2 EQU H'0002' IOCB1 EQU H'0001' IOCB0 EQU H'0000' ;----- IOC Bits -------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'E0'-H'FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3F7F' _CP_OFF EQU H'3FFF' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18f2510.inc0000644000175000017500000011674211156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2510 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2510 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2510 ; 2. LIST directive in the source file ; LIST P=PIC18F2510 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2510 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4458.inc0000644000175000017500000015217311156521301013244 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4458 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4458 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4458 ; 2. LIST directive in the source file ; LIST P=PIC18F4458 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4458 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SPPDATA EQU H'0F62' SPPCFG EQU H'0F63' SPPEPS EQU H'0F64' SPPCON EQU H'0F65' UFRM EQU H'0F66' UFRML EQU H'0F66' UFRMH EQU H'0F67' UIR EQU H'0F68' UIE EQU H'0F69' UEIR EQU H'0F6A' UEIE EQU H'0F6B' USTAT EQU H'0F6C' UCON EQU H'0F6D' UADDR EQU H'0F6E' UCFG EQU H'0F6F' UEP0 EQU H'0F70' UEP1 EQU H'0F71' UEP2 EQU H'0F72' UEP3 EQU H'0F73' UEP4 EQU H'0F74' UEP5 EQU H'0F75' UEP6 EQU H'0F76' UEP7 EQU H'0F77' UEP8 EQU H'0F78' UEP9 EQU H'0F79' UEP10 EQU H'0F7A' UEP11 EQU H'0F7B' UEP12 EQU H'0F7C' UEP13 EQU H'0F7D' UEP14 EQU H'0F7E' UEP15 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP1AS EQU H'0FB6' ECCP1AS EQU H'0FB6' CCP1DEL EQU H'0FB7' ECCP1DEL EQU H'0FB7' BAUDCON EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SPPCFG Bits ----------------------------------------------------- WS0 EQU H'0000' WS1 EQU H'0001' WS2 EQU H'0002' WS3 EQU H'0003' CLK1EN EQU H'0004' CSEN EQU H'0005' CLKCFG0 EQU H'0006' CLKCFG1 EQU H'0007' ;----- SPPEPS Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' SPPBUSY EQU H'0004' WRSPP EQU H'0006' RDSPP EQU H'0007' ;----- SPPCON Bits ----------------------------------------------------- SPPEN EQU H'0000' SPPOWN EQU H'0001' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SPP0 EQU H'0000' SPP1 EQU H'0001' SPP2 EQU H'0002' SPP3 EQU H'0003' SPP4 EQU H'0004' SPP5 EQU H'0005' SPP6 EQU H'0006' SPP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RDPU EQU H'0007' CK1SPP EQU H'0000' CK2SPP EQU H'0001' OESPP EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SPPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SPPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SPPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' USBIE EQU H'0005' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' USBIF EQU H'0005' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' USBIP EQU H'0005' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- CCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; PLL Prescaler Selection bits: ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; ; CPU System Clock Postscaler: ; CPUDIV = OSC1_PLL2 [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] ; CPUDIV = OSC2_PLL3 [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] ; CPUDIV = OSC3_PLL4 [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] ; CPUDIV = OSC4_PLL6 [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] ; ; USB Clock Selection bit (used in Full Speed USB mode only; UCFG:FSEN = 1): ; USBDIV = 1 USB clock source comes directly from the primary oscillator block with no postscale ; USBDIV = 2 USB clock source comes from the 96 MHz PLL divided by 2 ; ; Oscillator Selection bits: ; FOSC = XT_XT XT oscillator, XT used by USB ; FOSC = XTPLL_XT XT oscillator, PLL enabled, XT used by USB ; FOSC = ECIO_EC External clock, port function on RA6, EC used by USB ; FOSC = EC_EC External clock, CLKOUT on RA6, EC used by USB ; FOSC = ECPLLIO_EC External clock, PLL enabled, port function on RA6, EC used by USB ; FOSC = ECPLL_EC External clock, PLL enabled, CLKOUT on RA6, EC used by USB ; FOSC = INTOSCIO_EC Internal oscillator, port function on RA6, EC used by USB ; FOSC = INTOSC_EC Internal oscillator, CLKOUT on RA6, EC used by USB ; FOSC = INTOSC_XT Internal oscillator, XT used by USB ; FOSC = INTOSC_HS Internal oscillator, HS used by USB ; FOSC = HS HS oscillator, HS used by USB ; FOSC = HSPLL_HS HS oscillator, PLL enabled, HS used by USB ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = ON_ACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; USB Voltage Regulator Enable bit: ; VREGEN = OFF USB voltage regulator disabled ; VREGEN = ON USB voltage regulator enabled ; ; Watchdog Timer Enable bit: ; WDT = OFF HW Disabled - SW Controlled ; WDT = ON HW Enabled - SW Disabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 input/output is multiplexed with RB3 ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPRT = OFF ICPORT disabled ; ICPRT = ON ICPORT enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 300000h ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1L Options -------------------------------------------------- _PLLDIV_1_1L EQU H'F8' ; No prescale (4 MHz oscillator input drives PLL directly) _PLLDIV_2_1L EQU H'F9' ; Divide by 2 (8 MHz oscillator input) _PLLDIV_3_1L EQU H'FA' ; Divide by 3 (12 MHz oscillator input) _PLLDIV_4_1L EQU H'FB' ; Divide by 4 (16 MHz oscillator input) _PLLDIV_5_1L EQU H'FC' ; Divide by 5 (20 MHz oscillator input) _PLLDIV_6_1L EQU H'FD' ; Divide by 6 (24 MHz oscillator input) _PLLDIV_10_1L EQU H'FE' ; Divide by 10 (40 MHz oscillator input) _PLLDIV_12_1L EQU H'FF' ; Divide by 12 (48 MHz oscillator input) _CPUDIV_OSC1_PLL2_1L EQU H'E7' ; [OSC1/OSC2 Src: /1][96 MHz PLL Src: /2] _CPUDIV_OSC2_PLL3_1L EQU H'EF' ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] _CPUDIV_OSC3_PLL4_1L EQU H'F7' ; [OSC1/OSC2 Src: /3][96 MHz PLL Src: /4] _CPUDIV_OSC4_PLL6_1L EQU H'FF' ; [OSC1/OSC2 Src: /4][96 MHz PLL Src: /6] _USBDIV_1_1L EQU H'DF' ; USB clock source comes directly from the primary oscillator block with no postscale _USBDIV_2_1L EQU H'FF' ; USB clock source comes from the 96 MHz PLL divided by 2 ;----- CONFIG1H Options -------------------------------------------------- _FOSC_XT_XT_1H EQU H'F0' ; XT oscillator, XT used by USB _FOSC_XTPLL_XT_1H EQU H'F2' ; XT oscillator, PLL enabled, XT used by USB _FOSC_ECIO_EC_1H EQU H'F4' ; External clock, port function on RA6, EC used by USB _FOSC_EC_EC_1H EQU H'F5' ; External clock, CLKOUT on RA6, EC used by USB _FOSC_ECPLLIO_EC_1H EQU H'F6' ; External clock, PLL enabled, port function on RA6, EC used by USB _FOSC_ECPLL_EC_1H EQU H'F7' ; External clock, PLL enabled, CLKOUT on RA6, EC used by USB _FOSC_INTOSCIO_EC_1H EQU H'F8' ; Internal oscillator, port function on RA6, EC used by USB _FOSC_INTOSC_EC_1H EQU H'F9' ; Internal oscillator, CLKOUT on RA6, EC used by USB _FOSC_INTOSC_XT_1H EQU H'FA' ; Internal oscillator, XT used by USB _FOSC_INTOSC_HS_1H EQU H'FB' ; Internal oscillator, HS used by USB _FOSC_HS_1H EQU H'FC' ; HS oscillator, HS used by USB _FOSC_HSPLL_HS_1H EQU H'FE' ; HS oscillator, PLL enabled, HS used by USB _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_ON_ACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting _VREGEN_OFF_2L EQU H'DF' ; USB voltage regulator disabled _VREGEN_ON_2L EQU H'FF' ; USB voltage regulator enabled ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; HW Disabled - SW Controlled _WDT_ON_2H EQU H'FF' ; HW Enabled - SW Disabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_OFF_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _ICPRT_OFF_4L EQU H'DF' ; ICPORT disabled _ICPRT_ON_4L EQU H'FF' ; ICPORT enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18c801.inc0000644000175000017500000006004711156521301013143 00000000000000 LIST ; P18C801.INC Standard Header File, Version 0.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C801 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C801 ; 2. LIST directive in the source file ; LIST P=PIC18C801 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ; Rev: Date: Details: Who: ; 0.01 11 Oct 2000 Original nr ; 0.02 09 May 2001 Added Configuration bits nr ; 0.03 13 Jun 2001 Fixed RAM map and changed config bit labels MG ; 0.04 22 Jun 2001 Fixed OSCCON bits nr ; 0.05 27 Jun 2001 Fixed LVDCON, IPR2, PIR2, PIE2 bits nr ; 0.06 12 Mar 2008 Added SWDPS0, SWDPS1, and SWDPS2 src ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C801 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' ;RESERVED_0FB5 EQU H'0FB5' ;RESERVED_0FB4 EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' CSEL2 EQU H'0FA7' CSELIO EQU H'0FA6' ;RESERVED_0FA5 EQU H'0FA5' ;RESERVED_0FA4 EQU H'0FA4' ;RESERVED_0FA3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' TRISJ EQU H'0F9A' TRISH EQU H'0F99' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' DDRJ EQU H'0F9A' DDRH EQU H'0F99' DDRG EQU H'0F98' DDRF EQU H'0F97' DDRE EQU H'0F96' DDRD EQU H'0F95' DDRC EQU H'0F94' DDRB EQU H'0F93' DDRA EQU H'0F92' LATJ EQU H'0F91' LATH EQU H'0F90' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTJ EQU H'0F88' PORTH EQU H'0F87' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' STKPTR4 EQU H'0004' STKPTR3 EQU H'0003' STKPTR2 EQU H'0002' STKPTR1 EQU H'0001' STKPTR0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- LOCK EQU H'0003' PLLEN EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- WDPS2 EQU H'0003' SWDPS2 EQU H'0003' WDPS1 EQU H'0002' SWDPS1 EQU H'0002' WDPS0 EQU H'0001' SWDPS0 EQU H'0001' SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_IPEN EQU H'0007' RI EQU H'0004' NOT_RI EQU H'0004' TO EQU H'0003' NOT_TO EQU H'0003' PD EQU H'0002' NOT_PD EQU H'0002' POR EQU H'0001' NOT_POR EQU H'0001' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCPX EQU H'0005' DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' T3SYNC EQU H'0002' NOT_T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits --------------------------------------------------------- CMLK1 EQU H'0001' CMLK0 EQU H'0000' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- MEMCON Bits ---------------------------------------------------------- EBDIS EQU H'0007' PGRM EQU H'0006' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFN EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2 EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 AD0 EQU 0 RD1 EQU 1 AD1 EQU 1 RD2 EQU 2 AD2 EQU 2 RD3 EQU 3 AD3 EQU 3 RD4 EQU 4 AD4 EQU 4 RD5 EQU 5 AD5 EQU 5 RD6 EQU 6 AD6 EQU 6 RD7 EQU 7 AD7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 AD8 EQU 0 RE1 EQU 1 AD9 EQU 1 RE2 EQU 2 AD10 EQU 2 RE3 EQU 3 AD11 EQU 3 RE4 EQU 4 AD12 EQU 4 RE5 EQU 5 AD13 EQU 5 RE6 EQU 6 AD14 EQU 6 RE7 EQU 7 AD15 EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 RF2 EQU 2 AN7 EQU 2 RF3 EQU 3 CSIO EQU 3 RF4 EQU 4 CS2 EQU 4 RF5 EQU 5 CS1 EQU 5 RF6 EQU 6 LB EQU 6 RF7 EQU 7 UB EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 ALE EQU 0 RG1 EQU 1 OE EQU 1 RG2 EQU 2 WRL EQU 2 RG3 EQU 3 WRH EQU 3 RG4 EQU 4 BA0 EQU 4 ;----- PORTH ------------------------------------------------------------------ RH0 EQU 0 A16 EQU 0 RH1 EQU 1 A17 EQU 1 RH2 EQU 2 A18 EQU 2 RH3 EQU 3 A19 EQU 3 RH4 EQU 4 AN8 EQU 4 RH5 EQU 5 AN9 EQU 5 RH6 EQU 6 AN10 EQU 6 RH7 EQU 7 AN11 EQU 7 ;----- PORTJ ------------------------------------------------------------------ RJ0 EQU 0 D0 EQU 0 RJ1 EQU 1 D1 EQU 1 RJ2 EQU 2 D2 EQU 2 RJ3 EQU 3 D3 EQU 3 RJ4 EQU 4 D4 EQU 4 RJ5 EQU 5 D5 EQU 5 RJ6 EQU 6 D6 EQU 6 RJ7 EQU 7 D7 EQU 7 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'400'-H'F7F', H'F9B', H'FA3'-H'FA5' __BADRAM H'FA8'-H'FAA', H'FB4'-H'FB9', H'FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP Oscillator ; OSC = EC EC Oscillator ; OSC = HS HS Oscillator ; OSC = RC RC Oscillator ; ; Power-up Timer: ; PWRT = ON Enable ; PWRT = OFF Disable ; ; External Bus Data Width: ; BW = 8 8-bit External Bus mode ; BW = 16 16-bit External Bus mode ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Timer Postscale Selection: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Full/Underflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG4L = Configuration Byte 4L 300006h ; ;========================================================================== ;Configuration Byte 1H Options _RC_OSC_1H EQU H'FF' _HS_OSC_1H EQU H'FE' ; Default mode. 4x PLL enabled in S/W _EC_OSC_1H EQU H'FD' ; External Clock w/OSC2 output divide by 4 _LP_OSC_1H EQU H'FC' ; Oscillator type ;Configuration Byte 2L Options _BW_16_BIT_2L EQU H'FF' ; Default bus width _BW_8_BIT_2L EQU H'BF' ; _PWRT_OFF_2L EQU H'FF' ; Disable Power-up Timer _PWRT_ON_2L EQU H'FE' ; Enable Power-up Timer ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as _HS_OSC_1H). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program _CONFIG1H ; __CONFIG _CONFIG1H, _RC_OSC_1H ;Program _CONFIG2L ; __CONFIG _CONFIG2L, _BW_16_BIT_2L & _PWRT_OFF_2L ;Program _CONFIG2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program _CONFIG4L ; __CONFIG _CONFIG4L, _STVR_ON_4L ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p16c76.inc0000644000175000017500000002771311156313161013073 00000000000000 LIST ; P16C76.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C76 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C76 ; 2. LIST directive in the source file ; LIST P=PIC16C76 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/13/96 Initial Release ;1.01 12/18/96 Modified per review ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C76 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'88'-H'89' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109', H'10C'-H'10F' __BADRAM H'185', H'187'-H'189', H'18C'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c74.inc0000644000175000017500000003025511156313161013064 00000000000000 LIST ; P16C74.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C74 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C74 ; 2. LIST directive in the source file ; LIST P=PIC16C74 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C74 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'3F8F' _CP_75 EQU H'3F9F' _CP_50 EQU H'3FAF' _CP_OFF EQU H'3FBF' _PWRTE_ON EQU H'3FBF' _PWRTE_OFF EQU H'3FB7' _WDT_ON EQU H'3FBF' _WDT_OFF EQU H'3FBB' _LP_OSC EQU H'3FBC' _XT_OSC EQU H'3FBD' _HS_OSC EQU H'3FBE' _RC_OSC EQU H'3FBF' LIST gputils-0.13.7/header/p18f25j10.inc0000644000175000017500000006631211156521301013400 00000000000000 LIST ;========================================================================== ; MPASM PIC18F25J10 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F25J10 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F25J10 ; 2. LIST directive in the source file ; LIST P=PIC18F25J10 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F25J10 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' SPBRGH EQU H'0FB0' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' VREFM EQU H'0002' VREFP EQU H'0003' SS1 EQU H'0005' CVREF EQU H'0002' C2OUT_PORTA EQU H'0005' NOT_SS1 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0006' PGD EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' T0CKI EQU H'0005' FLT0 EQU H'0000' C1OUT_PORTB EQU H'0005' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' SCL EQU H'0003' SDA EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' OSTS EQU H'0003' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' T0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0400'-H'0F7F' __BADRAM H'0F83'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB1'-H'0FB3' __BADRAM H'0FB9' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLKO function on OSC2 ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; CCP2 MUX bit: ; CCP2MX = ALTERNATE CCP2 is multiplexed with RB3 ; CCP2MX = DEFAULT CCP2 is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f67j11.inc0000644000175000017500000015027611156521301013412 00000000000000 LIST ;========================================================================== ; MPASM PIC18F67J11 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F67J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F67J11 ; 2. LIST directive in the source file ; LIST P=PIC18F67J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F67J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F5A' PMSTATL EQU H'0F5A' PMSTATH EQU H'0F5B' PMEL EQU H'0F5C' PMEN EQU H'0F5C' PMEH EQU H'0F5D' PMDIN2 EQU H'0F5E' PMDIN2L EQU H'0F5E' PMDIN2H EQU H'0F5F' PMDOUT2 EQU H'0F60' PMDOUT2L EQU H'0F60' PMDOUT2H EQU H'0F61' PMMODE EQU H'0F62' PMMODEL EQU H'0F62' PMMODEH EQU H'0F63' PMCON EQU H'0F64' PMCONL EQU H'0F64' PMCONH EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2OUT EQU H'0001' C1OUT EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7 ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled ; FOSC = EC EC Oscillator with clock out on RA6 ; FOSC = ECPLL EC Oscillator with PLL ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18c858.inc0000644000175000017500000014535411156313161013167 00000000000000 LIST ; P18C858.INC Standard Header File, Version 0.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18C858 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18C858 ; 2. LIST directive in the source file ; LIST P=PIC18C858 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ; Rev: Date: Details: Who: ; 0.01 15 May 2000 Created from 958 dj ; 0.02 06 Jun 2000 Fixed typos fn ; 0.03 11 Oct 2000 Matched register, configuration defs with nr ; PIC18CXX8 datasheet, fixed RXM1EIDH ; address mismatch ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18C858 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Cxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' ;RESERVED_0FB9 EQU H'0FB9' ;RESERVED_0FB8 EQU H'0FB8' ;RESERVED_0FB7 EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' RCREG EQU H'0FAE' TXREG EQU H'0FAD' TXSTA EQU H'0FAC' RCSTA EQU H'0FAB' ;RESERVED_0FAA EQU H'0FAA' ;RESERVED_0FA9 EQU H'0FA9' ;RESERVED_0FA8 EQU H'0FA8' ;RESERVED_0FA7 EQU H'0FA7' ;RESERVED_0FA6 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' TRISJ EQU H'0F9A' TRISH EQU H'0F99' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' DDRJ EQU H'0F9A' DDRH EQU H'0F99' DDRG EQU H'0F98' DDRF EQU H'0F97' DDRE EQU H'0F96' DDRD EQU H'0F95' DDRC EQU H'0F94' DDRB EQU H'0F93' DDRA EQU H'0F92' LATJ EQU H'0F91' LATH EQU H'0F90' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTJ EQU H'0F88' PORTH EQU H'0F87' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TRISK EQU H'0F7F' DDRK EQU H'0F7F' LATK EQU H'0F7E' PORTK EQU H'0F7D' ;TRISL EQU H'0F7C' ;DDRL EQU H'0F7C' ;LATL EQU H'0F7B' ;PORTL EQU H'0F7A' ;RESERVED_0F79 EQU H'0F79' ;RESERVED_0F78 EQU H'0F78' ;RESERVED_0F77 EQU H'0F77' TXERRCNT EQU H'0F76' RXERRCNT EQU H'0F75' COMSTAT EQU H'0F74' CIOCON EQU H'0F73' BRGCON3 EQU H'0F72' BRGCON2 EQU H'0F71' BRGCON1 EQU H'0F70' CANCON EQU H'0F6F' CANSTAT EQU H'0F6E' RXB0D7 EQU H'0F6D' RXB0D6 EQU H'0F6C' RXB0D5 EQU H'0F6B' RXB0D4 EQU H'0F6A' RXB0D3 EQU H'0F69' RXB0D2 EQU H'0F68' RXB0D1 EQU H'0F67' RXB0D0 EQU H'0F66' RXB0DLC EQU H'0F65' RXB0EIDL EQU H'0F64' RXB0EIDH EQU H'0F63' RXB0SIDL EQU H'0F62' RXB0SIDH EQU H'0F61' RXB0CON EQU H'0F60' ;RESERVED_0F5F EQU H'0F5F' CANSTAT_RO1 EQU H'0F5E' ;CANSTAT is repeated RXB1D7 EQU H'0F5D' RXB1D6 EQU H'0F5C' RXB1D5 EQU H'0F5B' RXB1D4 EQU H'0F5A' RXB1D3 EQU H'0F59' RXB1D2 EQU H'0F58' RXB1D1 EQU H'0F57' RXB1D0 EQU H'0F56' RXB1DLC EQU H'0F55' RXB1EIDL EQU H'0F54' RXB1EIDH EQU H'0F53' RXB1SIDL EQU H'0F52' RXB1SIDH EQU H'0F51' RXB1CON EQU H'0F50' ;RESERVED_0F4F EQU H'0F4F' CANSTAT_RO2 EQU H'0F4E' ;CANSTAT is repeated TXB0D7 EQU H'0F4D' TXB0D6 EQU H'0F4C' TXB0D5 EQU H'0F4B' TXB0D4 EQU H'0F4A' TXB0D3 EQU H'0F49' TXB0D2 EQU H'0F48' TXB0D1 EQU H'0F47' TXB0D0 EQU H'0F46' TXB0DLC EQU H'0F45' TXB0EIDL EQU H'0F44' TXB0EIDH EQU H'0F43' TXB0SIDL EQU H'0F42' TXB0SIDH EQU H'0F41' TXB0CON EQU H'0F40' ;RESERVED_0F3F EQU H'0F3F' CANSTAT_RO3 EQU H'0F3E' ;CANSTAT is repeated TXB1D7 EQU H'0F3D' TXB1D6 EQU H'0F3C' TXB1D5 EQU H'0F3B' TXB1D4 EQU H'0F3A' TXB1D3 EQU H'0F39' TXB1D2 EQU H'0F38' TXB1D1 EQU H'0F37' TXB1D0 EQU H'0F36' TXB1DLC EQU H'0F35' TXB1EIDL EQU H'0F34' TXB1EIDH EQU H'0F33' TXB1SIDL EQU H'0F32' TXB1SIDH EQU H'0F31' TXB1CON EQU H'0F30' ;RESERVED_0F2F EQU H'0F2F' CANSTAT_RO4 EQU H'0F2E' ;CANSTAT is repeated TXB2D7 EQU H'0F2D' TXB2D6 EQU H'0F2C' TXB2D5 EQU H'0F2B' TXB2D4 EQU H'0F2A' TXB2D3 EQU H'0F29' TXB2D2 EQU H'0F28' TXB2D1 EQU H'0F27' TXB2D0 EQU H'0F26' TXB2DLC EQU H'0F25' TXB2EIDL EQU H'0F24' TXB2EIDH EQU H'0F23' TXB2SIDL EQU H'0F22' TXB2SIDH EQU H'0F21' TXB2CON EQU H'0F20' RXM1EIDL EQU H'0F1F' RXM1EIDH EQU H'0F1E' RXM1SIDL EQU H'0F1D' RXM1SIDH EQU H'0F1C' RXM0EIDL EQU H'0F1B' RXM0EIDH EQU H'0F1A' RXM0SIDL EQU H'0F19' RXM0SIDH EQU H'0F18' RXF5EIDL EQU H'0F17' RXF5EIDH EQU H'0F16' RXF5SIDL EQU H'0F15' RXF5SIDH EQU H'0F14' RXF4EIDL EQU H'0F13' RXF4EIDH EQU H'0F12' RXF4SIDL EQU H'0F11' RXF4SIDH EQU H'0F10' RXF3EIDL EQU H'0F0F' RXF3EIDH EQU H'0F0E' RXF3SIDL EQU H'0F0D' RXF3SIDH EQU H'0F0C' RXF2EIDL EQU H'0F0B' RXF2EIDH EQU H'0F0A' RXF2SIDL EQU H'0F09' RXF2SIDH EQU H'0F08' RXF1EIDL EQU H'0F07' RXF1EIDH EQU H'0F06' RXF1SIDL EQU H'0F05' RXF1SIDH EQU H'0F04' RXF0EIDL EQU H'0F03' RXF0EIDH EQU H'0F02' RXF0SIDL EQU H'0F01' RXF0SIDH EQU H'0F00' ;----- STKPTR Bits -------------------------------------------------------- STKFUL EQU H'0007' STKUNF EQU H'0006' STKPTR4 EQU H'0004' STKPTR3 EQU H'0003' STKPTR2 EQU H'0002' STKPTR1 EQU H'0001' STKPTR0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' INTEDG3 EQU h'0003' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF INT3P EQU H'0001' RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT2P EQU H'0007' INT1IP EQU H'0006' INT1P EQU H'0006' INT3IE EQU H'0005' INT3E EQU H'0005' INT2IE EQU H'0004' INT2E EQU H'0004' INT1IE EQU H'0003' INT1E EQU H'0003' INT3IF EQU H'0002' INT3F EQU H'0002' INT2IF EQU H'0001' INT2F EQU H'0001' INT1IF EQU H'0000' INT1F EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_IPEN EQU H'0007' LWRT EQU H'0006' NOT_LWRT EQU H'0006' RI EQU H'0004' NOT_RI EQU H'0004' TO EQU H'0003' NOT_TO EQU H'0003' PD EQU H'0002' NOT_PD EQU H'0002' POR EQU H'0001' NOT_POR EQU H'0001' BOR EQU H'0000' NOT_BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' T1SYNC EQU H'0002' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DC1B1 EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DC1B0 EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DC2B1 EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCPX EQU H'0005' DC2B0 EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- VRCON Bits ------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VRSS EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CMCON Bits ------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' T3SYNC EQU H'0002' NOT_T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; Backward compatibility only TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- PSPCON Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- TXSTA Bits ------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' ;----- RCSTA Bits ------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' SREN EQU H'0005' CREN EQU H'0004' ADEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' ;----- IPR3 Bits ------------------------------------------------------- IRXIP EQU H'0007' WAKIP EQU H'0006' ERRIP EQU H'0005' TXB2IP EQU H'0004' TXB1IP EQU H'0003' TXB0IP EQU H'0002' RXB1IP EQU H'0001' RXB0IP EQU H'0000' ;----- PIR3 Bits ------------------------------------------------------- IRXIF EQU H'0007' WAKIF EQU H'0006' ERRIF EQU H'0005' TXB2IF EQU H'0004' TXB1IF EQU H'0003' TXB0IF EQU H'0002' RXB1IF EQU H'0001' RXB0IF EQU H'0000' ;----- PIE3 Bits ------------------------------------------------------- IRXIE EQU H'0007' WAKIE EQU H'0006' ERRIE EQU H'0005' TXB2IE EQU H'0004' TXB1IE EQU H'0003' TXB0IE EQU H'0002' RXB1IE EQU H'0001' RXB0IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- MEMCON Bits ---------------------------------------------------------- EBDIS EQU H'0007' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;----- TXERRCNT Bits ---------------------------------------------------------- TEC7 EQU H'0007' TEC6 EQU H'0006' TEC5 EQU H'0005' TEC4 EQU H'0004' TEC3 EQU H'0003' TEC2 EQU H'0002' TEC1 EQU H'0001' TEC0 EQU H'0000' ;----- RXERRCNT Bits ---------------------------------------------------------- REC7 EQU H'0007' REC6 EQU H'0006' REC5 EQU H'0005' REC4 EQU H'0004' REC3 EQU H'0003' REC2 EQU H'0002' REC1 EQU H'0001' REC0 EQU H'0000' ;----- COMSTAT Bits ---------------------------------------------------------- RXB0OVFL EQU H'0007' RXB1OVFL EQU H'0006' TXBO EQU H'0005' TXBP EQU H'0004' RXBP EQU H'0003' TXWARN EQU H'0002' RXWARN EQU H'0001' EWARN EQU H'0000' ;----- TXBxDLC ---------------------------------------------------------- TXRTR EQU H'0006' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DCL0 EQU H'0000' ;----- CIOCON Bits ---------------------------------------------------------- TX1SRC EQU H'0007' TX1EN EQU H'0006' ENDRHI EQU H'0005' CANCAP EQU H'0004' ;----- BRGCON1 Bits ---------------------------------------------------------- SJW1 EQU H'0007' SJW0 EQU H'0006' BRP5 EQU H'0005' BRP4 EQU H'0004' BRP3 EQU H'0003' BRP2 EQU H'0002' BRP1 EQU H'0001' BRP0 EQU H'0000' ;----- BRGCON2 Bits ---------------------------------------------------------- SEG2PHTS EQU H'0007' SAM EQU H'0006' SEG1PH2 EQU H'0005' SEG1PH1 EQU H'0004' SEG1PH0 EQU H'0003' PRSEG2 EQU H'0002' PRSEG1 EQU H'0001' PRSEG0 EQU H'0000' ;----- BRGCON3 Bits ---------------------------------------------------------- WAKFIL EQU H'0006' SEG2PH2 EQU H'0002' SEG2PH1 EQU H'0001' SEG2PH0 EQU H'0000' ;----- CANCON Bits ---------------------------------------------------------- REQOP2 EQU H'0007' REQOP1 EQU H'0006' REQOP0 EQU H'0005' ABAT EQU H'0004' WIN2 EQU H'0003' WIN1 EQU H'0002' WIN0 EQU H'0001' ;----- CANSTAT Bits ---------------------------------------------------------- OPMODE2 EQU H'0007' OPMODE1 EQU H'0006' OPMODE0 EQU H'0005' ICODE2 EQU H'0003' ICODE1 EQU H'0002' ICODE0 EQU H'0001' ;----- RXFxSIDL Bits ---------------------------------------------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' EXIDE EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXB0D7 Bits ---------------------------------------------------------- RB0D77 EQU H'0007' RB0D76 EQU H'0006' RB0D75 EQU H'0005' RB0D74 EQU H'0004' RB0D73 EQU H'0003' RB0D72 EQU H'0002' RB0D71 EQU H'0001' RB0D70 EQU H'0000' ;----- RXB0D6 Bits ---------------------------------------------------------- RB0D67 EQU H'0007' RB0D66 EQU H'0006' RB0D65 EQU H'0005' RB0D64 EQU H'0004' RB0D63 EQU H'0003' RB0D62 EQU H'0002' RB0D61 EQU H'0001' RB0D60 EQU H'0000' ;----- RXB0D5 Bits ---------------------------------------------------------- RB0D57 EQU H'0007' RB0D56 EQU H'0006' RB0D55 EQU H'0005' RB0D54 EQU H'0004' RB0D53 EQU H'0003' RB0D52 EQU H'0002' RB0D51 EQU H'0001' RB0D50 EQU H'0000' ;----- RXB0D4 Bits ---------------------------------------------------------- RB0D47 EQU H'0007' RB0D46 EQU H'0006' RB0D45 EQU H'0005' RB0D44 EQU H'0004' RB0D43 EQU H'0003' RB0D42 EQU H'0002' RB0D41 EQU H'0001' RB0D40 EQU H'0000' ;----- RXB0D3 Bits ---------------------------------------------------------- RB0D37 EQU H'0007' RB0D36 EQU H'0006' RB0D35 EQU H'0005' RB0D34 EQU H'0004' RB0D33 EQU H'0003' RB0D32 EQU H'0002' RB0D31 EQU H'0001' RB0D30 EQU H'0000' ;----- RXB0D2 Bits ---------------------------------------------------------- RB0D27 EQU H'0007' RB0D26 EQU H'0006' RB0D25 EQU H'0005' RB0D24 EQU H'0004' RB0D23 EQU H'0003' RB0D22 EQU H'0002' RB0D21 EQU H'0001' RB0D20 EQU H'0000' ;----- RXB0D1 Bits ---------------------------------------------------------- RB0D17 EQU H'0007' RB0D16 EQU H'0006' RB0D15 EQU H'0005' RB0D14 EQU H'0004' RB0D13 EQU H'0003' RB0D12 EQU H'0002' RB0D11 EQU H'0001' RB0D10 EQU H'0000' ;----- RXB0D0 Bits ---------------------------------------------------------- RB0D07 EQU H'0007' RB0D06 EQU H'0006' RB0D05 EQU H'0005' RB0D04 EQU H'0004' RB0D03 EQU H'0003' RB0D02 EQU H'0002' RB0D01 EQU H'0001' RB0D00 EQU H'0000' ;----- RXB1D7 Bits ---------------------------------------------------------- RXB1D77 EQU H'0007' RXB1D76 EQU H'0006' RXB1D75 EQU H'0005' RXB1D74 EQU H'0004' RXB1D73 EQU H'0003' RXB1D72 EQU H'0002' RXB1D71 EQU H'0001' RXB1D70 EQU H'0000' ;----- RXB1D6 Bits ---------------------------------------------------------- RXB1D67 EQU H'0007' RXB1D66 EQU H'0006' RXB1D65 EQU H'0005' RXB1D64 EQU H'0004' RXB1D63 EQU H'0003' RXB1D62 EQU H'0002' RXB1D61 EQU H'0001' RXB1D60 EQU H'0000' ;----- RXB1D5 Bits ---------------------------------------------------------- RXB1D57 EQU H'0007' RXB1D56 EQU H'0006' RXB1D55 EQU H'0005' RXB1D54 EQU H'0004' RXB1D53 EQU H'0003' RXB1D52 EQU H'0002' RXB1D51 EQU H'0001' RXB1D50 EQU H'0000' ;----- RXB1D4 Bits ---------------------------------------------------------- RXB1D47 EQU H'0007' RXB1D46 EQU H'0006' RXB1D45 EQU H'0005' RXB1D44 EQU H'0004' RXB1D43 EQU H'0003' RXB1D42 EQU H'0002' RXB1D41 EQU H'0001' RXB1D40 EQU H'0000' ;----- RXB1D3 Bits ---------------------------------------------------------- RXB1D37 EQU H'0007' RXB1D36 EQU H'0006' RXB1D35 EQU H'0005' RXB1D34 EQU H'0004' RXB1D33 EQU H'0003' RXB1D32 EQU H'0002' RXB1D31 EQU H'0001' RXB1D30 EQU H'0000' ;----- RXB1D2 Bits ---------------------------------------------------------- RXB1D27 EQU H'0007' RXB1D26 EQU H'0006' RXB1D25 EQU H'0005' RXB1D24 EQU H'0004' RXB1D23 EQU H'0003' RXB1D22 EQU H'0002' RXB1D21 EQU H'0001' RXB1D20 EQU H'0000' ;----- RXB1D1 Bits ---------------------------------------------------------- RXB1D17 EQU H'0007' RXB1D16 EQU H'0006' RXB1D15 EQU H'0005' RXB1D14 EQU H'0004' RXB1D13 EQU H'0003' RXB1D12 EQU H'0002' RXB1D11 EQU H'0001' RXB1D10 EQU H'0000' ;----- RXB1D0 Bits ---------------------------------------------------------- RXB1D07 EQU H'0007' RXB1D06 EQU H'0006' RXB1D05 EQU H'0005' RXB1D04 EQU H'0004' RXB1D03 EQU H'0003' RXB1D02 EQU H'0002' RXB1D01 EQU H'0001' RXB1D00 EQU H'0000' ;----- TXB2D7 Bits ---------------------------------------------------------- TXB2D77 EQU H'0007' TXB2D76 EQU H'0006' TXB2D75 EQU H'0005' TXB2D74 EQU H'0004' TXB2D73 EQU H'0003' TXB2D72 EQU H'0002' TXB2D71 EQU H'0001' TXB2D70 EQU H'0000' ;----- TXB2D6 Bits ---------------------------------------------------------- TXB2D67 EQU H'0007' TXB2D66 EQU H'0006' TXB2D65 EQU H'0005' TXB2D64 EQU H'0004' TXB2D63 EQU H'0003' TXB2D62 EQU H'0002' TXB2D61 EQU H'0001' TXB2D60 EQU H'0000' ;----- TXB2D5 Bits ---------------------------------------------------------- TXB2D57 EQU H'0007' TXB2D56 EQU H'0006' TXB2D55 EQU H'0005' TXB2D54 EQU H'0004' TXB2D53 EQU H'0003' TXB2D52 EQU H'0002' TXB2D51 EQU H'0001' TXB2D50 EQU H'0000' ;----- TXB2D4 Bits ---------------------------------------------------------- TXB2D47 EQU H'0007' TXB2D46 EQU H'0006' TXB2D45 EQU H'0005' TXB2D44 EQU H'0004' TXB2D43 EQU H'0003' TXB2D42 EQU H'0002' TXB2D41 EQU H'0001' TXB2D40 EQU H'0000' ;----- TXB2D3 Bits ---------------------------------------------------------- TXB2D37 EQU H'0007' TXB2D36 EQU H'0006' TXB2D35 EQU H'0005' TXB2D34 EQU H'0004' TXB2D33 EQU H'0003' TXB2D32 EQU H'0002' TXB2D31 EQU H'0001' TXB2D30 EQU H'0000' ;----- TXB2D2 Bits ---------------------------------------------------------- TXB2D27 EQU H'0007' TXB2D26 EQU H'0006' TXB2D25 EQU H'0005' TXB2D24 EQU H'0004' TXB2D23 EQU H'0003' TXB2D22 EQU H'0002' TXB2D21 EQU H'0001' TXB2D20 EQU H'0000' ;----- TXB2D1 Bits ---------------------------------------------------------- TXB2D17 EQU H'0007' TXB2D16 EQU H'0006' TXB2D15 EQU H'0005' TXB2D14 EQU H'0004' TXB2D13 EQU H'0003' TXB2D12 EQU H'0002' TXB2D11 EQU H'0001' TXB2D10 EQU H'0000' ;----- TXB2D0 Bits ---------------------------------------------------------- TXB2D07 EQU H'0007' TXB2D06 EQU H'0006' TXB2D05 EQU H'0005' TXB2D04 EQU H'0004' TXB2D03 EQU H'0003' TXB2D02 EQU H'0002' TXB2D01 EQU H'0001' TXB2D00 EQU H'0000' ;----- TXB1D7 Bits ---------------------------------------------------------- TXB1D77 EQU H'0007' TXB1D76 EQU H'0006' TXB1D75 EQU H'0005' TXB1D74 EQU H'0004' TXB1D73 EQU H'0003' TXB1D72 EQU H'0002' TXB1D71 EQU H'0001' TXB1D70 EQU H'0000' ;----- TXB1D6 Bits ---------------------------------------------------------- TXB1D67 EQU H'0007' TXB1D66 EQU H'0006' TXB1D65 EQU H'0005' TXB1D64 EQU H'0004' TXB1D63 EQU H'0003' TXB1D62 EQU H'0002' TXB1D61 EQU H'0001' TXB1D60 EQU H'0000' ;----- TXB1D5 Bits ---------------------------------------------------------- TXB1D57 EQU H'0007' TXB1D56 EQU H'0006' TXB1D55 EQU H'0005' TXB1D54 EQU H'0004' TXB1D53 EQU H'0003' TXB1D52 EQU H'0002' TXB1D51 EQU H'0001' TXB1D50 EQU H'0000' ;----- TXB1D4 Bits ---------------------------------------------------------- TXB1D47 EQU H'0007' TXB1D46 EQU H'0006' TXB1D45 EQU H'0005' TXB1D44 EQU H'0004' TXB1D43 EQU H'0003' TXB1D42 EQU H'0002' TXB1D41 EQU H'0001' TXB1D40 EQU H'0000' ;----- TXB1D3 Bits ---------------------------------------------------------- TXB1D37 EQU H'0007' TXB1D36 EQU H'0006' TXB1D35 EQU H'0005' TXB1D34 EQU H'0004' TXB1D33 EQU H'0003' TXB1D32 EQU H'0002' TXB1D31 EQU H'0001' TXB1D30 EQU H'0000' ;----- TXB1D2 Bits ---------------------------------------------------------- TXB1D27 EQU H'0007' TXB1D26 EQU H'0006' TXB1D25 EQU H'0005' TXB1D24 EQU H'0004' TBB1D23 EQU H'0003' TXB1D22 EQU H'0002' TXB1D21 EQU H'0001' TXB1D20 EQU H'0000' ;----- TXB1D1 Bits ---------------------------------------------------------- TXB1D17 EQU H'0007' TXB1D16 EQU H'0006' TXB1D15 EQU H'0005' TXB1D14 EQU H'0004' TXB1D13 EQU H'0003' TXB1D12 EQU H'0002' TXB1D11 EQU H'0001' TXB1D10 EQU H'0000' ;----- TXB1D0 Bits ---------------------------------------------------------- TXB1D07 EQU H'0007' TXB1D06 EQU H'0006' TXB1D05 EQU H'0005' TXB1D04 EQU H'0004' TXB1D03 EQU H'0003' TXB1D02 EQU H'0002' TXB1D01 EQU H'0001' TXB1D00 EQU H'0000' ;----- TXB0D7 Bits ---------------------------------------------------------- TXB0D77 EQU H'0007' TXB0D76 EQU H'0006' TXB0D75 EQU H'0005' TXB0D74 EQU H'0004' TXB0D73 EQU H'0003' TXB0D72 EQU H'0002' TXB0D71 EQU H'0001' TXB0D70 EQU H'0000' ;----- TXB0D6 Bits ---------------------------------------------------------- TXB0D67 EQU H'0007' TXB0D66 EQU H'0006' TXB0D65 EQU H'0005' TXB0D64 EQU H'0004' TXB0D63 EQU H'0003' TXB0D62 EQU H'0002' TXB0D61 EQU H'0001' TXB0D60 EQU H'0000' ;----- TXB0D5 Bits ---------------------------------------------------------- TXB0D57 EQU H'0007' TXB0D56 EQU H'0006' TXB0D55 EQU H'0005' TXB0D54 EQU H'0004' TXB0D53 EQU H'0003' TXB0D52 EQU H'0002' TXB0D51 EQU H'0001' TXB0D50 EQU H'0000' ;----- TXB0D4 Bits ---------------------------------------------------------- TXB0D47 EQU H'0007' TXB0D46 EQU H'0006' TXB0D45 EQU H'0005' TXB0D44 EQU H'0004' TXB0D43 EQU H'0003' TXB0D42 EQU H'0002' TXB0D41 EQU H'0001' TXB0D40 EQU H'0000' ;----- TXB0D3 Bits ---------------------------------------------------------- TXB0D37 EQU H'0007' TXB0D36 EQU H'0006' TXB0D35 EQU H'0005' TXB0D34 EQU H'0004' TXB0D33 EQU H'0003' TXB0D32 EQU H'0002' TXB0D31 EQU H'0001' TXB0D30 EQU H'0000' ;----- TXB0D2 Bits ---------------------------------------------------------- TXB0D27 EQU H'0007' TXB0D26 EQU H'0006' TXB0D25 EQU H'0005' TXB0D24 EQU H'0004' TXB0D23 EQU H'0003' TXB0D22 EQU H'0002' TXB0D21 EQU H'0001' TXB0D20 EQU H'0000' ;----- TXB0D1 Bits ---------------------------------------------------------- TXB0D17 EQU H'0007' TXB0D16 EQU H'0006' TXB0D15 EQU H'0005' TXB0D14 EQU H'0004' TXB0D13 EQU H'0003' TXB0D12 EQU H'0002' TXB0D11 EQU H'0001' TXB0D10 EQU H'0000' ;----- TXB0D0 Bits ---------------------------------------------------------- TXB0D07 EQU H'0007' TXB0D06 EQU H'0006' TXB0D05 EQU H'0005' TXB0D04 EQU H'0004' TXB0D03 EQU H'0003' TXB0D02 EQU H'0002' TXB0D01 EQU H'0001' TXB0D00 EQU H'0000' ;----- RXB0DLC and TXB0DLC Bits ---------------------------------------------------------- RXRTR EQU H'0006' RESB1 EQU H'0005' RESBO EQU H'0004' DLC3 EQU H'0003' DLC2 EQU H'0002' DLC1 EQU H'0001' DLC0 EQU H'0000' ;----- RXB0EIDL and RXB1EIDL Bits ---------------------------------------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXB0EIDH, RXFnEIDH, and RXMnEIDH Bits ---------------------------------------------------------- EID15 EQU H'0007' EID14 EQU H'0006' EID13 EQU H'0005' EID12 EQU H'0004' EID11 EQU H'0003' EID10 EQU H'0002' EID9 EQU H'0001' EID8 EQU H'0000' ;----- RXB0EIDL and TXB0EIDL Bits ---------------------------------------------------------- EID7 EQU H'0007' EID6 EQU H'0006' EID5 EQU H'0005' EID4 EQU H'0004' EID3 EQU H'0003' EID2 EQU H'0002' EID1 EQU H'0001' EID0 EQU H'0000' ;----- RXB0SIDL, RXFnSIDL, and RXMnSIDL Bits ---------------------------------------------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' SRR EQU H'0004' EXID EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;----- RXB0SIDH, RXFnSIDH, RXMnSIDH Bits ---------------------------------------------------------- SID10 EQU H'0007' SID9 EQU H'0006' SID8 EQU H'0005' SID7 EQU H'0004' SID6 EQU H'0003' SID5 EQU H'0002' SID4 EQU H'0001' SID3 EQU H'0001' ;----- RXB0CON Bits ---------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' RX0DBEN EQU H'0002' JTOFF EQU H'0001' FILHIT0 EQU H'0000' ;----- RXB1CON Bits ---------------------------------------------------------- RXFUL EQU H'0007' RXM1 EQU H'0006' RXM0 EQU H'0005' RXRTRRO EQU H'0003' FILHIT2 EQU H'0002' FILHIT1 EQU H'0001' ;----- TXB0CON Bits ---------------------------------------------------------- TXABT EQU H'0006' TXLARB EQU H'0005' TXERR EQU H'0004' TXREQ EQU H'0003' TXPRI1 EQU H'0001' TXPRI0 EQU H'0000' ;----- TXBnSIDL Bits ---------------------------------------------------------- SID2 EQU H'0007' SID1 EQU H'0006' SID0 EQU H'0005' EXIDE EQU H'0003' EID17 EQU H'0001' EID16 EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 SS EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLK0 EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 INT3 EQU 3 RB4 EQU 4 RB5 EQU 5 RB6 EQU 6 RB7 EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T1CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 ALE EQU 0 AN5 EQU 0 RE1 EQU 1 OE EQU 1 RE2 EQU 2 WRL EQU 2 RE3 EQU 3 WRH EQU 3 RE4 EQU 4 RE5 EQU 5 RE6 EQU 6 RE7 EQU 7 CCP2 EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 RF2 EQU 2 AN7 EQU 2 RF3 EQU 3 AN8 EQU 3 RF4 EQU 4 AN9 EQU 4 RF5 EQU 5 AN10 EQU 5 RF6 EQU 6 AN11 EQU 6 RF7 EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 CANTX1 EQU 0 RG1 EQU 1 CANTX2 EQU 1 RG2 EQU 2 CANRX EQU 2 RG3 EQU 3 RG4 EQU 4 ;----- PORTH ------------------------------------------------------------------ RH0 EQU 0 ;A16 EQU 0 RH1 EQU 1 ;A17 EQU 1 RH2 EQU 2 ;A18 EQU 2 RH3 EQU 3 ;A19 EQU 3 RH4 EQU 4 ;AN12 EQU 4 RH5 EQU 5 ;AN13 EQU 5 RH6 EQU 6 ;AN14 EQU 6 RH7 EQU 7 ;AN15 EQU 7 ;----- PORTJ ------------------------------------------------------------------ RJ0 EQU 0 RJ1 EQU 1 RJ2 EQU 2 RJ3 EQU 3 ;----- PORTK ------------------------------------------------------------------ RK0 EQU 0 RK1 EQU 1 RK2 EQU 2 RK3 EQU 3 RK4 EQU 4 RK5 EQU 5 RK6 EQU 6 RK7 EQU 7 ;========================================================================== ;========================================================================== ; ; RAM Definition ; ;========================================================================== ; __MAXRAM H'5FF' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Code Protect: ; CP = ON Enabled ; CP = OFF Disabled ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 0 300000h ; CONFIG1H = Configuration Byte 1 300001h ; CONFIG2L = Configuration Byte 3 300002h ; CONFIG2H = Configuration Byte 4 300003h ; CONFIG3L = Configuration Byte 5 300004h ; CONFIG3H = Configuration Byte 6 300005h ; CONFIG4L = Configuration Byte 7 300006h ; CONFIG4H = Configuration Byte 8 300007h ; ;========================================================================== ; ;Configuration Byte 0 Options _CP_ON_0 EQU H'00' ; Code Protect enable _CP_OFF_0 EQU H'FF' ;Configuration Byte 1 Options _OSCS_ON_1 EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1 EQU H'FF' _LP_OSC_1 EQU H'F8' ; Oscillator type _XT_OSC_1 EQU H'F9' _HS_OSC_1 EQU H'FA' _RC_OSC_1 EQU H'FB' _EC_OSC_1 EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1 EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1 EQU H'FE' ; HS PLL _RCIO_OSC_1 EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2 Options _BOR_ON_2 EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2 EQU H'FD' _PWRT_OFF_2 EQU H'FF' ; Power-up Timer enable _PWRT_ON_2 EQU H'FE' _BORV_25_2 EQU H'FF' ; BOR Voltage - 2.5v _BORV_27_2 EQU H'FB' ; 2.7v _BORV_42_2 EQU H'F7' ; 4.2v _BORV_45_2 EQU H'F3' ; 4.5v ;Configuration Byte 3 Options _WDT_ON_3 EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_3 EQU H'FE' _WDTPS_128_3 EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_3 EQU H'FD' _WDTPS_32_3 EQU H'FB' _WDTPS_16_3 EQU H'F9' _WDTPS_8_3 EQU H'F7' _WDTPS_4_3 EQU H'F5' _WDTPS_2_3 EQU H'F3' _WDTPS_1_3 EQU H'F1' ;Configuration Byte 6 Options _STVR_ON_6 EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_6 EQU H'FE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG0 EQU H'300000' _CONFIG1 EQU H'300001' _CONFIG2 EQU H'300002' _CONFIG3 EQU H'300003' _CONFIG4 EQU H'300004' _CONFIG5 EQU H'300005' _CONFIG6 EQU H'300006' _CONFIG7 EQU H'300007' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 0 ; __CONFIG _CONFIG0, _CP_OFF_0 ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _OSCS_OFF_1 & _RCIO_OSC_1 ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _BOR_ON_2 & _BORV_25_2 & _PWRT_OFF_2 ;Program Configuration Register 3 ; __CONFIG _CONFIG3, _WDT_ON_3 & _WDTPS_128_3 ;Program Configuration Register 6 ; __CONFIG _CONFIG6, _STVR_ON_6 ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 ;========================================================================== LIST gputils-0.13.7/header/p18f4539.inc0000644000175000017500000007457611156521301013256 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4539 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4539 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4539 ; 2. LIST directive in the source file ; LIST P=PIC18F4539 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4539 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' CLK0 EQU H'0006' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' CCP2_PORTE EQU H'0007' AN5 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCPX EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0002' CHS0 EQU H'0003' CHS1 EQU H'0004' CHS2 EQU H'0005' ADCS0 EQU H'0006' ADCS1 EQU H'0007' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' TMR0IP EQU H'0002' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0580'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB4'-H'0FB9' __BADRAM H'0FC0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F8' ; LP _OSC_XT_1H EQU H'F9' ; XT _OSC_HS_1H EQU H'FA' ; HS _OSC_RC_1H EQU H'FB' ; RC _OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6 ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_25_2L EQU H'FF' ; 2.5V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'F1' ; 1:1 _WDTPS_2_2H EQU H'F3' ; 1:2 _WDTPS_4_2H EQU H'F5' ; 1:4 _WDTPS_8_2H EQU H'F7' ; 1:8 _WDTPS_16_2H EQU H'F9' ; 1:16 _WDTPS_32_2H EQU H'FB' ; 1:32 _WDTPS_64_2H EQU H'FD' ; 1:64 _WDTPS_128_2H EQU H'FF' ; 1:128 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled _CP2_ON_5L EQU H'FB' ; Enabled _CP2_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled _WRT2_ON_6L EQU H'FB' ; Enabled _WRT2_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled _EBTR2_ON_7L EQU H'FB' ; Enabled _EBTR2_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2420.inc0000644000175000017500000011437511156521301013231 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2420 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2420 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2420 ; 2. LIST directive in the source file ; LIST P=PIC18F2420 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2420 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' T0CKI EQU H'0004' AN4 EQU H'0005' SS EQU H'0005' NOT_SS EQU H'0005' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' T0PS3 EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T016BIT EQU H'0006' TMR0ON EQU H'0007' PSA EQU H'0003' T08BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c774.inc0000644000175000017500000003467011156313161013160 00000000000000 LIST ; P16C774.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C774 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C774 ; 2. LIST directive in the source file ; LIST P=PIC16C774 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 08/07/98 Initial Release ;1.01 25Jan99 Fixed LVVx bits ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C774 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' REFCON EQU H'009B' LVDCON EQU H'009C' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- LVDIF EQU H'0007' BCLIF EQU H'0003' CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- LVDIE EQU H'0007' BCLIE EQU H'0003' CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- REFCON Bits -------------------------------------------------------- VRHEN EQU H'0007' VRLEN EQU H'0006' VRHOEN EQU H'0005' VRLOEN EQU H'0004' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'90', H'95'-H'97', H'9A', H'9D' __BADRAM H'105', H'107'-H'109', H'10C'-H'11F' __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CCF' _CP_75 EQU H'1DDF' _CP_50 EQU H'2EEF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f6720.inc0000644000175000017500000011243211156313161013233 00000000000000 LIST ; P18F6720.INC Standard Header File, Version .1 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC18F6720 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC18F6720 ; 2. LIST directive in the source file ; LIST P=PIC18F6720 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Details: ; 1.09 10/12/04 Added SPBRG, TXREG, TXSTA and RCSTA src ; 1.08 09/26/02 Include both names SWDTE and SWDTEN pas ; 1.07 11/16/2001 Changed CVREF_CVRCON => CVRSS, ADEN => ADDEN pas ; 1.06 10/23/01 Corrected CONFIG bits/registers, LVDCON bits tr/pas ; 1.05 10/08/01 Corrected names of T2CON and T4CON bits ; (TOUTPS3 => T2OUTPS3 and T4OUTPS3, etc.) pas ; 1.04 10/03/01 Changed T0CON bit 3 name from T0PS3 to PSA. pas ; 1.03 10/01/01 Added definitions of the CCP4, CCP5, TMR4, and ; USART2 registers (0x0F6B to 0x0F78); corrected names ; of INTCON3 bits (i.e., INT2P => INT2IP). pas Who: ; 1.02 09/18/01 Some bits have identical names in the data sheet; ; for instance, CCP2 in PORTB and CCP2 in PORTC. ; The assembler does not allow multiple definitions of ; the same name, however. So I postfixed these names ; with the name of the register to make them ; unique. (Now we have CCP2_PORTB and CCP2_PORTC). pas ; 1.01 09/14/01 Preliminary release tr ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6720 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18Fxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution #define DDRF TRISF ; PIC17Cxxx SFR substitution #define DDRG TRISG ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- TOSU EQU H'0FFF' TOSH EQU H'0FFE' TOSL EQU H'0FFD' STKPTR EQU H'0FFC' PCLATU EQU H'0FFB' PCLATH EQU H'0FFA' PCL EQU H'0FF9' TBLPTRU EQU H'0FF8' TBLPTRH EQU H'0FF7' TBLPTRL EQU H'0FF6' TABLAT EQU H'0FF5' PRODH EQU H'0FF4' PRODL EQU H'0FF3' INTCON EQU H'0FF2' INTCON1 EQU H'0FF2' INTCON2 EQU H'0FF1' INTCON3 EQU H'0FF0' INDF0 EQU H'0FEF' POSTINC0 EQU H'0FEE' POSTDEC0 EQU H'0FED' PREINC0 EQU H'0FEC' PLUSW0 EQU H'0FEB' FSR0H EQU H'0FEA' FSR0L EQU H'0FE9' WREG EQU H'0FE8' INDF1 EQU H'0FE7' POSTINC1 EQU H'0FE6' POSTDEC1 EQU H'0FE5' PREINC1 EQU H'0FE4' PLUSW1 EQU H'0FE3' FSR1H EQU H'0FE2' FSR1L EQU H'0FE1' BSR EQU H'0FE0' INDF2 EQU H'0FDF' POSTINC2 EQU H'0FDE' POSTDEC2 EQU H'0FDD' PREINC2 EQU H'0FDC' PLUSW2 EQU H'0FDB' FSR2H EQU H'0FDA' FSR2L EQU H'0FD9' STATUS EQU H'0FD8' TMR0H EQU H'0FD7' TMR0L EQU H'0FD6' T0CON EQU H'0FD5' ;RESERVED_0FD4 EQU H'0FD4' OSCCON EQU H'0FD3' LVDCON EQU H'0FD2' WDTCON EQU H'0FD1' RCON EQU H'0FD0' TMR1H EQU H'0FCF' TMR1L EQU H'0FCE' T1CON EQU H'0FCD' TMR2 EQU H'0FCC' PR2 EQU H'0FCB' T2CON EQU H'0FCA' SSPBUF EQU H'0FC9' SSPADD EQU H'0FC8' SSPSTAT EQU H'0FC7' SSPCON1 EQU H'0FC6' SSPCON2 EQU H'0FC5' ADRESH EQU H'0FC4' ADRESL EQU H'0FC3' ADCON0 EQU H'0FC2' ADCON1 EQU H'0FC1' ADCON2 EQU H'0FC0' CCPR1H EQU H'0FBF' CCPR1L EQU H'0FBE' CCP1CON EQU H'0FBD' CCPR2H EQU H'0FBC' CCPR2L EQU H'0FBB' CCP2CON EQU H'0FBA' CCPR3H EQU H'0FB9' CCPR3L EQU H'0FB8' CCP3CON EQU H'0FB7' ;RESERVED_0FB6 EQU H'0FB6' CVRCON EQU H'0FB5' CMCON EQU H'0FB4' TMR3H EQU H'0FB3' TMR3L EQU H'0FB2' T3CON EQU H'0FB1' PSPCON EQU H'0FB0' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' RCREG1 EQU H'0FAE' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' EEADRH EQU H'0FAA' EEADR EQU H'0FA9' EEDATA EQU H'0FA8' EECON2 EQU H'0FA7' EECON1 EQU H'0FA6' IPR3 EQU H'0FA5' PIR3 EQU H'0FA4' PIE3 EQU H'0FA3' IPR2 EQU H'0FA2' PIR2 EQU H'0FA1' PIE2 EQU H'0FA0' IPR1 EQU H'0F9F' PIR1 EQU H'0F9E' PIE1 EQU H'0F9D' MEMCON EQU H'0F9C' ;RESERVED_0F9B EQU H'0F9B' TRISG EQU H'0F98' TRISF EQU H'0F97' TRISE EQU H'0F96' TRISD EQU H'0F95' TRISC EQU H'0F94' TRISB EQU H'0F93' TRISA EQU H'0F92' LATG EQU H'0F8F' LATF EQU H'0F8E' LATE EQU H'0F8D' LATD EQU H'0F8C' LATC EQU H'0F8B' LATB EQU H'0F8A' LATA EQU H'0F89' PORTG EQU H'0F86' PORTF EQU H'0F85' PORTE EQU H'0F84' PORTD EQU H'0F83' PORTC EQU H'0F82' PORTB EQU H'0F81' PORTA EQU H'0F80' TMR4 EQU H'0F78' PR4 EQU H'0F77' T4CON EQU H'0F76' CCPR4H EQU H'0F75' CCPR4L EQU H'0F74' CCP4CON EQU H'0F73' CCPR5H EQU H'0F72' CCPR5L EQU H'0F71' CCP5CON EQU H'0F70' SPBRG2 EQU H'0F6F' RCREG2 EQU H'0F6E' TXREG2 EQU H'0F6D' TXSTA2 EQU H'0F6C' RCSTA2 EQU H'0F6B' ;----- STKPTR Bits -------------------------------------------------------- STKOVF EQU H'0007' STKUNF EQU H'0006' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' GIEH EQU H'0007' PEIE EQU H'0006' GIEL EQU H'0006' TMR0IE EQU H'0005' T0IE EQU H'0005' ; For backward compatibility INT0IE EQU H'0004' INT0E EQU H'0004' ; For backward compatibility RBIE EQU H'0003' TMR0IF EQU H'0002' T0IF EQU H'0002' ; For backward compatibility INT0IF EQU H'0001' INT0F EQU H'0001' ; For backward compatibility RBIF EQU H'0000' ;----- INTCON2 Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' INTEDG0 EQU H'0006' INTEDG1 EQU H'0005' INTEDG2 EQU H'0004' INTEDG3 EQU H'0003' TMR0IP EQU H'0002' T0IP EQU H'0002' ; For compatibility with T0IE and T0IF INT3P EQU H'0001' RBIP EQU H'0000' ;----- INTCON3 Bits -------------------------------------------------------- INT2IP EQU H'0007' INT1IP EQU H'0006' INT3IE EQU H'0005' INT2IE EQU H'0004' INT1IE EQU H'0003' INT3IF EQU H'0002' INT2IF EQU H'0001' INT1IF EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- N EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- T0CON Bits --------------------------------------------------------- TMR0ON EQU H'0007' T08BIT EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' T0PS2 EQU H'0002' T0PS1 EQU H'0001' T0PS0 EQU H'0000' ;----- OSCCON Bits --------------------------------------------------------- SCS EQU H'0000' ;----- LVDCON Bits --------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL3 EQU H'0003' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- WDTCON Bits --------------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- RCON Bits ----------------------------------------------------------- IPEN EQU H'0007' NOT_RI EQU H'0004' RI EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- RD16 EQU H'0007' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; For backward compatibility TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- T2OUTPS3 EQU H'0006' T2OUTPS2 EQU H'0005' T2OUTPS1 EQU H'0004' T2OUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DAT EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- SSPCON1 Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- VCFG1 EQU H'0005' VCFG0 EQU H'0004' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- ADCON2 Bits -------------------------------------------------------- ADFM EQU H'0007' ADCS2 EQU H'0002' ADCS1 EQU H'0001' ADCS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- DCCP1X EQU H'0005' CCP1X EQU H'0005' ; For backward compatibility DCCP1Y EQU H'0004' CCP1Y EQU H'0004' ; For backward compatibility CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- CCP2CON Bits ------------------------------------------------------- DCCP2X EQU H'0005' CCP2X EQU H'0005' ; For backward compatibility DCCP2Y EQU H'0004' CCP2Y EQU H'0004' ; For backward compatibility CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- CCP3CON Bits ------------------------------------------------------- DCCP3X EQU H'0005' DCCP3Y EQU H'0004' CCP3M3 EQU H'0003' CCP3M2 EQU H'0002' CCP3M1 EQU H'0001' CCP3M0 EQU H'0000' ;----- CCP4CON Bits ------------------------------------------------------- DCCP4X EQU H'0005' DCCP4Y EQU H'0004' CCP4M3 EQU H'0003' CCP4M2 EQU H'0002' CCP4M1 EQU H'0001' CCP4M0 EQU H'0000' ;----- CCP5CON Bits ------------------------------------------------------- DCCP5X EQU H'0005' DCCP5Y EQU H'0004' CCP5M3 EQU H'0003' CCP5M2 EQU H'0002' CCP5M1 EQU H'0001' CCP5M0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVRSS EQU H'0004' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT_CMCON EQU H'0007' C1OUT_CMCON EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- T3CON Bits --------------------------------------------------------- RD16 EQU H'0007' T3CCP2 EQU H'0006' T3CKPS1 EQU H'0005' T3CKPS0 EQU H'0004' T3CCP1 EQU H'0003' NOT_T3SYNC EQU H'0002' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ; For backward compatibility TMR3CS EQU H'0001' TMR3ON EQU H'0000' ;----- T4CON Bits --------------------------------------------------------- T4OUTPS3 EQU H'0006' T4OUTPS2 EQU H'0005' T4OUTPS1 EQU H'0004' T4OUTPS0 EQU H'0003' TMR4ON EQU H'0002' T4CKPS1 EQU H'0001' T4CKPS0 EQU H'0000' ;----- TXSTA, TXSTA1 and TXSTA2 Bits -------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; For backward compatibility TX8_9 EQU H'0006' ; For backward compatibility TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; For backward compatibility ;----- RCSTA, RCSTA1 and RCSTA2 Bits -------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; For backward compatibility NOT_RC8 EQU H'0006' ; For backward compatibility RC8_9 EQU H'0006' ; For backward compatibility SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; For backward compatibility ;----- IPR3 Bits ---------------------------------------------------------- RC2IP EQU H'0005' TX2IP EQU H'0004' TMR4IP EQU H'0003' CCP5IP EQU H'0002' CCP4IP EQU H'0001' CCP3IP EQU H'0000' ;----- PIR3 Bits ---------------------------------------------------------- RC2IF EQU H'0005' TX2IF EQU H'0004' TMR4IF EQU H'0003' CCP5IF EQU H'0002' CCP4IF EQU H'0001' CCP3IF EQU H'0000' ;----- PIE3 Bits ---------------------------------------------------------- RC2IE EQU H'0005' TX2IE EQU H'0004' TMR4IE EQU H'0003' CCP5IE EQU H'0002' CCP4IE EQU H'0001' CCP3IE EQU H'0000' ;----- IPR2 Bits ---------------------------------------------------------- CMIP EQU H'0006' EEIP EQU H'0004' BCLIP EQU H'0003' LVDIP EQU H'0002' TMR3IP EQU H'0001' CCP2IP EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CMIF EQU H'0006' EEIF EQU H'0004' BCLIF EQU H'0003' LVDIF EQU H'0002' TMR3IF EQU H'0001' CCP2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CMIE EQU H'0006' EEIE EQU H'0004' BCLIE EQU H'0003' LVDIE EQU H'0002' TMR3IE EQU H'0001' CCP2IE EQU H'0000' ;----- IPR1 Bits ---------------------------------------------------------- PSPIP EQU H'0007' ADIP EQU H'0006' RCIP EQU H'0005' TXIP EQU H'0004' SSPIP EQU H'0003' CCP1IP EQU H'0002' TMR2IP EQU H'0001' TMR1IP EQU H'0000' RC1IP EQU H'0005' TX1IP EQU H'0004' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' RC1IF EQU H'0005' TX1IF EQU H'0004' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' RC1IE EQU H'0005' TX1IE EQU H'0004' ;----- PSPCON Bits -------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' ;----- MEMCON Bits -------------------------------------------------------- EBDIS EQU H'0007' WAIT1 EQU H'0005' WAIT0 EQU H'0004' WM1 EQU H'0001' WM0 EQU H'0000' ;----- EECON1 Bits --------------------------------------------------------- EEPGD EQU H'0007' CFGS EQU H'0006' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; I/O Pin Name Definitions ; ;========================================================================== ;----- PORTA ------------------------------------------------------------------ RA0 EQU 0 AN0 EQU 0 RA1 EQU 1 AN1 EQU 1 RA2 EQU 2 AN2 EQU 2 VREFM EQU 2 RA3 EQU 3 AN3 EQU 3 VREFP EQU 3 RA4 EQU 4 T0CKI EQU 4 RA5 EQU 5 AN4 EQU 5 LVDIN EQU 5 RA6 EQU 6 OSC2 EQU 6 CLKO EQU 6 ;----- PORTB ------------------------------------------------------------------ RB0 EQU 0 INT0 EQU 0 RB1 EQU 1 INT1 EQU 1 RB2 EQU 2 INT2 EQU 2 RB3 EQU 3 CCP2A EQU 3 INT3 EQU 3 RB4 EQU 4 KBI0 EQU 4 RB5 EQU 5 KBI1 EQU 5 PGM EQU 5 RB6 EQU 6 KBI2 EQU 6 PGC EQU 6 RB7 EQU 7 KBI3 EQU 7 PGD EQU 7 ;----- PORTC ------------------------------------------------------------------ RC0 EQU 0 T1OSO EQU 0 T13CKI EQU 0 RC1 EQU 1 T1OSI EQU 1 CCP2 EQU 1 RC2 EQU 2 CCP1 EQU 2 RC3 EQU 3 SCK EQU 3 SCL EQU 3 RC4 EQU 4 SDI EQU 4 SDA EQU 4 RC5 EQU 5 SDO EQU 5 RC6 EQU 6 TX EQU 6 CK EQU 6 RC7 EQU 7 RX EQU 7 ;****DT EQU 7 ;*** Not Available due to conflict with ;*** Define Table (DT) directive ;----- PORTD ------------------------------------------------------------------ RD0 EQU 0 PSP0 EQU 0 RD1 EQU 1 PSP1 EQU 1 RD2 EQU 2 PSP2 EQU 2 RD3 EQU 3 PSP3 EQU 3 RD4 EQU 4 PSP4 EQU 4 RD5 EQU 5 PSP5 EQU 5 RD6 EQU 6 PSP6 EQU 6 RD7 EQU 7 PSP7 EQU 7 ;----- PORTE ------------------------------------------------------------------ RE0 EQU 0 RD EQU 0 RE1 EQU 1 WR EQU 1 RE2 EQU 2 CS EQU 2 RE3 EQU 3 RE4 EQU 4 RE5 EQU 5 RE6 EQU 6 RE7 EQU 7 CCP2C EQU 7 ;----- PORTF ------------------------------------------------------------------ RF0 EQU 0 AN5 EQU 0 RF1 EQU 1 AN6 EQU 1 C2OUT EQU 1 RF2 EQU 2 AN7 EQU 2 C1OUT EQU 2 RF3 EQU 3 AN8 EQU 3 RF4 EQU 4 AN9 EQU 4 RF5 EQU 5 AN10 EQU 5 CVREF EQU 5 RF6 EQU 6 AN11 EQU 6 RF7 EQU 7 SS EQU 7 ;----- PORTG ------------------------------------------------------------------ RG0 EQU 0 CCP3 EQU 0 RG1 EQU 1 TX2 EQU 1 CK2 EQU 1 RG2 EQU 2 RX2 EQU 2 DT2 EQU 2 RG3 EQU 3 CCP4 EQU 3 RG4 EQU 4 CCP5 EQU 4 ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FFF' __BADRAM H'F00'-H'F6A' __BADRAM H'F79'-H'F7F' __BADRAM H'F9B',H'FB6',H'FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Osc. Switch Enable: ; OSCS = ON Enabled ; OSCS = OFF Disabled ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; CCP2 MUX: ; CCP2MUX = OFF Disabled ; CCP2MUX = ON Enabled ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Code Protection Block 2: ; CP2 = ON Enabled ; CP2 = OFF Disabled ; ; Code Protection Block 3: ; CP3 = ON Enabled ; CP3 = OFF Disabled ; ; Code Protection Block 4: ; CP4 = ON Enabled ; CP4 = OFF Disabled ; ; Code Protection Block 5: ; CP5 = ON Enabled ; CP5 = OFF Disabled ; ; Code Protection Block 6: ; CP6 = ON Enabled ; CP6 = OFF Disabled ; ; Code Protection Block 7: ; CP7 = ON Enabled ; CP7 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Write Protection Block 2: ; WRT2 = ON Enabled ; WRT2 = OFF Disabled ; ; Write Protection Block 3: ; WRT3 = ON Enabled ; WRT3 = OFF Disabled ; ; Write Protection Block 4: ; WRT4 = ON Enabled ; WRT4 = OFF Disabled ; ; Write Protection Block 5: ; WRT5 = ON Enabled ; WRT5 = OFF Disabled ; ; Write Protection Block 6: ; WRT6 = ON Enabled ; WRT6 = OFF Disabled ; ; Write Protection Block 7: ; WRT7 = ON Enabled ; WRT7 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Table Read Protection Block 2: ; EBTR2 = ON Enabled ; EBTR2 = OFF Disabled ; ; Table Read Protection Block 3: ; EBTR3 = ON Enabled ; EBTR3 = OFF Disabled ; ; Table Read Protection Block 4: ; EBTR4 = ON Enabled ; EBTR4 = OFF Disabled ; ; Table Read Protection Block 5: ; EBTR5 = ON Enabled ; EBTR5 = OFF Disabled ; ; Table Read Protection Block 6: ; EBTR6 = ON Enabled ; EBTR6 = OFF Disabled ; ; Table Read Protection Block 7: ; EBTR7 = ON Enabled ; EBTR7 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; Data Sheet Include File Address ; CONFIG1L = Configuration Byte 1L 300000h ; CONFIG1H = Configuration Byte 1H 300001h ; CONFIG2L = Configuration Byte 2L 300002h ; CONFIG2H = Configuration Byte 2H 300003h ; CONFIG3L = Configuration Byte 3L 300004h ; CONFIG3H = Configuration Byte 3H 300005h ; CONFIG4L = Configuration Byte 4L 300006h ; CONFIG4H = Configuration Byte 4H 300007h ; CONFIG5L = Configuration Byte 5L 300008h ; CONFIG5H = Configuration Byte 5H 300009h ; CONFIG6L = Configuration Byte 6L 30000ah ; CONFIG6H = Configuration Byte 6H 30000bh ; CONFIG7L = Configuration Byte 7L 30000ch ; CONFIG7H = Configuration Byte 7H 30000dh ; ;========================================================================== ;Configuration Byte 1H Options _OSCS_ON_1H EQU H'DF' ; Oscillator Switch enable _OSCS_OFF_1H EQU H'FF' _LP_OSC_1H EQU H'F8' ; Oscillator type _XT_OSC_1H EQU H'F9' _HS_OSC_1H EQU H'FA' _RC_OSC_1H EQU H'FB' _EC_OSC_1H EQU H'FC' ; External Clock w/OSC2 output divide by 4 _ECIO_OSC_1H EQU H'FD' ; w/OSC2 as an IO pin (RA6) _HSPLL_OSC_1H EQU H'FE' ; HS PLL _RCIO_OSC_1H EQU H'FF' ; RC w/OSC2 as an IO pin (RA6) ;Configuration Byte 2L Options _BOR_ON_2L EQU H'FF' ; Brown-out Reset enable _BOR_OFF_2L EQU H'FD' _PWRT_OFF_2L EQU H'FF' ; Power-up Timer enable _PWRT_ON_2L EQU H'FE' _BORV_20_2L EQU H'FF' ; BOR Voltage - 2.0v _BORV_27_2L EQU H'FB' ; 2.7v _BORV_42_2L EQU H'F7' ; 4.2v _BORV_45_2L EQU H'F3' ; 4.5v ;Configuration Byte 2H Options _WDT_ON_2H EQU H'FF' ; Watch Dog Timer enable _WDT_OFF_2H EQU H'FE' _WDTPS_128_2H EQU H'FF' ; Watch Dog Timer PostScaler count _WDTPS_64_2H EQU H'FD' _WDTPS_32_2H EQU H'FB' _WDTPS_16_2H EQU H'F9' _WDTPS_8_2H EQU H'F7' _WDTPS_4_2H EQU H'F5' _WDTPS_2_2H EQU H'F3' _WDTPS_1_2H EQU H'F1' ;Configuration Byte 3L Options _MC_MODE_3L EQU H'FF' ; Processor Mode Select bits _MP_MODE_3L EQU H'FE' _MPB_MODE_3L EQU H'FD' _XMC_MODE_3L EQU H'FC' _WAIT_ON_3L EQU H'7F' ; External Bus Data Wait Enable _WAIT_OFF_3L EQU H'FF' ;Configuration Byte 3H Options _CCP2MX_ON_3H EQU H'FF' ; CCP2 pin MUX enable _CCP2MX_OFF_3H EQU H'FE' ;Configuration Byte 4L Options _STVR_ON_4L EQU H'FF' ; Stack over/underflow Reset enable _STVR_OFF_4L EQU H'FE' _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enable _LVP_OFF_4L EQU H'FB' _DEBUG_ON_4L EQU H'7F' ; Backgound Debugger enable _DEBUG_OFF_4L EQU H'FF' ;Configuration Byte 5L Options _CP0_ON_5L EQU H'FE' ; Code protect user block enable _CP0_OFF_5L EQU H'FF' _CP1_ON_5L EQU H'FD' _CP1_OFF_5L EQU H'FF' _CP2_ON_5L EQU H'FB' _CP2_OFF_5L EQU H'FF' _CP3_ON_5L EQU H'F7' _CP3_OFF_5L EQU H'FF' _CP4_ON_5L EQU H'EF' _CP4_OFF_5L EQU H'FF' _CP5_ON_5L EQU H'DF' _CP5_OFF_5L EQU H'FF' _CP6_ON_5L EQU H'BF' _CP6_OFF_5L EQU H'FF' _CP7_ON_5L EQU H'7F' _CP7_OFF_5L EQU H'FF' ;Configuration Byte 5H Options _CPB_ON_5H EQU H'BF' ; Code protect boot block enable _CPB_OFF_5H EQU H'FF' _CPD_ON_5H EQU H'7F' ; Code protect Data EE enable _CPD_OFF_5H EQU H'FF' ;Configuration Byte 6L Options _WRT0_ON_6L EQU H'FE' ; Write protect user block enable _WRT0_OFF_6L EQU H'FF' _WRT1_ON_6L EQU H'FD' _WRT1_OFF_6L EQU H'FF' _WRT2_ON_6L EQU H'FB' _WRT2_OFF_6L EQU H'FF' _WRT3_ON_6L EQU H'F7' _WRT3_OFF_6L EQU H'FF' _WRT4_ON_6L EQU H'EF' _WRT4_OFF_6L EQU H'FF' _WRT5_ON_6L EQU H'DF' _WRT5_OFF_6L EQU H'FF' _WRT6_ON_6L EQU H'BF' _WRT6_OFF_6L EQU H'FF' _WRT7_ON_6L EQU H'7F' _WRT7_OFF_6L EQU H'FF' ;Configuration Byte 6H Options _WRTC_ON_6H EQU H'DF' ; Write protect CONFIG regs enable _WRTC_OFF_6H EQU H'FF' _WRTB_ON_6H EQU H'BF' ; Write protect boot block enable _WRTB_OFF_6H EQU H'FF' _WRTD_ON_6H EQU H'7F' ; Write protect Data EE enable _WRTD_OFF_6H EQU H'FF' ;Configuration Byte 7L Options _EBTR0_ON_7L EQU H'FE' ; Table Read protect user block enable _EBTR0_OFF_7L EQU H'FF' _EBTR1_ON_7L EQU H'FD' _EBTR1_OFF_7L EQU H'FF' _EBTR2_ON_7L EQU H'FB' _EBTR2_OFF_7L EQU H'FF' _EBTR3_ON_7L EQU H'F7' _EBTR3_OFF_7L EQU H'FF' _EBTR4_ON_7L EQU H'EF' _EBTR4_OFF_7L EQU H'FF' _EBTR5_ON_7L EQU H'DF' _EBTR5_OFF_7L EQU H'FF' _EBTR6_ON_7L EQU H'BF' _EBTR6_OFF_7L EQU H'FF' _EBTR7_ON_7L EQU H'7F' _EBTR7_OFF_7L EQU H'FF' ;Configuration Byte 7H Options _EBTRB_ON_7H EQU H'BF' ; Table Read protect boot block enable _EBTRB_OFF_7H EQU H'FF' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ON). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ; The following is a assignment of address values for all of the configuration ; registers for the purpose of table reads _CONFIG1L EQU H'300000' _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG4H EQU H'300007' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' ;Program Configuration Register 1H ; __CONFIG _CONFIG1H, _OSCS_OFF_1H & _RCIO_OSC_1H ;Program Configuration Register 2L ; __CONFIG _CONFIG2L, _BOR_ON_2L & _BORV_20_2L & _PWRT_OFF_2L ;Program Configuration Register 2H ; __CONFIG _CONFIG2H, _WDT_ON_2H & _WDTPS_128_2H ;Program Configuration Register 3L ; __CONFIG _CONFIG3L, _WAIT_OFF_3L & _MC_MODE_3L ;Program Configuration Register 3H ; __CONFIG _CONFIG3H, _CCP2MX_ON_3H ;Program Configuration Register 4L ; __CONFIG _CONFIG4L, _STVR_ON_4L & _LVP_OFF_4L & _DEBUG_OFF_4L ;Program Configuration Register 5L ; __CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L & _CP2_OFF_5L & _CP3_OFF_5L & _CP4_OFF_5L & _CP5_OFF_5L & _CP6_OFF_5L & _CP7_OFF_5L ;Program Configuration Register 5H ; __CONFIG _CONFIG5H, _CPB_ON_5H & _CPD_OFF_5H ;Program Configuration Register 6L ; __CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L & _WRT2_OFF_6L & _WRT3_OFF_6L & _WRT4_OFF_6L & _WRT5_OFF_6L & _WRT6_OFF_6L & _WRT7_OFF_6L ;Program Configuration Register 6H ; __CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H ;Program Configuration Register 7L ; __CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L & _EBTR2_OFF_7L & _EBTR3_OFF_7L & _EBTR4_OFF_7L & _EBTR5_OFF_7L & _EBTR6_OFF_7L & _EBTR7_OFF_7L ;Program Configuration Register 7H ; __CONFIG _CONFIG7H, _EBTRB_OFF_7H ;ID Locations Register 0 ; __IDLOCS _IDLOC0, ;ID Locations Register 1 ; __IDLOCS _IDLOC1, ;ID Locations Register 2 ; __IDLOCS _IDLOC2, ;ID Locations Register 3 ; __IDLOCS _IDLOC3, ;ID Locations Register 4 ; __IDLOCS _IDLOC4, ;ID Locations Register 5 ; __IDLOCS _IDLOC5, ;ID Locations Register 6 ; __IDLOCS _IDLOC6, ;ID Locations Register 7 ; __IDLOCS _IDLOC7, ;Device ID registers hold device ID and revision number and can only be read ;Device ID Register 1 ; DEV2, DEV1, DEV0, REV4, REV3, REV2, REV1, REV0 ;Device ID Register 2 ; DEV10, DEV9, DEV8, DEV7, DEV6, DEV5, DEV4, DEV3 LIST gputils-0.13.7/header/p12c671.inc0000644000175000017500000001436011156313161013142 00000000000000 LIST ; P12C671.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12C671 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C671 ; 2. LIST directive in the source file ; LIST P=PIC12C671 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.03 07/22/97 Corrected BADRAM ;1.02 05/12/97 Corrected configuration bits, RAM map ;1.01 12/18/96 Modified per review ;1.00 11/12/96 Original ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12C671 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'008F' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- OSCCAL Bits -------------------------------------------------------- CAL3 EQU H'0007' CAL2 EQU H'0006' CAL1 EQU H'0005' CAL0 EQU H'0004' CALFST EQU H'0003' CALSLW EQU H'0002' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D'-H'1D' __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3F7F' _CP_ALL EQU H'009F' _CP_75 EQU H'15BF' _CP_50 EQU H'2ADF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _INTRC_OSC EQU H'3FFC' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC EQU H'3FFE' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18f8490.inc0000644000175000017500000017646211156521301013253 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8490 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8490 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8490 ; 2. LIST directive in the source file ; LIST P=PIC18F8490 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8490 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- LCDPS EQU H'0F58' LCDCON EQU H'0F59' LCDSE0 EQU H'0F5A' LCDSE1 EQU H'0F5B' LCDSE2 EQU H'0F5C' LCDSE3 EQU H'0F5D' LCDSE4 EQU H'0F5E' LCDSE5 EQU H'0F5F' LCDDATA0 EQU H'0F60' LCDDATA1 EQU H'0F61' LCDDATA2 EQU H'0F62' LCDDATA3 EQU H'0F63' LCDDATA4 EQU H'0F64' LCDDATA5 EQU H'0F65' LCDDATA6 EQU H'0F66' LCDDATA7 EQU H'0F67' LCDDATA8 EQU H'0F68' LCDDATA9 EQU H'0F69' LCDDATA10 EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' LCDDATA11 EQU H'0F70' LCDDATA12 EQU H'0F71' LCDDATA13 EQU H'0F72' LCDDATA14 EQU H'0F73' LCDDATA15 EQU H'0F74' LCDDATA16 EQU H'0F75' LCDDATA17 EQU H'0F76' LCDDATA18 EQU H'0F77' LCDDATA19 EQU H'0F78' LCDDATA20 EQU H'0F79' LCDDATA21 EQU H'0F7A' LCDDATA22 EQU H'0F7B' LCDDATA23 EQU H'0F7C' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SE33 EQU H'0001' SE34 EQU H'0002' SE35 EQU H'0003' SE36 EQU H'0004' SE37 EQU H'0005' SE38 EQU H'0006' SE39 EQU H'0007' SEGEN32 EQU H'0000' SEGEN33 EQU H'0001' SEGEN34 EQU H'0002' SEGEN35 EQU H'0003' SEGEN36 EQU H'0004' SEGEN37 EQU H'0005' SEGEN38 EQU H'0006' SEGEN39 EQU H'0007' ;----- LCDSE5 Bits ----------------------------------------------------- SE40 EQU H'0000' SE41 EQU H'0001' SE42 EQU H'0002' SE43 EQU H'0003' SE44 EQU H'0004' SE45 EQU H'0005' SE46 EQU H'0006' SE47 EQU H'0007' SEGEN40 EQU H'0000' SEGEN41 EQU H'0001' SEGEN42 EQU H'0002' SEGEN43 EQU H'0003' SEGEN44 EQU H'0004' SEGEN45 EQU H'0005' SEGEN46 EQU H'0006' SEGEN47 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' S33C0 EQU H'0001' S34C0 EQU H'0002' S35C0 EQU H'0003' S36C0 EQU H'0004' S37C0 EQU H'0005' S38C0 EQU H'0006' S39C0 EQU H'0007' SEG32COM0 EQU H'0000' SEG33COM0 EQU H'0001' SEG34COM0 EQU H'0002' SEG35COM0 EQU H'0003' SEG36COM0 EQU H'0004' SEG37COM0 EQU H'0005' SEG38COM0 EQU H'0006' SEG39COM0 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- S40C0 EQU H'0000' S41C0 EQU H'0001' S42C0 EQU H'0002' S43C0 EQU H'0003' S44C0 EQU H'0004' S45C0 EQU H'0005' S46C0 EQU H'0006' S47C0 EQU H'0007' SEG40COM0 EQU H'0000' SEG41COM0 EQU H'0001' SEG42COM0 EQU H'0002' SEG43COM0 EQU H'0003' SEG44COM0 EQU H'0004' SEG45COM0 EQU H'0005' SEG46COM0 EQU H'0006' SEG47COM0 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' S33C1 EQU H'0001' S34C1 EQU H'0002' S35C1 EQU H'0003' S36C1 EQU H'0004' S37C1 EQU H'0005' S38C1 EQU H'0006' S39C1 EQU H'0007' SEG32COM1 EQU H'0000' SEG33COM1 EQU H'0001' SEG34COM1 EQU H'0002' SEG35COM1 EQU H'0003' SEG36COM1 EQU H'0004' SEG37COM1 EQU H'0005' SEG38COM1 EQU H'0006' SEG39COM1 EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- LCDDATA11 Bits ----------------------------------------------------- S40C1 EQU H'0000' S41C1 EQU H'0001' S42C1 EQU H'0002' S43C1 EQU H'0003' S44C1 EQU H'0004' S45C1 EQU H'0005' S46C1 EQU H'0006' S47C1 EQU H'0007' SEG40COM1 EQU H'0000' SEG41COM1 EQU H'0001' SEG42COM1 EQU H'0002' SEG43COM1 EQU H'0003' SEG44COM1 EQU H'0004' SEG45COM1 EQU H'0005' SEG46COM1 EQU H'0006' SEG47COM1 EQU H'0007' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' S33C2 EQU H'0001' S34C2 EQU H'0002' S35C2 EQU H'0003' S36C2 EQU H'0004' S37C2 EQU H'0005' S38C2 EQU H'0006' S39C2 EQU H'0007' SEG32COM2 EQU H'0000' SEG33COM2 EQU H'0001' SEG34COM2 EQU H'0002' SEG35COM2 EQU H'0003' SEG36COM2 EQU H'0004' SEG37COM2 EQU H'0005' SEG38COM2 EQU H'0006' SEG39COM2 EQU H'0007' ;----- LCDDATA17 Bits ----------------------------------------------------- S40C2 EQU H'0000' S41C2 EQU H'0001' S42C2 EQU H'0002' S43C2 EQU H'0003' S44C2 EQU H'0004' S45C2 EQU H'0005' S46C2 EQU H'0006' S47C2 EQU H'0007' SEG40COM2 EQU H'0000' SEG41COM2 EQU H'0001' SEG42COM2 EQU H'0002' SEG43COM2 EQU H'0003' SEG44COM2 EQU H'0004' SEG45COM2 EQU H'0005' SEG46COM2 EQU H'0006' SEG47COM2 EQU H'0007' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' S33C3 EQU H'0001' S34C3 EQU H'0002' S35C3 EQU H'0003' S36C3 EQU H'0004' S37C3 EQU H'0005' S38C3 EQU H'0006' S39C3 EQU H'0007' SEG32COM3 EQU H'0000' SEG33COM3 EQU H'0001' SEG34COM3 EQU H'0002' SEG35COM3 EQU H'0003' SEG36COM3 EQU H'0004' SEG37COM3 EQU H'0005' SEG38COM3 EQU H'0006' SEG39COM3 EQU H'0007' ;----- LCDDATA23 Bits ----------------------------------------------------- S40C3 EQU H'0000' S41C3 EQU H'0001' S42C3 EQU H'0002' S43C3 EQU H'0003' S44C3 EQU H'0004' S45C3 EQU H'0005' S46C3 EQU H'0006' S47C3 EQU H'0007' SEG40COM3 EQU H'0000' SEG41COM3 EQU H'0001' SEG42COM3 EQU H'0002' SEG43COM3 EQU H'0003' SEG44COM3 EQU H'0004' SEG45COM3 EQU H'0005' SEG46COM3 EQU H'0006' SEG47COM3 EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SEG16 EQU H'0002' SEG17 EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' SEG13 EQU H'0002' SEG12 EQU H'0003' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' LCDBIAS3 EQU H'0002' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' SEG31 EQU H'0007' BIAS1 EQU H'0000' BIAS2 EQU H'0001' BIAS3 EQU H'0002' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' SEG18 EQU H'0000' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' SEG30 EQU H'0000' SEG29 EQU H'0001' SEG28 EQU H'0002' SEG27 EQU H'0003' SEG26 EQU H'0004' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' SEG47 EQU H'0000' SEG46 EQU H'0001' SEG45 EQU H'0002' SEG44 EQU H'0003' SEG40 EQU H'0004' SEG41 EQU H'0005' SEG42 EQU H'0006' SEG43 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' SEG32 EQU H'0000' SEG33 EQU H'0001' SEG34 EQU H'0002' SEG35 EQU H'0003' SEG39 EQU H'0004' SEG38 EQU H'0005' SEG37 EQU H'0006' SEG36 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F7D' __BADRAM H'0F9C' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB6'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block (000000-003FFFh) code-protected ; CP = OFF Program memory block (000000-003FFFh) not code-protected ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block (000000-003FFFh) code-protected _CP_OFF_5L EQU H'FF' ; Program memory block (000000-003FFFh) not code-protected _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f2423.inc0000644000175000017500000011546311156521301013233 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2423 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2423 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2423 ; 2. LIST directive in the source file ; LIST P=PIC18F2423 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2423 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFN EQU H'0002' VREFP EQU H'0003' C1OUT_PORTA EQU H'0004' SS EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF EQU H'0002' NOT_SS EQU H'0005' HLVDIN EQU H'0005' LVDIN EQU H'0005' C2OUT_PORTA EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' HLVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' LVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' HLVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' LVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' HLVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' LVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RXDTP EQU H'0005' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = PORTB CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTB_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16hv540.inc0000644000175000017500000000655311156313161013341 00000000000000 LIST ; P16HV540.INC Standard Header File, Version 4.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the 16HV540 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; There is one group of symbols that is valid for all microcontrollers. ; Each microcontroller in this family also has its own section of special ; symbols. Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P16HV540 ; 2. LIST directive in the source file ; LIST P=16HV540 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 10 Feb 1999 initial release. ;========================================================================== ; ; Generic Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' ;----- STATUS Bits -------------------------------------------------------- PCF EQU H'0007' PA1 EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OPTION2 Bits -------------------------------------------------------- WPC EQU H'0005' SWE EQU H'0004' RL EQU H'0003' SL EQU H'0002' BL EQU H'0001' BE EQU H'0000' __MAXRAM H'01F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _HS_OSC EQU H'0FFE' _RC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16c65b.inc0000644000175000017500000002712711156313161013232 00000000000000 LIST ; P16C65B.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C65B microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C65B ; 2. LIST directive in the source file ; LIST P=PIC16C65B ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/17/97 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C65B MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c64a.inc0000644000175000017500000002213711156313161013224 00000000000000 LIST ; P16C64A.INC Standard Header File, Version 1.02 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C64A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C64A ; 2. LIST directive in the source file ; LIST P=PIC16C64A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.02 04/22/96 Added TRISE bits ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C64A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'BF' __BADRAM H'0D', H'18'-H'1F', H'8D', H'8F'-H'91', H'95'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f77.inc0000644000175000017500000003145411156313161013074 00000000000000 LIST ; P16F77.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F77 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F77 ; 2. LIST directive in the source file ; LIST P=PIC16F77 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 00/00/00 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F77 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18D'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f26j11.inc0000644000175000017500000014654711156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F26J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F26J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F26J11 ; 2. LIST directive in the source file ; LIST P=PIC18F26J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F26J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ULPWU EQU H'0000' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F65' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select : ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR : ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f4321.inc0000644000175000017500000012153111156521301013223 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4321 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4321 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4321 ; 2. LIST directive in the source file ; LIST P=PIC18F4321 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4321 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1N EQU H'0000' C2N EQU H'0001' C2P EQU H'0002' C1P EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' HLVDIN EQU H'0005' CVREF EQU H'0002' T0CKI EQU H'0004' NOT_SS EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' P1B EQU H'0005' P1C EQU H'0006' P1D EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' MCLR EQU H'0003' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' NOT_MCLR EQU H'0003' VPP EQU H'0003' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T016BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' T0IF EQU H'0002' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = RB3 CCP2 input/output is multiplexed with RB3 ; CCP2MX = RC1 CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPORT = OFF ICPORT disabled ; ICPORT = ON ICPORT enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Word ; BBSIZ = BB512 512 Word ; BBSIZ = BB1K 1024 Word ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP Oscillator _OSC_XT_1H EQU H'F1' ; XT Oscillator _OSC_HS_1H EQU H'F2' ; HS Oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO2_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO1_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_DIG_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ANA_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_RB3_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_RC1_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _ICPORT_OFF_4L EQU H'F7' ; ICPORT disabled _ICPORT_ON_4L EQU H'FF' ; ICPORT enabled _BBSIZ_BB256_4L EQU H'CF' ; 256 Word _BBSIZ_BB512_4L EQU H'DF' ; 512 Word _BBSIZ_BB1K_4L EQU H'FF' ; 1024 Word _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f4439.inc0000644000175000017500000007346111156521301013245 00000000000000 LIST ;========================================================================== ; MPASM PIC18F4439 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F4439 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F4439 ; 2. LIST directive in the source file ; LIST P=PIC18F4439 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F4439 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' CLK0 EQU H'0006' LVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T1CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' CCP2_PORTE EQU H'0007' AN5 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' DCCPX EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0002' CHS0 EQU H'0003' CHS1 EQU H'0004' CHS2 EQU H'0005' ADCS0 EQU H'0006' ADCS1 EQU H'0007' NOT_DONE EQU H'0002' DONE EQU H'0002' GO_DONE EQU H'0002' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_LWRT EQU H'0006' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' LWRT EQU H'0006' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' TMR0IP EQU H'0002' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0280'-H'0F7F' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8E'-H'0F91' __BADRAM H'0F97'-H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB0' __BADRAM H'0FB4'-H'0FB9' __BADRAM H'0FC0' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection: ; OSC = LP LP ; OSC = XT XT ; OSC = HS HS ; OSC = RC RC ; OSC = EC EC-OSC2 as Clock Out ; OSC = ECIO EC-OSC2 as RA6 ; OSC = HSPLL HS-PLL Enabled ; OSC = RCIO RC-OSC2 as RA6 ; ; Power-up Timer: ; PWRT = ON Enabled ; PWRT = OFF Disabled ; ; Brown-out Reset: ; BOR = OFF Disabled ; BOR = ON Enabled ; ; Brown-out Voltage: ; BORV = 45 4.5V ; BORV = 42 4.2V ; BORV = 27 2.7V ; BORV = 25 2.5V ; ; Watchdog Timer: ; WDT = OFF Disabled ; WDT = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; ; Stack Overflow Reset: ; STVR = OFF Disabled ; STVR = ON Enabled ; ; Low Voltage ICSP: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Background Debugger Enable: ; DEBUG = ON Enabled ; DEBUG = OFF Disabled ; ; Code Protection Block 0: ; CP0 = ON Enabled ; CP0 = OFF Disabled ; ; Code Protection Block 1: ; CP1 = ON Enabled ; CP1 = OFF Disabled ; ; Boot Block Code Protection: ; CPB = ON Enabled ; CPB = OFF Disabled ; ; Data EEPROM Code Protection: ; CPD = ON Enabled ; CPD = OFF Disabled ; ; Write Protection Block 0: ; WRT0 = ON Enabled ; WRT0 = OFF Disabled ; ; Write Protection Block 1: ; WRT1 = ON Enabled ; WRT1 = OFF Disabled ; ; Boot Block Write Protection: ; WRTB = ON Enabled ; WRTB = OFF Disabled ; ; Configuration Register Write Protection: ; WRTC = ON Enabled ; WRTC = OFF Disabled ; ; Data EEPROM Write Protection: ; WRTD = ON Enabled ; WRTD = OFF Disabled ; ; Table Read Protection Block 0: ; EBTR0 = ON Enabled ; EBTR0 = OFF Disabled ; ; Table Read Protection Block 1: ; EBTR1 = ON Enabled ; EBTR1 = OFF Disabled ; ; Boot Block Table Read Protection: ; EBTRB = ON Enabled ; EBTRB = OFF Disabled ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F8' ; LP _OSC_XT_1H EQU H'F9' ; XT _OSC_HS_1H EQU H'FA' ; HS _OSC_RC_1H EQU H'FB' ; RC _OSC_EC_1H EQU H'FC' ; EC-OSC2 as Clock Out _OSC_ECIO_1H EQU H'FD' ; EC-OSC2 as RA6 _OSC_HSPLL_1H EQU H'FE' ; HS-PLL Enabled _OSC_RCIO_1H EQU H'FF' ; RC-OSC2 as RA6 ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; Enabled _PWRT_OFF_2L EQU H'FF' ; Disabled _BOR_OFF_2L EQU H'FD' ; Disabled _BOR_ON_2L EQU H'FF' ; Enabled _BORV_45_2L EQU H'F3' ; 4.5V _BORV_42_2L EQU H'F7' ; 4.2V _BORV_27_2L EQU H'FB' ; 2.7V _BORV_25_2L EQU H'FF' ; 2.5V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; Disabled _WDT_ON_2H EQU H'FF' ; Enabled _WDTPS_1_2H EQU H'F1' ; 1:1 _WDTPS_2_2H EQU H'F3' ; 1:2 _WDTPS_4_2H EQU H'F5' ; 1:4 _WDTPS_8_2H EQU H'F7' ; 1:8 _WDTPS_16_2H EQU H'F9' ; 1:16 _WDTPS_32_2H EQU H'FB' ; 1:32 _WDTPS_64_2H EQU H'FD' ; 1:64 _WDTPS_128_2H EQU H'FF' ; 1:128 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Disabled _STVR_ON_4L EQU H'FF' ; Enabled _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _DEBUG_ON_4L EQU H'7F' ; Enabled _DEBUG_OFF_4L EQU H'FF' ; Disabled ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Enabled _CP0_OFF_5L EQU H'FF' ; Disabled _CP1_ON_5L EQU H'FD' ; Enabled _CP1_OFF_5L EQU H'FF' ; Disabled ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Enabled _CPB_OFF_5H EQU H'FF' ; Disabled _CPD_ON_5H EQU H'7F' ; Enabled _CPD_OFF_5H EQU H'FF' ; Disabled ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Enabled _WRT0_OFF_6L EQU H'FF' ; Disabled _WRT1_ON_6L EQU H'FD' ; Enabled _WRT1_OFF_6L EQU H'FF' ; Disabled ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Enabled _WRTB_OFF_6H EQU H'FF' ; Disabled _WRTC_ON_6H EQU H'DF' ; Enabled _WRTC_OFF_6H EQU H'FF' ; Disabled _WRTD_ON_6H EQU H'7F' ; Enabled _WRTD_OFF_6H EQU H'FF' ; Disabled ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Enabled _EBTR0_OFF_7L EQU H'FF' ; Disabled _EBTR1_ON_7L EQU H'FD' ; Enabled _EBTR1_OFF_7L EQU H'FF' ; Disabled ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Enabled _EBTRB_OFF_7H EQU H'FF' ; Disabled _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f66j11.inc0000644000175000017500000015027611156521301013411 00000000000000 LIST ;========================================================================== ; MPASM PIC18F66J11 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F66J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F66J11 ; 2. LIST directive in the source file ; LIST P=PIC18F66J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F66J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PMSTAT EQU H'0F5A' PMSTATL EQU H'0F5A' PMSTATH EQU H'0F5B' PMEL EQU H'0F5C' PMEN EQU H'0F5C' PMEH EQU H'0F5D' PMDIN2 EQU H'0F5E' PMDIN2L EQU H'0F5E' PMDIN2H EQU H'0F5F' PMDOUT2 EQU H'0F60' PMDOUT2L EQU H'0F60' PMDOUT2H EQU H'0F61' PMMODE EQU H'0F62' PMMODEL EQU H'0F62' PMMODEH EQU H'0F63' PMCON EQU H'0F64' PMCONL EQU H'0F64' PMCONH EQU H'0F65' PMDIN1 EQU H'0F66' PMDIN1L EQU H'0F66' PMDIN1H EQU H'0F67' PMADDR EQU H'0F68' PMADDRL EQU H'0F68' PMDOUT1 EQU H'0F68' PMDOUT1L EQU H'0F68' PMADDRH EQU H'0F69' PMDOUT1H EQU H'0F69' CMSTAT EQU H'0F6A' CMSTATUS EQU H'0F6A' SSP2CON2 EQU H'0F6B' SSP2CON1 EQU H'0F6C' SSP2STAT EQU H'0F6D' SSP2ADD EQU H'0F6E' SSP2MSK EQU H'0F6E' SSP2BUF EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' CVRCON EQU H'0F77' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CCP3CON EQU H'0FB1' ECCP3CON EQU H'0FB1' CCPR3 EQU H'0FB2' CCPR3L EQU H'0FB2' CCPR3H EQU H'0FB3' ECCP3DEL EQU H'0FB4' ECCP3AS EQU H'0FB5' CCP2CON EQU H'0FB6' ECCP2CON EQU H'0FB6' CCPR2 EQU H'0FB7' CCPR2L EQU H'0FB7' CCPR2H EQU H'0FB8' ECCP2DEL EQU H'0FB9' ECCP2AS EQU H'0FBA' CCP1CON EQU H'0FBB' ECCP1CON EQU H'0FBB' CCPR1 EQU H'0FBC' CCPR1L EQU H'0FBC' CCPR1H EQU H'0FBD' ECCP1DEL EQU H'0FBE' ECCP1AS EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ANCON0 EQU H'0FC1' ADCON0 EQU H'0FC2' ANCON1 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSP1MSK EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' PADCFG1 EQU H'0FCC' TMR2 EQU H'0FCC' ODCON3 EQU H'0FCD' T1CON EQU H'0FCD' ODCON2 EQU H'0FCE' TMR1L EQU H'0FCE' ODCON1 EQU H'0FCF' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' REFOCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' CS2 EQU H'0007' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSP2MSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' DTRXP EQU H'0005' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' TXCKP EQU H'0004' RXDTP EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGC EQU H'0005' PGD EQU H'0006' PMA4 EQU H'0001' PMA3 EQU H'0002' PMA2 EQU H'0003' PMA1 EQU H'0004' PMA0 EQU H'0005' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMD0 EQU H'0000' PMD1 EQU H'0001' PMD2 EQU H'0002' PMD3 EQU H'0003' PMD4 EQU H'0004' PMD5 EQU H'0005' PMD6 EQU H'0006' PMD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' PMRD EQU H'0000' PMWR EQU H'0001' PMBE EQU H'0002' PMA13 EQU H'0003' PMA12 EQU H'0004' PMA11 EQU H'0005' PMA10 EQU H'0006' PMA9 EQU H'0007' REFO EQU H'0003' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' CVREF EQU H'0005' C2OUT EQU H'0001' C1OUT EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' PMA5 EQU H'0002' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' PMA8 EQU H'0000' PMA7 EQU H'0001' PMA6 EQU H'0002' PMCS1 EQU H'0003' PMCS2 EQU H'0004' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' DEVCFG EQU H'0004' LVDSTAT EQU H'0006' REGSLP EQU H'0007' ADSHR EQU H'0004' ;----- ADCON1 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADCAL EQU H'0006' ADFM EQU H'0007' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' NOT_DONE EQU H'0001' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' PCFG13 EQU H'0005' PCFG14 EQU H'0006' PCFG15 EQU H'0007' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- ODCON2 Bits ----------------------------------------------------- USART1OD EQU H'0000' USART2OD EQU H'0001' U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ECCP3OD EQU H'0002' CCP4OD EQU H'0003' CCP5OD EQU H'0004' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' CREF EQU H'0002' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Oscillator Selection bits: ; FOSC = INTOSC Internal oscillator, port function on RA6 and RA7 ; FOSC = INTOSCO Internal oscillator, CLKOUT on RA6 and port function on RA7 ; FOSC = INTOSCPLL INTOSC with PLL enabled, port function on RA6 and RA7 ; FOSC = INTOSCPLLO INTOSC with PLL enabled,CLKOUT on RA6 and port function on RA7 ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled ; FOSC = EC EC Oscillator with clock out on RA6 ; FOSC = ECPLL EC Oscillator with PLL ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MSSP Address Mask: ; MSSPMSK = MSK5 5 Bit address masking ; MSSPMSK = MSK7 7 Bit address masking ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p17c756.inc0000644000175000017500000004551611156313161013162 00000000000000 LIST ; P17C756.INC Standard Header File, Version 1.05 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC17C756 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC17C756 ; 2. LIST directive in the source file ; LIST P=PIC17C756 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/14/96 Initial Release ;1.01 12/12/96 Corrections to 1st pass Rev A Beta Data Sheet ;1.02 01/31/97 Corrections to 2nd pass Rev A Beta Data Sheet ;1.03 03/14/97 Corrected configuration bits value for protected ; microcontroller mode and brownout detect off ;1.04 06/19/97 Added secondary definitions to match the data sheet ;1.05 08/19/97 Added _WDT_1 for compatibility ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __17C756 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' BANK0 EQU H'0000' BANK1 EQU H'0001' BANK2 EQU H'0002' BANK3 EQU H'0003' BANK4 EQU H'0004' BANK5 EQU H'0005' BANK6 EQU H'0006' BANK7 EQU H'0007' GPR_BANK0 EQU H'0000' GPR_BANK1 EQU H'0008' GPR_BANK2 EQU H'0010' GPR_BANK3 EQU H'0018' ;----- Register Files ----------------------------------------------------- INDF0 EQU H'0000' FSR0 EQU H'0001' PCL EQU H'0002' PCLATH EQU H'0003' ALUSTA EQU H'0004' T0STA EQU H'0005' CPUSTA EQU H'0006' INTSTA EQU H'0007' INDF1 EQU H'0008' FSR1 EQU H'0009' WREG EQU H'000A' TMR0L EQU H'000B' TMR0H EQU H'000C' TBLPTRL EQU H'000D' TBLPTRH EQU H'000E' BSR EQU H'000F' ;----- Bank 0 ------------------------------------------------------------- PORTA EQU H'0010' DDRB EQU H'0011' PORTB EQU H'0012' RCSTA EQU H'0013' RCSTA1 EQU H'0013' RCREG EQU H'0014' ; Backward compatibility only RCREG1 EQU H'0014' TXSTA EQU H'0015' ; Backward compatibility only TXSTA1 EQU H'0015' TXREG EQU H'0016' ; Backward compatibility only TXREG1 EQU H'0016' SPBRG EQU H'0017' ; Backward compatibility only SPBRG1 EQU H'0017' ;----- Bank 1 ------------------------------------------------------------- DDRC EQU H'0110' PORTC EQU H'0111' DDRD EQU H'0112' PORTD EQU H'0113' DDRE EQU H'0114' PORTE EQU H'0115' PIR EQU H'0116' ; Backward compatibility only PIR1 EQU H'0116' PIE EQU H'0117' ; Backward compatibility only PIE1 EQU H'0117' ;----- Bank 2 ------------------------------------------------------------- TMR1 EQU H'0210' TMR2 EQU H'0211' TMR3L EQU H'0212' TMR3H EQU H'0213' PR1 EQU H'0214' PR2 EQU H'0215' PR3L EQU H'0216' PR3H EQU H'0217' CA1L EQU H'0216' CA1H EQU H'0217' ;----- Bank 3 ------------------------------------------------------------- PW1DCL EQU H'0310' PW2DCL EQU H'0311' PW1DCH EQU H'0312' PW2DCH EQU H'0313' CA2L EQU H'0314' CA2H EQU H'0315' TCON1 EQU H'0316' TCON2 EQU H'0317' ;----- Bank 4 ------------------------------------------------------------- PIR2 EQU H'0410' PIE2 EQU H'0411' RCSTA2 EQU H'0413' RCREG2 EQU H'0414' TXSTA2 EQU H'0415' TXREG2 EQU H'0416' SPBRG2 EQU H'0417' ;----- Bank 5 ------------------------------------------------------------- DDRF EQU H'0510' PORTF EQU H'0511' DDRG EQU H'0512' PORTG EQU H'0513' ADCON0 EQU H'0514' ADCON1 EQU H'0515' ADRESL EQU H'0516' ADRESH EQU H'0517' ;----- Bank 6 ------------------------------------------------------------- SSPADD EQU H'0610' SSPCON1 EQU H'0611' SSPCON2 EQU H'0612' SSPSTAT EQU H'0613' SSPBUF EQU H'0614' ;----- Bank 7 ------------------------------------------------------------- PW3DCL EQU H'0710' PW3DCH EQU H'0711' CA3L EQU H'0712' CA3H EQU H'0713' CA4L EQU H'0714' CA4H EQU H'0715' TCON3 EQU H'0716' ;----- Unbanked ----------------------------------------------------------- PRODL EQU H'0018' PL EQU H'0018' ; Backward compatibility only PRODH EQU H'0019' PH EQU H'0019' ; Backward compatibility only ;----- Special Function Register Bit Definitions -------------------------- ; ;----- ALUSTA Bits -------------------------------------------------------- FS3 EQU H'0007' FS2 EQU H'0006' FS1 EQU H'0005' FS0 EQU H'0004' OV EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- CPUSTA Bits -------------------------------------------------------- STKAV EQU H'0005' GLINTD EQU H'0004' NOT_TO EQU H'0003' TO EQU H'0003' NOT_PD EQU H'0002' PD EQU H'0002' NOT_POR EQU H'0001' POR EQU H'0001' NOT_BOR EQU H'0000' BOR EQU H'0000' ;----- INTSTA Bits -------------------------------------------------------- PEIF EQU H'0007' T0CKIF EQU H'0006' T0IF EQU H'0005' INTF EQU H'0004' PEIE EQU H'0003' T0CKIE EQU H'0002' T0IE EQU H'0001' INTE EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RBIF EQU H'0007' TMR3IF EQU H'0006' TMR2IF EQU H'0005' TMR1IF EQU H'0004' CA2IF EQU H'0003' CA1IF EQU H'0002' TXIF EQU H'0001' ; Backward compatibility only TX1IF EQU H'0001' RCIF EQU H'0000' ; Backward compatibility only RC1IF EQU H'0000' ;----- PIE1 Bits ----------------------------------------------------------- RBIE EQU H'0007' TMR3IE EQU H'0006' TMR2IE EQU H'0005' TMR1IE EQU H'0004' CA2IE EQU H'0003' CA1IE EQU H'0002' TXIE EQU H'0001' ; Backward compatibility only TX1IE EQU H'0001' RCIE EQU H'0000' ; Backward compatibility only RC1IE EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- NOT_RBPU EQU H'0007' RBPU EQU H'0007' ;----- RCSTA1 and 2 Bits -------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- T0STA Bits -------------------------------------------------------- INTEDG EQU H'0007' T0SE EQU H'0006' T0CS EQU H'0005' T0PS3 EQU H'0004' PS3 EQU H'0004' ; Backward compatibility only T0PS2 EQU H'0003' PS2 EQU H'0003' ; Backward compatibility only T0PS1 EQU H'0002' PS1 EQU H'0002' ; Backward compatibility only T0PS0 EQU H'0001' PS0 EQU H'0001' ; Backward compatibility only ;----- TCON1 Bits --------------------------------------------------------- CA2ED1 EQU H'0007' CA2ED0 EQU H'0006' CA1ED1 EQU H'0005' CA1ED0 EQU H'0004' T16 EQU H'0003' TMR3CS EQU H'0002' TMR2CS EQU H'0001' TMR1CS EQU H'0000' ;----- TCON2 Bits --------------------------------------------------------- CA2OVF EQU H'0007' CA1OVF EQU H'0006' PWM2ON EQU H'0005' PWM1ON EQU H'0004' CA1 EQU H'0003' NOT_PR3 EQU H'0003' PR3 EQU H'0003' CA1_PR3 EQU H'0003' TMR3ON EQU H'0002' TMR2ON EQU H'0001' TMR1ON EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- SSPIF EQU H'0007' BCLIF EQU H'0006' ADIF EQU H'0005' CA4IF EQU H'0003' CA3IF EQU H'0002' TX2IF EQU H'0001' RC2IF EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- SSPIE EQU H'0007' BCLIE EQU H'0006' ADIE EQU H'0005' CA4IE EQU H'0003' CA3IE EQU H'0002' TX2IE EQU H'0001' RC2IE EQU H'0000' ;----- TXSTA1 and 2 Bits -------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- CHS3 EQU H'0007' CHS2 EQU H'0006' CHS1 EQU H'0005' CHS0 EQU H'0004' GO EQU H'0002' NOT_DONE EQU H'0002' DONE EQU H'0002' ADON EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' ADFM EQU H'0005' PCFG3 EQU H'0003' PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- SSPCON1 Bits ------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- SSPCON2 Bits ------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' AKSTAT EQU H'0006' ACKDT EQU H'0005' AKDT EQU H'0005' ACKEN EQU H'0004' AKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' NOT_A EQU H'0005' D_A EQU H'0005' P EQU H'0004' S EQU H'0003' R EQU H'0002' NOT_W EQU H'0002' R_W EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TCON3 Bits --------------------------------------------------------- CA4OVF EQU H'0006' CA3OVF EQU H'0005' CA4ED1 EQU H'0004' CA4ED0 EQU H'0003' CA3ED1 EQU H'0002' CA3ED0 EQU H'0001' PWM3ON EQU H'0000' ;----- PW2DCL Bit --------------------------------------------------------- TM2PW2 EQU H'0005' ;----- PW3DCL Bit --------------------------------------------------------- TM2PW3 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7FF' __BADRAM H'118'-H'11F', H'218'-H'21F', H'318'-H'31F' __BADRAM H'412', H'418'-H'4FF' __BADRAM H'518'-H'5FF' __BADRAM H'615'-H'6FF' __BADRAM H'717'-H'7FF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _PMC_MODE EQU H'7FAF' _XMC_MODE EQU H'FFBF' _MC_MODE EQU H'FFEF' _MP_MODE EQU H'FFFF' _BODEN_OFF EQU H'BFFF' _BODEN_ON EQU H'FFFF' _WDT_NORM EQU H'FFF3' _WDT_OFF EQU H'FFF3' _WDT_64 EQU H'FFF7' _WDT_256 EQU H'FFFB' _WDT_1 EQU H'FFFF' _WDT_0 EQU H'FFFF' _LF_OSC EQU H'FFFC' _RC_OSC EQU H'FFFD' _XT_OSC EQU H'FFFE' _EC_OSC EQU H'FFFF' LIST gputils-0.13.7/header/p16c642.inc0000644000175000017500000001413611156313161013145 00000000000000 LIST ; P16C642.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C642 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C642 ; 2. LIST directive in the source file ; LIST P=PIC16C642 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/12/96 Initial Release ;1.01 12/18/96 Modified per review ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C642 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- MPEEN EQU H'0007' NOT_PER EQU H'0002' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'08', H'09', H'88', H'89' __BADRAM H'0D'-H'1E', H'8D', H'8F'-H'9E' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MPEEN_ON EQU H'3FFF' _MPEEN_OFF EQU H'3F7F' LIST gputils-0.13.7/header/p18f65j11.inc0000644000175000017500000011570611156521301013407 00000000000000 LIST ;========================================================================== ; MPASM PIC18F65J11 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F65J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F65J11 ; 2. LIST directive in the source file ; LIST P=PIC18F65J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F65J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2_PORTB EQU H'0003' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' REPU EQU H'0006' RDPU EQU H'0007' TX2 EQU H'0001' RX2 EQU H'0002' CK2 EQU H'0001' DT2 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F6B'-H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA8'-H'0FAA' __BADRAM H'0FB6'-H'0FBF' __BADRAM H'0FD2' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1L 7FF8h ; CONFIG1H 7FF9h ; CONFIG2L 7FFAh ; CONFIG2H 7FFBh ; CONFIG3L 7FFCh ; CONFIG3H 7FFDh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1L EQU H'7FF8' _CONFIG1H EQU H'7FF9' _CONFIG2L EQU H'7FFA' _CONFIG2H EQU H'7FFB' _CONFIG3L EQU H'7FFC' _CONFIG3H EQU H'7FFD' ;----- CONFIG1L Options -------------------------------------------------- _DEBUG_ON_1L EQU H'7F' ; Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_1L EQU H'FF' ; Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_1L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_1L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _STVREN_OFF_1L EQU H'DF' ; Reset on stack overflow/underflow disabled _STVREN_ON_1L EQU H'FF' ; Reset on stack overflow/underflow enabled _WDTEN_OFF_1L EQU H'FE' ; WDT disabled (control is placed on SWDTEN bit) _WDTEN_ON_1L EQU H'FF' ; WDT enabled ;----- CONFIG1H Options -------------------------------------------------- _CP0_ON_1H EQU H'FB' ; Program memory is code-protected _CP0_OFF_1H EQU H'FF' ; Program memory is not code-protected ;----- CONFIG2L Options -------------------------------------------------- _IESO_OFF_2L EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_2L EQU H'FF' ; Two-Speed Start-up enabled _FCMEN_OFF_2L EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_2L EQU H'FF' ; Fail-Safe Clock Monitor enabled _FOSC2_OFF_2L EQU H'FB' ; INTRC enabled as system clock when OSCCON<1:0> = 00 _FOSC2_ON_2L EQU H'FF' ; Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 _FOSC_HS_2L EQU H'FC' ; HS oscillator _FOSC_HSPLL_2L EQU H'FD' ; HS oscillator, PLL enabled and under software control _FOSC_EC_2L EQU H'FE' ; EC oscillator, CLKO function on OSC2 _FOSC_ECPLL_2L EQU H'FF' ; EC oscillator, PLL enabled and under software control, CLK function on OSC2 ;----- CONFIG2H Options -------------------------------------------------- _WDTPS_1_2H EQU H'F0' ; 1:1 _WDTPS_2_2H EQU H'F1' ; 1:2 _WDTPS_4_2H EQU H'F2' ; 1:4 _WDTPS_8_2H EQU H'F3' ; 1:8 _WDTPS_16_2H EQU H'F4' ; 1:16 _WDTPS_32_2H EQU H'F5' ; 1:32 _WDTPS_64_2H EQU H'F6' ; 1:64 _WDTPS_128_2H EQU H'F7' ; 1:128 _WDTPS_256_2H EQU H'F8' ; 1:256 _WDTPS_512_2H EQU H'F9' ; 1:512 _WDTPS_1024_2H EQU H'FA' ; 1:1024 _WDTPS_2048_2H EQU H'FB' ; 1:2048 _WDTPS_4096_2H EQU H'FC' ; 1:4096 _WDTPS_8192_2H EQU H'FD' ; 1:8192 _WDTPS_16384_2H EQU H'FE' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- ;----- CONFIG3H Options -------------------------------------------------- _CCP2MX_ALTERNATE_3H EQU H'FE' ; ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode _CCP2MX_DEFAULT_3H EQU H'FF' ; ECCP2/P2A is multiplexed with RC1 _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f24j50.inc0000644000175000017500000016037011156521301013402 00000000000000 LIST ;========================================================================== ; MPASM PIC18F24J50 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F24J50 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F24J50 ; 2. LIST directive in the source file ; LIST P=PIC18F24J50 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F24J50 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' UEP0 EQU H'0F26' UEP1 EQU H'0F27' UEP2 EQU H'0F28' UEP3 EQU H'0F29' UEP4 EQU H'0F2A' UEP5 EQU H'0F2B' UEP6 EQU H'0F2C' UEP7 EQU H'0F2D' UEP8 EQU H'0F2E' UEP9 EQU H'0F2F' UEP10 EQU H'0F30' UEP11 EQU H'0F31' UEP12 EQU H'0F32' UEP13 EQU H'0F33' UEP14 EQU H'0F34' UEP15 EQU H'0F35' UIE EQU H'0F36' UEIE EQU H'0F37' UADDR EQU H'0F38' UCFG EQU H'0F39' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' UFRM EQU H'0F60' UFRML EQU H'0F60' UFRMH EQU H'0F61' UIR EQU H'0F62' UEIR EQU H'0F63' USTAT EQU H'0F64' UCON EQU H'0F65' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- UEP0 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP1 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP2 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP3 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP4 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP5 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP6 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP7 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP8 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP9 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP10 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP11 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP12 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP13 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP14 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UEP15 Bits ----------------------------------------------------- EPSTALL EQU H'0000' EPINEN EQU H'0001' EPOUTEN EQU H'0002' EPCONDIS EQU H'0003' EPHSHK EQU H'0004' ;----- UIE Bits ----------------------------------------------------- URSTIE EQU H'0000' UERRIE EQU H'0001' ACTVIE EQU H'0002' TRNIE EQU H'0003' IDLEIE EQU H'0004' STALLIE EQU H'0005' SOFIE EQU H'0006' ;----- UEIE Bits ----------------------------------------------------- PIDEE EQU H'0000' CRC5EE EQU H'0001' CRC16EE EQU H'0002' DFN8EE EQU H'0003' BTOEE EQU H'0004' BTSEE EQU H'0007' ;----- UADDR Bits ----------------------------------------------------- ADDR0 EQU H'0000' ADDR1 EQU H'0001' ADDR2 EQU H'0002' ADDR3 EQU H'0003' ADDR4 EQU H'0004' ADDR5 EQU H'0005' ADDR6 EQU H'0006' ;----- UCFG Bits ----------------------------------------------------- PPB0 EQU H'0000' PPB1 EQU H'0001' FSEN EQU H'0002' UTRDIS EQU H'0003' UPUEN EQU H'0004' UOEMON EQU H'0006' UTEYE EQU H'0007' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- UFRML Bits ----------------------------------------------------- FRM0 EQU H'0000' FRM1 EQU H'0001' FRM2 EQU H'0002' FRM3 EQU H'0003' FRM4 EQU H'0004' FRM5 EQU H'0005' FRM6 EQU H'0006' FRM7 EQU H'0007' ;----- UFRMH Bits ----------------------------------------------------- FRM8 EQU H'0000' FRM9 EQU H'0001' FRM10 EQU H'0002' ;----- UIR Bits ----------------------------------------------------- URSTIF EQU H'0000' UERRIF EQU H'0001' ACTVIF EQU H'0002' TRNIF EQU H'0003' IDLEIF EQU H'0004' STALLIF EQU H'0005' SOFIF EQU H'0006' ;----- UEIR Bits ----------------------------------------------------- PIDEF EQU H'0000' CRC5EF EQU H'0001' CRC16EF EQU H'0002' DFN8EF EQU H'0003' BTOEF EQU H'0004' BTSEF EQU H'0007' ;----- USTAT Bits ----------------------------------------------------- PPBI EQU H'0001' DIR EQU H'0002' ENDP0 EQU H'0003' ENDP1 EQU H'0004' ENDP2 EQU H'0005' ENDP3 EQU H'0006' ;----- UCON Bits ----------------------------------------------------- SUSPND EQU H'0001' RESUME EQU H'0002' USBEN EQU H'0003' PKTDIS EQU H'0004' SE0 EQU H'0005' PPBRST EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' SCK1 EQU H'0004' SDI1 EQU H'0005' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' VMO EQU H'0002' VPO EQU H'0003' SCL1 EQU H'0004' SDA1 EQU H'0005' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' D_MINUS EQU H'0004' D_PLUS EQU H'0005' T1CK EQU H'0000' NOT_UOE EQU H'0001' CTPLS EQU H'0002' VM EQU H'0004' VP EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' SDO1 EQU H'0007' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' USBIE EQU H'0004' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' USBIF EQU H'0004' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' USBIP EQU H'0004' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED4'-H'0ED6' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F25' __BADRAM H'0F3A'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F5F' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; PLL Prescaler Selection bits: ; PLLDIV = 12 Divide by 12 (48 MHz oscillator input) ; PLLDIV = 10 Divide by 10 (40 MHz oscillator input) ; PLLDIV = 6 Divide by 6 (24 MHz oscillator input) ; PLLDIV = 5 Divide by 5 (20 MHz oscillator input) ; PLLDIV = 4 Divide by 4 (16 MHz oscillator input) ; PLLDIV = 3 Divide by 3 (12 MHz oscillator input) ; PLLDIV = 2 Divide by 2 (8 MHz oscillator input) ; PLLDIV = 1 No prescale (4 MHz oscillator input drives PLL directly) ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; CPU System Clock Postscaler: ; CPUDIV = OSC4_PLL6 CPU system clock divide by 6 ; CPUDIV = OSC3_PLL3 CPU system clock divide by 3 ; CPUDIV = OSC2_PLL2 CPU system clock divide by 2 ; CPUDIV = OSC1 No CPU system clock divide ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS, USB-HS ; OSC = HSPLL HS+PLL, USB-HS+PLL ; OSC = EC EC (CLKO-RA6), USB-EC ; OSC = ECPLL EC+PLL (CLKO-RA6), USB-EC+PLL ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p10f220.inc0000644000175000017500000001240211156313161013124 00000000000000 LIST ; P10F220.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC10f220 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P10F220 ; 2. LIST directive in the source file ; LIST P=10F220 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 01/19/05 Initial Release ;1.01 08/09/05 fixed formatting and corrected osc speed select fuse name ;1.02 01/13/06 Added GPIO bit descriptions ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __10F220 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' ADCON0 EQU H'0007' ADRES EQU H'0008' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' FOSC4 EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- ADRES Bits -------------------------------------------------------- ADRES7 EQU H'0007' ADRES6 EQU H'0006' ADRES5 EQU H'0005' ADRES4 EQU H'0004' ADRES3 EQU H'0003' ADRES2 EQU H'0002' ADRES1 EQU H'0001' ADRES0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1F' __BADRAM H'09'-H'0F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _MCPU_ON EQU H'0FFD' _MCPU_OFF EQU H'0FFF' _IOFSCS_8MHZ EQU H'0FFF' _IOFSCS_4MHZ EQU H'0FFE' _IOSCFS_8MHZ EQU H'0FFF' ;Matches datasheet _IOSCFS_4MHZ EQU H'0FFE' ;Matches datasheet LIST gputils-0.13.7/header/p18f8585.inc0000644000175000017500000042201111156521301013240 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8585 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8585 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8585 ; 2. LIST directive in the source file ; LIST P=PIC18F8585 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8585 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' ECCP1DEL EQU H'0F79' BAUDCON EQU H'0F7E' SPBRGH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' TXRTR EQU H'0006' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDM EQU H'0003' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXRTRR0 EQU H'0003' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RTRR0 EQU H'0005' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE0 EQU H'0001' ICODE1 EQU H'0002' ICODE2 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' TX2EN EQU H'0006' TX2SRC EQU H'0007' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' NOT_FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CANTX1 EQU H'0000' CANTX2 EQU H'0001' CANRX EQU H'0002' P1D EQU H'0004' MCLR EQU H'0005' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' AD16 EQU H'0000' AD17 EQU H'0001' AD18 EQU H'0002' AD19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' TRISG5 EQU H'0005' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVREF EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVRSS EQU H'0004' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' IPEN EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' PLLEN EQU H'0002' LOCK EQU H'0003' SCS EQU H'0000' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E2E'-H'0E2F' __BADRAM H'0E3E'-H'0E3F' __BADRAM H'0E4E'-H'0E4F' __BADRAM H'0E5E'-H'0E5F' __BADRAM H'0E6E'-H'0E6F' __BADRAM H'0E7E'-H'0EFF' __BADRAM H'0F2E'-H'0F2F' __BADRAM H'0F3E'-H'0F3F' __BADRAM H'0F4E'-H'0F4F' __BADRAM H'0F5E'-H'0F5F' __BADRAM H'0F78' __BADRAM H'0F7A'-H'0F7D' __BADRAM H'0F9B' __BADRAM H'0FB7'-H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC RC oscillator with OSC2 configured as divide by 4 clock output ; OSC = EC EC oscillator with OSC2 configured as divide by 4 clock output ; OSC = ECIO EC oscillator with OSC2 configured as RA6 ; OSC = HSPLL HS oscillator with HW enabled 4x PLL ; OSC = RCIO RC oscillator with OSC2 configured as RA6 ; OSC = ECIOPLL EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL ; OSC = ECIOSWPLL EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL ; OSC = HSSWPLL HS oscillator with SW enabled 4x PLL ; ; Oscillator System Clock Switch Enable bit: ; OSCS = ON Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) ; OSCS = OFF Oscillator system clock switch option is disabled (main oscillator is source) ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bit: ; BOR = OFF Brown-out Reset disabled ; BOR = ON Brown-out Reset enabled ; ; Brown-out Reset Voltage bits: ; BORV = 45 VBOR set to 4.5V ; BORV = 42 VBOR set to 4.2V ; BORV = 27 VBOR set to 2.7V ; BORV = 20 VBOR set to 2.0V ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) ; WAIT = OFF Wait selections unavailable for table reads and table writes ; ; MCLR Enable bit: ; MCLRE = OFF RG5 input enabled, MCLR disabled ; MCLRE = ON MCLR pin enabled, RG5 input pin disabled ; ; CCP1 PWM outputs P1B, P1C mux bit: ; ECCPMX = PORTH P1B, P1C are multiplexed with RH7, RH6 ; ECCPMX = PORTE P1B, P1C are multiplexed with RE6, RE5 ; ; CCP2 MUX bit: ; CCP2MX = OFF CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = ON CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVR = OFF Stack full/underflow will not cause Reset ; STVR = ON Stack full/underflow will cause Reset ; ; Low-Voltage ICSP Enable bit: ; LVP = OFF Low-voltage ICSP disabled ; LVP = ON Low-voltage ICSP enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. ; DEBUG = OFF Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; RC oscillator with OSC2 configured as divide by 4 clock output _OSC_EC_1H EQU H'F4' ; EC oscillator with OSC2 configured as divide by 4 clock output _OSC_ECIO_1H EQU H'F5' ; EC oscillator with OSC2 configured as RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator with HW enabled 4x PLL _OSC_RCIO_1H EQU H'F7' ; RC oscillator with OSC2 configured as RA6 _OSC_ECIOPLL_1H EQU H'FC' ; EC oscillator with OSC2 configured as RA6 and HW enabled 4x PLL _OSC_ECIOSWPLL_1H EQU H'FD' ; EC oscillator with OSC2 configured as RA6 and SW enabled 4x PLL _OSC_HSSWPLL_1H EQU H'FE' ; HS oscillator with SW enabled 4x PLL _OSCS_ON_1H EQU H'DF' ; Timer1 oscillator system clock switch option is enabled (oscillator switching is enabled) _OSCS_OFF_1H EQU H'FF' ; Oscillator system clock switch option is disabled (main oscillator is source) ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'FD' ; Brown-out Reset disabled _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled _BORV_45_2L EQU H'F3' ; VBOR set to 4.5V _BORV_42_2L EQU H'F7' ; VBOR set to 4.2V _BORV_27_2L EQU H'FB' ; VBOR set to 2.7V _BORV_20_2L EQU H'FF' ; VBOR set to 2.0V ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by WAIT1:WAIT0 bits (MEMCOM<5:4>) _WAIT_OFF_3L EQU H'FF' ; Wait selections unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input enabled, MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RG5 input pin disabled _ECCPMX_PORTH_3H EQU H'FD' ; P1B, P1C are multiplexed with RH7, RH6 _ECCPMX_PORTE_3H EQU H'FF' ; P1B, P1C are multiplexed with RE6, RE5 _CCP2MX_OFF_3H EQU H'FE' ; CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_ON_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVR_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVR_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Low-voltage ICSP disabled _LVP_ON_4L EQU H'FF' ; Low-voltage ICSP enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled. RB6 and RB7 are dedicated to in-circuit debug. _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins. ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16c67.inc0000644000175000017500000002734011156313161013067 00000000000000 LIST ; P16C67.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C67 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C67 ; 2. LIST directive in the source file ; LIST P=PIC16C67 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/13/96 Initial Release ;1.01 12/18/96 Modified per review ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C67 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' __BADRAM H'1E'-H'1F' __BADRAM H'105', H'107'-H'109', H'10C'-H'10F' __BADRAM H'185', H'187'-H'189', H'18C'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16f73.inc0000644000175000017500000003031511156313161013063 00000000000000 LIST ; P16F73.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F73 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F73 ; 2. LIST directive in the source file ; LIST P=PIC16F73 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 00/00/00 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F73 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09' __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18D'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16ce625.inc0000644000175000017500000001431211156313161013307 00000000000000 LIST ; P16CE625.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16CE625 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16CE625 ; 2. LIST directive in the source file ; LIST P=PIC16CE625 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 17 Dec 1997 Initial Release ;1.01 02 Apr 1998 Fix incorrect BADRAM and MAXRAM information ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16CE625 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' CMCON EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PCON EQU H'008E' EEINTF EQU H'0090' VRCON EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- CMIF EQU H'0006' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- CMIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EEINTF Bits ---------------------------------------------------------- EESDA EQU H'0001' EESCL EQU H'0002' EEVDD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'0FF' __BADRAM H'07'-H'09', H'0D'-H'1E' __BADRAM H'87'-H'89', H'8D', H'8F', H'91'-H'9E' __BADRAM H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16c433.inc0000644000175000017500000001454411156313161013146 00000000000000 LIST ; P16C433.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C433 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C433 ; 2. LIST directive in the source file ; LIST P=PIC16C433 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 31 Aug 2000 Original Release ;1.10 28 Mar 2001 Corrected definitions of LINTX and LINRX. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C433 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCCAL EQU H'008F' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- LIN Port bits (within GPIO) ---------------------------------------- LINTX EQU H'0007' LINRX EQU H'0006' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' ;----- OSCCAL Bits -------------------------------------------------------- CAL3 EQU H'0007' CAL2 EQU H'0006' CAL1 EQU H'0005' CAL0 EQU H'0004' CALFST EQU H'0003' CALSLW EQU H'0002' ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D'-H'1D' __BADRAM H'86'-H'89', H'8D', H'90'-H'9E', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3F7F' _CP_ALL EQU H'009F' _CP_75 EQU H'15BF' _CP_50 EQU H'2ADF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _INTRC_OSC EQU H'3FFC' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC EQU H'3FFE' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' LIST gputils-0.13.7/header/p18f44j11.inc0000644000175000017500000015475411156521301013412 00000000000000 LIST ;========================================================================== ; MPASM PIC18F44J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F44J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F44J11 ; 2. LIST directive in the source file ; LIST P=PIC18F44J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F44J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F60'-H'0F65' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; DSWDT Clock Select: ; DSWDTOSC = T1OSCREF DSWDT uses T1OSC/T1CKI ; DSWDTOSC = INTOSCREF DSWDT uses INTRC ; ; RTCC Clock Select : ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; Deep Sleep BOR: ; DSBOREN = OFF Disabled ; DSBOREN = ON Enabled ; ; Deep Sleep Watchdog Timer: ; DSWDTEN = OFF Disabled ; DSWDTEN = ON Enabled ; ; Deep Sleep Watchdog Postscaler: ; DSWDTPS = 2 1:2 (2.1 ms) ; DSWDTPS = 8 1:8 (8.3 ms) ; DSWDTPS = 32 1:32 (33 ms) ; DSWDTPS = 128 1:128 (132 ms) ; DSWDTPS = 512 1:512 (528 ms) ; DSWDTPS = 2048 1:2,048 (2.1 seconds) ; DSWDTPS = 8192 1:8,192 (8.5 seconds) ; DSWDTPS = K32 1:32,768 (34 seconds) ; DSWDTPS = K131 1:131,072 (135 seconds) ; DSWDTPS = K524 1:524,288 (9 minutes) ; DSWDTPS = M2 1:2,097,152 (36 minutes) ; DSWDTPS = M8 1:8,388,608 (2.4 hours) ; DSWDTPS = M33 1:33,554,432 (9.6 hours) ; DSWDTPS = M134 1:134,217,728 (38.5 hours) ; DSWDTPS = M536 1:536,870,912 (6.4 days) ; DSWDTPS = G2 1:2,147,483,648 (25.7 days) ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/pmcv08a.inc0000644000175000017500000001265411156521301013416 00000000000000 LIST ; PMCV08A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the MCV08A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PMCV08A ; 2. LIST directive in the source file ; LIST P=MCV08A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 12/13/04 Initial Release ;1.01 07/13/05 Updated comparator names and fuse section ;1.02 08/26/05 Added port bit names ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __MCV08A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' GPIO EQU H'0006' CM1CON0 EQU H'0007' ADCON0 EQU H'0008' ADRES EQU H'0009' ;----- STATUS Bits -------------------------------------------------------- GPWUF EQU H'0007' CWUF EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPWU EQU H'0007' NOT_GPPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;----- CM1CON0 Bits -------------------------------------------------------- C1OUT EQU H'0007' NOT_C1OUTEN EQU H'0006' C1POL EQU H'0005' NOT_C1T0CS EQU H'0004' C1ON EQU H'0003' C1NREF EQU H'0002' C1PREF EQU H'0001' NOT_C1WU EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- GPIO Bits -------------------------------------------------------- GP0 EQU H'0000' GP1 EQU H'0001' GP2 EQU H'0002' GP3 EQU H'0003' GP4 EQU H'0004' GP5 EQU H'0005' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _IOSCFS_ON EQU H'0FFF' _IOSCFS_OFF EQU H'0FDF' _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDT_ON EQU H'0FFF' _WDT_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p12f519.inc0000644000175000017500000001073611156521301013146 00000000000000 LIST ; P12F519.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12F509 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /P12F519 ; 2. LIST directive in the source file ; LIST P=12F519 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 1/24/07 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12F519 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' PORTB EQU H'0006' EECON EQU H'0021' EEDATA EQU H'0025' EEADR EQU H'0026' ;----- EECON ------------------------------------------------------------- FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- RBWUF EQU H'0007' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBWU EQU H'0007' NOT_RBPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'3F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPDF_OFF EQU H'0FFF' _CPDF_ON EQU H'0FBF' _IOSCFS_8MHz EQU H'0FFF' _IOSCFS_4MHz EQU H'0FDF' _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FEF' _CP_ON EQU H'0FF7' _CP_OFF EQU H'0FFF' _WDTE_ON EQU H'0FFF' _WDTE_OFF EQU H'0FFB' _LP_OSC EQU H'0FFC' _XT_OSC EQU H'0FFD' _IntRC_OSC EQU H'0FFE' _ExtRC_OSC EQU H'0FFF' LIST gputils-0.13.7/header/p16f684.inc0000644000175000017500000003422011156521301013147 00000000000000 LIST ; P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F684 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F684 ; 2. LIST directive in the source file ; LIST P=PIC16F684 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 03/20/03 Original ;1.01 08/04/03 Updated CMCON1 address ;1.02 08/05/03 Updated names to match datasheet ;1.03 08/11/03 Updated ULPWUE bit name to match datasheet ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F684 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' PWM1CON EQU H'0016' ECCPAS EQU H'0017' WDTCON EQU H'0018' CMCON0 EQU H'0019' CMCON1 EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISC EQU H'0087' PIE1 EQU H'008C' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' VRCON EQU H'0099' EEDAT EQU H'009A' EEDATA EQU H'009A' EEADR EQU H'009B' EECON1 EQU H'009C' EECON2 EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RAIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RAIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' CCP1IF EQU H'0005' C2IF EQU H'0004' C1IF EQU H'0003' OSFIF EQU H'0002' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M1 EQU H'0007' P1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' ;----- COMCON0 Bits ------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- COMCON1 Bits ------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RAPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' CCP1IE EQU H'0005' C2IE EQU H'0004' C1IE EQU H'0003' OSFIE EQU H'0002' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- ULPWUE EQU H'0005' SBODEN EQU H'0004' NOT_POR EQU H'0001' NOT_BOD EQU H'0000' ;----- OSCCON Bits -------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS7 EQU H'0007' ANS6 EQU H'0006' ANS5 EQU H'0005' ANS4 EQU H'0004' ANS3 EQU H'0003' ANS2 EQU H'0002' ANS1 EQU H'0001' ANS0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- VRCON Bits --------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D' __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16c770.inc0000644000175000017500000003012511156313161013143 00000000000000 LIST ; P16C770.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C770 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C770 ; 2. LIST directive in the source file ; LIST P=PIC16C770 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 14Sep1999 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C770 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' SSPCON2 EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' IOCB EQU H'0096' P1DEL EQU H'0097' REFCON EQU H'009B' LVDCON EQU H'009C' ANSEL EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' PMDATL EQU H'010C' PMADRL EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- LVDIF EQU H'0007' BCLIF EQU H'0003' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- PWM1M1 EQU H'0007' PWM1M0 EQU H'0006' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' CHS3 EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ---------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- LVDIE EQU H'0007' BCLIE EQU H'0003' ;----- PCON Bits ---------------------------------------------------------- OSCF EQU H'0003' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPCON2 Bits -------------------------------------------------------- GCEN EQU H'0007' ACKSTAT EQU H'0006' ACKDT EQU H'0005' ACKEN EQU H'0004' RCEN EQU H'0003' PEN EQU H'0002' RSEN EQU H'0001' SEN EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- REFCON Bits -------------------------------------------------------- VRHEN EQU H'0007' VRLEN EQU H'0006' VRHOEN EQU H'0005' VRLOEN EQU H'0004' ;----- LVDCON Bits -------------------------------------------------------- BGST EQU H'0005' LVDEN EQU H'0004' LV3 EQU H'0003' LV2 EQU H'0002' LV1 EQU H'0001' LV0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG2 EQU H'0006' VCFG1 EQU H'0005' VCFG0 EQU H'0004' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'18'-H'1D' __BADRAM H'87'-H'89' __BADRAM H'8F'-H'90', H'98'-H'9A' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'0CFF' _CP_OFF EQU H'3FFF' _VBOR_25 EQU H'3FFF' _VBOR_27 EQU H'3BFF' _VBOR_42 EQU H'37FF' _VBOR_45 EQU H'33FF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _MCLRE_OFF EQU H'3FDF' _MCLRE_ON EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _ER_OSC_CLKOUT EQU H'3FFF' _ER_OSC_NOCLKOUT EQU H'3FFE' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _EXTCLK_OSC EQU H'3FFB' _HS_OSC EQU H'3FFA' _XT_OSC EQU H'3FF9' _LP_OSC EQU H'3FF8' LIST gputils-0.13.7/header/p18lf25j11.inc0000644000175000017500000014044511156521301013555 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF25J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF25J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF25J11 ; 2. LIST directive in the source file ; LIST P=PIC18LF25J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF25J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ULPWU EQU H'0000' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0ED9'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F53'-H'0F65' __BADRAM H'0F6C'-H'0F6F' __BADRAM H'0F83'-H'0F84' __BADRAM H'0F87' __BADRAM H'0F8C'-H'0F8D' __BADRAM H'0F95'-H'0F96' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset : ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/pmcv14a.inc0000644000175000017500000001542311156521301013410 00000000000000 LIST ; PMCV14A.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PMCV14A ; 2. LIST directive in the source file ; LIST P=MCV14A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 1/3/2008 New Revision. ; ; ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __MCV14A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files ----------------------------------------------------- INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' OSCCAL EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' CM1CON0 EQU H'0008' ADCON0 EQU H'0009' ADRES EQU H'000A' CM2CON0 EQU H'000B' VRCON EQU H'000C' EECON EQU H'0021' EEDATA EQU H'0025' EEADR EQU H'0026' ;----- EECON ------------------------------------------------------------- FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;----- STATUS Bits -------------------------------------------------------- RBWUF EQU H'0007' CWUF EQU H'0006' PA0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- VRCON0 Bits --------------------------------------------------------- VREN EQU H'0007' VROE EQU H'0006' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CM1CON0 Bits ------------------------------------------------------- C1OUT EQU H'0007' NOT_C1OUTEN EQU H'0006' C1POL EQU H'0005' NOT_C1T0CS EQU H'0004' C1ON EQU H'0003' C1NREF EQU H'0002' C1PREF EQU H'0001' NOT_C1WU EQU H'0000' ;----- CM2CON0 Bits ------------------------------------------------------- C2OUT EQU H'0007' NOT_C2OUTEN EQU H'0006' C2POL EQU H'0005' C2PREF2 EQU H'0004' C2ON EQU H'0003' C2NREF EQU H'0002' C2PREF1 EQU H'0001' NOT_C2WU EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ANS1 EQU H'0007' ANS0 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' ADON EQU H'0000' ;----- ADRES Bits -------------------------------------------------------- ADRES7 EQU H'0007' ADRES6 EQU H'0006' ADRES5 EQU H'0005' ADRES4 EQU H'0004' ADRES3 EQU H'0003' ADRES2 EQU H'0002' ADRES1 EQU H'0001' ADRES0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBWU EQU H'0007' NOT_RBPU EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- OSCCAL Bits -------------------------------------------------------- CAL6 EQU H'0007' CAL5 EQU H'0006' CAL4 EQU H'0005' CAL3 EQU H'0004' CAL2 EQU H'0003' CAL1 EQU H'0002' CAL0 EQU H'0001' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'7F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CPDF_OFF EQU H'0FFF' _CPDF_ON EQU H'0F7F' _IOSCFS_8MHz EQU H'0FFF' _IOSCFS_4MHz EQU H'0FBF' _MCLRE_ON EQU H'0FFF' _MCLRE_OFF EQU H'0FDF' _CP_ON EQU H'0FEF' _CP_OFF EQU H'0FFF' _WDTE_ON EQU H'0FFF' _WDTE_OFF EQU H'0FF7' _LP_OSC EQU H'0FF8' _XT_OSC EQU H'0FF9' _HS_OSC EQU H'0FFA' _EC_OSC EQU H'0FFB' _IntRC_OSC_RB4 EQU H'0FFC' _IntRC_OSC_CLKOUT EQU H'0FFD' _ExtRC_OSC_RB4 EQU H'0FFE' _ExtRC_OSC_CLKOUT EQU H'0FFF' LIST gputils-0.13.7/header/p12hv615.inc0000644000175000017500000003567111156521301013340 00000000000000 LIST ; P12HV615.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; Based on P12F615.INC ; This header file defines configurations, registers, and other useful bits of ; information for the PIC12HV615 microcontroller. The names are taken to match ; the data sheet as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC12HV615 ; 2. LIST directive in the source file ; LIST P=PIC12HV615 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;1.00 04/19/06 Original ;1.01 05/03/06 Remove references to 12HV615 ;1.02 12/08/06 Corrected references of comparator C1 to CM, with aliases ;1.03 12/11/06 Added TRISA and IOCA aliases ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __12HV615 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' GPIO EQU H'0005' PORTA EQU H'0005' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' CCPR1L EQU H'0013' CCPR1H EQU H'0014' CCP1CON EQU H'0015' PWM1CON EQU H'0016' ECCPAS EQU H'0017' VRCON EQU H'0019' CMCON0 EQU H'001A' CMCON1 EQU H'001C' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISIO EQU H'0085' TRISA EQU H'0085' PIE1 EQU H'008C' PCON EQU H'008E' OSCTUNE EQU H'0090' PR2 EQU H'0092' APFCON EQU H'0093' WPU EQU H'0095' WPUA EQU H'0095' IOC EQU H'0096' IOCA EQU H'0096' ADRESL EQU H'009E' ANSEL EQU H'009F' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- GPIO Bits ---------------------------------------------------------- GP5 EQU H'0005' GPIO5 EQU H'0005' GP4 EQU H'0004' GPIO4 EQU H'0004' GP3 EQU H'0003' GPIO3 EQU H'0003' GP2 EQU H'0002' GPIO2 EQU H'0002' GP1 EQU H'0001' GPIO1 EQU H'0001' GP0 EQU H'0000' GPIO0 EQU H'0000' ;----- PORTA Bits --------------------------------------------------------- RA5 EQU H'0005' RA4 EQU H'0004' RA3 EQU H'0003' RA2 EQU H'0002' RA1 EQU H'0001' RA0 EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' GPIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' GPIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- ADIF EQU H'0006' CCP1IF EQU H'0005' C1IF EQU H'0003' CMIF EQU H'0003' T2IF EQU H'0001' TMR2IF EQU H'0001' T1IF EQU H'0000' TMR1IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' TMR1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- P1M EQU H'0007' DC1B1 EQU H'0005' DC1B0 EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- PWM1CON Bits ------------------------------------------------------- PRSEN EQU H'0007' PDC6 EQU H'0006' PDC5 EQU H'0005' PDC4 EQU H'0004' PDC3 EQU H'0003' PDC2 EQU H'0002' PDC1 EQU H'0001' PDC0 EQU H'0000' ;----- ECCPAS Bits -------------------------------------------------------- ECCPASE EQU H'0007' ECCPAS2 EQU H'0006' ECCPAS1 EQU H'0005' ECCPAS0 EQU H'0004' PSSAC1 EQU H'0003' PSSAC0 EQU H'0002' PSSBD1 EQU H'0001' PSSBD0 EQU H'0000' ;----- VRCON Bits ------------------------------------------------------- C1VREN EQU H'0007' CMVREN EQU H'0007' VRR EQU H'0005' VP6EN EQU H'0004' FVREN EQU H'0004' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- CMCON0 Bits ------------------------------------------------------- C1ON EQU H'0007' CMON EQU H'0007' C1OUT EQU H'0006' COUT EQU H'0006' C1OE EQU H'0005' CMOE EQU H'0005' C1POL EQU H'0004' CMPOL EQU H'0004' C1R EQU H'0002' CMR EQU H'0002' C1CH0 EQU H'0000' CMCH EQU H'0000' ;----- CMCON1 Bits ------------------------------------------------------- T1ACS EQU H'0004' C1HYS EQU H'0003' CMHYS EQU H'0003' T1GSS EQU H'0001' C1SYNC EQU H'0000' CMSYNC EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG EQU H'0006' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' GO EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_GPPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISIO Bits -------------------------------------------------------- TRISIO5 EQU H'0005' TRISIO4 EQU H'0004' TRISIO3 EQU H'0003' TRISIO2 EQU H'0002' TRISIO1 EQU H'0001' TRISIO0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- ADIE EQU H'0006' CCP1IE EQU H'0005' C1IE EQU H'0003' CMIE EQU H'0003' T2IE EQU H'0001' TMR2IE EQU H'0001' T1IE EQU H'0000' TMR1IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BOD EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- APFCON Bits -------------------------------------------------------- T1GSEL EQU H'0004' P1BSEL EQU H'0001' P1ASEL EQU H'0000' ;----- WPU Bits --------------------------------------------------------- WPU5 EQU H'0005' WPU4 EQU H'0004' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- WPUA Bits --------------------------------------------------------- WPUA5 EQU H'0005' WPUA4 EQU H'0004' WPUA2 EQU H'0002' WPUA1 EQU H'0001' WPUA0 EQU H'0000' ;----- IOC Bits --------------------------------------------------------- IOC5 EQU H'0005' IOC4 EQU H'0004' IOC3 EQU H'0003' IOC2 EQU H'0002' IOC1 EQU H'0001' IOC0 EQU H'0000' ;----- IOCA Bits --------------------------------------------------------- IOCA5 EQU H'0005' IOCA4 EQU H'0004' IOCA3 EQU H'0003' IOCA2 EQU H'0002' IOCA1 EQU H'0001' IOCA0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' AN3 EQU H'0003' AN2 EQU H'0002' AN1 EQU H'0001' AN0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'06'-H'09', H'0D', H'18', H'1B', H'1D', H'20'-H'3F' __BADRAM H'86'-H'89', H'8D', H'8F', H'91', H'94', H'97'-H'9D', H'A0'-H'EF' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BOR_ON EQU H'3FFF' _BOR_NSLEEP EQU H'3EFF' _BOR_OFF EQU H'3CFF' _IOSCFS8 EQU H'3FFF' _IOSCFS_8MHZ EQU H'3FFF' _IOSCFS4 EQU H'3F7F' _IOSCFS_4MHZ EQU H'3F7F' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FEF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16c66.inc0000644000175000017500000002615411156313161013070 00000000000000 LIST ; P16C66.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C66 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C66 ; 2. LIST directive in the source file ; LIST P=PIC16C66 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 11/13/96 Initial Release ;1.01 12/18/96 Modified per review ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C66 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08'-H'09', H'88'-H'89' __BADRAM H'1E'-H'1F' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' __BADRAM H'105', H'107'-H'109', H'10C'-H'10F' __BADRAM H'185', H'187'-H'189', H'18C'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18lf46j11.inc0000644000175000017500000016053511156521301013562 00000000000000 LIST ;========================================================================== ; MPASM PIC18LF46J11 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18LF46J11 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18LF46J11 ; 2. LIST directive in the source file ; LIST P=PIC18LF46J11 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18LF46J11 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RPOR0 EQU H'0EC6' RPOR1 EQU H'0EC7' RPOR2 EQU H'0EC8' RPOR3 EQU H'0EC9' RPOR4 EQU H'0ECA' RPOR5 EQU H'0ECB' RPOR6 EQU H'0ECC' RPOR7 EQU H'0ECD' RPOR8 EQU H'0ECE' RPOR9 EQU H'0ECF' RPOR10 EQU H'0ED0' RPOR11 EQU H'0ED1' RPOR12 EQU H'0ED2' RPOR13 EQU H'0ED3' RPOR14 EQU H'0ED4' RPOR15 EQU H'0ED5' RPOR16 EQU H'0ED6' RPOR17 EQU H'0ED7' RPOR18 EQU H'0ED8' RPOR19 EQU H'0ED9' RPOR20 EQU H'0EDA' RPOR21 EQU H'0EDB' RPOR22 EQU H'0EDC' RPOR23 EQU H'0EDD' RPOR24 EQU H'0EDE' RPINR1 EQU H'0EE7' RPINR2 EQU H'0EE8' RPINR3 EQU H'0EE9' RPINR4 EQU H'0EEA' RPINR6 EQU H'0EEC' RPINR7 EQU H'0EED' RPINR8 EQU H'0EEE' RPINR12 EQU H'0EF2' RPINR13 EQU H'0EF3' RPINR16 EQU H'0EF6' RPINR17 EQU H'0EF7' RPINR21 EQU H'0EFB' RPINR22 EQU H'0EFC' RPINR23 EQU H'0EFD' RPINR24 EQU H'0EFE' PPSCON EQU H'0EFF' PADCFG1 EQU H'0F3C' REFOCON EQU H'0F3D' RTCCAL EQU H'0F3E' RTCCFG EQU H'0F3F' ODCON3 EQU H'0F40' ODCON2 EQU H'0F41' ODCON1 EQU H'0F42' ANCON0 EQU H'0F48' ANCON1 EQU H'0F49' DSWAKEL EQU H'0F4A' DSWAKEH EQU H'0F4B' DSCONL EQU H'0F4C' DSCONH EQU H'0F4D' DSGPR0 EQU H'0F4E' DSGPR1 EQU H'0F4F' TCLKCON EQU H'0F52' CVRCON EQU H'0F53' PMSTATL EQU H'0F54' PMSTATH EQU H'0F55' PMEL EQU H'0F56' PMEH EQU H'0F57' PMDIN2L EQU H'0F58' PMDIN2H EQU H'0F59' PMDOUT2L EQU H'0F5A' PMDOUT2H EQU H'0F5B' PMMODEL EQU H'0F5C' PMMODEH EQU H'0F5D' PMCONL EQU H'0F5E' PMCONH EQU H'0F5F' DMABCH EQU H'0F66' DMABCL EQU H'0F67' RXADDRH EQU H'0F68' RXADDRL EQU H'0F69' TXADDRH EQU H'0F6A' TXADDRL EQU H'0F6B' PMDIN1L EQU H'0F6C' PMDIN1H EQU H'0F6D' PMADDRL EQU H'0F6E' PMDOUT1L EQU H'0F6E' PMADDRH EQU H'0F6F' PMDOUT1H EQU H'0F6F' CMSTAT EQU H'0F70' CMSTATUS EQU H'0F70' SSP2CON2 EQU H'0F71' SSP2CON1 EQU H'0F72' SSP2STAT EQU H'0F73' SSP2ADD EQU H'0F74' SSP2BUF EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' T3CON EQU H'0F79' TMR3L EQU H'0F7A' TMR3H EQU H'0F7B' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' BAUDCTL EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' HLVDCON EQU H'0F85' DMACON2 EQU H'0F86' DMACON1 EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' ALRMVALL EQU H'0F8E' ALRMVALH EQU H'0F8F' ALRMRPT EQU H'0F90' ALRMCFG EQU H'0F91' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' TRISD EQU H'0F95' TRISE EQU H'0F96' T3GCON EQU H'0F97' RTCVALL EQU H'0F98' RTCVALH EQU H'0F99' T1GCON EQU H'0F9A' OSCTUNE EQU H'0F9B' RCSTA2 EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' TXSTA2 EQU H'0FA8' TXREG2 EQU H'0FA9' RCREG2 EQU H'0FAA' SPBRG2 EQU H'0FAB' RCSTA EQU H'0FAC' RCSTA1 EQU H'0FAC' TXSTA EQU H'0FAD' TXSTA1 EQU H'0FAD' TXREG EQU H'0FAE' TXREG1 EQU H'0FAE' RCREG EQU H'0FAF' RCREG1 EQU H'0FAF' SPBRG EQU H'0FB0' SPBRG1 EQU H'0FB0' CTMUICON EQU H'0FB1' CTMUCONL EQU H'0FB2' CTMUCONH EQU H'0FB3' CCP2CON EQU H'0FB4' ECCP2CON EQU H'0FB4' CCPR2 EQU H'0FB5' CCPR2L EQU H'0FB5' CCPR2H EQU H'0FB6' ECCP2DEL EQU H'0FB7' PWM2CON EQU H'0FB7' ECCP2AS EQU H'0FB8' PSTR2CON EQU H'0FB9' CCP1CON EQU H'0FBA' ECCP1CON EQU H'0FBA' CCPR1 EQU H'0FBB' CCPR1L EQU H'0FBB' CCPR1H EQU H'0FBC' ECCP1DEL EQU H'0FBD' PWM1CON EQU H'0FBD' ECCP1AS EQU H'0FBE' PSTR1CON EQU H'0FBF' WDTCON EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' CM2CON EQU H'0FD1' CM2CON1 EQU H'0FD1' CM1CON EQU H'0FD2' CM1CON1 EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PPSCON Bits ----------------------------------------------------- IOLOCK EQU H'0000' ;----- PADCFG1 Bits ----------------------------------------------------- PMPTTL EQU H'0000' RTSECSEL0 EQU H'0001' RTSECSEL1 EQU H'0002' ;----- REFOCON Bits ----------------------------------------------------- ROSEL EQU H'0004' ROSSLP EQU H'0005' ROON EQU H'0007' RODIV0 EQU H'0000' RODIV1 EQU H'0001' RODIV2 EQU H'0002' RODIV3 EQU H'0003' ;----- RTCCAL Bits ----------------------------------------------------- CAL0 EQU H'0000' CAL1 EQU H'0001' CAL2 EQU H'0002' CAL3 EQU H'0003' CAL4 EQU H'0004' CAL5 EQU H'0005' CAL6 EQU H'0006' CAL7 EQU H'0007' ;----- RTCCFG Bits ----------------------------------------------------- RTCPTR0 EQU H'0000' RTCPTR1 EQU H'0001' RTCOE EQU H'0002' HALFSEC EQU H'0003' RTCSYNC EQU H'0004' RTCWREN EQU H'0005' RTCEN EQU H'0007' ;----- ODCON3 Bits ----------------------------------------------------- SPI1OD EQU H'0000' SPI2OD EQU H'0001' ;----- ODCON2 Bits ----------------------------------------------------- U1OD EQU H'0000' U2OD EQU H'0001' ;----- ODCON1 Bits ----------------------------------------------------- ECCP1OD EQU H'0000' ECCP2OD EQU H'0001' ;----- ANCON0 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' PCFG4 EQU H'0004' PCFG5 EQU H'0005' PCFG6 EQU H'0006' PCFG7 EQU H'0007' ;----- ANCON1 Bits ----------------------------------------------------- PCFG8 EQU H'0000' PCFG9 EQU H'0001' PCFG10 EQU H'0002' PCFG11 EQU H'0003' PCFG12 EQU H'0004' VBG2EN EQU H'0006' VBGEN EQU H'0007' ;----- DSWAKEL Bits ----------------------------------------------------- DSPOR EQU H'0000' DSMCLR EQU H'0002' DSRTC EQU H'0003' DSWDT EQU H'0004' DSULP EQU H'0005' DSFLT EQU H'0007' ;----- DSWAKEH Bits ----------------------------------------------------- DSINT0 EQU H'0000' ;----- DSCONL Bits ----------------------------------------------------- RELEASE EQU H'0000' DSBOR EQU H'0001' ULPWDIS EQU H'0002' ;----- DSCONH Bits ----------------------------------------------------- RTCWDIS EQU H'0000' DSULPEN EQU H'0001' DSEN EQU H'0007' ;----- TCLKCON Bits ----------------------------------------------------- T3CCP1 EQU H'0000' T3CCP2 EQU H'0001' T1RUN EQU H'0004' ;----- CVRCON Bits ----------------------------------------------------- CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' ;----- PMSTATL Bits ----------------------------------------------------- OB0E EQU H'0000' OB1E EQU H'0001' OB2E EQU H'0002' OB3E EQU H'0003' OBUF EQU H'0006' OBE EQU H'0007' ;----- PMSTATH Bits ----------------------------------------------------- IB0F EQU H'0000' IB1F EQU H'0001' IB2F EQU H'0002' IB3F EQU H'0003' IBOV EQU H'0006' IBF EQU H'0007' ;----- PMEL Bits ----------------------------------------------------- PTEN0 EQU H'0000' PTEN1 EQU H'0001' PTEN2 EQU H'0002' PTEN3 EQU H'0003' PTEN4 EQU H'0004' PTEN5 EQU H'0005' PTEN6 EQU H'0006' PTEN7 EQU H'0007' ;----- PMEH Bits ----------------------------------------------------- PTEN8 EQU H'0000' PTEN9 EQU H'0001' PTEN10 EQU H'0002' PTEN11 EQU H'0003' PTEN12 EQU H'0004' PTEN13 EQU H'0005' PTEN14 EQU H'0006' PTEN15 EQU H'0007' ;----- PMMODEL Bits ----------------------------------------------------- WAITE0 EQU H'0000' WAITE1 EQU H'0001' WAITM0 EQU H'0002' WAITM1 EQU H'0003' WAITM2 EQU H'0004' WAITM3 EQU H'0005' WAITB0 EQU H'0006' WAITB1 EQU H'0007' ;----- PMMODEH Bits ----------------------------------------------------- MODE0 EQU H'0000' MODE1 EQU H'0001' MODE16 EQU H'0002' INCM0 EQU H'0003' INCM1 EQU H'0004' IRQM0 EQU H'0005' IRQM1 EQU H'0006' BUSY EQU H'0007' ;----- PMCONL Bits ----------------------------------------------------- RDSP EQU H'0000' WRSP EQU H'0001' BEP EQU H'0002' CS1P EQU H'0003' CS2P EQU H'0004' ALP EQU H'0005' CSF0 EQU H'0006' CSF1 EQU H'0007' ;----- PMCONH Bits ----------------------------------------------------- PTRDEN EQU H'0000' PTWREN EQU H'0001' PTBEEN EQU H'0002' ADRMUX0 EQU H'0003' ADRMUX1 EQU H'0004' PSIDL EQU H'0005' PMPEN EQU H'0007' ;----- PMADDRH Bits ----------------------------------------------------- CS1 EQU H'0006' ;----- CMSTAT Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- CMSTATUS Bits ----------------------------------------------------- COUT1 EQU H'0000' COUT2 EQU H'0001' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP2CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSP2ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- TMR4ON EQU H'0002' T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' RD16 EQU H'0001' T3SYNC EQU H'0002' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' TMR3CS0 EQU H'0006' TMR3CS1 EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' TXCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1INA EQU H'0000' C2INA EQU H'0001' VREF_MINUS EQU H'0002' VREF_PLUS EQU H'0003' NOT_SS1 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' PMPA6 EQU H'0000' PMPA7 EQU H'0001' CVREF_MINUS EQU H'0002' C1INB EQU H'0003' HLVDIN EQU H'0005' RP0 EQU H'0000' RP1 EQU H'0001' C2INB EQU H'0002' RCV EQU H'0005' ULPWU EQU H'0000' RP2 EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' PMPA1 EQU H'0004' PMPA0 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' INT0 EQU H'0000' PMPBE EQU H'0001' CTEDG1 EQU H'0002' CTEDG2 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' RP3 EQU H'0000' RTCC EQU H'0001' PMPA3 EQU H'0002' PMPA2 EQU H'0003' RP9 EQU H'0006' RP10 EQU H'0007' RP4 EQU H'0001' REFO EQU H'0002' RP6 EQU H'0003' RP7 EQU H'0004' RP8 EQU H'0005' RP5 EQU H'0002' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' AN11 EQU H'0002' SCK1 EQU H'0003' PMPA5 EQU H'0006' PMPA4 EQU H'0007' T1CKI EQU H'0000' CTPLS EQU H'0002' SCL1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' RP11 EQU H'0000' RP12 EQU H'0001' RP13 EQU H'0002' RP14 EQU H'0003' RP15 EQU H'0004' RP16 EQU H'0005' CK1 EQU H'0006' DT1 EQU H'0007' RP17 EQU H'0006' RP18 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PMPD0 EQU H'0000' PMPD1 EQU H'0001' PMPD2 EQU H'0002' PMPD3 EQU H'0003' PMPD4 EQU H'0004' PMPD5 EQU H'0005' PMPD6 EQU H'0006' PMPD7 EQU H'0007' SCL2 EQU H'0000' SDA2 EQU H'0001' RP19 EQU H'0002' RP20 EQU H'0003' RP21 EQU H'0004' RP22 EQU H'0005' RP23 EQU H'0006' RP24 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' REPU EQU H'0006' RDPU EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' PMPRD EQU H'0000' PMPWR EQU H'0001' PMPCS EQU H'0002' ;----- HLVDCON Bits ----------------------------------------------------- HLVDEN EQU H'0004' IRVST EQU H'0005' BGVST EQU H'0006' VDIRMAG EQU H'0007' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' ;----- DMACON2 Bits ----------------------------------------------------- INTLVL0 EQU H'0000' INTLVL1 EQU H'0001' INTLVL2 EQU H'0002' INTLVL3 EQU H'0003' DLYCYC0 EQU H'0004' DLYCYC1 EQU H'0005' DLYCYC2 EQU H'0006' DLYCYC3 EQU H'0007' ;----- DMACON1 Bits ----------------------------------------------------- DMAEN EQU H'0000' DLYINTEN EQU H'0001' DUPLEX0 EQU H'0002' DUPLEX1 EQU H'0003' RXINC EQU H'0004' TXINC EQU H'0005' SSCON0 EQU H'0006' SSCON1 EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- ALRMRPT Bits ----------------------------------------------------- ARPT0 EQU H'0000' ARPT1 EQU H'0001' ARPT2 EQU H'0002' ARPT3 EQU H'0003' ARPT4 EQU H'0004' ARPT5 EQU H'0005' ARPT6 EQU H'0006' ARPT7 EQU H'0007' ;----- ALRMCFG Bits ----------------------------------------------------- CHIME EQU H'0006' ALRMEN EQU H'0007' ALRMPTR0 EQU H'0000' ALRMPTR1 EQU H'0001' AMASK0 EQU H'0002' AMASK1 EQU H'0003' AMASK2 EQU H'0004' AMASK3 EQU H'0005' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- T3GCON Bits ----------------------------------------------------- T3GSS0 EQU H'0000' T3GSS1 EQU H'0001' T3GVAL EQU H'0002' T3GGO_T3DONE EQU H'0003' T3GSPM EQU H'0004' T3GTM EQU H'0005' T3GPOL EQU H'0006' TMR3GE EQU H'0007' T3GGO EQU H'0003' T3DONE EQU H'0003' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO_T1DONE EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' T1GGO EQU H'0003' T1DONE EQU H'0003' ;----- OSCTUNE Bits ----------------------------------------------------- PLLEN EQU H'0006' INTSRC EQU H'0007' TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PMPIE EQU H'0007' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PMPIF EQU H'0007' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PMPIP EQU H'0007' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCL1IE EQU H'0003' CM1IE EQU H'0005' CM2IE EQU H'0006' OSCFIE EQU H'0007' BCLIE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCL1IF EQU H'0003' CM1IF EQU H'0005' CM2IF EQU H'0006' OSCFIF EQU H'0007' BCLIF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCL1IP EQU H'0003' CM1IP EQU H'0005' CM2IP EQU H'0006' OSCFIP EQU H'0007' BCLIP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- RTCCIE EQU H'0000' TMR3GIE EQU H'0001' CTMUIE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- RTCCIF EQU H'0000' TMR3GIF EQU H'0001' CTMUIF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- RTCCIP EQU H'0000' TMR3GIP EQU H'0001' CTMUIP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' WPROG EQU H'0005' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' ADEN EQU H'0003' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CTMUICON Bits ----------------------------------------------------- IRNG0 EQU H'0000' IRNG1 EQU H'0001' ITRIM0 EQU H'0002' ITRIM1 EQU H'0003' ITRIM2 EQU H'0004' ITRIM3 EQU H'0005' ITRIM4 EQU H'0006' ITRIM5 EQU H'0007' ;----- CTMUCONL Bits ----------------------------------------------------- EDG1STAT EQU H'0000' EDG2STAT EQU H'0001' EDG1SEL0 EQU H'0002' EDG1SEL1 EQU H'0003' EDG1POL EQU H'0004' EDG2SEL0 EQU H'0005' EDG2SEL1 EQU H'0006' EDG2POL EQU H'0007' ;----- CTMUCONH Bits ----------------------------------------------------- CTTRIG EQU H'0000' IDISSEN EQU H'0001' EDGSEQEN EQU H'0002' EDGEN EQU H'0003' TGEN EQU H'0004' CTMUSIDL EQU H'0005' CTMUEN EQU H'0007' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- PWM2CON Bits ----------------------------------------------------- P2RSEN EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- ECCP2AS Bits ----------------------------------------------------- ECCP2ASE EQU H'0007' PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ;----- PSTR2CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1DEL Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- PWM1CON Bits ----------------------------------------------------- P1RSEN EQU H'0007' P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' ;----- ECCP1AS Bits ----------------------------------------------------- ECCP1ASE EQU H'0007' PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ;----- PSTR1CON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' CMPL0 EQU H'0006' CMPL1 EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' ULPSINK EQU H'0001' ULPEN EQU H'0002' DS EQU H'0003' ULPLVL EQU H'0005' LVDSTAT EQU H'0006' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- ADCON1 Bits ----------------------------------------------------- ADCAL EQU H'0006' ADFM EQU H'0007' ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' VCFG0 EQU H'0006' VCFG1 EQU H'0007' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSP1CON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSPCON1 Bits ----------------------------------------------------- CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' R EQU H'0002' D EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' ;----- SSP1ADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SSPADD Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- TMR2ON EQU H'0002' T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' RD16 EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' NOT_CM EQU H'0005' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' CM EQU H'0005' ;----- CM2CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- CM1CON1 Bits ----------------------------------------------------- CREF EQU H'0002' CPOL EQU H'0005' COE EQU H'0006' CON EQU H'0007' CCH0 EQU H'0000' CCH1 EQU H'0001' EVPOL0 EQU H'0003' EVPOL1 EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- OSTS EQU H'0003' IDLEN EQU H'0007' SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' ;----- T0CON Bits ----------------------------------------------------- PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE_GIEL EQU H'0006' GIE_GIEH EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0EDF'-H'0EE6' __BADRAM H'0EEB' __BADRAM H'0EEF'-H'0EF1' __BADRAM H'0EF4'-H'0EF5' __BADRAM H'0EF8'-H'0EFA' __BADRAM H'0F00'-H'0F3B' __BADRAM H'0F43'-H'0F47' __BADRAM H'0F50'-H'0F51' __BADRAM H'0F60'-H'0F65' __BADRAM H'0F87' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Watchdog Timer: ; WDTEN = OFF Disabled - Controlled by SWDTEN bit ; WDTEN = ON Enabled ; ; Stack Overflow/Underflow Reset: ; STVREN = OFF Disabled ; STVREN = ON Enabled ; ; Extended Instruction Set: ; XINST = OFF Disabled ; XINST = ON Enabled ; ; Code Protect: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Oscillator: ; OSC = INTOSC INTOSC ; OSC = INTOSCO INTOSCO (CLKO-RA6) ; OSC = INTOSCPLL INTOSCPLL ; OSC = INTOSCPLLO INTOSCPLLO (CLKO-RA6) ; OSC = HS HS ; OSC = HSPLL HS+PLL ; OSC = EC EC (CLKO-RA6) ; OSC = ECPLL EC+PLL (CLKO-RA6) ; ; T1OSCEN Enforcement: ; T1DIG = OFF Secondary Oscillator clock source may not be selected ; T1DIG = ON Secondary Oscillator clock source may be selected ; ; Low-Power Timer1 Oscillator: ; LPT1OSC = ON Low-power operation ; LPT1OSC = OFF High-power operation ; ; Fail-Safe Clock Monitor: ; FCMEN = OFF Disabled ; FCMEN = ON Enabled ; ; Internal External Oscillator Switch Over Mode: ; IESO = OFF Disabled ; IESO = ON Enabled ; ; Watchdog Postscaler: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; RTCC Clock Select: ; RTCOSC = INTOSCREF RTCC uses INTRC ; RTCOSC = T1OSCREF RTCC uses T1OSC/T1CKI ; ; IOLOCK One-Way Set Enable bit: ; IOL1WAY = OFF The IOLOCK bit (PPSCON<0>) can be set and cleared as needed ; IOL1WAY = ON The IOLOCK bit (PPSCON<0>) can be set once ; ; MSSP address masking: ; MSSP7B_EN = MSK5 5 Bit address masking mode ; MSSP7B_EN = MSK7 7 Bit address masking mode ; ; Write/Erase Protect Page Start/End Location: ; WPFP = PAGE_0 Write Protect Program Flash Page 0 ; WPFP = PAGE_1 Write Protect Program Flash Page 1 ; WPFP = PAGE_2 Write Protect Program Flash Page 2 ; WPFP = PAGE_3 Write Protect Program Flash Page 3 ; WPFP = PAGE_4 Write Protect Program Flash Page 4 ; WPFP = PAGE_5 Write Protect Program Flash Page 5 ; WPFP = PAGE_6 Write Protect Program Flash Page 6 ; WPFP = PAGE_7 Write Protect Program Flash Page 7 ; WPFP = PAGE_8 Write Protect Program Flash Page 8 ; WPFP = PAGE_9 Write Protect Program Flash Page 9 ; WPFP = PAGE_10 Write Protect Program Flash Page 10 ; WPFP = PAGE_11 Write Protect Program Flash Page 11 ; WPFP = PAGE_12 Write Protect Program Flash Page 12 ; WPFP = PAGE_13 Write Protect Program Flash Page 13 ; WPFP = PAGE_14 Write Protect Program Flash Page 14 ; WPFP = PAGE_15 Write Protect Program Flash Page 15 ; WPFP = PAGE_16 Write Protect Program Flash Page 16 ; WPFP = PAGE_17 Write Protect Program Flash Page 17 ; WPFP = PAGE_18 Write Protect Program Flash Page 18 ; WPFP = PAGE_19 Write Protect Program Flash Page 19 ; WPFP = PAGE_20 Write Protect Program Flash Page 20 ; WPFP = PAGE_21 Write Protect Program Flash Page 21 ; WPFP = PAGE_22 Write Protect Program Flash Page 22 ; WPFP = PAGE_23 Write Protect Program Flash Page 23 ; WPFP = PAGE_24 Write Protect Program Flash Page 24 ; WPFP = PAGE_25 Write Protect Program Flash Page 25 ; WPFP = PAGE_26 Write Protect Program Flash Page 26 ; WPFP = PAGE_27 Write Protect Program Flash Page 27 ; WPFP = PAGE_28 Write Protect Program Flash Page 28 ; WPFP = PAGE_29 Write Protect Program Flash Page 29 ; WPFP = PAGE_30 Write Protect Program Flash Page 30 ; WPFP = PAGE_31 Write Protect Program Flash Page 31 ; WPFP = PAGE_32 Write Protect Program Flash Page 32 ; WPFP = PAGE_33 Write Protect Program Flash Page 33 ; WPFP = PAGE_34 Write Protect Program Flash Page 34 ; WPFP = PAGE_35 Write Protect Program Flash Page 35 ; WPFP = PAGE_36 Write Protect Program Flash Page 36 ; WPFP = PAGE_37 Write Protect Program Flash Page 37 ; WPFP = PAGE_38 Write Protect Program Flash Page 38 ; WPFP = PAGE_39 Write Protect Program Flash Page 39 ; WPFP = PAGE_40 Write Protect Program Flash Page 40 ; WPFP = PAGE_41 Write Protect Program Flash Page 41 ; WPFP = PAGE_42 Write Protect Program Flash Page 42 ; WPFP = PAGE_43 Write Protect Program Flash Page 43 ; WPFP = PAGE_44 Write Protect Program Flash Page 44 ; WPFP = PAGE_45 Write Protect Program Flash Page 45 ; WPFP = PAGE_46 Write Protect Program Flash Page 46 ; WPFP = PAGE_47 Write Protect Program Flash Page 47 ; WPFP = PAGE_48 Write Protect Program Flash Page 48 ; WPFP = PAGE_49 Write Protect Program Flash Page 49 ; WPFP = PAGE_50 Write Protect Program Flash Page 50 ; WPFP = PAGE_51 Write Protect Program Flash Page 51 ; WPFP = PAGE_52 Write Protect Program Flash Page 52 ; WPFP = PAGE_53 Write Protect Program Flash Page 53 ; WPFP = PAGE_54 Write Protect Program Flash Page 54 ; WPFP = PAGE_55 Write Protect Program Flash Page 55 ; WPFP = PAGE_56 Write Protect Program Flash Page 56 ; WPFP = PAGE_57 Write Protect Program Flash Page 57 ; WPFP = PAGE_58 Write Protect Program Flash Page 58 ; WPFP = PAGE_59 Write Protect Program Flash Page 59 ; WPFP = PAGE_60 Write Protect Program Flash Page 60 ; WPFP = PAGE_61 Write Protect Program Flash Page 61 ; WPFP = PAGE_62 Write Protect Program Flash Page 62 ; WPFP = PAGE_63 Write Protect Program Flash Page 63 ; ; Write/Erase Protect Region Select bit (valid when WPDIS = 0): ; WPEND = PAGE_0 Page 0 to WPFP<5:0> erase/write-protected ; WPEND = PAGE_WPFP Pages WPFP<5:0> to (Configuration Words page) write/erase protected ; ; Write/Erase Protect Configuration Region : ; WPCFG = ON Configuration Words page erase/write-protected ; WPCFG = OFF Configuration Words page not erase/write-protected ; ; Write Protect Disable bit: ; WPDIS = ON WPFP[5:0], WPEND, and WPCFG bits enabled ; WPDIS = OFF WPFP[5:0], WPEND, and WPCFG bits ignored ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p16f74.inc0000644000175000017500000003147311156313161013072 00000000000000 LIST ; P16F74.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F74 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F74 ; 2. LIST directive in the source file ; LIST P=PIC16F74 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 00/00/00 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F74 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' ADRES EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ADCON1 EQU H'009F' PMDATA EQU H'010C' PMADR EQU H'010D' PMDATH EQU H'010E' PMADRH EQU H'010F' PMCON1 EQU H'018C' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- ADCON0 Bits -------------------------------------------------------- ADCS1 EQU H'0007' ADCS0 EQU H'0006' CHS2 EQU H'0005' CHS1 EQU H'0004' CHS0 EQU H'0003' GO EQU H'0002' NOT_DONE EQU H'0002' GO_DONE EQU H'0002' ADON EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- ADCON1 Bits -------------------------------------------------------- PCFG2 EQU H'0002' PCFG1 EQU H'0001' PCFG0 EQU H'0000' ;----- PMCON1 Bits -------------------------------------------------------- RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E' __BADRAM H'105', H'107'-H'109', H'110'-H'11F' __BADRAM H'185', H'187'-H'189', H'18D'-H'19F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'3FEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p16lf1934.inc0000644000175000017500000012544411156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC16LF1934 processor include ; ; (c) Copyright 1999-2009 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC16LF1934 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC16LF1934 ; 2. LIST directive in the source file ; LIST P=PIC16LF1934 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16LF1934 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF W EQU 0 F EQU 1 ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- ;-----Bank0------------------ INDF0 EQU H'0000' INDF1 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR0L EQU H'0004' FSR0 EQU H'0004' FSR0H EQU H'0005' FSR1L EQU H'0006' FSR1 EQU H'0006' FSR1H EQU H'0007' BSR EQU H'0008' WREG EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PORTA EQU H'000C' PORTB EQU H'000D' PORTC EQU H'000E' PORTD EQU H'000F' PORTE EQU H'0010' PIR1 EQU H'0011' PIR2 EQU H'0012' PIR3 EQU H'0013' TMR0 EQU H'0015' TMR1L EQU H'0016' TMR1 EQU H'0016' TMR1H EQU H'0017' T1CON EQU H'0018' T1GCON EQU H'0019' TMR2 EQU H'001A' PR2 EQU H'001B' T2CON EQU H'001C' CPSCON0 EQU H'001E' CPSCON1 EQU H'001F' ;-----Bank1------------------ TRISA EQU H'008C' TRISB EQU H'008D' TRISC EQU H'008E' TRISD EQU H'008F' TRISE EQU H'0090' PIE1 EQU H'0091' PIE2 EQU H'0092' PIE3 EQU H'0093' OPTION_REG EQU H'0095' PCON EQU H'0096' WDTCON EQU H'0097' OSCTUNE EQU H'0098' OSCCON EQU H'0099' OSCCONL EQU H'0099' OSCCONH EQU H'009A' OSCSTAT EQU H'009A' ADRESL EQU H'009B' ADRES EQU H'009B' ADRESH EQU H'009C' ADCON0 EQU H'009D' ADCON1 EQU H'009E' ;-----Bank2------------------ LATA EQU H'010C' LATB EQU H'010D' LATC EQU H'010E' LATD EQU H'010F' LATE EQU H'0110' CM1CON0 EQU H'0111' CM1CON1 EQU H'0112' CM2CON0 EQU H'0113' CM2CON1 EQU H'0114' CMOUT EQU H'0115' BORCON EQU H'0116' VREFCON0 EQU H'0117' VREFCON1 EQU H'0118' VREFCON2 EQU H'0119' SRCON0 EQU H'011A' SRCON1 EQU H'011B' APFCON EQU H'011D' ;-----Bank3------------------ ANSELA EQU H'018C' ANSELB EQU H'018D' ANSELD EQU H'018F' ANSELE EQU H'0190' EEADRL EQU H'0191' EEADR EQU H'0191' EEADRH EQU H'0192' EEDATL EQU H'0193' EEDAT EQU H'0193' EEDATH EQU H'0194' EECON1 EQU H'0195' EECON2 EQU H'0196' RCREG EQU H'0199' TXREG EQU H'019A' SPBRGL EQU H'019B' SPBRG EQU H'019B' SPBRGH EQU H'019C' RCSTA EQU H'019D' TXSTA EQU H'019E' BAUDCTL EQU H'019F' ;-----Bank4------------------ WPUB EQU H'020D' WPUE EQU H'0210' SSPBUF EQU H'0211' SSPADD EQU H'0212' SSPMSK EQU H'0213' SSPSTAT EQU H'0214' SSPCON EQU H'0215' SSPCON2 EQU H'0216' SSPCON3 EQU H'0217' ;-----Bank5------------------ CCPR1L EQU H'0291' CCPR1H EQU H'0292' CCP1CON EQU H'0293' PWM1CON EQU H'0294' ECCP1AS EQU H'0295' PSTR1CON EQU H'0296' CCPR2L EQU H'0298' CCPR2H EQU H'0299' CCP2CON EQU H'029A' PWM2CON EQU H'029B' ECCP2AS EQU H'029C' PSTR2CON EQU H'029D' CCPTMRS0 EQU H'029E' CCPTMRS1 EQU H'029F' ;-----Bank6------------------ CCPR3L EQU H'0311' CCPR3H EQU H'0312' CCP3CON EQU H'0313' PWM3CON EQU H'0314' ECCP3AS EQU H'0315' PSTR3CON EQU H'0316' CCPR4L EQU H'0318' CCPR4H EQU H'0319' CCP4CON EQU H'031A' CCPR5L EQU H'031C' CCPR5H EQU H'031D' CCP5CON EQU H'031E' ;-----Bank7------------------ IOCBP EQU H'0394' IOCBN EQU H'0395' IOCBF EQU H'0396' ;-----Bank8------------------ TMR4 EQU H'0415' PR4 EQU H'0416' T4CON EQU H'0417' TMR6 EQU H'041C' PR6 EQU H'041D' T6CON EQU H'041E' ;-----Bank15------------------ LCDCON EQU H'0791' LCDPS EQU H'0792' LCDREF EQU H'0793' LCDCST EQU H'0794' LCDRL EQU H'0795' LCDSE0 EQU H'0798' LCDSE1 EQU H'0799' LCDSE2 EQU H'079A' LCDDATA0 EQU H'07A0' LCDDATA1 EQU H'07A1' LCDDATA2 EQU H'07A2' LCDDATA3 EQU H'07A3' LCDDATA4 EQU H'07A4' LCDDATA5 EQU H'07A5' LCDDATA6 EQU H'07A6' LCDDATA7 EQU H'07A7' LCDDATA8 EQU H'07A8' LCDDATA9 EQU H'07A9' LCDDATA10 EQU H'07AA' LCDDATA11 EQU H'07AB' ;-----Bank31------------------ STATUS_SHAD EQU H'0FE4' WREG_SHAD EQU H'0FE5' BSR_SHAD EQU H'0FE6' PCLATH_SHAD EQU H'0FE7' FSR0L_SHAD EQU H'0FE8' FSR0H_SHAD EQU H'0FE9' FSR1L_SHAD EQU H'0FEA' FSR1H_SHAD EQU H'0FEB' STKPTR EQU H'0FED' TOSL EQU H'0FEE' TOSH EQU H'0FEF' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' NOT_PD EQU H'0003' NOT_TO EQU H'0004' ;----- BSR Bits ----------------------------------------------------- BSR0 EQU H'0000' BSR1 EQU H'0001' BSR2 EQU H'0002' BSR3 EQU H'0003' BSR4 EQU H'0004' ;----- INTCON Bits ----------------------------------------------------- IOCIF EQU H'0000' INTF EQU H'0001' TMR0IF EQU H'0002' IOCIE EQU H'0003' INTE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' TMR1GIF EQU H'0007' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' LCDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C1IF EQU H'0005' C2IF EQU H'0006' OSFIF EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- TMR4IF EQU H'0001' TMR6IF EQU H'0003' CCP3IF EQU H'0004' CCP4IF EQU H'0005' CCP5IF EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' TMR1CS0 EQU H'0006' TMR1CS1 EQU H'0007' ;----- T1GCON Bits ----------------------------------------------------- T1GSS0 EQU H'0000' T1GSS1 EQU H'0001' T1GVAL EQU H'0002' T1GGO EQU H'0003' T1GSPM EQU H'0004' T1GTM EQU H'0005' T1GPOL EQU H'0006' TMR1GE EQU H'0007' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- CPSCON0 Bits ----------------------------------------------------- T0XCS EQU H'0000' CPSOUT EQU H'0001' CPSRNG0 EQU H'0002' CPSRNG1 EQU H'0003' CPSON EQU H'0007' ;----- CPSCON1 Bits ----------------------------------------------------- CPSCH0 EQU H'0000' CPSCH1 EQU H'0001' CPSCH2 EQU H'0002' CPSCH3 EQU H'0003' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' TMR1GIE EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' LCDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C1IE EQU H'0005' C2IE EQU H'0006' OSFIE EQU H'0007' ;----- PIE3 Bits ----------------------------------------------------- TMR4IE EQU H'0001' TMR6IE EQU H'0003' CCP3IE EQU H'0004' CCP4IE EQU H'0005' CCP5IE EQU H'0006' ;----- OPTION_REG Bits ----------------------------------------------------- PS0 EQU H'0000' PS1 EQU H'0001' PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' INTEDG EQU H'0006' NOT_WPUEN EQU H'0007' ;----- PCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_RI EQU H'0002' NOT_RMCLR EQU H'0003' STKUNF EQU H'0006' STKOVF EQU H'0007' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' WDTPS0 EQU H'0001' WDTPS1 EQU H'0002' WDTPS2 EQU H'0003' WDTPS3 EQU H'0004' WDTPS4 EQU H'0005' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IRCF0 EQU H'0003' IRCF1 EQU H'0004' IRCF2 EQU H'0005' IRFC3 EQU H'0006' SPLLEN EQU H'0007' ;----- OSCSTAT Bits ----------------------------------------------------- HFIOFS EQU H'0000' LFIOFR EQU H'0001' MFIOFR EQU H'0002' HFIOFL EQU H'0003' HFIOFR EQU H'0004' OSTS EQU H'0005' PLLR EQU H'0006' T1OSCR EQU H'0007' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_NOT_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' CHS4 EQU H'0006' ADGO EQU H'0001' ;----- ADCON1 Bits ----------------------------------------------------- ADPREF0 EQU H'0000' ADPREF1 EQU H'0001' ADNREF EQU H'0002' ADCS0 EQU H'0004' ADCS1 EQU H'0005' ADCS2 EQU H'0006' ADFM EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' ;----- CM1CON0 Bits ----------------------------------------------------- C1SYNC EQU H'0000' C1HYS EQU H'0001' C1SP EQU H'0002' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT EQU H'0006' C1ON EQU H'0007' ;----- CM1CON1 Bits ----------------------------------------------------- C1NCH0 EQU H'0000' C1NCH1 EQU H'0001' C1PCH0 EQU H'0004' C1PCH1 EQU H'0005' C1INTN EQU H'0006' C1INTP EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2SYNC EQU H'0000' C2HYS EQU H'0001' C2SP EQU H'0002' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT EQU H'0006' C2ON EQU H'0007' ;----- CM2CON1 Bits ----------------------------------------------------- C2NCH0 EQU H'0000' C2NCH1 EQU H'0001' C2PCH0 EQU H'0004' C2PCH1 EQU H'0005' C2INTN EQU H'0006' C2INTP EQU H'0007' ;----- CMOUT Bits ----------------------------------------------------- MC1OUT EQU H'0000' MC2OUT EQU H'0001' ;----- BORCON Bits ----------------------------------------------------- BORRDY EQU H'0000' SBOREN EQU H'0007' ;----- VREFCON0 Bits ----------------------------------------------------- ADFVR0 EQU H'0000' ADFVR1 EQU H'0001' CDAFVR0 EQU H'0002' CDAFVR1 EQU H'0003' TSRNG EQU H'0004' TSEN EQU H'0005' FVRRDY EQU H'0006' FVREN EQU H'0007' ;----- VREFCON1 Bits ----------------------------------------------------- D1NSS EQU H'0000' D1PSS0 EQU H'0002' D1PSS1 EQU H'0003' DAC1OE EQU H'0005' D1LPS EQU H'0006' D1EN EQU H'0007' ;----- VREFCON2 Bits ----------------------------------------------------- DAC1R0 EQU H'0000' DAC1R1 EQU H'0001' DAC1R2 EQU H'0002' DAC1R3 EQU H'0003' DAC1R4 EQU H'0004' ;----- SRCON0 Bits ----------------------------------------------------- SRPR EQU H'0000' SRPS EQU H'0001' SRNQEN EQU H'0002' SRQEN EQU H'0003' SRCLK0 EQU H'0004' SRCLK1 EQU H'0005' SRCLK2 EQU H'0006' SRLEN EQU H'0007' ;----- SRCON1 Bits ----------------------------------------------------- SRRC1E EQU H'0000' SRRC2E EQU H'0001' SRRCKE EQU H'0002' SRRPE EQU H'0003' SRSC1E EQU H'0004' SRSC2E EQU H'0005' SRSCKE EQU H'0006' SRSPE EQU H'0007' ;----- APFCON Bits ----------------------------------------------------- CCP2SEL EQU H'0000' SSSEL EQU H'0001' C2OUTSEL EQU H'0002' SRNQSEL EQU H'0003' P2BSEL EQU H'0004' T1GSEL EQU H'0005' CCP3SEL EQU H'0006' ;----- ANSELA Bits ----------------------------------------------------- ANSA0 EQU H'0000' ANSA1 EQU H'0001' ANSA2 EQU H'0002' ANSA3 EQU H'0003' ANSA4 EQU H'0004' ANSA5 EQU H'0005' ;----- ANSELB Bits ----------------------------------------------------- ANSB0 EQU H'0000' ANSB1 EQU H'0001' ANSB2 EQU H'0002' ANSB3 EQU H'0003' ANSB4 EQU H'0004' ANSB5 EQU H'0005' ;----- ANSELD Bits ----------------------------------------------------- ANSD0 EQU H'0000' ANSD1 EQU H'0001' ANSD2 EQU H'0002' ANSD3 EQU H'0003' ANSD4 EQU H'0004' ANSD5 EQU H'0005' ANSD6 EQU H'0006' ANSD7 EQU H'0007' ;----- ANSELE Bits ----------------------------------------------------- ANSE0 EQU H'0000' ANSE1 EQU H'0001' ANSE2 EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' LWLO EQU H'0005' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- WPUE Bits ----------------------------------------------------- WPUE3 EQU H'0003' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_NOT_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_NOT_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' ;----- SSPCON Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON3 Bits ----------------------------------------------------- DHEN EQU H'0000' AHEN EQU H'0001' SBCDE EQU H'0002' SDAHT EQU H'0003' BOEN EQU H'0004' ACKTIM EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' CCP1AS0 EQU H'0004' CCP1AS1 EQU H'0005' CCP1AS2 EQU H'0006' CCP1ASE EQU H'0007' ;----- PSTR1CON Bits ----------------------------------------------------- STR1A EQU H'0000' STR1B EQU H'0001' STR1C EQU H'0002' STR1D EQU H'0003' STR1SYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' ;----- PWM2CON Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' CCP2AS0 EQU H'0004' CCP2AS1 EQU H'0005' CCP2AS2 EQU H'0006' CCP2ASE EQU H'0007' ;----- PSTR2CON Bits ----------------------------------------------------- STR2A EQU H'0000' STR2B EQU H'0001' STR2C EQU H'0002' STR2D EQU H'0003' STR2SYNC EQU H'0004' ;----- CCPTMRS0 Bits ----------------------------------------------------- C1TSEL0 EQU H'0000' C1TSEL1 EQU H'0001' C2TSEL0 EQU H'0002' C2TSEL1 EQU H'0003' C3TSEL0 EQU H'0004' C3TSEL1 EQU H'0005' C4TSEL0 EQU H'0006' C4TSEL1 EQU H'0007' ;----- CCPTMRS1 Bits ----------------------------------------------------- C5TSEL0 EQU H'0000' C5TSEL1 EQU H'0001' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' ;----- PWM3CON Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' CCP3AS0 EQU H'0004' CCP3AS1 EQU H'0005' CCP3AS2 EQU H'0006' CCP3ASE EQU H'0007' ;----- PSTR3CON Bits ----------------------------------------------------- STR3A EQU H'0000' STR3B EQU H'0001' STR3C EQU H'0002' STR3D EQU H'0003' STR3SYNC EQU H'0004' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- IOCBP Bits ----------------------------------------------------- IOCBP0 EQU H'0000' IOCBP1 EQU H'0001' IOCBP2 EQU H'0002' IOCBP3 EQU H'0003' IOCBP4 EQU H'0004' IOCBP5 EQU H'0005' IOCBP6 EQU H'0006' IOCBP7 EQU H'0007' ;----- IOCBN Bits ----------------------------------------------------- IOCBN0 EQU H'0000' IOCBN1 EQU H'0001' IOCBN2 EQU H'0002' IOCBN3 EQU H'0003' IOCBN4 EQU H'0004' IOCBN5 EQU H'0005' IOCBN6 EQU H'0006' IOCBN7 EQU H'0007' ;----- IOCBF Bits ----------------------------------------------------- IOCBF0 EQU H'0000' IOCBF1 EQU H'0001' IOCBF2 EQU H'0002' IOCBF3 EQU H'0003' IOCBF4 EQU H'0004' IOCBF5 EQU H'0005' IOCBF6 EQU H'0006' IOCBF7 EQU H'0007' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- T6CON Bits ----------------------------------------------------- T6CKPS0 EQU H'0000' T6CKPS1 EQU H'0001' TMR6ON EQU H'0002' T6OUTPS0 EQU H'0003' T6OUTPS1 EQU H'0004' T6OUTPS2 EQU H'0005' T6OUTPS3 EQU H'0006' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' ;----- LCDREF Bits ----------------------------------------------------- VLCD1PE EQU H'0001' VLCD2PE EQU H'0002' VLCD3PE EQU H'0003' LCDIRI EQU H'0005' LCDIRS EQU H'0006' LCDIRE EQU H'0007' ;----- LCDCST Bits ----------------------------------------------------- LCDCST0 EQU H'0000' LCDCST1 EQU H'0001' LCDCST2 EQU H'0002' ;----- LCDRL Bits ----------------------------------------------------- LRLAT0 EQU H'0000' LRLAT1 EQU H'0001' LRLAT2 EQU H'0002' LRLBP0 EQU H'0004' LRLBP1 EQU H'0005' LRLAP0 EQU H'0006' LRLAP1 EQU H'0007' ;----- LCDSE0 Bits ----------------------------------------------------- SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SEG8 EQU H'0000' SEG9 EQU H'0001' SEG10 EQU H'0002' SEG11 EQU H'0003' SEG12 EQU H'0004' SEG13 EQU H'0005' SEG14 EQU H'0006' SEG15 EQU H'0007' ;----- LCDSE2 Bits ----------------------------------------------------- SEG16 EQU H'0000' SEG17 EQU H'0001' SEG18 EQU H'0002' SEG19 EQU H'0003' SEG20 EQU H'0004' SEG21 EQU H'0005' SEG22 EQU H'0006' SEG23 EQU H'0007' ;----- LCDDATA0 Bits ----------------------------------------------------- SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' ;----- LCDDATA2 Bits ----------------------------------------------------- SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' ;----- LCDDATA5 Bits ----------------------------------------------------- SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA6 Bits ----------------------------------------------------- SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' ;----- LCDDATA8 Bits ----------------------------------------------------- SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' ;----- LCDDATA11 Bits ----------------------------------------------------- SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- STATUS_SHAD Bits ----------------------------------------------------- C_SHAD EQU H'0000' DC_SHAD EQU H'0001' Z_SHAD EQU H'0002' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0014' __BADRAM H'001D' __BADRAM H'0094' __BADRAM H'009F' __BADRAM H'011C' __BADRAM H'011E'-H'011F' __BADRAM H'018E' __BADRAM H'0197'-H'0198' __BADRAM H'01A0'-H'01EF' __BADRAM H'020C' __BADRAM H'020E'-H'020F' __BADRAM H'0218'-H'021F' __BADRAM H'0220'-H'026F' __BADRAM H'028C'-H'0290' __BADRAM H'0297' __BADRAM H'02A0'-H'02EF' __BADRAM H'030C'-H'0310' __BADRAM H'0317' __BADRAM H'031B' __BADRAM H'031F' __BADRAM H'0320'-H'036F' __BADRAM H'038C'-H'0393' __BADRAM H'0397'-H'039F' __BADRAM H'03A0'-H'03EF' __BADRAM H'040C'-H'0414' __BADRAM H'0418'-H'041B' __BADRAM H'041F' __BADRAM H'0420'-H'046F' __BADRAM H'048C'-H'049F' __BADRAM H'04A0'-H'04EF' __BADRAM H'050C'-H'051F' __BADRAM H'0520'-H'056F' __BADRAM H'058C'-H'059F' __BADRAM H'05A0'-H'05EF' __BADRAM H'060C'-H'061F' __BADRAM H'0620'-H'066F' __BADRAM H'068C'-H'069F' __BADRAM H'06A0'-H'06EF' __BADRAM H'070C'-H'071F' __BADRAM H'0720'-H'076F' __BADRAM H'078C'-H'0790' __BADRAM H'0796'-H'0797' __BADRAM H'079B'-H'079F' __BADRAM H'07AC'-H'07EF' __BADRAM H'080C'-H'081F' __BADRAM H'0820'-H'086F' __BADRAM H'088C'-H'089F' __BADRAM H'08A0'-H'08EF' __BADRAM H'090C'-H'091F' __BADRAM H'0920'-H'096F' __BADRAM H'098C'-H'099F' __BADRAM H'09A0'-H'09EF' __BADRAM H'0A0C'-H'0A1F' __BADRAM H'0A20'-H'0A6F' __BADRAM H'0A8C'-H'0A9F' __BADRAM H'0AA0'-H'0AEF' __BADRAM H'0B0C'-H'0B1F' __BADRAM H'0B20'-H'0B6F' __BADRAM H'0B8C'-H'0B9F' __BADRAM H'0BA0'-H'0BEF' __BADRAM H'0C0C'-H'0C1F' __BADRAM H'0C20'-H'0C6F' __BADRAM H'0C8C'-H'0C9F' __BADRAM H'0CA0'-H'0CEF' __BADRAM H'0D0C'-H'0D1F' __BADRAM H'0D20'-H'0D6F' __BADRAM H'0D8C'-H'0D9F' __BADRAM H'0DA0'-H'0DEF' __BADRAM H'0E0C'-H'0E1F' __BADRAM H'0E20'-H'0E6F' __BADRAM H'0E8C'-H'0E9F' __BADRAM H'0EA0'-H'0EEF' __BADRAM H'0F0C'-H'0F1F' __BADRAM H'0F20'-H'0F6F' __BADRAM H'0F8C'-H'0FE3' __BADRAM H'0FEC' ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1 8007h ; CONFIG2 8008h ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1 EQU H'8007' _CONFIG2 EQU H'8008' ;----- CONFIG1 Options -------------------------------------------------- _FOSC_LP EQU H'FFF8' ; LP Oscillator, Low-power crystal on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_XT EQU H'FFF9' ; XT Oscillator, Crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_HS EQU H'FFFA' ; HS Oscillator, High speed crystal/resonator on RA6/OSC2/CLKO pin and RA7/OSC1/CLKI _FOSC_EXTRC EQU H'FFFB' ; EXTRC Oscillator, RC on RA7/OSC1/CLKIN _FOSC_INTOSC EQU H'FFFC' ; INTOSC Oscillator, I/O function on RA7/OSC1/CLKI _FOSC_ECL EQU H'FFFD' ; ECL, External Clock, Low Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECM EQU H'FFFE' ; ECM, External Clock, Medium Power Mode: CLKI on RA7/OSC1/CLKI _FOSC_ECH EQU H'FFFF' ; ECH, External Clock, High Power Mode: CLKI on RA7/OSC1/CLKI _WDTE_OFF EQU H'FFE7' ; WDT disabled _WDTE_SWDTEN EQU H'FFEF' ; WDT controlled by the SWDTEN bit in the WDTCON register _WDTE_NSLEEP EQU H'FFF7' ; WDT enabled while running and disabled in Sleep _WDTE_ON EQU H'FFFF' ; WDT enabled _nPWRTE_OFF EQU H'FFDF' ; PWRT enabled _nPWRTE_ON EQU H'FFFF' ; PWRT disabled _MCLRE_OFF EQU H'FFBF' ; RE3/MCLR/VPP pin function is digital input _MCLRE_ON EQU H'FFFF' ; RE3/MCLR/VPP pin function is MCLR _CP_ON EQU H'FF7F' ; Program memory code protection is enabled _CP_OFF EQU H'FFFF' ; Program memory code protection is disabled _CPD_ON EQU H'FEFF' ; Data memory code protection is enabled _CPD_OFF EQU H'FFFF' ; Data memory code protection is disabled _BOREN_OFF EQU H'F9FF' ; Brown-out Reset disabled _BOREN_SBODEN EQU H'FBFF' ; Brown-out Reset controlled by the SBOREN bit in the PCON register _BOREN_NSLEEP EQU H'FDFF' ; Brown-out Reset enabled while running and disabled in Sleep _BOREN_ON EQU H'FFFF' ; Brown-out Reset enabled _CLKOUTEN_OFF EQU H'F7FF' ; CLKOUT function is enabled on RA6/CLKOUT pin _CLKOUTEN_ON EQU H'FFFF' ; CLKOUT function is disabled. I/O or oscillator function on RA6/CLKOUT _IESO_OFF EQU H'EFFF' ; Internal/External Switchover mode is disabled _IESO_ON EQU H'FFFF' ; Internal/External Switchover mode is enabled _FCMEN_OFF EQU H'DFFF' ; Fail-Safe Clock Monitor is disabled _FCMEN_ON EQU H'FFFF' ; Fail-Safe Clock Monitor is enabled ;----- CONFIG2 Options -------------------------------------------------- _WRT_ALL EQU H'FFFC' ; 000h to 1FFFh write protected, no addresses may be modified by EECON control _WRT_HALF EQU H'FFFD' ; 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control _WRT_BOOT EQU H'FFFE' ; 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control _WRT_OFF EQU H'FFFF' ; Write protection off _VCAPEN_RA0 EQU H'FFCF' ; VCAP functionality is enabled on RA0 _VCAPEN_RA5 EQU H'FFDF' ; VCAP functionality is enabled on RA5 _VCAPEN_RA6 EQU H'FFEF' ; VCAP functionality is enabled on RA6 _VCAPEN_OFF EQU H'FFFF' ; All VCAP pin functions are disabled _PLLEN_OFF EQU H'FEFF' ; 4x PLL disabled _PLLEN_ON EQU H'FFFF' ; 4x PLL enabled _STVREN_OFF EQU H'FDFF' ; Stack Overflow or underflow will not cause a Reset _STVREN_ON EQU H'FFFF' ; Stack Overflow or underflow will cause a Reset _BORV_27 EQU H'FBFF' ; Brown-out Reset Voltage (VBOR) set to 2.7 V _BORV_19 EQU H'FFFF' ; Brown-out Reset Voltage (VBOR) set to 1.9 V _nDEBUG_ON EQU H'EFFF' ; Background debugger is enabled _nDEBUG_OFF EQU H'FFFF' ; Background debugger is disabled _LVP_OFF EQU H'DFFF' ; HV on MCLR/VPP must be used for programming _LVP_ON EQU H'FFFF' ; Low voltage programming enabled _DEVID1 EQU H'008006' _IDLOC0 EQU H'008000' _IDLOC1 EQU H'008001' _IDLOC2 EQU H'008002' _IDLOC3 EQU H'008003' LIST gputils-0.13.7/header/p18f2321.inc0000644000175000017500000011274311156521301013226 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2321 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2321 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2321 ; 2. LIST directive in the source file ; LIST P=PIC18F2321 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2321 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' TRISA EQU H'0F92' TRISB EQU H'0F93' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' ECCP1DEL EQU H'0FB7' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' C1N EQU H'0000' C2N EQU H'0001' C2P EQU H'0002' C1P EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' HLVDIN EQU H'0005' CVREF EQU H'0002' T0CKI EQU H'0004' NOT_SS EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP1DEL Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RXDTP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' TXCKP EQU H'0004' RCMT EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ADMSK1 EQU H'0001' ADMSK2 EQU H'0002' ADMSK3 EQU H'0003' ADMSK4 EQU H'0004' ADMSK5 EQU H'0005' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' TOUTPS0 EQU H'0003' TOUTPS1 EQU H'0004' TOUTPS2 EQU H'0005' TOUTPS3 EQU H'0006' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T016BIT EQU H'0006' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' T0IF EQU H'0002' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0200'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FB9' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = RB3 CCP2 input/output is multiplexed with RB3 ; CCP2MX = RC1 CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Word ; BBSIZ = BB512 512 Word ; BBSIZ = BB1K 1024 Word ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP Oscillator _OSC_XT_1H EQU H'F1' ; XT Oscillator _OSC_HS_1H EQU H'F2' ; HS Oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO2_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO1_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOR_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOR_SOFT_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOR_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOR_ON_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_DIG_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ANA_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_RB3_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_RC1_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB256_4L EQU H'CF' ; 256 Word _BBSIZ_BB512_4L EQU H'DF' ; 512 Word _BBSIZ_BB1K_4L EQU H'FF' ; 1024 Word _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block code-protected _CPB_OFF_5H EQU H'FF' ; Boot block not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTB_ON_6H EQU H'BF' ; Boot block write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f6628.inc0000644000175000017500000017661511156521302013255 00000000000000 LIST ;========================================================================== ; MPASM PIC18F6628 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F6628 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F6628 ; 2. LIST directive in the source file ; LIST P=PIC18F6628 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F6628 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C EQU H'0003' P3B EQU H'0004' P1C EQU H'0005' P1B EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F99'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTE ECCP2 input/output is multiplexed with RE7 ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTE_3H EQU H'FE' ; ECCP2 input/output is multiplexed with RE7 _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f8527.inc0000644000175000017500000020515611156521301013245 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8527 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8527 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8527 ; 2. LIST directive in the source file ; LIST P=PIC18F8527 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8527 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ECCP2_PORTB EQU H'0003' P2A_PORTB EQU H'0003' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C_PORTE EQU H'0003' P3B_PORTE EQU H'0004' P1C_PORTE EQU H'0005' P1B_PORTE EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' P3C_PORTH EQU H'0004' P3B_PORTH EQU H'0005' P1C_PORTH EQU H'0006' P1B_PORTH EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; Address Bus Width Select bits: ; ADDRBW = ADDR8BIT 8-bit Address Bus ; ADDRBW = ADDR12BIT 12-bit Address Bus ; ADDRBW = ADDR16BIT 16-bit Address Bus ; ADDRBW = ADDR20BIT 20-bit Address Bus ; ; Data Bus Width Select bit: ; DATABW = DATA8BIT 8-bit External Bus mode ; DATABW = DATA16BIT 16-bit External Bus mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits ; WAIT = OFF Wait selections are unavailable for table reads and table writes ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; ECCP MUX bit: ; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively ; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively ; ; CCP2 MUX bit: ; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _ADDRBW_ADDR8BIT_3L EQU H'CF' ; 8-bit Address Bus _ADDRBW_ADDR12BIT_3L EQU H'DF' ; 12-bit Address Bus _ADDRBW_ADDR16BIT_3L EQU H'EF' ; 16-bit Address Bus _ADDRBW_ADDR20BIT_3L EQU H'FF' ; 20-bit Address Bus _DATABW_DATA8BIT_3L EQU H'BF' ; 8-bit External Bus mode _DATABW_DATA16BIT_3L EQU H'FF' ; 16-bit External Bus mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits _WAIT_OFF_3L EQU H'FF' ; Wait selections are unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _ECCPMX_PORTH_3H EQU H'FD' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively _ECCPMX_PORTE_3H EQU H'FF' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively _CCP2MX_PORTBE_3H EQU H'FE' ; ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f65j90.inc0000644000175000017500000015023611156521301013413 00000000000000 LIST ;========================================================================== ; MPASM PIC18F65J90 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F65J90 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F65J90 ; 2. LIST directive in the source file ; LIST P=PIC18F65J90 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F65J90 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F60' TXSTA2 EQU H'0F61' TXREG2 EQU H'0F62' RCREG2 EQU H'0F63' SPBRG2 EQU H'0F64' CCP2CON EQU H'0F65' CCPR2 EQU H'0F66' CCPR2L EQU H'0F66' CCPR2H EQU H'0F67' CCP1CON EQU H'0F68' CCPR1 EQU H'0F69' CCPR1L EQU H'0F69' CCPR1H EQU H'0F6A' LCDDATA6 EQU H'0F6C' LCDDATA7 EQU H'0F6D' LCDDATA8 EQU H'0F6E' LCDDATA9 EQU H'0F6F' LCDDATA10 EQU H'0F70' LCDDATA12 EQU H'0F72' LCDDATA13 EQU H'0F73' LCDDATA14 EQU H'0F74' LCDDATA15 EQU H'0F75' LCDDATA16 EQU H'0F76' LCDDATA18 EQU H'0F78' LCDDATA19 EQU H'0F79' LCDDATA20 EQU H'0F7A' LCDDATA21 EQU H'0F7B' LCDDATA22 EQU H'0F7C' BAUDCON1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' LCDCON EQU H'0FA8' LCDSE0 EQU H'0FA9' LCDPS EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' LCDSE1 EQU H'0FB6' LCDSE2 EQU H'0FB7' LCDSE3 EQU H'0FB8' LCDSE4 EQU H'0FB9' LCDDATA0 EQU H'0FBB' LCDDATA1 EQU H'0FBC' LCDDATA2 EQU H'0FBD' LCDDATA3 EQU H'0FBE' LCDDATA4 EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' LCDREG EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- LCDDATA6 Bits ----------------------------------------------------- S0C1 EQU H'0000' S1C1 EQU H'0001' S2C1 EQU H'0002' S3C1 EQU H'0003' S4C1 EQU H'0004' S5C1 EQU H'0005' S6C1 EQU H'0006' S7C1 EQU H'0007' SEG0COM1 EQU H'0000' SEG1COM1 EQU H'0001' SEG2COM1 EQU H'0002' SEG3COM1 EQU H'0003' SEG4COM1 EQU H'0004' SEG5COM1 EQU H'0005' SEG6COM1 EQU H'0006' SEG7COM1 EQU H'0007' S00C1 EQU H'0000' S01C1 EQU H'0001' S02C1 EQU H'0002' S03C1 EQU H'0003' S04C1 EQU H'0004' S05C1 EQU H'0005' S06C1 EQU H'0006' S07C1 EQU H'0007' ;----- LCDDATA7 Bits ----------------------------------------------------- S8C1 EQU H'0000' S9C1 EQU H'0001' S10C1 EQU H'0002' S11C1 EQU H'0003' S12C1 EQU H'0004' S13C1 EQU H'0005' S14C1 EQU H'0006' S15C1 EQU H'0007' SEG8COM1 EQU H'0000' SEG9COM1 EQU H'0001' SEG10COM1 EQU H'0002' SEG11COM1 EQU H'0003' SEG12COM1 EQU H'0004' SEG13COM1 EQU H'0005' SEG14COM1 EQU H'0006' SEG15COM1 EQU H'0007' S08C1 EQU H'0000' S09C1 EQU H'0001' ;----- LCDDATA8 Bits ----------------------------------------------------- S16C1 EQU H'0000' S17C1 EQU H'0001' S18C1 EQU H'0002' S19C1 EQU H'0003' S20C1 EQU H'0004' S21C1 EQU H'0005' S22C1 EQU H'0006' S23C1 EQU H'0007' SEG16COM1 EQU H'0000' SEG17COM1 EQU H'0001' SEG18COM1 EQU H'0002' SEG19COM1 EQU H'0003' SEG20COM1 EQU H'0004' SEG21COM1 EQU H'0005' SEG22COM1 EQU H'0006' SEG23COM1 EQU H'0007' ;----- LCDDATA9 Bits ----------------------------------------------------- S24C1 EQU H'0000' S25C1 EQU H'0001' S26C1 EQU H'0002' S27C1 EQU H'0003' S28C1 EQU H'0004' S29C1 EQU H'0005' S30C1 EQU H'0006' S31C1 EQU H'0007' SEG24COM1 EQU H'0000' SEG25COM1 EQU H'0001' SEG26COM1 EQU H'0002' SEG27COM1 EQU H'0003' SEG28COM1 EQU H'0004' SEG29COM1 EQU H'0005' SEG30COM1 EQU H'0006' SEG31COM1 EQU H'0007' ;----- LCDDATA10 Bits ----------------------------------------------------- S32C1 EQU H'0000' SEG32COM1 EQU H'0000' ;----- LCDDATA12 Bits ----------------------------------------------------- S0C2 EQU H'0000' S1C2 EQU H'0001' S2C2 EQU H'0002' S3C2 EQU H'0003' S4C2 EQU H'0004' S5C2 EQU H'0005' S6C2 EQU H'0006' S7C2 EQU H'0007' SEG0COM2 EQU H'0000' SEG1COM2 EQU H'0001' SEG2COM2 EQU H'0002' SEG3COM2 EQU H'0003' SEG4COM2 EQU H'0004' SEG5COM2 EQU H'0005' SEG6COM2 EQU H'0006' SEG7COM2 EQU H'0007' S00C2 EQU H'0000' S01C2 EQU H'0001' S02C2 EQU H'0002' S03C2 EQU H'0003' S04C2 EQU H'0004' S05C2 EQU H'0005' S06C2 EQU H'0006' S07C2 EQU H'0007' ;----- LCDDATA13 Bits ----------------------------------------------------- S8C2 EQU H'0000' S9C2 EQU H'0001' S10C2 EQU H'0002' S11C2 EQU H'0003' S12C2 EQU H'0004' S13C2 EQU H'0005' S14C2 EQU H'0006' S15C2 EQU H'0007' SEG8COM2 EQU H'0000' SEG9COM2 EQU H'0001' SEG10COM2 EQU H'0002' SEG11COM2 EQU H'0003' SEG12COM2 EQU H'0004' SEG13COM2 EQU H'0005' SEG14COM2 EQU H'0006' SEG15COM2 EQU H'0007' S08C2 EQU H'0000' S09C2 EQU H'0001' ;----- LCDDATA14 Bits ----------------------------------------------------- S16C2 EQU H'0000' S17C2 EQU H'0001' S18C2 EQU H'0002' S19C2 EQU H'0003' S20C2 EQU H'0004' S21C2 EQU H'0005' S22C2 EQU H'0006' S23C2 EQU H'0007' SEG16COM2 EQU H'0000' SEG17COM2 EQU H'0001' SEG18COM2 EQU H'0002' SEG19COM2 EQU H'0003' SEG20COM2 EQU H'0004' SEG21COM2 EQU H'0005' SEG22COM2 EQU H'0006' SEG23COM2 EQU H'0007' ;----- LCDDATA15 Bits ----------------------------------------------------- S24C2 EQU H'0000' S25C2 EQU H'0001' S26C2 EQU H'0002' S27C2 EQU H'0003' S28C2 EQU H'0004' S29C2 EQU H'0005' S30C2 EQU H'0006' S31C2 EQU H'0007' SEG24COM2 EQU H'0000' SEG25COM2 EQU H'0001' SEG26COM2 EQU H'0002' SEG27COM2 EQU H'0003' SEG28COM2 EQU H'0004' SEG29COM2 EQU H'0005' SEG30COM2 EQU H'0006' SEG31COM2 EQU H'0007' ;----- LCDDATA16 Bits ----------------------------------------------------- S32C2 EQU H'0000' SEG32COM2 EQU H'0000' ;----- LCDDATA18 Bits ----------------------------------------------------- S0C3 EQU H'0000' S1C3 EQU H'0001' S2C3 EQU H'0002' S3C3 EQU H'0003' S4C3 EQU H'0004' S5C3 EQU H'0005' S6C3 EQU H'0006' S7C3 EQU H'0007' SEG0COM3 EQU H'0000' SEG1COM3 EQU H'0001' SEG2COM3 EQU H'0002' SEG3COM3 EQU H'0003' SEG4COM3 EQU H'0004' SEG5COM3 EQU H'0005' SEG6COM3 EQU H'0006' SEG7COM3 EQU H'0007' S00C3 EQU H'0000' S01C3 EQU H'0001' S02C3 EQU H'0002' S03C3 EQU H'0003' S04C3 EQU H'0004' S05C3 EQU H'0005' S06C3 EQU H'0006' S07C3 EQU H'0007' ;----- LCDDATA19 Bits ----------------------------------------------------- S8C3 EQU H'0000' S9C3 EQU H'0001' S10C3 EQU H'0002' S11C3 EQU H'0003' S12C3 EQU H'0004' S13C3 EQU H'0005' S14C3 EQU H'0006' S15C3 EQU H'0007' SEG8COM3 EQU H'0000' SEG9COM3 EQU H'0001' SEG10COM3 EQU H'0002' SEG11COM3 EQU H'0003' SEG12COM3 EQU H'0004' SEG13COM3 EQU H'0005' SEG14COM3 EQU H'0006' SEG15COM3 EQU H'0007' S08C3 EQU H'0000' S09C3 EQU H'0001' ;----- LCDDATA20 Bits ----------------------------------------------------- S16C3 EQU H'0000' S17C3 EQU H'0001' S18C3 EQU H'0002' S19C3 EQU H'0003' S20C3 EQU H'0004' S21C3 EQU H'0005' S22C3 EQU H'0006' S23C3 EQU H'0007' SEG16COM3 EQU H'0000' SEG17COM3 EQU H'0001' SEG18COM3 EQU H'0002' SEG19COM3 EQU H'0003' SEG20COM3 EQU H'0004' SEG21COM3 EQU H'0005' SEG22COM3 EQU H'0006' SEG23COM3 EQU H'0007' ;----- LCDDATA21 Bits ----------------------------------------------------- S24C3 EQU H'0000' S25C3 EQU H'0001' S26C3 EQU H'0002' S27C3 EQU H'0003' S28C3 EQU H'0004' S29C3 EQU H'0005' S30C3 EQU H'0006' S31C3 EQU H'0007' SEG24COM3 EQU H'0000' SEG25COM3 EQU H'0001' SEG26COM3 EQU H'0002' SEG27COM3 EQU H'0003' SEG28COM3 EQU H'0004' SEG29COM3 EQU H'0005' SEG30COM3 EQU H'0006' SEG31COM3 EQU H'0007' ;----- LCDDATA22 Bits ----------------------------------------------------- S32C3 EQU H'0000' SEG32COM3 EQU H'0000' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCMT EQU H'0006' ABDOVF EQU H'0007' RCIDL EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' SEG18 EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' SEG14 EQU H'0004' SEG15 EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' SEG30 EQU H'0000' SEG8 EQU H'0001' SEG9 EQU H'0002' SEG10 EQU H'0003' SEG11 EQU H'0004' SEG29 EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' SEG32 EQU H'0001' SEG13 EQU H'0002' SEG17 EQU H'0003' SEG16 EQU H'0004' SEG12 EQU H'0005' SEG27 EQU H'0006' SEG28 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' SEG0 EQU H'0000' SEG1 EQU H'0001' SEG2 EQU H'0002' SEG3 EQU H'0003' SEG4 EQU H'0004' SEG5 EQU H'0005' SEG6 EQU H'0006' SEG7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' LCDBIAS1 EQU H'0000' LCDBIAS2 EQU H'0001' COM0 EQU H'0003' COM1 EQU H'0004' COM2 EQU H'0005' COM3 EQU H'0006' CCP2_PORTE EQU H'0007' SEG31 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' AN5 EQU H'0007' CVREF EQU H'0005' SEG19 EQU H'0001' SEG20 EQU H'0002' SEG21 EQU H'0003' SEG22 EQU H'0004' SEG23 EQU H'0005' SEG24 EQU H'0006' SEG25 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' C2INB EQU H'0003' C2INA EQU H'0004' C1INB EQU H'0005' C1INA EQU H'0006' SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' REPU EQU H'0006' RDPU EQU H'0007' LCDBIAS0 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' VLCAP2 EQU H'0003' SEG26 EQU H'0004' CK2 EQU H'0001' DT2 EQU H'0002' VLCAP1 EQU H'0002' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' U1OD EQU H'0006' U2OD EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' CCP1OD EQU H'0005' CCP2OD EQU H'0006' SPIOD EQU H'0007' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP1IE EQU H'0001' CCP2IE EQU H'0002' TX2IE EQU H'0004' RC2IE EQU H'0005' LCDIE EQU H'0006' ;----- PIR3 Bits ----------------------------------------------------- CCP1IF EQU H'0001' CCP2IF EQU H'0002' TX2IF EQU H'0004' RC2IF EQU H'0005' LCDIF EQU H'0006' ;----- IPR3 Bits ----------------------------------------------------- CCP1IP EQU H'0001' CCP2IP EQU H'0002' TX2IP EQU H'0004' RC2IP EQU H'0005' LCDIP EQU H'0006' ;----- EECON1 Bits ----------------------------------------------------- WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' ;----- LCDCON Bits ----------------------------------------------------- LMUX0 EQU H'0000' LMUX1 EQU H'0001' CS0 EQU H'0002' CS1 EQU H'0003' WERR EQU H'0005' SLPEN EQU H'0006' LCDEN EQU H'0007' LCDCS0 EQU H'0002' LCDCS1 EQU H'0003' LCDWERR EQU H'0005' LCDSLPEN EQU H'0006' ;----- LCDSE0 Bits ----------------------------------------------------- SE0 EQU H'0000' SE1 EQU H'0001' SE2 EQU H'0002' SE3 EQU H'0003' SE4 EQU H'0004' SE5 EQU H'0005' SE6 EQU H'0006' SE7 EQU H'0007' SEGEN0 EQU H'0000' SEGEN1 EQU H'0001' SEGEN2 EQU H'0002' SEGEN3 EQU H'0003' SEGEN4 EQU H'0004' SEGEN5 EQU H'0005' SEGEN6 EQU H'0006' SEGEN7 EQU H'0007' SE00 EQU H'0000' SE01 EQU H'0001' SE02 EQU H'0002' SE03 EQU H'0003' SE04 EQU H'0004' SE05 EQU H'0005' SE06 EQU H'0006' SE07 EQU H'0007' ;----- LCDPS Bits ----------------------------------------------------- LP0 EQU H'0000' LP1 EQU H'0001' LP2 EQU H'0002' LP3 EQU H'0003' WA EQU H'0004' LCDA EQU H'0005' BIASMD EQU H'0006' WFT EQU H'0007' LCDPS0 EQU H'0000' LCDPS1 EQU H'0001' LCDPS2 EQU H'0002' LCDPS3 EQU H'0003' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- LCDSE1 Bits ----------------------------------------------------- SE8 EQU H'0000' SE9 EQU H'0001' SE10 EQU H'0002' SE11 EQU H'0003' SE12 EQU H'0004' SE13 EQU H'0005' SE14 EQU H'0006' SE15 EQU H'0007' SEGEN8 EQU H'0000' SEGEN9 EQU H'0001' SEGEN10 EQU H'0002' SEGEN11 EQU H'0003' SEGEN12 EQU H'0004' SEGEN13 EQU H'0005' SEGEN14 EQU H'0006' SEGEN15 EQU H'0007' SE08 EQU H'0000' SE09 EQU H'0001' ;----- LCDSE2 Bits ----------------------------------------------------- SE16 EQU H'0000' SE17 EQU H'0001' SE18 EQU H'0002' SE19 EQU H'0003' SE20 EQU H'0004' SE21 EQU H'0005' SE22 EQU H'0006' SE23 EQU H'0007' SEGEN16 EQU H'0000' SEGEN17 EQU H'0001' SEGEN18 EQU H'0002' SEGEN19 EQU H'0003' SEGEN20 EQU H'0004' SEGEN21 EQU H'0005' SEGEN22 EQU H'0006' SEGEN23 EQU H'0007' ;----- LCDSE3 Bits ----------------------------------------------------- SE24 EQU H'0000' SE25 EQU H'0001' SE26 EQU H'0002' SE27 EQU H'0003' SE28 EQU H'0004' SE29 EQU H'0005' SE30 EQU H'0006' SE31 EQU H'0007' SEGEN24 EQU H'0000' SEGEN25 EQU H'0001' SEGEN26 EQU H'0002' SEGEN27 EQU H'0003' SEGEN28 EQU H'0004' SEGEN29 EQU H'0005' SEGEN30 EQU H'0006' SEGEN31 EQU H'0007' ;----- LCDSE4 Bits ----------------------------------------------------- SE32 EQU H'0000' SEGEN32 EQU H'0000' ;----- LCDDATA0 Bits ----------------------------------------------------- S0C0 EQU H'0000' S1C0 EQU H'0001' S2C0 EQU H'0002' S3C0 EQU H'0003' S4C0 EQU H'0004' S5C0 EQU H'0005' S6C0 EQU H'0006' S7C0 EQU H'0007' SEG0COM0 EQU H'0000' SEG1COM0 EQU H'0001' SEG2COM0 EQU H'0002' SEG3COM0 EQU H'0003' SEG4COM0 EQU H'0004' SEG5COM0 EQU H'0005' SEG6COM0 EQU H'0006' SEG7COM0 EQU H'0007' S00C0 EQU H'0000' S01C0 EQU H'0001' S02C0 EQU H'0002' S03C0 EQU H'0003' S04C0 EQU H'0004' S05C0 EQU H'0005' S06C0 EQU H'0006' S07C0 EQU H'0007' ;----- LCDDATA1 Bits ----------------------------------------------------- S8C0 EQU H'0000' S9C0 EQU H'0001' S10C0 EQU H'0002' S11C0 EQU H'0003' S12C0 EQU H'0004' S13C0 EQU H'0005' S14C0 EQU H'0006' S15C0 EQU H'0007' SEG8COM0 EQU H'0000' SEG9COM0 EQU H'0001' SEG10COM0 EQU H'0002' SEG11COM0 EQU H'0003' SEG12COM0 EQU H'0004' SEG13COM0 EQU H'0005' SEG14COM0 EQU H'0006' SEG15COM0 EQU H'0007' S08C0 EQU H'0000' S09C0 EQU H'0001' ;----- LCDDATA2 Bits ----------------------------------------------------- S16C0 EQU H'0000' S17C0 EQU H'0001' S18C0 EQU H'0002' S19C0 EQU H'0003' S20C0 EQU H'0004' S21C0 EQU H'0005' S22C0 EQU H'0006' S23C0 EQU H'0007' SEG16COM0 EQU H'0000' SEG17COM0 EQU H'0001' SEG18COM0 EQU H'0002' SEG19COM0 EQU H'0003' SEG20COM0 EQU H'0004' SEG21COM0 EQU H'0005' SEG22COM0 EQU H'0006' SEG23COM0 EQU H'0007' ;----- LCDDATA3 Bits ----------------------------------------------------- S24C0 EQU H'0000' S25C0 EQU H'0001' S26C0 EQU H'0002' S27C0 EQU H'0003' S28C0 EQU H'0004' S29C0 EQU H'0005' S30C0 EQU H'0006' S31C0 EQU H'0007' SEG24COM0 EQU H'0000' SEG25COM0 EQU H'0001' SEG26COM0 EQU H'0002' SEG27COM0 EQU H'0003' SEG28COM0 EQU H'0004' SEG29COM0 EQU H'0005' SEG30COM0 EQU H'0006' SEG31COM0 EQU H'0007' ;----- LCDDATA4 Bits ----------------------------------------------------- S32C0 EQU H'0000' SEG32COM0 EQU H'0000' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' ADCAL EQU H'0007' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' REGSLP EQU H'0007' SWDTE EQU H'0000' ;----- LCDREG Bits ----------------------------------------------------- CKSEL0 EQU H'0000' CKSEL1 EQU H'0001' MODE13 EQU H'0002' BIAS0 EQU H'0003' BIAS1 EQU H'0004' BIAS2 EQU H'0005' CPEN EQU H'0006' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0800'-H'0F5F' __BADRAM H'0F6B' __BADRAM H'0F71' __BADRAM H'0F77' __BADRAM H'0F7D' __BADRAM H'0F87'-H'0F88' __BADRAM H'0F90'-H'0F91' __BADRAM H'0F9C' __BADRAM H'0FB0' __BADRAM H'0FBA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Stack Overflow/Underflow Reset Enable bit: ; STVREN = OFF Reset on stack overflow/underflow disabled ; STVREN = ON Reset on stack overflow/underflow enabled ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT disabled (control is placed on SWDTEN bit) ; WDTEN = ON WDT enabled ; ; Code Protection bit: ; CP0 = ON Program memory is code-protected ; CP0 = OFF Program memory is not code-protected ; ; Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Default/Reset System Clock Select bit: ; FOSC2 = OFF INTRC enabled as system clock when OSCCON<1:0> = 00 ; FOSC2 = ON Clock selected by FOSC1:FOSC0 as system clock is enabled when OSCCON<1:0> = 00 ; ; Oscillator Selection bits: ; FOSC = HS HS oscillator ; FOSC = HSPLL HS oscillator, PLL enabled and under software control ; FOSC = EC EC oscillator, CLKO function on OSC2 ; FOSC = ECPLL EC oscillator, PLL enabled and under software control, CLK function on OSC2 ; ; Watchdog Timer Postscaler Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; ECCP2 MUX bit: ; CCP2MX = ALTERNATE ECCP2/P2A is multiplexed with RE7 in Microcontroller mode or with RB3 in Extended Microcontroller mode ; CCP2MX = DEFAULT ECCP2/P2A is multiplexed with RC1 ; ;========================================================================== _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' LIST gputils-0.13.7/header/p18f2682.inc0000644000175000017500000041600311156521301013234 00000000000000 LIST ;========================================================================== ; MPASM PIC18F2682 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F2682 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F2682 ; 2. LIST directive in the source file ; LIST P=PIC18F2682 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F2682 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RXF6SIDH EQU H'0D60' RXF6SIDL EQU H'0D61' RXF6EIDH EQU H'0D62' RXF6EIDL EQU H'0D63' RXF7SIDH EQU H'0D64' RXF7SIDL EQU H'0D65' RXF7EIDH EQU H'0D66' RXF7EIDL EQU H'0D67' RXF8SIDH EQU H'0D68' RXF8SIDL EQU H'0D69' RXF8EIDH EQU H'0D6A' RXF8EIDL EQU H'0D6B' RXF9SIDH EQU H'0D70' RXF9SIDL EQU H'0D71' RXF9EIDH EQU H'0D72' RXF9EIDL EQU H'0D73' RXF10SIDH EQU H'0D74' RXF10SIDL EQU H'0D75' RXF10EIDH EQU H'0D76' RXF10EIDL EQU H'0D77' RXF11SIDH EQU H'0D78' RXF11SIDL EQU H'0D79' RXF11EIDH EQU H'0D7A' RXF11EIDL EQU H'0D7B' RXF12SIDH EQU H'0D80' RXF12SIDL EQU H'0D81' RXF12EIDH EQU H'0D82' RXF12EIDL EQU H'0D83' RXF13SIDH EQU H'0D84' RXF13SIDL EQU H'0D85' RXF13EIDH EQU H'0D86' RXF13EIDL EQU H'0D87' RXF14SIDH EQU H'0D88' RXF14SIDL EQU H'0D89' RXF14EIDH EQU H'0D8A' RXF14EIDL EQU H'0D8B' RXF15SIDH EQU H'0D90' RXF15SIDL EQU H'0D91' RXF15EIDH EQU H'0D92' RXF15EIDL EQU H'0D93' RXFCON0 EQU H'0DD4' RXFCON1 EQU H'0DD5' SDFLC EQU H'0DD8' RXFBCON0 EQU H'0DE0' RXFBCON1 EQU H'0DE1' RXFBCON2 EQU H'0DE2' RXFBCON3 EQU H'0DE3' RXFBCON4 EQU H'0DE4' RXFBCON5 EQU H'0DE5' RXFBCON6 EQU H'0DE6' RXFBCON7 EQU H'0DE7' MSEL0 EQU H'0DF0' MSEL1 EQU H'0DF1' MSEL2 EQU H'0DF2' MSEL3 EQU H'0DF3' BSEL0 EQU H'0DF8' BIE0 EQU H'0DFA' TXBIE EQU H'0DFC' B0CON EQU H'0E20' B0SIDH EQU H'0E21' B0SIDL EQU H'0E22' B0EIDH EQU H'0E23' B0EIDL EQU H'0E24' B0DLC EQU H'0E25' B0D0 EQU H'0E26' B0D1 EQU H'0E27' B0D2 EQU H'0E28' B0D3 EQU H'0E29' B0D4 EQU H'0E2A' B0D5 EQU H'0E2B' B0D6 EQU H'0E2C' B0D7 EQU H'0E2D' CANSTAT_RO9 EQU H'0E2E' CANCON_RO9 EQU H'0E2F' B1CON EQU H'0E30' B1SIDH EQU H'0E31' B1SIDL EQU H'0E32' B1EIDH EQU H'0E33' B1EIDL EQU H'0E34' B1DLC EQU H'0E35' B1D0 EQU H'0E36' B1D1 EQU H'0E37' B1D2 EQU H'0E38' B1D3 EQU H'0E39' B1D4 EQU H'0E3A' B1D5 EQU H'0E3B' B1D6 EQU H'0E3C' B1D7 EQU H'0E3D' CANSTAT_RO8 EQU H'0E3E' CANCON_RO8 EQU H'0E3F' B2CON EQU H'0E40' B2SIDH EQU H'0E41' B2SIDL EQU H'0E42' B2EIDH EQU H'0E43' B2EIDL EQU H'0E44' B2DLC EQU H'0E45' B2D0 EQU H'0E46' B2D1 EQU H'0E47' B2D2 EQU H'0E48' B2D3 EQU H'0E49' B2D4 EQU H'0E4A' B2D5 EQU H'0E4B' B2D6 EQU H'0E4C' B2D7 EQU H'0E4D' CANSTAT_RO7 EQU H'0E4E' CANCON_RO7 EQU H'0E4F' B3CON EQU H'0E50' B3SIDH EQU H'0E51' B3SIDL EQU H'0E52' B3EIDH EQU H'0E53' B3EIDL EQU H'0E54' B3DLC EQU H'0E55' B3D0 EQU H'0E56' B3D1 EQU H'0E57' B3D2 EQU H'0E58' B3D3 EQU H'0E59' B3D4 EQU H'0E5A' B3D5 EQU H'0E5B' B3D6 EQU H'0E5C' B3D7 EQU H'0E5D' CANSTAT_RO6 EQU H'0E5E' CANCON_RO6 EQU H'0E5F' B4CON EQU H'0E60' B4SIDH EQU H'0E61' B4SIDL EQU H'0E62' B4EIDH EQU H'0E63' B4EIDL EQU H'0E64' B4DLC EQU H'0E65' B4D0 EQU H'0E66' B4D1 EQU H'0E67' B4D2 EQU H'0E68' B4D3 EQU H'0E69' B4D4 EQU H'0E6A' B4D5 EQU H'0E6B' B4D6 EQU H'0E6C' B4D7 EQU H'0E6D' CANSTAT_RO5 EQU H'0E6E' CANCON_RO5 EQU H'0E6F' B5CON EQU H'0E70' B5SIDH EQU H'0E71' B5SIDL EQU H'0E72' B5EIDH EQU H'0E73' B5EIDL EQU H'0E74' B5DLC EQU H'0E75' B5D0 EQU H'0E76' B5D1 EQU H'0E77' B5D2 EQU H'0E78' B5D3 EQU H'0E79' B5D4 EQU H'0E7A' B5D5 EQU H'0E7B' B5D6 EQU H'0E7C' B5D7 EQU H'0E7D' CANSTAT_RO4 EQU H'0E7E' CANCON_RO4 EQU H'0E7F' RXF0SIDH EQU H'0F00' RXF0SIDL EQU H'0F01' RXF0EIDH EQU H'0F02' RXF0EIDL EQU H'0F03' RXF1SIDH EQU H'0F04' RXF1SIDL EQU H'0F05' RXF1EIDH EQU H'0F06' RXF1EIDL EQU H'0F07' RXF2SIDH EQU H'0F08' RXF2SIDL EQU H'0F09' RXF2EIDH EQU H'0F0A' RXF2EIDL EQU H'0F0B' RXF3SIDH EQU H'0F0C' RXF3SIDL EQU H'0F0D' RXF3EIDH EQU H'0F0E' RXF3EIDL EQU H'0F0F' RXF4SIDH EQU H'0F10' RXF4SIDL EQU H'0F11' RXF4EIDH EQU H'0F12' RXF4EIDL EQU H'0F13' RXF5SIDH EQU H'0F14' RXF5SIDL EQU H'0F15' RXF5EIDH EQU H'0F16' RXF5EIDL EQU H'0F17' RXM0SIDH EQU H'0F18' RXM0SIDL EQU H'0F19' RXM0EIDH EQU H'0F1A' RXM0EIDL EQU H'0F1B' RXM1SIDH EQU H'0F1C' RXM1SIDL EQU H'0F1D' RXM1EIDH EQU H'0F1E' RXM1EIDL EQU H'0F1F' TXB2CON EQU H'0F20' TXB2SIDH EQU H'0F21' TXB2SIDL EQU H'0F22' TXB2EIDH EQU H'0F23' TXB2EIDL EQU H'0F24' TXB2DLC EQU H'0F25' TXB2D0 EQU H'0F26' TXB2D1 EQU H'0F27' TXB2D2 EQU H'0F28' TXB2D3 EQU H'0F29' TXB2D4 EQU H'0F2A' TXB2D5 EQU H'0F2B' TXB2D6 EQU H'0F2C' TXB2D7 EQU H'0F2D' CANSTAT_RO3 EQU H'0F2E' CANCON_RO3 EQU H'0F2F' TXB1CON EQU H'0F30' TXB1SIDH EQU H'0F31' TXB1SIDL EQU H'0F32' TXB1EIDH EQU H'0F33' TXB1EIDL EQU H'0F34' TXB1DLC EQU H'0F35' TXB1D0 EQU H'0F36' TXB1D1 EQU H'0F37' TXB1D2 EQU H'0F38' TXB1D3 EQU H'0F39' TXB1D4 EQU H'0F3A' TXB1D5 EQU H'0F3B' TXB1D6 EQU H'0F3C' TXB1D7 EQU H'0F3D' CANSTAT_RO2 EQU H'0F3E' CANCON_RO2 EQU H'0F3F' TXB0CON EQU H'0F40' TXB0SIDH EQU H'0F41' TXB0SIDL EQU H'0F42' TXB0EIDH EQU H'0F43' TXB0EIDL EQU H'0F44' TXB0DLC EQU H'0F45' TXB0D0 EQU H'0F46' TXB0D1 EQU H'0F47' TXB0D2 EQU H'0F48' TXB0D3 EQU H'0F49' TXB0D4 EQU H'0F4A' TXB0D5 EQU H'0F4B' TXB0D6 EQU H'0F4C' TXB0D7 EQU H'0F4D' CANSTAT_RO1 EQU H'0F4E' CANCON_RO1 EQU H'0F4F' RXB1CON EQU H'0F50' RXB1SIDH EQU H'0F51' RXB1SIDL EQU H'0F52' RXB1EIDH EQU H'0F53' RXB1EIDL EQU H'0F54' RXB1DLC EQU H'0F55' RXB1D0 EQU H'0F56' RXB1D1 EQU H'0F57' RXB1D2 EQU H'0F58' RXB1D3 EQU H'0F59' RXB1D4 EQU H'0F5A' RXB1D5 EQU H'0F5B' RXB1D6 EQU H'0F5C' RXB1D7 EQU H'0F5D' CANSTAT_RO0 EQU H'0F5E' CANCON_RO0 EQU H'0F5F' RXB0CON EQU H'0F60' RXB0SIDH EQU H'0F61' RXB0SIDL EQU H'0F62' RXB0EIDH EQU H'0F63' RXB0EIDL EQU H'0F64' RXB0DLC EQU H'0F65' RXB0D0 EQU H'0F66' RXB0D1 EQU H'0F67' RXB0D2 EQU H'0F68' RXB0D3 EQU H'0F69' RXB0D4 EQU H'0F6A' RXB0D5 EQU H'0F6B' RXB0D6 EQU H'0F6C' RXB0D7 EQU H'0F6D' CANSTAT EQU H'0F6E' CANCON EQU H'0F6F' BRGCON1 EQU H'0F70' BRGCON2 EQU H'0F71' BRGCON3 EQU H'0F72' CIOCON EQU H'0F73' COMSTAT EQU H'0F74' RXERRCNT EQU H'0F75' TXERRCNT EQU H'0F76' ECANCON EQU H'0F77' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' BAUDCON EQU H'0FB8' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RXF6SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF6SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF6EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF6EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF7SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF7SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF7EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF7EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF8SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF8SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF8EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF8EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF9SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF9SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF9EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF9EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF10SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF10SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF10EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF10EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF11SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF11SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF11EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF11EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF12SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF12SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF12EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF12EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF13SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF13SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF13EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF13EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF14SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF14SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF14EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF14EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF15SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF15SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF15EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF15EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXFCON0 Bits ----------------------------------------------------- RXF0EN EQU H'0000' RXF1EN EQU H'0001' RXF2EN EQU H'0002' RXF3EN EQU H'0003' RXF4EN EQU H'0004' RXF5EN EQU H'0005' RXF6EN EQU H'0006' RXF7EN EQU H'0007' ;----- RXFCON1 Bits ----------------------------------------------------- RXF8EN EQU H'0000' RXF9EN EQU H'0001' RXF10EN EQU H'0002' RXF11EN EQU H'0003' RXF12EN EQU H'0004' RXF13EN EQU H'0005' RXF14EN EQU H'0006' RXF15EN EQU H'0007' ;----- SDFLC Bits ----------------------------------------------------- DFLC0 EQU H'0000' DFLC1 EQU H'0001' DFLC2 EQU H'0002' DFLC3 EQU H'0003' DFLC4 EQU H'0004' FLC0 EQU H'0000' FLC1 EQU H'0001' FLC2 EQU H'0002' FLC3 EQU H'0003' FLC4 EQU H'0004' ;----- RXFBCON0 Bits ----------------------------------------------------- F0BP_0 EQU H'0000' F0BP_1 EQU H'0001' F0BP_2 EQU H'0002' F0BP_3 EQU H'0003' F1BP_0 EQU H'0004' F1BP_1 EQU H'0005' F1BP_2 EQU H'0006' F1BP_3 EQU H'0007' ;----- RXFBCON1 Bits ----------------------------------------------------- F2BP_0 EQU H'0000' F2BP_1 EQU H'0001' F2BP_2 EQU H'0002' F2BP_3 EQU H'0003' F3BP_0 EQU H'0004' F3BP_1 EQU H'0005' F3BP_2 EQU H'0006' F3BP_3 EQU H'0007' ;----- RXFBCON2 Bits ----------------------------------------------------- F4BP_0 EQU H'0000' F4BP_1 EQU H'0001' F4BP_2 EQU H'0002' F4BP_3 EQU H'0003' F5BP_0 EQU H'0004' F5BP_1 EQU H'0005' F5BP_2 EQU H'0006' F5BP_3 EQU H'0007' ;----- RXFBCON3 Bits ----------------------------------------------------- F6BP_0 EQU H'0000' F6BP_1 EQU H'0001' F6BP_2 EQU H'0002' F6BP_3 EQU H'0003' F7BP_0 EQU H'0004' F7BP_1 EQU H'0005' F7BP_2 EQU H'0006' F7BP_3 EQU H'0007' ;----- RXFBCON4 Bits ----------------------------------------------------- F8BP_0 EQU H'0000' F8BP_1 EQU H'0001' F8BP_2 EQU H'0002' F8BP_3 EQU H'0003' F9BP_0 EQU H'0004' F9BP_1 EQU H'0005' F9BP_2 EQU H'0006' F9BP_3 EQU H'0007' ;----- RXFBCON5 Bits ----------------------------------------------------- F10BP_0 EQU H'0000' F10BP_1 EQU H'0001' F10BP_2 EQU H'0002' F10BP_3 EQU H'0003' F11BP_0 EQU H'0004' F11BP_1 EQU H'0005' F11BP_2 EQU H'0006' F11BP_3 EQU H'0007' ;----- RXFBCON6 Bits ----------------------------------------------------- F12BP_0 EQU H'0000' F12BP_1 EQU H'0001' F12BP_2 EQU H'0002' F12BP_3 EQU H'0003' F13BP_0 EQU H'0004' F13BP_1 EQU H'0005' F13BP_2 EQU H'0006' F13BP_3 EQU H'0007' ;----- RXFBCON7 Bits ----------------------------------------------------- F14BP_0 EQU H'0000' F14BP_1 EQU H'0001' F14BP_2 EQU H'0002' F14BP_3 EQU H'0003' F15BP_0 EQU H'0004' F15BP_1 EQU H'0005' F15BP_2 EQU H'0006' F15BP_3 EQU H'0007' ;----- MSEL0 Bits ----------------------------------------------------- FIL0_0 EQU H'0000' FIL0_1 EQU H'0001' FIL1_0 EQU H'0002' FIL1_1 EQU H'0003' FIL2_0 EQU H'0004' FIL2_1 EQU H'0005' FIL3_0 EQU H'0006' FIL3_1 EQU H'0007' ;----- MSEL1 Bits ----------------------------------------------------- FIL4_0 EQU H'0000' FIL4_1 EQU H'0001' FIL5_0 EQU H'0002' FIL5_1 EQU H'0003' FIL6_0 EQU H'0004' FIL6_1 EQU H'0005' FIL7_0 EQU H'0006' FIL7_1 EQU H'0007' ;----- MSEL2 Bits ----------------------------------------------------- FIL8_0 EQU H'0000' FIL8_1 EQU H'0001' FIL9_0 EQU H'0002' FIL9_1 EQU H'0003' FIL10_0 EQU H'0004' FIL10_1 EQU H'0005' FIL11_0 EQU H'0006' FIL11_1 EQU H'0007' ;----- MSEL3 Bits ----------------------------------------------------- FIL12_0 EQU H'0000' FIL12_1 EQU H'0001' FIL13_0 EQU H'0002' FIL13_1 EQU H'0003' FIL14_0 EQU H'0004' FIL14_1 EQU H'0005' FIL15_0 EQU H'0006' FIL15_1 EQU H'0007' ;----- BSEL0 Bits ----------------------------------------------------- B0TXEN EQU H'0002' B1TXEN EQU H'0003' B2TXEN EQU H'0004' B3TXEN EQU H'0005' B4TXEN EQU H'0006' B5TXEN EQU H'0007' ;----- BIE0 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' B0IE EQU H'0002' B1IE EQU H'0003' B2IE EQU H'0004' B3IE EQU H'0005' B4IE EQU H'0006' B5IE EQU H'0007' ;----- TXBIE Bits ----------------------------------------------------- TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ;----- B0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B0CON EQU H'0005' ;----- B0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B0DLC EQU H'0004' RB1_B0DLC EQU H'0005' ;----- B0D0 Bits ----------------------------------------------------- B0D00 EQU H'0000' B0D01 EQU H'0001' B0D02 EQU H'0002' B0D03 EQU H'0003' B0D04 EQU H'0004' B0D05 EQU H'0005' B0D06 EQU H'0006' B0D07 EQU H'0007' ;----- B0D1 Bits ----------------------------------------------------- B0D10 EQU H'0000' B0D11 EQU H'0001' B0D12 EQU H'0002' B0D13 EQU H'0003' B0D14 EQU H'0004' B0D15 EQU H'0005' B0D16 EQU H'0006' B0D17 EQU H'0007' ;----- B0D2 Bits ----------------------------------------------------- B0D20 EQU H'0000' B0D21 EQU H'0001' B0D22 EQU H'0002' B0D23 EQU H'0003' B0D24 EQU H'0004' B0D25 EQU H'0005' B0D26 EQU H'0006' B0D27 EQU H'0007' ;----- B0D3 Bits ----------------------------------------------------- B0D30 EQU H'0000' B0D31 EQU H'0001' B0D32 EQU H'0002' B0D33 EQU H'0003' B0D34 EQU H'0004' B0D35 EQU H'0005' B0D36 EQU H'0006' B0D37 EQU H'0007' ;----- B0D4 Bits ----------------------------------------------------- B0D40 EQU H'0000' B0D41 EQU H'0001' B0D42 EQU H'0002' B0D43 EQU H'0003' B0D44 EQU H'0004' B0D45 EQU H'0005' B0D46 EQU H'0006' B0D47 EQU H'0007' ;----- B0D5 Bits ----------------------------------------------------- B0D50 EQU H'0000' B0D51 EQU H'0001' B0D52 EQU H'0002' B0D53 EQU H'0003' B0D54 EQU H'0004' B0D55 EQU H'0005' B0D56 EQU H'0006' B0D57 EQU H'0007' ;----- B0D6 Bits ----------------------------------------------------- B0D60 EQU H'0000' B0D61 EQU H'0001' B0D62 EQU H'0002' B0D63 EQU H'0003' B0D64 EQU H'0004' B0D65 EQU H'0005' B0D66 EQU H'0006' B0D67 EQU H'0007' ;----- B0D7 Bits ----------------------------------------------------- B0D70 EQU H'0000' B0D71 EQU H'0001' B0D72 EQU H'0002' B0D73 EQU H'0003' B0D74 EQU H'0004' B0D75 EQU H'0005' B0D76 EQU H'0006' B0D77 EQU H'0007' ;----- CANSTAT_RO9 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO9 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B1CON EQU H'0005' ;----- B1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B1DLC EQU H'0004' RB1_B1DLC EQU H'0005' TXRTR EQU H'0006' ;----- B1D0 Bits ----------------------------------------------------- B1D00 EQU H'0000' B1D01 EQU H'0001' B1D02 EQU H'0002' B1D03 EQU H'0003' B1D04 EQU H'0004' B1D05 EQU H'0005' B1D06 EQU H'0006' B1D07 EQU H'0007' ;----- B1D1 Bits ----------------------------------------------------- B1D10 EQU H'0000' B1D11 EQU H'0001' B1D12 EQU H'0002' B1D13 EQU H'0003' B1D14 EQU H'0004' B1D15 EQU H'0005' B1D16 EQU H'0006' B1D17 EQU H'0007' ;----- B1D2 Bits ----------------------------------------------------- B1D20 EQU H'0000' B1D21 EQU H'0001' B1D22 EQU H'0002' B1D23 EQU H'0003' B1D24 EQU H'0004' B1D25 EQU H'0005' B1D26 EQU H'0006' B1D27 EQU H'0007' ;----- B1D3 Bits ----------------------------------------------------- B1D30 EQU H'0000' B1D31 EQU H'0001' B1D32 EQU H'0002' B1D33 EQU H'0003' B1D34 EQU H'0004' B1D35 EQU H'0005' B1D36 EQU H'0006' B1D37 EQU H'0007' ;----- B1D4 Bits ----------------------------------------------------- B1D40 EQU H'0000' B1D41 EQU H'0001' B1D42 EQU H'0002' B1D43 EQU H'0003' B1D44 EQU H'0004' B1D45 EQU H'0005' B1D46 EQU H'0006' B1D47 EQU H'0007' ;----- B1D5 Bits ----------------------------------------------------- B1D50 EQU H'0000' B1D51 EQU H'0001' B1D52 EQU H'0002' B1D53 EQU H'0003' B1D54 EQU H'0004' B1D55 EQU H'0005' B1D56 EQU H'0006' B1D57 EQU H'0007' ;----- B1D6 Bits ----------------------------------------------------- B1D60 EQU H'0000' B1D61 EQU H'0001' B1D62 EQU H'0002' B1D63 EQU H'0003' B1D64 EQU H'0004' B1D65 EQU H'0005' B1D66 EQU H'0006' B1D67 EQU H'0007' ;----- B1D7 Bits ----------------------------------------------------- B1D70 EQU H'0000' B1D71 EQU H'0001' B1D72 EQU H'0002' B1D73 EQU H'0003' B1D74 EQU H'0004' B1D75 EQU H'0005' B1D76 EQU H'0006' B1D77 EQU H'0007' ;----- CANSTAT_RO8 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO8 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B2CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B2CON EQU H'0005' ;----- B2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B2DLC EQU H'0004' RB1_B2DLC EQU H'0005' ;----- B2D0 Bits ----------------------------------------------------- B2D00 EQU H'0000' B2D01 EQU H'0001' B2D02 EQU H'0002' B2D03 EQU H'0003' B2D04 EQU H'0004' B2D05 EQU H'0005' B2D06 EQU H'0006' B2D07 EQU H'0007' ;----- B2D1 Bits ----------------------------------------------------- B2D10 EQU H'0000' B2D11 EQU H'0001' B2D12 EQU H'0002' B2D13 EQU H'0003' B2D14 EQU H'0004' B2D15 EQU H'0005' B2D16 EQU H'0006' B2D17 EQU H'0007' ;----- B2D2 Bits ----------------------------------------------------- B2D20 EQU H'0000' B2D21 EQU H'0001' B2D22 EQU H'0002' B2D23 EQU H'0003' B2D24 EQU H'0004' B2D25 EQU H'0005' B2D26 EQU H'0006' B2D27 EQU H'0007' ;----- B2D3 Bits ----------------------------------------------------- B2D30 EQU H'0000' B2D31 EQU H'0001' B2D32 EQU H'0002' B2D33 EQU H'0003' B2D34 EQU H'0004' B2D35 EQU H'0005' B2D36 EQU H'0006' B2D37 EQU H'0007' ;----- B2D4 Bits ----------------------------------------------------- B2D40 EQU H'0000' B2D41 EQU H'0001' B2D42 EQU H'0002' B2D43 EQU H'0003' B2D44 EQU H'0004' B2D45 EQU H'0005' B2D46 EQU H'0006' B2D47 EQU H'0007' ;----- B2D5 Bits ----------------------------------------------------- B2D50 EQU H'0000' B2D51 EQU H'0001' B2D52 EQU H'0002' B2D53 EQU H'0003' B2D54 EQU H'0004' B2D55 EQU H'0005' B2D56 EQU H'0006' B2D57 EQU H'0007' ;----- B2D6 Bits ----------------------------------------------------- B2D60 EQU H'0000' B2D61 EQU H'0001' B2D62 EQU H'0002' B2D63 EQU H'0003' B2D64 EQU H'0004' B2D65 EQU H'0005' B2D66 EQU H'0006' B2D67 EQU H'0007' ;----- B2D7 Bits ----------------------------------------------------- B2D70 EQU H'0000' B2D71 EQU H'0001' B2D72 EQU H'0002' B2D73 EQU H'0003' B2D74 EQU H'0004' B2D75 EQU H'0005' B2D76 EQU H'0006' B2D77 EQU H'0007' ;----- CANSTAT_RO7 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO7 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B3CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B3CON EQU H'0005' ;----- B3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B3DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B3DLC EQU H'0004' RB1_B3DLC EQU H'0005' ;----- B3D0 Bits ----------------------------------------------------- B3D00 EQU H'0000' B3D01 EQU H'0001' B3D02 EQU H'0002' B3D03 EQU H'0003' B3D04 EQU H'0004' B3D05 EQU H'0005' B3D06 EQU H'0006' B3D07 EQU H'0007' ;----- B3D1 Bits ----------------------------------------------------- B3D10 EQU H'0000' B3D11 EQU H'0001' B3D12 EQU H'0002' B3D13 EQU H'0003' B3D14 EQU H'0004' B3D15 EQU H'0005' B3D16 EQU H'0006' B3D17 EQU H'0007' ;----- B3D2 Bits ----------------------------------------------------- B3D20 EQU H'0000' B3D21 EQU H'0001' B3D22 EQU H'0002' B3D23 EQU H'0003' B3D24 EQU H'0004' B3D25 EQU H'0005' B3D26 EQU H'0006' B3D27 EQU H'0007' ;----- B3D3 Bits ----------------------------------------------------- B3D30 EQU H'0000' B3D31 EQU H'0001' B3D32 EQU H'0002' B3D33 EQU H'0003' B3D34 EQU H'0004' B3D35 EQU H'0005' B3D36 EQU H'0006' B3D37 EQU H'0007' ;----- B3D4 Bits ----------------------------------------------------- B3D40 EQU H'0000' B3D41 EQU H'0001' B3D42 EQU H'0002' B3D43 EQU H'0003' B3D44 EQU H'0004' B3D45 EQU H'0005' B3D46 EQU H'0006' B3D47 EQU H'0007' ;----- B3D5 Bits ----------------------------------------------------- B3D50 EQU H'0000' B3D51 EQU H'0001' B3D52 EQU H'0002' B3D53 EQU H'0003' B3D54 EQU H'0004' B3D55 EQU H'0005' B3D56 EQU H'0006' B3D57 EQU H'0007' ;----- B3D6 Bits ----------------------------------------------------- B3D60 EQU H'0000' B3D61 EQU H'0001' B3D62 EQU H'0002' B3D63 EQU H'0003' B3D64 EQU H'0004' B3D65 EQU H'0005' B3D66 EQU H'0006' B3D67 EQU H'0007' ;----- B3D7 Bits ----------------------------------------------------- B3D70 EQU H'0000' B3D71 EQU H'0001' B3D72 EQU H'0002' B3D73 EQU H'0003' B3D74 EQU H'0004' B3D75 EQU H'0005' B3D76 EQU H'0006' B3D77 EQU H'0007' ;----- CANSTAT_RO6 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO6 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B4CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B4CON EQU H'0005' ;----- B4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDE EQU H'0003' ;----- B4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B4DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' TXRTR EQU H'0006' RB0_B4DLC EQU H'0004' RB1_B4DLC EQU H'0005' ;----- B4D0 Bits ----------------------------------------------------- B4D00 EQU H'0000' B4D01 EQU H'0001' B4D02 EQU H'0002' B4D03 EQU H'0003' B4D04 EQU H'0004' B4D05 EQU H'0005' B4D06 EQU H'0006' B4D07 EQU H'0007' ;----- B4D1 Bits ----------------------------------------------------- B4D10 EQU H'0000' B4D11 EQU H'0001' B4D12 EQU H'0002' B4D13 EQU H'0003' B4D14 EQU H'0004' B4D15 EQU H'0005' B4D16 EQU H'0006' B4D17 EQU H'0007' ;----- B4D2 Bits ----------------------------------------------------- B4D20 EQU H'0000' B4D21 EQU H'0001' B4D22 EQU H'0002' B4D23 EQU H'0003' B4D24 EQU H'0004' B4D25 EQU H'0005' B4D26 EQU H'0006' B4D27 EQU H'0007' ;----- B4D3 Bits ----------------------------------------------------- B4D30 EQU H'0000' B4D31 EQU H'0001' B4D32 EQU H'0002' B4D33 EQU H'0003' B4D34 EQU H'0004' B4D35 EQU H'0005' B4D36 EQU H'0006' B4D37 EQU H'0007' ;----- B4D4 Bits ----------------------------------------------------- B4D40 EQU H'0000' B4D41 EQU H'0001' B4D42 EQU H'0002' B4D43 EQU H'0003' B4D44 EQU H'0004' B4D45 EQU H'0005' B4D46 EQU H'0006' B4D47 EQU H'0007' ;----- B4D5 Bits ----------------------------------------------------- B4D50 EQU H'0000' B4D51 EQU H'0001' B4D52 EQU H'0002' B4D53 EQU H'0003' B4D54 EQU H'0004' B4D55 EQU H'0005' B4D56 EQU H'0006' B4D57 EQU H'0007' ;----- B4D6 Bits ----------------------------------------------------- B4D60 EQU H'0000' B4D61 EQU H'0001' B4D62 EQU H'0002' B4D63 EQU H'0003' B4D64 EQU H'0004' B4D65 EQU H'0005' B4D66 EQU H'0006' B4D67 EQU H'0007' ;----- B4D7 Bits ----------------------------------------------------- B4D70 EQU H'0000' B4D71 EQU H'0001' B4D72 EQU H'0002' B4D73 EQU H'0003' B4D74 EQU H'0004' B4D75 EQU H'0005' B4D76 EQU H'0006' B46D77 EQU H'0007' B4D77 EQU H'0007' ;----- CANSTAT_RO5 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO5 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- B5CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' RTREN EQU H'0002' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' RXRTRRO_B5CON EQU H'0005' ;----- B5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- B5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- B5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- B5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- B5DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_B5DLC EQU H'0004' RB1_B5DLC EQU H'0005' ;----- B5D0 Bits ----------------------------------------------------- B5D00 EQU H'0000' B5D01 EQU H'0001' B5D02 EQU H'0002' B5D03 EQU H'0003' B5D04 EQU H'0004' B5D05 EQU H'0005' B5D06 EQU H'0006' B57D07 EQU H'0007' B5D07 EQU H'0007' ;----- B5D1 Bits ----------------------------------------------------- B5D10 EQU H'0000' B5D11 EQU H'0001' B5D12 EQU H'0002' B5D13 EQU H'0003' B5D14 EQU H'0004' B5D15 EQU H'0005' B5D16 EQU H'0006' B5D17 EQU H'0007' ;----- B5D2 Bits ----------------------------------------------------- B5D20 EQU H'0000' B5D21 EQU H'0001' B5D22 EQU H'0002' B57D23 EQU H'0003' B5D24 EQU H'0004' B5D25 EQU H'0005' B5D26 EQU H'0006' B5D27 EQU H'0007' B5D23 EQU H'0003' ;----- B5D3 Bits ----------------------------------------------------- B5D30 EQU H'0000' B5D31 EQU H'0001' B5D32 EQU H'0002' B5D33 EQU H'0003' B5D34 EQU H'0004' B5D35 EQU H'0005' B5D36 EQU H'0006' B5D37 EQU H'0007' ;----- B5D4 Bits ----------------------------------------------------- B5D40 EQU H'0000' B5D41 EQU H'0001' B5D42 EQU H'0002' B5D43 EQU H'0003' B5D44 EQU H'0004' B5D45 EQU H'0005' B5D46 EQU H'0006' B5D47 EQU H'0007' ;----- B5D5 Bits ----------------------------------------------------- B5D50 EQU H'0000' B5D51 EQU H'0001' B5D52 EQU H'0002' B5D53 EQU H'0003' B5D54 EQU H'0004' B5D55 EQU H'0005' B5D56 EQU H'0006' B5D57 EQU H'0007' ;----- B5D6 Bits ----------------------------------------------------- B5D60 EQU H'0000' B5D61 EQU H'0001' B5D62 EQU H'0002' B5D63 EQU H'0003' B5D64 EQU H'0004' B5D65 EQU H'0005' B5D66 EQU H'0006' B5D67 EQU H'0007' ;----- B5D7 Bits ----------------------------------------------------- B5D70 EQU H'0000' B5D71 EQU H'0001' B5D72 EQU H'0002' B5D73 EQU H'0003' B5D74 EQU H'0004' B5D75 EQU H'0005' B5D76 EQU H'0006' B5D77 EQU H'0007' ;----- CANSTAT_RO4 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO4 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXF0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF3SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF3SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF3EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF3EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF4SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF4SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF4EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF4EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXF5SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXF5SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' EXIDEN EQU H'0003' ;----- RXF5EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXF5EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXM1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXM1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDEN EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXM1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXM1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFBXB2CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB2SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB2SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB2EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB2EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB2DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB2D0 Bits ----------------------------------------------------- TXB2D00 EQU H'0000' TXB2D01 EQU H'0001' TXB2D02 EQU H'0002' TXB2D03 EQU H'0003' TXB2D04 EQU H'0004' TXB2D05 EQU H'0005' TXB2D06 EQU H'0006' TXB2D07 EQU H'0007' ;----- TXB2D1 Bits ----------------------------------------------------- TXB2D10 EQU H'0000' TXB2D11 EQU H'0001' TXB2D12 EQU H'0002' TXB2D13 EQU H'0003' TXB2D14 EQU H'0004' TXB2D15 EQU H'0005' TXB2D16 EQU H'0006' TXB2D17 EQU H'0007' ;----- TXB2D2 Bits ----------------------------------------------------- TXB2D20 EQU H'0000' TXB2D21 EQU H'0001' TXB2D22 EQU H'0002' TXB2D23 EQU H'0003' TXB2D24 EQU H'0004' TXB2D25 EQU H'0005' TXB2D26 EQU H'0006' TXB2D27 EQU H'0007' ;----- TXB2D3 Bits ----------------------------------------------------- TXB2D30 EQU H'0000' TXB2D31 EQU H'0001' TXB2D32 EQU H'0002' TXB2D33 EQU H'0003' TXB2D34 EQU H'0004' TXB2D35 EQU H'0005' TXB2D36 EQU H'0006' TXB2D37 EQU H'0007' ;----- TXB2D4 Bits ----------------------------------------------------- TXB2D40 EQU H'0000' TXB2D41 EQU H'0001' TXB2D42 EQU H'0002' TXB2D43 EQU H'0003' TXB2D44 EQU H'0004' TXB2D45 EQU H'0005' TXB2D46 EQU H'0006' TXB2D47 EQU H'0007' ;----- TXB2D5 Bits ----------------------------------------------------- TXB2D50 EQU H'0000' TXB2D51 EQU H'0001' TXB2D52 EQU H'0002' TXB2D53 EQU H'0003' TXB2D54 EQU H'0004' TXB2D55 EQU H'0005' TXB2D56 EQU H'0006' TXB2D57 EQU H'0007' ;----- TXB2D6 Bits ----------------------------------------------------- TXB2D60 EQU H'0000' TXB2D61 EQU H'0001' TXB2D62 EQU H'0002' TXB2D63 EQU H'0003' TXB2D64 EQU H'0004' TXB2D65 EQU H'0005' TXB2D66 EQU H'0006' TXB2D67 EQU H'0007' ;----- TXB2D7 Bits ----------------------------------------------------- TXB2D70 EQU H'0000' TXB2D71 EQU H'0001' TXB2D72 EQU H'0002' TXB2D73 EQU H'0003' TXB2D74 EQU H'0004' TXB2D75 EQU H'0005' TXB2D76 EQU H'0006' TXB2D77 EQU H'0007' ;----- CANSTAT_RO3 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO3 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB1CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIFTXB1CON EQU H'0007' TXBIF EQU H'0007' ;----- TXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB1D0 Bits ----------------------------------------------------- TXB1D00 EQU H'0000' TXB1D01 EQU H'0001' TXB1D02 EQU H'0002' TXB1D03 EQU H'0003' TXB1D04 EQU H'0004' TXB1D05 EQU H'0005' TXB1D06 EQU H'0006' TXB1D07 EQU H'0007' ;----- TXB1D1 Bits ----------------------------------------------------- TXB1D10 EQU H'0000' TXB1D11 EQU H'0001' TXB1D12 EQU H'0002' TXB1D13 EQU H'0003' TXB1D14 EQU H'0004' TXB1D15 EQU H'0005' TXB1D16 EQU H'0006' TXB1D17 EQU H'0007' ;----- TXB1D2 Bits ----------------------------------------------------- TXB1D20 EQU H'0000' TXB1D21 EQU H'0001' TXB1D22 EQU H'0002' TXB1D23 EQU H'0003' TXB1D24 EQU H'0004' TXB1D25 EQU H'0005' TXB1D26 EQU H'0006' TXB1D27 EQU H'0007' ;----- TXB1D3 Bits ----------------------------------------------------- TXB1D30 EQU H'0000' TXB1D31 EQU H'0001' TXB1D32 EQU H'0002' TXB1D33 EQU H'0003' TXB1D34 EQU H'0004' TXB1D35 EQU H'0005' TXB1D36 EQU H'0006' TXB1D37 EQU H'0007' ;----- TXB1D4 Bits ----------------------------------------------------- TXB1D40 EQU H'0000' TXB1D41 EQU H'0001' TXB1D42 EQU H'0002' TXB1D43 EQU H'0003' TXB1D44 EQU H'0004' TXB1D45 EQU H'0005' TXB1D46 EQU H'0006' TXB1D47 EQU H'0007' ;----- TXB1D5 Bits ----------------------------------------------------- TXB1D50 EQU H'0000' TXB1D51 EQU H'0001' TXB1D52 EQU H'0002' TXB1D53 EQU H'0003' TXB1D54 EQU H'0004' TXB1D55 EQU H'0005' TXB1D56 EQU H'0006' TXB1D57 EQU H'0007' ;----- TXB1D6 Bits ----------------------------------------------------- TXB1D60 EQU H'0000' TXB1D61 EQU H'0001' TXB1D62 EQU H'0002' TXB1D63 EQU H'0003' TXB1D64 EQU H'0004' TXB1D65 EQU H'0005' TXB1D66 EQU H'0006' TXB1D67 EQU H'0007' ;----- TXB1D7 Bits ----------------------------------------------------- TXB1D70 EQU H'0000' TXB1D71 EQU H'0001' TXB1D72 EQU H'0002' TXB1D73 EQU H'0003' TXB1D74 EQU H'0004' TXB1D75 EQU H'0005' TXB1D76 EQU H'0006' TXB1D77 EQU H'0007' ;----- CANSTAT_RO2 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO2 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- TXB0CON Bits ----------------------------------------------------- TXPRI0 EQU H'0000' TXPRI1 EQU H'0001' TXREQ EQU H'0003' TXERR EQU H'0004' TXLARB EQU H'0005' TXABT EQU H'0006' TXBIF EQU H'0007' ;----- TXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- TXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXIDE EQU H'0003' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- TXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- TXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- TXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' TXRTR EQU H'0006' ;----- TXB0D0 Bits ----------------------------------------------------- TXB0D00 EQU H'0000' TXB0D01 EQU H'0001' TXB0D02 EQU H'0002' TXB0D03 EQU H'0003' TXB0D04 EQU H'0004' TXB0D05 EQU H'0005' TXB0D06 EQU H'0006' TXB0D07 EQU H'0007' ;----- TXB0D1 Bits ----------------------------------------------------- TXB0D10 EQU H'0000' TXB0D11 EQU H'0001' TXB0D12 EQU H'0002' TXB0D13 EQU H'0003' TXB0D14 EQU H'0004' TXB0D15 EQU H'0005' TXB0D16 EQU H'0006' TXB0D17 EQU H'0007' ;----- TXB0D2 Bits ----------------------------------------------------- TXB0D20 EQU H'0000' TXB0D21 EQU H'0001' TXB0D22 EQU H'0002' TXB0D23 EQU H'0003' TXB0D24 EQU H'0004' TXB0D25 EQU H'0005' TXB0D26 EQU H'0006' TXB0D27 EQU H'0007' ;----- TXB0D3 Bits ----------------------------------------------------- TXB0D30 EQU H'0000' TXB0D31 EQU H'0001' TXB0D32 EQU H'0002' TXB0D33 EQU H'0003' TXB0D34 EQU H'0004' TXB0D35 EQU H'0005' TXB0D36 EQU H'0006' TXB0D37 EQU H'0007' ;----- TXB0D4 Bits ----------------------------------------------------- TXB0D40 EQU H'0000' TXB0D41 EQU H'0001' TXB0D42 EQU H'0002' TXB0D43 EQU H'0003' TXB0D44 EQU H'0004' TXB0D45 EQU H'0005' TXB0D46 EQU H'0006' TXB0D47 EQU H'0007' ;----- TXB0D5 Bits ----------------------------------------------------- TXB0D50 EQU H'0000' TXB0D51 EQU H'0001' TXB0D52 EQU H'0002' TXB0D53 EQU H'0003' TXB0D54 EQU H'0004' TXB0D55 EQU H'0005' TXB0D56 EQU H'0006' TXB0D57 EQU H'0007' ;----- TXB0D6 Bits ----------------------------------------------------- TXB0D60 EQU H'0000' TXB0D61 EQU H'0001' TXB0D62 EQU H'0002' TXB0D63 EQU H'0003' TXB0D64 EQU H'0004' TXB0D65 EQU H'0005' TXB0D66 EQU H'0006' TXB0D67 EQU H'0007' ;----- TXB0D7 Bits ----------------------------------------------------- TXB0D70 EQU H'0000' TXB0D71 EQU H'0001' TXB0D72 EQU H'0002' TXB0D73 EQU H'0003' TXB0D74 EQU H'0004' TXB0D75 EQU H'0005' TXB0D76 EQU H'0006' TXB0D77 EQU H'0007' ;----- CANSTAT_RO1 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO1 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB1CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' RXRTRRO_RXB1CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' ;----- RXB1SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB1SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB1EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB1EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB1DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB1DLC EQU H'0004' RB1_RXB1DLC EQU H'0005' ;----- RXB1D0 Bits ----------------------------------------------------- RXB1D00 EQU H'0000' RXB1D01 EQU H'0001' RXB1D02 EQU H'0002' RXB1D03 EQU H'0003' RXB1D04 EQU H'0004' RXB1D05 EQU H'0005' RXB1D06 EQU H'0006' RXB1D07 EQU H'0007' ;----- RXB1D1 Bits ----------------------------------------------------- RXB1D10 EQU H'0000' RXB1D11 EQU H'0001' RXB1D12 EQU H'0002' RXB1D13 EQU H'0003' RXB1D14 EQU H'0004' RXB1D15 EQU H'0005' RXB1D16 EQU H'0006' RXB1D17 EQU H'0007' ;----- RXB1D2 Bits ----------------------------------------------------- RXB1D20 EQU H'0000' RXB1D21 EQU H'0001' RXB1D22 EQU H'0002' RXB1D23 EQU H'0003' RXB1D24 EQU H'0004' RXB1D25 EQU H'0005' RXB1D26 EQU H'0006' RXB1D27 EQU H'0007' ;----- RXB1D3 Bits ----------------------------------------------------- RXB1D30 EQU H'0000' RXB1D31 EQU H'0001' RXB1D32 EQU H'0002' RXB1D33 EQU H'0003' RXB1D34 EQU H'0004' RXB1D35 EQU H'0005' RXB1D36 EQU H'0006' RXB1D37 EQU H'0007' ;----- RXB1D4 Bits ----------------------------------------------------- RXB1D40 EQU H'0000' RXB1D41 EQU H'0001' RXB1D42 EQU H'0002' RXB1D43 EQU H'0003' RXB1D44 EQU H'0004' RXB1D45 EQU H'0005' RXB1D46 EQU H'0006' RXB1D47 EQU H'0007' ;----- RXB1D5 Bits ----------------------------------------------------- RXB1D50 EQU H'0000' RXB1D51 EQU H'0001' RXB1D52 EQU H'0002' RXB1D53 EQU H'0003' RXB1D54 EQU H'0004' RXB1D55 EQU H'0005' RXB1D56 EQU H'0006' RXB1D57 EQU H'0007' ;----- RXB1D6 Bits ----------------------------------------------------- RXB1D60 EQU H'0000' RXB1D61 EQU H'0001' RXB1D62 EQU H'0002' RXB1D63 EQU H'0003' RXB1D64 EQU H'0004' RXB1D65 EQU H'0005' RXB1D66 EQU H'0006' RXB1D67 EQU H'0007' ;----- RXB1D7 Bits ----------------------------------------------------- RXB1D70 EQU H'0000' RXB1D71 EQU H'0001' RXB1D72 EQU H'0002' RXB1D73 EQU H'0003' RXB1D74 EQU H'0004' RXB1D75 EQU H'0005' RXB1D76 EQU H'0006' RXB1D77 EQU H'0007' ;----- CANSTAT_RO0 Bits ----------------------------------------------------- ICODE0 EQU H'0000' ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' ICODE4 EQU H'0004' OPMODE EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- CANCON_RO0 Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' ;----- RXB0CON Bits ----------------------------------------------------- FILHIT0 EQU H'0000' JTOFF EQU H'0001' RXB0DBEN EQU H'0002' RXRTRRO_RXB0CON EQU H'0003' RXM0 EQU H'0005' RXM1 EQU H'0006' RXFUL EQU H'0007' FILHIT1 EQU H'0001' FILHIT2 EQU H'0002' FILHIT3 EQU H'0003' FILHIT4 EQU H'0004' RTRRO EQU H'0005' RXBODBEN EQU H'0002' ;----- RXB0SIDH Bits ----------------------------------------------------- SID3 EQU H'0000' SID4 EQU H'0001' SID5 EQU H'0002' SID6 EQU H'0003' SID7 EQU H'0004' SID8 EQU H'0005' SID9 EQU H'0006' SID10 EQU H'0007' ;----- RXB0SIDL Bits ----------------------------------------------------- EID16 EQU H'0000' EID17 EQU H'0001' EXID EQU H'0003' SRR EQU H'0004' SID0 EQU H'0005' SID1 EQU H'0006' SID2 EQU H'0007' ;----- RXB0EIDH Bits ----------------------------------------------------- EID8 EQU H'0000' EID9 EQU H'0001' EID10 EQU H'0002' EID11 EQU H'0003' EID12 EQU H'0004' EID13 EQU H'0005' EID14 EQU H'0006' EID15 EQU H'0007' ;----- RXB0EIDL Bits ----------------------------------------------------- EID0 EQU H'0000' EID1 EQU H'0001' EID2 EQU H'0002' EID3 EQU H'0003' EID4 EQU H'0004' EID5 EQU H'0005' EID6 EQU H'0006' EID7 EQU H'0007' ;----- RXB0DLC Bits ----------------------------------------------------- DLC0 EQU H'0000' DLC1 EQU H'0001' DLC2 EQU H'0002' DLC3 EQU H'0003' RESRB0 EQU H'0004' RESRB1 EQU H'0005' RXRTR EQU H'0006' RB0_RXB0DLC EQU H'0004' RB1_RXB0DLC EQU H'0005' ;----- RXB0D0 Bits ----------------------------------------------------- RXB0D00 EQU H'0000' RXB0D01 EQU H'0001' RXB0D02 EQU H'0002' RXB0D03 EQU H'0003' RXB0D04 EQU H'0004' RXB0D05 EQU H'0005' RXB0D06 EQU H'0006' RXB0D07 EQU H'0007' ;----- RXB0D1 Bits ----------------------------------------------------- RXB0D10 EQU H'0000' RXB0D11 EQU H'0001' RXB0D12 EQU H'0002' RXB0D13 EQU H'0003' RXB0D14 EQU H'0004' RXB0D15 EQU H'0005' RXB0D16 EQU H'0006' RXB0D17 EQU H'0007' ;----- RXB0D2 Bits ----------------------------------------------------- RXB0D20 EQU H'0000' RXB0D21 EQU H'0001' RXB0D22 EQU H'0002' RXB0D23 EQU H'0003' RXB0D24 EQU H'0004' RXB0D25 EQU H'0005' RXB0D26 EQU H'0006' RXB0D27 EQU H'0007' ;----- RXB0D3 Bits ----------------------------------------------------- RXB0D30 EQU H'0000' RXB0D31 EQU H'0001' RXB0D32 EQU H'0002' RXB0D33 EQU H'0003' RXB0D34 EQU H'0004' RXB0D35 EQU H'0005' RXB0D36 EQU H'0006' RXB0D37 EQU H'0007' ;----- RXB0D4 Bits ----------------------------------------------------- RXB0D40 EQU H'0000' RXB0D41 EQU H'0001' RXB0D42 EQU H'0002' RXB0D43 EQU H'0003' RXB0D44 EQU H'0004' RXB0D45 EQU H'0005' RXB0D46 EQU H'0006' RXB0D47 EQU H'0007' ;----- RXB0D5 Bits ----------------------------------------------------- RXB0D50 EQU H'0000' RXB0D51 EQU H'0001' RXB0D52 EQU H'0002' RXB0D53 EQU H'0003' RXB0D54 EQU H'0004' RXB0D55 EQU H'0005' RXB0D56 EQU H'0006' RXB0D57 EQU H'0007' ;----- RXB0D6 Bits ----------------------------------------------------- RXB0D60 EQU H'0000' RXB0D61 EQU H'0001' RXB0D62 EQU H'0002' RXB0D63 EQU H'0003' RXB0D64 EQU H'0004' RXB0D65 EQU H'0005' RXB0D66 EQU H'0006' RXB0D67 EQU H'0007' ;----- RXB0D7 Bits ----------------------------------------------------- RXB0D70 EQU H'0000' RXB0D71 EQU H'0001' RXB0D72 EQU H'0002' RXB0D73 EQU H'0003' RXB0D74 EQU H'0004' RXB0D75 EQU H'0005' RXB0D76 EQU H'0006' RXB0D77 EQU H'0007' ;----- CANSTAT Bits ----------------------------------------------------- ICODE1 EQU H'0001' ICODE2 EQU H'0002' ICODE3 EQU H'0003' OPMODE0 EQU H'0005' OPMODE1 EQU H'0006' OPMODE2 EQU H'0007' EICODE0 EQU H'0000' EICODE1 EQU H'0001' EICODE2 EQU H'0002' EICODE3 EQU H'0003' EICODE4 EQU H'0004' ;----- CANCON Bits ----------------------------------------------------- WIN0 EQU H'0001' WIN1 EQU H'0002' WIN2 EQU H'0003' ABAT EQU H'0004' REQOP0 EQU H'0005' REQOP1 EQU H'0006' REQOP2 EQU H'0007' FP0 EQU H'0000' FP1 EQU H'0001' FP2 EQU H'0002' FP3 EQU H'0003' ;----- BRGCON1 Bits ----------------------------------------------------- BRP0 EQU H'0000' BRP1 EQU H'0001' BRP2 EQU H'0002' BRP3 EQU H'0003' BRP4 EQU H'0004' BRP5 EQU H'0005' SJW0 EQU H'0006' SJW1 EQU H'0007' ;----- BRGCON2 Bits ----------------------------------------------------- PRSEG0 EQU H'0000' PRSEG1 EQU H'0001' PRSEG2 EQU H'0002' SEG1PH0 EQU H'0003' SEG1PH1 EQU H'0004' SEG1PH2 EQU H'0005' SAM EQU H'0006' SEG2PHTS EQU H'0007' SEG2PHT EQU H'0007' ;----- BRGCON3 Bits ----------------------------------------------------- SEG2PH0 EQU H'0000' SEG2PH1 EQU H'0001' SEG2PH2 EQU H'0002' WAKFIL EQU H'0006' WAKDIS EQU H'0007' ;----- CIOCON Bits ----------------------------------------------------- CANCAP EQU H'0004' ENDRHI EQU H'0005' ;----- COMSTAT Bits ----------------------------------------------------- EWARN EQU H'0000' RXWARN EQU H'0001' TXWARN EQU H'0002' RXBP EQU H'0003' TXBP EQU H'0004' TXBO EQU H'0005' RXB1OVFL EQU H'0006' RXB0OVFL EQU H'0007' RXBnOVFL EQU H'0006' FIFOEMPTY EQU H'0007' ;----- RXERRCNT Bits ----------------------------------------------------- REC0 EQU H'0000' REC1 EQU H'0001' REC2 EQU H'0002' REC3 EQU H'0003' REC4 EQU H'0004' REC5 EQU H'0005' REC6 EQU H'0006' REC7 EQU H'0007' ;----- TXERRCNT Bits ----------------------------------------------------- TEC0 EQU H'0000' TEC1 EQU H'0001' TEC2 EQU H'0002' TEC3 EQU H'0003' TEC4 EQU H'0004' TEC5 EQU H'0005' TEC6 EQU H'0006' TEC7 EQU H'0007' ;----- ECANCON Bits ----------------------------------------------------- EWIN0 EQU H'0000' EWIN1 EQU H'0001' EWIN2 EQU H'0002' EWIN3 EQU H'0003' EWIN4 EQU H'0004' FIFOWM EQU H'0005' MDSEL0 EQU H'0006' MDSEL1 EQU H'0007' F EQU H'0005' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' CVREF EQU H'0000' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' SS EQU H'0005' NOT_SS EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0_PORTB EQU H'0000' RB1_PORTB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CANRX EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN10 EQU H'0000' FLT0 EQU H'0000' AN8 EQU H'0001' CANTX EQU H'0002' AN9 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0_DDRB EQU H'0000' RB1_DDRB EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSCR EQU H'0007' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXBIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' TXIP EQU H'0004' ;----- PIE2 Bits ----------------------------------------------------- TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- RXB0IE EQU H'0000' RXB1IE EQU H'0001' TXB0IE EQU H'0002' TXB1IE EQU H'0003' TXB2IE EQU H'0004' ERRIE EQU H'0005' WAKIE EQU H'0006' IRXIE EQU H'0007' FIFOWMIE EQU H'0000' RXBnIE EQU H'0001' TXBnIE EQU H'0004' FIFOMWIE EQU H'0000' ;----- PIR3 Bits ----------------------------------------------------- RXB0IF EQU H'0000' RXB1IF EQU H'0001' TXB0IF EQU H'0002' TXB1IF EQU H'0003' TXB2IF EQU H'0004' ERRIF EQU H'0005' WAKIF EQU H'0006' IRXIF EQU H'0007' FIFOWMIF EQU H'0000' RXBnIF EQU H'0001' TXBnIF EQU H'0004' ;----- IPR3 Bits ----------------------------------------------------- RXB0IP EQU H'0000' RXB1IP EQU H'0001' TXB0IP EQU H'0002' TXB1IP EQU H'0003' TXB2IP EQU H'0004' ERRIP EQU H'0005' WAKIP EQU H'0006' IRXIP EQU H'0007' FIFOWMIP EQU H'0000' RXBnIP EQU H'0001' TXBnIP EQU H'0004' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3NSYNC EQU H'0002' T3ECCP1 EQU H'0006' NOT_T3SYNC EQU H'0002' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0D6C'-H'0D6F' __BADRAM H'0D7C'-H'0D7F' __BADRAM H'0D8C'-H'0D8F' __BADRAM H'0D94'-H'0DD3' __BADRAM H'0DD6'-H'0DD7' __BADRAM H'0DD9'-H'0DDF' __BADRAM H'0DE8'-H'0DEF' __BADRAM H'0DF4'-H'0DF7' __BADRAM H'0DF9' __BADRAM H'0DFB' __BADRAM H'0DFD'-H'0E1F' __BADRAM H'0E80'-H'0EFF' __BADRAM H'0F78'-H'0F7F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FB4'-H'0FB7' __BADRAM H'0FB9'-H'0FBC' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = IRCIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = IRCIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = SBORENCTRL Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = BOACTIVE Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = BOHW Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB Pins Configured for A/D: ; PBADEN = OFF PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset ; PBADEN = ON PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ; ; BackGround Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Boot Block Size Select Bits: ; BBSIZ = 1024 1K words (2K bytes) Boot Block ; BBSIZ = 2048 2K words (4K bytes) Boot Block ; BBSIZ = 4096 4K words (8K bytes) Boot Block ; ; Low Voltage Programming: ; LVP = OFF Disabled ; LVP = ON Enabled ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-003FFFh) code-protected ; CP0 = OFF Block 0 (000800-003FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Boot Block Code Protection: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800-003FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Boot Block Write Protection: ; WRTB = ON Boot Block (000000-0007FFh) write-protected ; WRTB = OFF Boot Block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection: ; EBTRB = ON Boot Block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_IRCIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_IRCIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_SBORENCTRL_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_BOACTIVE_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_BOHW_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RE3 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4> and PORTB<1:0> Configured as Digital I/O Pins on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4> and PORTB<1:0> Configured as Analog Pins on Reset ;----- CONFIG4L Options -------------------------------------------------- _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _BBSIZ_1024_4L EQU H'CF' ; 1K words (2K bytes) Boot Block _BBSIZ_2048_4L EQU H'DF' ; 2K words (4K bytes) Boot Block _BBSIZ_4096_4L EQU H'EF' ; 4K words (8K bytes) Boot Block _LVP_OFF_4L EQU H'FB' ; Disabled _LVP_ON_4L EQU H'FF' ; Enabled _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f916.inc0000644000175000017500000006276011156521301013157 00000000000000 LIST ; P16F916.INC Standard Header File, Version 1.04 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F916 microcontroller. ; These names are taken to match the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F916 ; 2. LIST directive in the source file ; LIST P=PIC16F916 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 06/11/04 Initial Release ;1.01 06/18/04 Corrected typo in 'bad ram' section ;1.02 08/16/04 Added EECON2 ;1.03 05/20/05 Removed EECON2 from badram ;1.04 10/05/05 Correct names of bits in ANSEL, Add EEADRH and EEADRL bit ;1.05 10/30/06 Added Alias of go_done, go ; definitions ;1.06 02/26/07 Added Alias of EEADR and EEDATA ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F916 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' ADRESH EQU H'001E' ADCON0 EQU H'001F' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' ANSEL EQU H'0091' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' WPUB EQU H'0095' WPU EQU H'0095' IOCB EQU H'0096' IOC EQU H'0096' CMCON1 EQU H'0097' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON0 EQU H'009C' VRCON EQU H'009D' ADRESL EQU H'009E' ADCON1 EQU H'009F' WDTCON EQU H'0105' LCDCON EQU H'0107' LCDPS EQU H'0108' LVDCON EQU H'0109' EEDATL EQU H'010C' EEDATA EQU H'010C' EEADRL EQU H'010D' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' LCDDATA0 EQU H'0110' LCDDATA1 EQU H'0111' LCDDATA3 EQU H'0113' LCDDATA4 EQU H'0114' LCDDATA6 EQU H'0116' LCDDATA7 EQU H'0117' LCDDATA9 EQU H'0119' LCDDATA10 EQU H'011A' LCDSE0 EQU H'011C' LCDSE1 EQU H'011D' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- EEIF EQU H'0007' ADIF EQU H'0006' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' C2IF EQU H'0006' C1IF EQU H'0005' LCDIF EQU H'0004' LVDIF EQU H'0002' ;----- T1CON Bits --------------------------------------------------------- T1GINV EQU H'0007' T1GE EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only T1SYNC EQU H'0002' TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- ADCON0 Bits -------------------------------------------------------- ADFM EQU H'0007' VCFG1 EQU H'0006' VCFG0 EQU H'0005' CHS2 EQU H'0004' CHS1 EQU H'0003' CHS0 EQU H'0002' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' GO EQU H'0001' ADON EQU H'0000' ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- EEIE EQU H'0007' ADIE EQU H'0006' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' C2IE EQU H'0006' C1IE EQU H'0005' LCDIE EQU H'0004' LVDIE EQU H'0002' ;----- PCON Bits ---------------------------------------------------------- SBOREN EQU H'0004' NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' HTS EQU H'0002' LTS EQU H'0001' SCS EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- ANSEL Bits --------------------------------------------------------- ANS4 EQU H'0004' AN4 EQU H'0004' ; Backward compatibility only ANS3 EQU H'0003' AN3 EQU H'0003' ; Backward compatibility only ANS2 EQU H'0002' AN2 EQU H'0002' ; Backward compatibility only ANS1 EQU H'0001' AN1 EQU H'0001' ; Backward compatibility only ANS0 EQU H'0000' AN0 EQU H'0000' ; Backward compatibility only ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- WPUB Bits ------------------------------------------------------- WPUB7 EQU H'0007' WPUB6 EQU H'0006' WPUB5 EQU H'0005' WPUB4 EQU H'0004' WPUB3 EQU H'0003' WPUB2 EQU H'0002' WPUB1 EQU H'0001' WPUB0 EQU H'0000' ;----- WPU Bits ------------------------------------------------------- WPU7 EQU H'0007' WPU6 EQU H'0006' WPU5 EQU H'0005' WPU4 EQU H'0004' WPU3 EQU H'0003' WPU2 EQU H'0002' WPU1 EQU H'0001' WPU0 EQU H'0000' ;----- IOCB Bits ------------------------------------------------------- IOCB7 EQU H'0007' IOCB6 EQU H'0006' IOCB5 EQU H'0005' IOCB4 EQU H'0004' ;----- IOC Bits ------------------------------------------------------- IOC7 EQU H'0007' IOC6 EQU H'0006' IOC5 EQU H'0005' IOC4 EQU H'0004' ;----- CMCON1 Bits -------------------------------------------------------- T1GSS EQU H'0001' C2SYNC EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- CMCON0 Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- VRCON Bits -------------------------------------------------------- VREN EQU H'0007' VRR EQU H'0005' VR3 EQU H'0003' VR2 EQU H'0002' VR1 EQU H'0001' VR0 EQU H'0000' ;----- ADCON1 Bits -------------------------------------------------------- ADCS2 EQU H'0006' ADCS1 EQU H'0005' ADCS0 EQU H'0004' ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- LCDCON Bits -------------------------------------------------------- LCDEN EQU H'0007' SLPEN EQU H'0006' WERR EQU H'0005' VLCDEN EQU H'0004' CS1 EQU H'0003' CS0 EQU H'0002' LMUX1 EQU H'0001' LMUX0 EQU H'0000' ;----- LCDPS Bits --------------------------------------------------------- WFT EQU H'0007' BIASMD EQU H'0006' LCDA EQU H'0005' WA EQU H'0004' LP3 EQU H'0003' LP2 EQU H'0002' LP1 EQU H'0001' LP0 EQU H'0000' ;----- LVDCON Bits -------------------------------------------------------- IRVST EQU H'0005' LVDEN EQU H'0004' LVDL2 EQU H'0002' LVDL1 EQU H'0001' LVDL0 EQU H'0000' ;----- LCDDATA0 Bits ------------------------------------------------------- SEG7COM0 EQU H'0007' SEG6COM0 EQU H'0006' SEG5COM0 EQU H'0005' SEG4COM0 EQU H'0004' SEG3COM0 EQU H'0003' SEG2COM0 EQU H'0002' SEG1COM0 EQU H'0001' SEG0COM0 EQU H'0000' S7C0 EQU H'0007' S6C0 EQU H'0006' S5C0 EQU H'0005' S4C0 EQU H'0004' S3C0 EQU H'0003' S2C0 EQU H'0002' S1C0 EQU H'0001' S0C0 EQU H'0000' ;----- LCDDATA1 Bits ------------------------------------------------------- SEG15COM0 EQU H'0007' SEG14COM0 EQU H'0006' SEG13COM0 EQU H'0005' SEG12COM0 EQU H'0004' SEG11COM0 EQU H'0003' SEG10COM0 EQU H'0002' SEG9COM0 EQU H'0001' SEG8COM0 EQU H'0000' S15C0 EQU H'0007' S14C0 EQU H'0006' S13C0 EQU H'0005' S12C0 EQU H'0004' S11C0 EQU H'0003' S10C0 EQU H'0002' S9C0 EQU H'0001' S8C0 EQU H'0000' ;----- LCDDATA3 Bits ------------------------------------------------------- SEG7COM1 EQU H'0007' SEG6COM1 EQU H'0006' SEG5COM1 EQU H'0005' SEG4COM1 EQU H'0004' SEG3COM1 EQU H'0003' SEG2COM1 EQU H'0002' SEG1COM1 EQU H'0001' SEG0COM1 EQU H'0000' S7C1 EQU H'0007' S6C1 EQU H'0006' S5C1 EQU H'0005' S4C1 EQU H'0004' S3C1 EQU H'0003' S2C1 EQU H'0002' S1C1 EQU H'0001' S0C1 EQU H'0000' ;----- LCDDATA4 Bits ------------------------------------------------------- SEG15COM1 EQU H'0007' SEG14COM1 EQU H'0006' SEG13COM1 EQU H'0005' SEG12COM1 EQU H'0004' SEG11COM1 EQU H'0003' SEG10COM1 EQU H'0002' SEG9COM1 EQU H'0001' SEG8COM1 EQU H'0000' S15C1 EQU H'0007' S14C1 EQU H'0006' S13C1 EQU H'0005' S12C1 EQU H'0004' S11C1 EQU H'0003' S10C1 EQU H'0002' S9C1 EQU H'0001' S8C1 EQU H'0000' ;----- LCDDATA6 Bits ------------------------------------------------------- SEG7COM2 EQU H'0007' SEG6COM2 EQU H'0006' SEG5COM2 EQU H'0005' SEG4COM2 EQU H'0004' SEG3COM2 EQU H'0003' SEG2COM2 EQU H'0002' SEG1COM2 EQU H'0001' SEG0COM2 EQU H'0000' S7C2 EQU H'0007' S6C2 EQU H'0006' S5C2 EQU H'0005' S4C2 EQU H'0004' S3C2 EQU H'0003' S2C2 EQU H'0002' S1C2 EQU H'0001' S0C2 EQU H'0000' ;----- LCDDATA7 Bits ------------------------------------------------------- SEG15COM2 EQU H'0007' SEG14COM2 EQU H'0006' SEG13COM2 EQU H'0005' SEG12COM2 EQU H'0004' SEG11COM2 EQU H'0003' SEG10COM2 EQU H'0002' SEG9COM2 EQU H'0001' SEG8COM2 EQU H'0000' S15C2 EQU H'0007' S14C2 EQU H'0006' S13C2 EQU H'0005' S12C2 EQU H'0004' S11C2 EQU H'0003' S10C2 EQU H'0002' S9C2 EQU H'0001' S8C2 EQU H'0000' ;----- LCDDATA9 Bits ------------------------------------------------------- SEG7COM3 EQU H'0007' SEG6COM3 EQU H'0006' SEG5COM3 EQU H'0005' SEG4COM3 EQU H'0004' SEG3COM3 EQU H'0003' SEG2COM3 EQU H'0002' SEG1COM3 EQU H'0001' SEG0COM3 EQU H'0000' S7C3 EQU H'0007' S6C3 EQU H'0006' S5C3 EQU H'0005' S4C3 EQU H'0004' S3C3 EQU H'0003' S2C3 EQU H'0002' S1C3 EQU H'0001' S0C3 EQU H'0000' ;----- LCDDATA10 Bits ------------------------------------------------------- SEG15COM3 EQU H'0007' SEG14COM3 EQU H'0006' SEG13COM3 EQU H'0005' SEG12COM3 EQU H'0004' SEG11COM3 EQU H'0003' SEG10COM3 EQU H'0002' SEG9COM3 EQU H'0001' SEG8COM3 EQU H'0000' S15C3 EQU H'0007' S14C3 EQU H'0006' S13C3 EQU H'0005' S12C3 EQU H'0004' S11C3 EQU H'0003' S10C3 EQU H'0002' S9C3 EQU H'0001' S8C3 EQU H'0000' ;----- LCDSE0 Bits -------------------------------------------------------- SE7 EQU H'0007' SE6 EQU H'0006' SE5 EQU H'0005' SE4 EQU H'0004' SE3 EQU H'0003' SE2 EQU H'0002' SE1 EQU H'0001' SE0 EQU H'0000' SEGEN7 EQU H'0007' SEGEN6 EQU H'0006' SEGEN5 EQU H'0005' SEGEN4 EQU H'0004' SEGEN3 EQU H'0003' SEGEN2 EQU H'0002' SEGEN1 EQU H'0001' SEGEN0 EQU H'0000' ;----- LCDSE1 Bits -------------------------------------------------------- SE15 EQU H'0007' SE14 EQU H'0006' SE13 EQU H'0005' SE12 EQU H'0004' SE11 EQU H'0003' SE10 EQU H'0002' SE9 EQU H'0001' SE8 EQU H'0000' SEGEN15 EQU H'0007' SEGEN14 EQU H'0006' SEGEN13 EQU H'0005' SEGEN12 EQU H'0004' SEGEN11 EQU H'0003' SEGEN10 EQU H'0002' SEGEN9 EQU H'0001' SEGEN8 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' EEWR EQU H'0001' RD EQU H'0000' EERD EQU H'0000' ;----- EEADRH Bits -------------------------------------------------------- EEADRH4 EQU H'0004' EEADRH3 EQU H'0003' EEADRH2 EQU H'0002' EEADRH1 EQU H'0001' EEADRH0 EQU H'0000' ;----- EEADRL Bits -------------------------------------------------------- EEADRL7 EQU H'0007' EEADRL6 EQU H'0006' EEADRL5 EQU H'0005' EEADRL4 EQU H'0004' EEADRL3 EQU H'0003' EEADRL2 EQU H'0002' EEADRL1 EQU H'0001' EEADRL0 EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'08', H'1B'-H'1D' __BADRAM H'88', H'9A'-H'9B' __BADRAM H'112', H'115', H'118', H'11B',H'11E'-H'11F' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG EQU H'2007' ;Configuration Byte 1 Options _DEBUG_ON EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'37FF' _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3BFF' _BOD_ON EQU H'3FFF' _BOD_NSLEEP EQU H'3EFF' _BOD_SBODEN EQU H'3DFF' _BOD_OFF EQU H'3CFF' _CPD_ON EQU H'3F7F' _CPD_OFF EQU H'3FFF' _CP_ON EQU H'3FBF' _CP_OFF EQU H'3FFF' _MCLRE_ON EQU H'3FFF' _MCLRE_OFF EQU H'3FDF' _PWRTE_ON EQU H'3FEF' _PWRTE_OFF EQU H'3FFF' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FF7' _LP_OSC EQU H'3FF8' _XT_OSC EQU H'3FF9' _HS_OSC EQU H'3FFA' _EC_OSC EQU H'3FFB' _INTRC_OSC_NOCLKOUT EQU H'3FFC' _INTRC_OSC_CLKOUT EQU H'3FFD' _EXTRC_OSC_NOCLKOUT EQU H'3FFE' _EXTRC_OSC_CLKOUT EQU H'3FFF' _INTOSCIO EQU H'3FFC' _INTOSC EQU H'3FFD' _EXTRCIO EQU H'3FFE' _EXTRC EQU H'3FFF' LIST gputils-0.13.7/header/p16c65a.inc0000644000175000017500000002706711156313161013234 00000000000000 LIST ; P16C65A.INC Standard Header File, Version 1.01 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16C65A microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16C65A ; 2. LIST directive in the source file ; LIST P=PIC16C65A ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.01 11/28/95 Added NOT_BOR to match revised datasheet ;1.00 10/31/95 Initial Release ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16C65A MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PORTC EQU H'0007' PORTD EQU H'0008' PORTE EQU H'0009' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' CCPR2L EQU H'001B' CCPR2H EQU H'001C' CCP2CON EQU H'001D' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' TRISC EQU H'0087' TRISD EQU H'0088' TRISE EQU H'0089' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' T0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' T0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- PSPIF EQU H'0007' RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- CCP2IF EQU H'0000' ;----- T1CON Bits --------------------------------------------------------- T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- CCP2CON Bits ------------------------------------------------------- CCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2M3 EQU H'0003' CCP2M2 EQU H'0002' CCP2M1 EQU H'0001' CCP2M0 EQU H'0000' ;----- OPTION Bits -------------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- TRISE Bits --------------------------------------------------------- IBF EQU H'0007' OBF EQU H'0006' IBOV EQU H'0005' PSPMODE EQU H'0004' TRISE2 EQU H'0002' TRISE1 EQU H'0001' TRISE0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- PSPIE EQU H'0007' RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- CCP2IE EQU H'0000' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'FF' __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _CP_ALL EQU H'00CF' _CP_75 EQU H'15DF' _CP_50 EQU H'2AEF' _CP_OFF EQU H'3FFF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _LP_OSC EQU H'3FFC' _XT_OSC EQU H'3FFD' _HS_OSC EQU H'3FFE' _RC_OSC EQU H'3FFF' LIST gputils-0.13.7/header/p18f8310.inc0000644000175000017500000013507211156521301013232 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8310 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8310 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8310 ; 2. LIST directive in the source file ; LIST P=PIC18F8310 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8310 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' BAUDCON1 EQU H'0F7E' BAUDCTL1 EQU H'0F7E' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' CCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- RCSTA2 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ADDEN EQU H'0003' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCTL1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' T0CKI EQU H'0004' AN4 EQU H'0005' OSC2 EQU H'0006' OSC1 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' LVDIN EQU H'0005' CLKO EQU H'0006' CLKI EQU H'0007' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' CCP2B EQU H'0003' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2C EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' CCP2E EQU H'0007' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS EQU H'0007' C2OUTF EQU H'0001' C1OUTF EQU H'0002' CVREFF EQU H'0005' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' CCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' MCLR EQU H'0005' CK2 EQU H'0001' DT2 EQU H'0002' VPP EQU H'0005' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' TXIE EQU H'0004' RCIE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' TXIF EQU H'0004' RCIF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' TXIP EQU H'0004' RCIP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' TX2IE EQU H'0004' RC2IE EQU H'0005' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' TX2IF EQU H'0004' RC2IF EQU H'0005' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' TX2IP EQU H'0004' RC2IP EQU H'0005' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' NOT_T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3SYNC EQU H'0002' T3INSYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT EQU H'0006' C2OUT EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' CVREF EQU H'0004' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DCCP3Y EQU H'0004' DCCP3X EQU H'0005' DC3B0 EQU H'0004' DC3B1 EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DCCP2Y EQU H'0004' DCCP2X EQU H'0005' CCP2Y EQU H'0004' CCP2X EQU H'0005' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DCCP1Y EQU H'0004' DCCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1X EQU H'0005' DC1B0 EQU H'0004' DC1B1 EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO_DONE EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' GO EQU H'0001' NOT_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' NOT_T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' VDIRMAG EQU H'0007' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3IP EQU H'0001' TMR0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3P EQU H'0001' T0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0IF EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0IE EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0F EQU H'0001' T0IF EQU H'0002' INT0E EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0300'-H'0F3F' __BADRAM H'0F70'-H'0F7D' __BADRAM H'0FA6'-H'0FAA' __BADRAM H'0FB6' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; PM = EM Extended Microcontroller mode ; PM = MPB Microprocessor with Boot Block mode ; PM = MP Microprocessor mode ; PM = MC Microcontroller mode ; ; External Bus Data Width Select bit: ; BW = 8 8-bit External Bus Data Width ; BW = 16 16-bit External Bus Data Width ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) ; WAIT = OFF Wait selections unavailable, device will not wait ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer 1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; CCP2 MUX bit: ; CCP2MX = PORTBE CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit: ; CP = ON Program memory block code-protected ; CP = OFF Program memory block not code-protected ; ; Table Read Protection bit: ; EBTR = ON Internal program memory block protected from table reads executed from external memory block ; EBTR = OFF Internal program memory block not protected from table reads executed from external memory block ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG7L 30000Ch ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG7L EQU H'30000C' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (clock frequency = 4 x FOSC1) _OSC_RCIO_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum Setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum Setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _PM_EM_3L EQU H'FC' ; Extended Microcontroller mode _PM_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _PM_MP_3L EQU H'FE' ; Microprocessor mode _PM_MC_3L EQU H'FF' ; Microcontroller mode _BW_8_3L EQU H'BF' ; 8-bit External Bus Data Width _BW_16_3L EQU H'FF' ; 16-bit External Bus Data Width _WAIT_ON_3L EQU H'7F' ; Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>) _WAIT_OFF_3L EQU H'FF' ; Wait selections unavailable, device will not wait ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP_ON_5L EQU H'FE' ; Program memory block code-protected _CP_OFF_5L EQU H'FF' ; Program memory block not code-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR_ON_7L EQU H'FE' ; Internal program memory block protected from table reads executed from external memory block _EBTR_OFF_7L EQU H'FF' ; Internal program memory block not protected from table reads executed from external memory block _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f25k20.inc0000644000175000017500000013135111156521301013376 00000000000000 LIST ;========================================================================== ; MPASM PIC18F25K20 processor include ; ; (c) Copyright 1999-2008 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F25K20 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F25K20 ; 2. LIST directive in the source file ; LIST P=PIC18F25K20 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F25K20 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSPMSK EQU H'0F77' SLRCON EQU H'0F78' CM2CON1 EQU H'0F79' CM2CON0 EQU H'0F7A' CM1CON0 EQU H'0F7B' WPUB EQU H'0F7C' IOCB EQU H'0F7D' ANSEL EQU H'0F7E' ANSELH EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTE EQU H'0F84' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' OSCTUNE EQU H'0F9B' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' RCSTA EQU H'0FAB' TXSTA EQU H'0FAC' TXREG EQU H'0FAD' RCREG EQU H'0FAE' SPBRG EQU H'0FAF' SPBRGH EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CVRCON2 EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' PWM1CON EQU H'0FB7' BAUDCON EQU H'0FB8' BAUDCTL EQU H'0FB8' PSTRCON EQU H'0FB9' CCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSPCON2 EQU H'0FC5' SSPCON1 EQU H'0FC6' SSPSTAT EQU H'0FC7' SSPADD EQU H'0FC8' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSPMSK Bits ----------------------------------------------------- MSK0 EQU H'0000' MSK1 EQU H'0001' MSK2 EQU H'0002' MSK3 EQU H'0003' MSK4 EQU H'0004' MSK5 EQU H'0005' MSK6 EQU H'0006' MSK7 EQU H'0007' ;----- SLRCON Bits ----------------------------------------------------- SLRA EQU H'0000' SLRB EQU H'0001' SLRC EQU H'0002' SLRD EQU H'0003' SLRE EQU H'0004' ;----- CM2CON1 Bits ----------------------------------------------------- C2RSEL EQU H'0004' C1RSEL EQU H'0005' MC2OUT EQU H'0006' MC1OUT EQU H'0007' ;----- CM2CON0 Bits ----------------------------------------------------- C2CH0 EQU H'0000' C2CH1 EQU H'0001' C2R EQU H'0002' C2SP EQU H'0003' C2POL EQU H'0004' C2OE EQU H'0005' C2OUT_CM2CON0 EQU H'0006' C2ON EQU H'0007' ;----- CM1CON0 Bits ----------------------------------------------------- C1CH0 EQU H'0000' C1CH1 EQU H'0001' C1R EQU H'0002' C1SP EQU H'0003' C1POL EQU H'0004' C1OE EQU H'0005' C1OUT_CM1CON0 EQU H'0006' C1ON EQU H'0007' ;----- WPUB Bits ----------------------------------------------------- WPUB0 EQU H'0000' WPUB1 EQU H'0001' WPUB2 EQU H'0002' WPUB3 EQU H'0003' WPUB4 EQU H'0004' WPUB5 EQU H'0005' WPUB6 EQU H'0006' WPUB7 EQU H'0007' ;----- IOCB Bits ----------------------------------------------------- IOCB4 EQU H'0004' IOCB5 EQU H'0005' IOCB6 EQU H'0006' IOCB7 EQU H'0007' ;----- ANSEL Bits ----------------------------------------------------- ANS0 EQU H'0000' ANS1 EQU H'0001' ANS2 EQU H'0002' ANS3 EQU H'0003' ANS4 EQU H'0004' ANS5 EQU H'0005' ANS6 EQU H'0006' ANS7 EQU H'0007' ;----- ANSELH Bits ----------------------------------------------------- ANS8 EQU H'0000' ANS9 EQU H'0001' ANS10 EQU H'0002' ANS11 EQU H'0003' ANS12 EQU H'0004' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' C12IN0M EQU H'0000' C12IN1M EQU H'0001' C2INP EQU H'0002' C1INP EQU H'0003' C1OUT_PORTA EQU H'0004' C2OUT_PORTA EQU H'0005' C12IN0N EQU H'0000' C12IN1N EQU H'0001' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' SS EQU H'0005' VREFN EQU H'0002' NOT_SS EQU H'0005' CVREF EQU H'0002' LVDIN EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' CCP2_PORTB EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' AN12 EQU H'0000' AN10 EQU H'0001' AN8 EQU H'0002' AN9 EQU H'0003' AN11 EQU H'0004' PGM EQU H'0005' PGC EQU H'0006' PGD EQU H'0007' FLT0 EQU H'0000' C12IN3M EQU H'0001' C12IN2M EQU H'0003' C12IN3N EQU H'0001' C12IN2N EQU H'0003' P1C EQU H'0001' P1B EQU H'0002' P1D EQU H'0004' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' CCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' CCP2_PORTC EQU H'0001' P1A EQU H'0002' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' T1CKI EQU H'0000' T3CKI EQU H'0000' ;----- PORTE Bits ----------------------------------------------------- RE3 EQU H'0003' MCLR EQU H'0003' NOT_MCLR EQU H'0003' VPP EQU H'0003' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' TUN5 EQU H'0005' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' C2IE EQU H'0005' C1IE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' C2IF EQU H'0005' C1IF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' C2IP EQU H'0005' C1IP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ADDEN EQU H'0003' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' NOT_T3SYNC EQU H'0002' ;----- CVRCON2 Bits ----------------------------------------------------- FVRST EQU H'0006' FVREN EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- PWM1CON Bits ----------------------------------------------------- PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- BAUDCTL Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' CKTXP EQU H'0004' DTRXP EQU H'0005' RCIDL EQU H'0006' ABDOVF EQU H'0007' SCKP EQU H'0004' ;----- PSTRCON Bits ----------------------------------------------------- STRA EQU H'0000' STRB EQU H'0001' STRC EQU H'0002' STRD EQU H'0003' STRSYNC EQU H'0004' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' DONE EQU H'0001' NOT_DONE EQU H'0001' GO_DONE EQU H'0001' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R EQU H'0002' S EQU H'0003' P EQU H'0004' D EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' NOT_W EQU H'0002' NOT_A EQU H'0005' R_W EQU H'0002' D_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT1E EQU H'0003' INT2E EQU H'0004' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT1IE EQU H'0003' INT2IE EQU H'0004' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' TMR0IP EQU H'0002' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' RBPU EQU H'0007' NOT_RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' TMR0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' TMR0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' T0IF EQU H'0002' INT0IE EQU H'0004' T0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKUNF EQU H'0006' STKOVF EQU H'0007' STKFUL EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0600'-H'0F5F' __BADRAM H'0F83' __BADRAM H'0F85'-H'0F88' __BADRAM H'0F8C'-H'0F91' __BADRAM H'0F95'-H'0F9A' __BADRAM H'0F9C' __BADRAM H'0FA3'-H'0FA5' __BADRAM H'0FAA' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; FOSC = LP LP oscillator ; FOSC = XT XT oscillator ; FOSC = HS HS oscillator ; FOSC = RC External RC oscillator, CLKOUT function on RA6 ; FOSC = EC EC oscillator, CLKOUT function on RA6 ; FOSC = ECIO6 EC oscillator, port function on RA6 ; FOSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; FOSC = RCIO6 External RC oscillator, port function on RA6 ; FOSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; FOSC = INTIO7 Internal oscillator block, CLKOUT function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown Out Voltage: ; BORV = 30 VBOR set to 3.0 V nominal ; BORV = 27 VBOR set to 2.7 V nominal ; BORV = 22 VBOR set to 2.2 V nominal ; BORV = 18 VBOR set to 1.8 V nominal ; ; Watchdog Timer Enable bit: ; WDTEN = OFF WDT is controlled by SWDTEN bit of the WDTCON register ; WDTEN = ON WDT is always enabled. SWDTEN bit has no effect. ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled, RE3 input pin disabled ; ; HF-INTOSC Fast Startup: ; HFOFST = OFF The system clock is held off until the HF-INTOSC is stable. ; HFOFST = ON HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Disabled, T1 operates in standard power mode. ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = OFF PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ON PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 Mux bit: ; CCP2MX = PORTBE CCP2 input/output is multiplexed with RB3 ; CCP2MX = PORTC CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection Block 0: ; CP0 = ON Block 0 (000800-001FFFh) code-protected ; CP0 = OFF Block 0 (000800-001FFFh) not code-protected ; ; Code Protection Block 1: ; CP1 = ON Block 1 (002000-003FFFh) code-protected ; CP1 = OFF Block 1 (002000-003FFFh) not code-protected ; ; Code Protection Block 2: ; CP2 = ON Block 2 (004000-005FFFh) code-protected ; CP2 = OFF Block 2 (004000-005FFFh) not code-protected ; ; Code Protection Block 3: ; CP3 = ON Block 3 (006000-007FFFh) code-protected ; CP3 = OFF Block 3 (006000-007FFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block (000000-0007FFh) code-protected ; CPB = OFF Boot block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection Block 0: ; WRT0 = ON Block 0 (000800-001FFFh) write-protected ; WRT0 = OFF Block 0 (000800-001FFFh) not write-protected ; ; Write Protection Block 1: ; WRT1 = ON Block 1 (002000-003FFFh) write-protected ; WRT1 = OFF Block 1 (002000-003FFFh) not write-protected ; ; Write Protection Block 2: ; WRT2 = ON Block 2 (004000-005FFFh) write-protected ; WRT2 = OFF Block 2 (004000-005FFFh) not write-protected ; ; Write Protection Block 3: ; WRT3 = ON Block 3 (006000-007FFFh) write-protected ; WRT3 = OFF Block 3 (006000-007FFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block (000000-0007FFh) write-protected ; WRTB = OFF Boot block (000000-0007FFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection Block 0: ; EBTR0 = ON Block 0 (000800-001FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800-001FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 1: ; EBTR1 = ON Block 1 (002000-003FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 2: ; EBTR2 = ON Block 2 (004000-005FFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (004000-005FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection Block 3: ; EBTR3 = ON Block 3 (006000-007FFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block (000000-0007FFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot block (000000-0007FFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _FOSC_LP_1H EQU H'F0' ; LP oscillator _FOSC_XT_1H EQU H'F1' ; XT oscillator _FOSC_HS_1H EQU H'F2' ; HS oscillator _FOSC_RC_1H EQU H'F3' ; External RC oscillator, CLKOUT function on RA6 _FOSC_EC_1H EQU H'F4' ; EC oscillator, CLKOUT function on RA6 _FOSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _FOSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _FOSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _FOSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _FOSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKOUT function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled _IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal _BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal _BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal _BORV_18_2L EQU H'FF' ; VBOR set to 1.8 V nominal ;----- CONFIG2H Options -------------------------------------------------- _WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register _WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect. _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RE3 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled, RE3 input pin disabled _HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HF-INTOSC is stable. _HFOFST_ON_3H EQU H'FF' ; HF-INTOSC starts clocking the CPU without waiting for the oscillator to stablize. _LPT1OSC_OFF_3H EQU H'FB' ; Disabled, T1 operates in standard power mode. _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _PBADEN_OFF_3H EQU H'FD' ; PORTB<4:0> pins are configured as digital I/O on Reset _PBADEN_ON_3H EQU H'FF' ; PORTB<4:0> pins are configured as analog input channels on Reset _CCP2MX_PORTBE_3H EQU H'FE' ; CCP2 input/output is multiplexed with RB3 _CCP2MX_PORTC_3H EQU H'FF' ; CCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800-001FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800-001FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (002000-003FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (002000-003FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (004000-005FFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (004000-005FFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (006000-007FFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (006000-007FFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800-001FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800-001FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (002000-003FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (002000-003FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (004000-005FFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (004000-005FFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (006000-007FFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (006000-007FFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot block (000000-0007FFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot block (000000-0007FFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800-001FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (002000-003FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (004000-005FFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (006000-007FFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot block (000000-0007FFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p18f8723.inc0000644000175000017500000022037511156521302013244 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8723 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8723 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8723 ; 2. LIST directive in the source file ; LIST P=PIC18F8723 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8723 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ECCP2_PORTB EQU H'0003' P2A_PORTB EQU H'0003' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C_PORTE EQU H'0003' P3B_PORTE EQU H'0004' P1C_PORTE EQU H'0005' P1B_PORTE EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' P3C_PORTH EQU H'0004' P3B_PORTH EQU H'0005' P1C_PORTH EQU H'0006' P1B_PORTH EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; Address Bus Width Select bits: ; ADDRBW = ADDR8BIT 8-bit Address Bus ; ADDRBW = ADDR12BIT 12-bit Address Bus ; ADDRBW = ADDR16BIT 16-bit Address Bus ; ADDRBW = ADDR20BIT 20-bit Address Bus ; ; Data Bus Width Select bit: ; DATABW = DATA8BIT 8-bit External Bus mode ; DATABW = DATA16BIT 16-bit External Bus mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits ; WAIT = OFF Wait selections are unavailable for table reads and table writes ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; ECCP MUX bit: ; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively ; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively ; ; CCP2 MUX bit: ; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Code Protection bit Block 6: ; CP6 = ON Block 6 (01BFFF-018000h) code-protected ; CP6 = OFF Block 6 (01BFFF-018000h) not code-protected ; ; Code Protection bit Block 7: ; CP7 = ON Block 7 (01C000-01FFFFh) code-protected ; CP7 = OFF Block 7 (01C000-01FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Write Protection bit Block 6: ; WRT6 = ON Block 6 (01BFFF-018000h) write-protected ; WRT6 = OFF Block 6 (01BFFF-018000h) not write-protected ; ; Write Protection bit Block 7: ; WRT7 = ON Block 7 (01C000-01FFFFh) write-protected ; WRT7 = OFF Block 7 (01C000-01FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 6: ; EBTR6 = ON Block 6 (018000-01BFFFh) protected from table reads executed in other blocks ; EBTR6 = OFF Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 7: ; EBTR7 = ON Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks ; EBTR7 = OFF Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _ADDRBW_ADDR8BIT_3L EQU H'CF' ; 8-bit Address Bus _ADDRBW_ADDR12BIT_3L EQU H'DF' ; 12-bit Address Bus _ADDRBW_ADDR16BIT_3L EQU H'EF' ; 16-bit Address Bus _ADDRBW_ADDR20BIT_3L EQU H'FF' ; 20-bit Address Bus _DATABW_DATA8BIT_3L EQU H'BF' ; 8-bit External Bus mode _DATABW_DATA16BIT_3L EQU H'FF' ; 16-bit External Bus mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits _WAIT_OFF_3L EQU H'FF' ; Wait selections are unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _ECCPMX_PORTH_3H EQU H'FD' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively _ECCPMX_PORTE_3H EQU H'FF' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively _CCP2MX_PORTBE_3H EQU H'FE' ; ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected _CP6_ON_5L EQU H'BF' ; Block 6 (01BFFF-018000h) code-protected _CP6_OFF_5L EQU H'FF' ; Block 6 (01BFFF-018000h) not code-protected _CP7_ON_5L EQU H'7F' ; Block 7 (01C000-01FFFFh) code-protected _CP7_OFF_5L EQU H'FF' ; Block 7 (01C000-01FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected _WRT6_ON_6L EQU H'BF' ; Block 6 (01BFFF-018000h) write-protected _WRT6_OFF_6L EQU H'FF' ; Block 6 (01BFFF-018000h) not write-protected _WRT7_ON_6L EQU H'7F' ; Block 7 (01C000-01FFFFh) write-protected _WRT7_OFF_6L EQU H'FF' ; Block 7 (01C000-01FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks _EBTR6_ON_7L EQU H'BF' ; Block 6 (018000-01BFFFh) protected from table reads executed in other blocks _EBTR6_OFF_7L EQU H'FF' ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks _EBTR7_ON_7L EQU H'7F' ; Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks _EBTR7_OFF_7L EQU H'FF' ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/p16f87.inc0000644000175000017500000003650711156313161013101 00000000000000 LIST ; P16F87.INC Standard Header File, Version 1.00 Microchip Technology, Inc. NOLIST ; This header file defines configurations, registers, and other useful bits of ; information for the PIC16F87 microcontroller. These names are taken to match ; the data sheets as closely as possible. ; Note that the processor must be selected before this file is ; included. The processor may be selected the following ways: ; 1. Command line switch: ; C:\ MPASM MYFILE.ASM /PIC16F87 ; 2. LIST directive in the source file ; LIST P=PIC16F87 ; 3. Processor Type entry in the MPASM full-screen interface ;========================================================================== ; ; Revision History ; ;========================================================================== ;Rev: Date: Reason: ;1.00 07/29/02 Initial Release ;1.01 09/18/02 Changed name of bit-2 in the OSCCON register to IOFS ;1.02 01/10/03 Added bit names for TXSTA & RCSTA registers. ;1.03 01/24/03 Changed Config bit CCP1_RB2 to CCP1_RB0 ;1.04 12/02/03 Modified the WRT1:WRT0 bit definition in Config Word 1. ;1.05 02/08/04 Changed bit in _CONFIG1 example from CCP1_RB2 to CCP1_RB0. ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __16F87 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; ; Register Definitions ; ;========================================================================== W EQU H'0000' F EQU H'0001' ;----- Register Files------------------------------------------------------ INDF EQU H'0000' TMR0 EQU H'0001' PCL EQU H'0002' STATUS EQU H'0003' FSR EQU H'0004' PORTA EQU H'0005' PORTB EQU H'0006' PCLATH EQU H'000A' INTCON EQU H'000B' PIR1 EQU H'000C' PIR2 EQU H'000D' TMR1L EQU H'000E' TMR1H EQU H'000F' T1CON EQU H'0010' TMR2 EQU H'0011' T2CON EQU H'0012' SSPBUF EQU H'0013' SSPCON EQU H'0014' CCPR1L EQU H'0015' CCPR1H EQU H'0016' CCP1CON EQU H'0017' RCSTA EQU H'0018' TXREG EQU H'0019' RCREG EQU H'001A' OPTION_REG EQU H'0081' TRISA EQU H'0085' TRISB EQU H'0086' PIE1 EQU H'008C' PIE2 EQU H'008D' PCON EQU H'008E' OSCCON EQU H'008F' OSCTUNE EQU H'0090' PR2 EQU H'0092' SSPADD EQU H'0093' SSPSTAT EQU H'0094' TXSTA EQU H'0098' SPBRG EQU H'0099' CMCON EQU H'009C' CVRCON EQU H'009D' WDTCON EQU H'0105' EEDATA EQU H'010C' EEADR EQU H'010D' EEDATH EQU H'010E' EEADRH EQU H'010F' EECON1 EQU H'018C' EECON2 EQU H'018D' ;----- STATUS Bits -------------------------------------------------------- IRP EQU H'0007' RP1 EQU H'0006' RP0 EQU H'0005' NOT_TO EQU H'0004' NOT_PD EQU H'0003' Z EQU H'0002' DC EQU H'0001' C EQU H'0000' ;----- INTCON Bits -------------------------------------------------------- GIE EQU H'0007' PEIE EQU H'0006' TMR0IE EQU H'0005' INTE EQU H'0004' RBIE EQU H'0003' TMR0IF EQU H'0002' INTF EQU H'0001' RBIF EQU H'0000' ;----- PIR1 Bits ---------------------------------------------------------- RCIF EQU H'0005' TXIF EQU H'0004' SSPIF EQU H'0003' CCP1IF EQU H'0002' TMR2IF EQU H'0001' TMR1IF EQU H'0000' ;----- PIR2 Bits ---------------------------------------------------------- OSFIF EQU H'0007' CMIF EQU H'0006' EEIF EQU H'0004' ;----- T1CON Bits --------------------------------------------------------- T1RUN EQU H'0006' T1CKPS1 EQU H'0005' T1CKPS0 EQU H'0004' T1OSCEN EQU H'0003' NOT_T1SYNC EQU H'0002' T1INSYNC EQU H'0002' ; Backward compatibility only TMR1CS EQU H'0001' TMR1ON EQU H'0000' ;----- T2CON Bits --------------------------------------------------------- TOUTPS3 EQU H'0006' TOUTPS2 EQU H'0005' TOUTPS1 EQU H'0004' TOUTPS0 EQU H'0003' TMR2ON EQU H'0002' T2CKPS1 EQU H'0001' T2CKPS0 EQU H'0000' ;----- SSPCON Bits -------------------------------------------------------- WCOL EQU H'0007' SSPOV EQU H'0006' SSPEN EQU H'0005' CKP EQU H'0004' SSPM3 EQU H'0003' SSPM2 EQU H'0002' SSPM1 EQU H'0001' SSPM0 EQU H'0000' ;----- CCP1CON Bits ------------------------------------------------------- CCP1X EQU H'0005' CCP1Y EQU H'0004' CCP1M3 EQU H'0003' CCP1M2 EQU H'0002' CCP1M1 EQU H'0001' CCP1M0 EQU H'0000' ;----- RCSTA Bits --------------------------------------------------------- SPEN EQU H'0007' RX9 EQU H'0006' RC9 EQU H'0006' ; Backward compatibility only NOT_RC8 EQU H'0006' ; Backward compatibility only RC8_9 EQU H'0006' ; Backward compatibility only SREN EQU H'0005' CREN EQU H'0004' ADDEN EQU H'0003' FERR EQU H'0002' OERR EQU H'0001' RX9D EQU H'0000' RCD8 EQU H'0000' ; Backward compatibility only ;----- OPTION_REG Bits ----------------------------------------------------- NOT_RBPU EQU H'0007' INTEDG EQU H'0006' T0CS EQU H'0005' T0SE EQU H'0004' PSA EQU H'0003' PS2 EQU H'0002' PS1 EQU H'0001' PS0 EQU H'0000' ;----- PIE1 Bits ---------------------------------------------------------- RCIE EQU H'0005' TXIE EQU H'0004' SSPIE EQU H'0003' CCP1IE EQU H'0002' TMR2IE EQU H'0001' TMR1IE EQU H'0000' ;----- PIE2 Bits ---------------------------------------------------------- OSFIE EQU H'0007' CMIE EQU H'0006' EEIE EQU H'0004' ;----- PCON Bits ---------------------------------------------------------- NOT_POR EQU H'0001' NOT_BO EQU H'0000' NOT_BOR EQU H'0000' ;----- OSCCON Bits ------------------------------------------------------- IRCF2 EQU H'0006' IRCF1 EQU H'0005' IRCF0 EQU H'0004' OSTS EQU H'0003' IOFS EQU H'0002' SCS1 EQU H'0001' SCS0 EQU H'0000' ;----- OSCTUNE Bits ------------------------------------------------------- TUN5 EQU H'0005' TUN4 EQU H'0004' TUN3 EQU H'0003' TUN2 EQU H'0002' TUN1 EQU H'0001' TUN0 EQU H'0000' ;----- SSPSTAT Bits ------------------------------------------------------- SMP EQU H'0007' CKE EQU H'0006' D EQU H'0005' I2C_DATA EQU H'0005' NOT_A EQU H'0005' NOT_ADDRESS EQU H'0005' D_A EQU H'0005' DATA_ADDRESS EQU H'0005' P EQU H'0004' I2C_STOP EQU H'0004' S EQU H'0003' I2C_START EQU H'0003' R EQU H'0002' I2C_READ EQU H'0002' NOT_W EQU H'0002' NOT_WRITE EQU H'0002' R_W EQU H'0002' READ_WRITE EQU H'0002' UA EQU H'0001' BF EQU H'0000' ;----- TXSTA Bits --------------------------------------------------------- CSRC EQU H'0007' TX9 EQU H'0006' NOT_TX8 EQU H'0006' ; Backward compatibility only TX8_9 EQU H'0006' ; Backward compatibility only TXEN EQU H'0005' SYNC EQU H'0004' BRGH EQU H'0002' TRMT EQU H'0001' TX9D EQU H'0000' TXD8 EQU H'0000' ; Backward compatibility only ;----- WDTCON Bits -------------------------------------------------------- WDTPS3 EQU H'0004' WDTPS2 EQU H'0003' WDTPS1 EQU H'0002' WDTPS0 EQU H'0001' SWDTEN EQU H'0000' SWDTE EQU H'0000' ;----- CMCON Bits --------------------------------------------------------- C2OUT EQU H'0007' C1OUT EQU H'0006' C2INV EQU H'0005' C1INV EQU H'0004' CIS EQU H'0003' CM2 EQU H'0002' CM1 EQU H'0001' CM0 EQU H'0000' ;----- CVRCON Bits -------------------------------------------------------- CVREN EQU H'0007' CVROE EQU H'0006' CVRR EQU H'0005' CVR3 EQU H'0003' CVR2 EQU H'0002' CVR1 EQU H'0001' CVR0 EQU H'0000' ;----- EECON1 Bits -------------------------------------------------------- EEPGD EQU H'0007' FREE EQU H'0004' WRERR EQU H'0003' WREN EQU H'0002' WR EQU H'0001' RD EQU H'0000' ;========================================================================== ; ; RAM Definition ; ;========================================================================== __MAXRAM H'1FF' __BADRAM H'07'-H'09', H'1B'-H'1F' __BADRAM H'87'-H'89', H'91', H'95'-H'97', H'9A', H'9E'-H'9F' __BADRAM H'107'-H'109' __BADRAM H'185', H'187'-H'189', H'18E'-H'18F' ;========================================================================== ; ; Configuration Bits ; ;========================================================================== _CONFIG1 EQU H'2007' _CONFIG2 EQU H'2008' ;Configuration Byte 1 Options _CP_ALL EQU H'1FFF' _CP_OFF EQU H'3FFF' _CCP1_RB0 EQU H'3FFF' _CCP1_RB3 EQU H'2FFF' _DEBUG_OFF EQU H'3FFF' _DEBUG_ON EQU H'37FF' _WRT_PROTECT_OFF EQU H'3FFF' ;No program memory write protection _WRT_PROTECT_256 EQU H'3DFF' ;First 256 program memory protected _WRT_PROTECT_2048 EQU H'3BFF' ;First 2048 program memory protected _WRT_PROTECT_ALL EQU H'39FF' ;All of program memory protected _CPD_ON EQU H'3EFF' _CPD_OFF EQU H'3FFF' _LVP_ON EQU H'3FFF' _LVP_OFF EQU H'3F7F' _BODEN_ON EQU H'3FFF' _BODEN_OFF EQU H'3FBF' _MCLR_ON EQU H'3FFF' _MCLR_OFF EQU H'3FDF' _PWRTE_OFF EQU H'3FFF' _PWRTE_ON EQU H'3FF7' _WDT_ON EQU H'3FFF' _WDT_OFF EQU H'3FFB' _EXTRC_CLKOUT EQU H'3FFF' _EXTRC_IO EQU H'3FFE' _INTRC_CLKOUT EQU H'3FFD' _INTRC_IO EQU H'3FFC' _EXTCLK EQU H'3FEF' _HS_OSC EQU H'3FEE' _XT_OSC EQU H'3FED' _LP_OSC EQU H'3FEC' ;Configuration Byte 2 Options _IESO_ON EQU H'3FFF' _IESO_OFF EQU H'3FFD' _FCMEN_ON EQU H'3FFF' _FCMEN_OFF EQU H'3FFE' ; To use the Configuration Bits, place the following lines in your source code ; in the following format, and change the configuration value to the desired ; setting (such as CP_OFF to CP_ALL). These are currently commented out here ; and each __CONFIG line should have the preceding semicolon removed when ; pasted into your source code. ;Program Configuration Register 1 ; __CONFIG _CONFIG1, _CP_OFF & _CCP1_RB0 & _DEBUG_OFF & _WRT_PROTECT_OFF & _CPD_OFF & _LVP_OFF & _BODEN_OFF & _MCLR_OFF & _PWRTE_OFF & _WDT_OFF & _HS_OSC ;Program Configuration Register 2 ; __CONFIG _CONFIG2, _IESO_OFF & _FCMEN_OFF LIST gputils-0.13.7/header/p18f8722.inc0000644000175000017500000022037511156521301013242 00000000000000 LIST ;========================================================================== ; MPASM PIC18F8722 processor include ; ; (c) Copyright 1999-2007 Microchip Technology, All rights reserved ;========================================================================== NOLIST ;========================================================================== ; This header file defines configurations, registers, and other useful ; bits of information for the PIC18F8722 microcontroller. These names ; are taken to match the data sheets as closely as possible. ; ; Note that the processor must be selected before this file is included. ; The processor may be selected the following ways: ; ; 1. Command line switch: ; C:\MPASM MYFILE.ASM /PIC18F8722 ; 2. LIST directive in the source file ; LIST P=PIC18F8722 ; 3. Processor Type entry in the MPASM full-screen interface ; 4. Setting the processor in the MPLAB Project Dialog ;========================================================================== ;========================================================================== ; ; Verify Processor ; ;========================================================================== IFNDEF __18F8722 MESSG "Processor-header file mismatch. Verify selected processor." ENDIF ;========================================================================== ; 18xxxx Family EQUates ;========================================================================== FSR0 EQU 0 FSR1 EQU 1 FSR2 EQU 2 FAST EQU 1 W EQU 0 A EQU 0 ACCESS EQU 0 BANKED EQU 1 ;========================================================================== ;========================================================================== ; 16Cxxx/17Cxxx Substitutions ;========================================================================== #define DDRA TRISA ; PIC17Cxxx SFR substitution #define DDRB TRISB ; PIC17Cxxx SFR substitution #define DDRC TRISC ; PIC17Cxxx SFR substitution #define DDRD TRISD ; PIC17Cxxx SFR substitution #define DDRE TRISE ; PIC17Cxxx SFR substitution ;========================================================================== ; ; Register Definitions ; ;========================================================================== ;----- Register Files ----------------------------------------------------- SSP2CON2 EQU H'0F62' SSP2CON1 EQU H'0F63' SSP2STAT EQU H'0F64' SSP2ADD EQU H'0F65' SSP2BUF EQU H'0F66' ECCP2DEL EQU H'0F67' ECCP2AS EQU H'0F68' ECCP3DEL EQU H'0F69' ECCP3AS EQU H'0F6A' RCSTA2 EQU H'0F6B' TXSTA2 EQU H'0F6C' TXREG2 EQU H'0F6D' RCREG2 EQU H'0F6E' SPBRG2 EQU H'0F6F' CCP5CON EQU H'0F70' CCPR5 EQU H'0F71' CCPR5L EQU H'0F71' CCPR5H EQU H'0F72' CCP4CON EQU H'0F73' CCPR4 EQU H'0F74' CCPR4L EQU H'0F74' CCPR4H EQU H'0F75' T4CON EQU H'0F76' PR4 EQU H'0F77' TMR4 EQU H'0F78' ECCP1DEL EQU H'0F79' BAUDCON2 EQU H'0F7C' SPBRGH2 EQU H'0F7D' BAUDCON EQU H'0F7E' BAUDCON1 EQU H'0F7E' SPBRGH EQU H'0F7F' SPBRGH1 EQU H'0F7F' PORTA EQU H'0F80' PORTB EQU H'0F81' PORTC EQU H'0F82' PORTD EQU H'0F83' PORTE EQU H'0F84' PORTF EQU H'0F85' PORTG EQU H'0F86' PORTH EQU H'0F87' PORTJ EQU H'0F88' LATA EQU H'0F89' LATB EQU H'0F8A' LATC EQU H'0F8B' LATD EQU H'0F8C' LATE EQU H'0F8D' LATF EQU H'0F8E' LATG EQU H'0F8F' LATH EQU H'0F90' LATJ EQU H'0F91' DDRA EQU H'0F92' TRISA EQU H'0F92' DDRB EQU H'0F93' TRISB EQU H'0F93' DDRC EQU H'0F94' TRISC EQU H'0F94' DDRD EQU H'0F95' TRISD EQU H'0F95' DDRE EQU H'0F96' TRISE EQU H'0F96' DDRF EQU H'0F97' TRISF EQU H'0F97' DDRG EQU H'0F98' TRISG EQU H'0F98' DDRH EQU H'0F99' TRISH EQU H'0F99' DDRJ EQU H'0F9A' TRISJ EQU H'0F9A' OSCTUNE EQU H'0F9B' MEMCON EQU H'0F9C' PIE1 EQU H'0F9D' PIR1 EQU H'0F9E' IPR1 EQU H'0F9F' PIE2 EQU H'0FA0' PIR2 EQU H'0FA1' IPR2 EQU H'0FA2' PIE3 EQU H'0FA3' PIR3 EQU H'0FA4' IPR3 EQU H'0FA5' EECON1 EQU H'0FA6' EECON2 EQU H'0FA7' EEDATA EQU H'0FA8' EEADR EQU H'0FA9' EEADRH EQU H'0FAA' RCSTA EQU H'0FAB' RCSTA1 EQU H'0FAB' TXSTA EQU H'0FAC' TXSTA1 EQU H'0FAC' TXREG EQU H'0FAD' TXREG1 EQU H'0FAD' RCREG EQU H'0FAE' RCREG1 EQU H'0FAE' SPBRG EQU H'0FAF' SPBRG1 EQU H'0FAF' PSPCON EQU H'0FB0' T3CON EQU H'0FB1' TMR3L EQU H'0FB2' TMR3H EQU H'0FB3' CMCON EQU H'0FB4' CVRCON EQU H'0FB5' ECCP1AS EQU H'0FB6' CCP3CON EQU H'0FB7' ECCP3CON EQU H'0FB7' CCPR3 EQU H'0FB8' CCPR3L EQU H'0FB8' CCPR3H EQU H'0FB9' CCP2CON EQU H'0FBA' ECCP2CON EQU H'0FBA' CCPR2 EQU H'0FBB' CCPR2L EQU H'0FBB' CCPR2H EQU H'0FBC' CCP1CON EQU H'0FBD' ECCP1CON EQU H'0FBD' CCPR1 EQU H'0FBE' CCPR1L EQU H'0FBE' CCPR1H EQU H'0FBF' ADCON2 EQU H'0FC0' ADCON1 EQU H'0FC1' ADCON0 EQU H'0FC2' ADRES EQU H'0FC3' ADRESL EQU H'0FC3' ADRESH EQU H'0FC4' SSP1CON2 EQU H'0FC5' SSPCON2 EQU H'0FC5' SSP1CON1 EQU H'0FC6' SSPCON1 EQU H'0FC6' SSP1STAT EQU H'0FC7' SSPSTAT EQU H'0FC7' SSP1ADD EQU H'0FC8' SSPADD EQU H'0FC8' SSP1BUF EQU H'0FC9' SSPBUF EQU H'0FC9' T2CON EQU H'0FCA' PR2 EQU H'0FCB' TMR2 EQU H'0FCC' T1CON EQU H'0FCD' TMR1L EQU H'0FCE' TMR1H EQU H'0FCF' RCON EQU H'0FD0' WDTCON EQU H'0FD1' HLVDCON EQU H'0FD2' LVDCON EQU H'0FD2' OSCCON EQU H'0FD3' T0CON EQU H'0FD5' TMR0L EQU H'0FD6' TMR0H EQU H'0FD7' STATUS EQU H'0FD8' FSR2L EQU H'0FD9' FSR2H EQU H'0FDA' PLUSW2 EQU H'0FDB' PREINC2 EQU H'0FDC' POSTDEC2 EQU H'0FDD' POSTINC2 EQU H'0FDE' INDF2 EQU H'0FDF' BSR EQU H'0FE0' FSR1L EQU H'0FE1' FSR1H EQU H'0FE2' PLUSW1 EQU H'0FE3' PREINC1 EQU H'0FE4' POSTDEC1 EQU H'0FE5' POSTINC1 EQU H'0FE6' INDF1 EQU H'0FE7' WREG EQU H'0FE8' FSR0L EQU H'0FE9' FSR0H EQU H'0FEA' PLUSW0 EQU H'0FEB' PREINC0 EQU H'0FEC' POSTDEC0 EQU H'0FED' POSTINC0 EQU H'0FEE' INDF0 EQU H'0FEF' INTCON3 EQU H'0FF0' INTCON2 EQU H'0FF1' INTCON EQU H'0FF2' PROD EQU H'0FF3' PRODL EQU H'0FF3' PRODH EQU H'0FF4' TABLAT EQU H'0FF5' TBLPTR EQU H'0FF6' TBLPTRL EQU H'0FF6' TBLPTRH EQU H'0FF7' TBLPTRU EQU H'0FF8' PC EQU H'0FF9' PCL EQU H'0FF9' PCLATH EQU H'0FFA' PCLATU EQU H'0FFB' STKPTR EQU H'0FFC' TOS EQU H'0FFD' TOSL EQU H'0FFD' TOSH EQU H'0FFE' TOSU EQU H'0FFF' ;----- SSP2CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP2CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP2STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- ECCP2DEL Bits ----------------------------------------------------- P2DC0 EQU H'0000' P2DC1 EQU H'0001' P2DC2 EQU H'0002' P2DC3 EQU H'0003' P2DC4 EQU H'0004' P2DC5 EQU H'0005' P2DC6 EQU H'0006' P2RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP2AS Bits ----------------------------------------------------- PSS2BD0 EQU H'0000' PSS2BD1 EQU H'0001' PSS2AC0 EQU H'0002' PSS2AC1 EQU H'0003' ECCP2AS0 EQU H'0004' ECCP2AS1 EQU H'0005' ECCP2AS2 EQU H'0006' ECCP2ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- ECCP3DEL Bits ----------------------------------------------------- P3DC0 EQU H'0000' P3DC1 EQU H'0001' P3DC2 EQU H'0002' P3DC3 EQU H'0003' P3DC4 EQU H'0004' P3DC5 EQU H'0005' P3DC6 EQU H'0006' P3RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- ECCP3AS Bits ----------------------------------------------------- PSS3BD0 EQU H'0000' PSS3BD1 EQU H'0001' PSS3AC0 EQU H'0002' PSS3AC1 EQU H'0003' ECCP3AS0 EQU H'0004' ECCP3AS1 EQU H'0005' ECCP3AS2 EQU H'0006' ECCP3ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- RCSTA2 Bits ----------------------------------------------------- RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' ;----- TXSTA2 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- CCP5CON Bits ----------------------------------------------------- CCP5M0 EQU H'0000' CCP5M1 EQU H'0001' CCP5M2 EQU H'0002' CCP5M3 EQU H'0003' DCCP5Y EQU H'0004' DCCP5X EQU H'0005' DC5B0 EQU H'0004' DC5B1 EQU H'0005' ;----- CCP4CON Bits ----------------------------------------------------- CCP4M0 EQU H'0000' CCP4M1 EQU H'0001' CCP4M2 EQU H'0002' CCP4M3 EQU H'0003' DCCP4Y EQU H'0004' DCCP4X EQU H'0005' DC4B0 EQU H'0004' DC4B1 EQU H'0005' ;----- T4CON Bits ----------------------------------------------------- T4CKPS0 EQU H'0000' T4CKPS1 EQU H'0001' TMR4ON EQU H'0002' T4OUTPS0 EQU H'0003' T4OUTPS1 EQU H'0004' T4OUTPS2 EQU H'0005' T4OUTPS3 EQU H'0006' ;----- ECCP1DEL Bits ----------------------------------------------------- P1DC0 EQU H'0000' P1DC1 EQU H'0001' P1DC2 EQU H'0002' P1DC3 EQU H'0003' P1DC4 EQU H'0004' P1DC5 EQU H'0005' P1DC6 EQU H'0006' P1RSEN EQU H'0007' PDC0 EQU H'0000' PDC1 EQU H'0001' PDC2 EQU H'0002' PDC3 EQU H'0003' PDC4 EQU H'0004' PDC5 EQU H'0005' PDC6 EQU H'0006' PRSEN EQU H'0007' ;----- BAUDCON2 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- BAUDCON1 Bits ----------------------------------------------------- ABDEN EQU H'0000' WUE EQU H'0001' BRG16 EQU H'0003' SCKP EQU H'0004' RCIDL EQU H'0006' ABDOVF EQU H'0007' RCMT EQU H'0006' ;----- PORTA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' VREFM EQU H'0002' VREFP EQU H'0003' T0CKI EQU H'0004' LVDIN EQU H'0005' AN0 EQU H'0000' AN1 EQU H'0001' AN2 EQU H'0002' AN3 EQU H'0003' AN4 EQU H'0005' HLVDIN EQU H'0005' ;----- PORTB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' INT0 EQU H'0000' INT1 EQU H'0001' INT2 EQU H'0002' INT3 EQU H'0003' KBI0 EQU H'0004' KBI1 EQU H'0005' KBI2 EQU H'0006' KBI3 EQU H'0007' FLT0 EQU H'0000' ECCP2_PORTB EQU H'0003' P2A_PORTB EQU H'0003' CCP2_PORTB EQU H'0003' ;----- PORTC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' T1OSO EQU H'0000' T1OSI EQU H'0001' ECCP1 EQU H'0002' SCK EQU H'0003' SDI EQU H'0004' SDO EQU H'0005' TX EQU H'0006' RX EQU H'0007' T13CKI EQU H'0000' ECCP2_PORTC EQU H'0001' SCL EQU H'0003' SDA EQU H'0004' CK EQU H'0006' ; DT is a reserved word ; DT EQU H'0007' CCP2_PORTC EQU H'0001' CCP1 EQU H'0002' SCL1 EQU H'0003' SDA1 EQU H'0004' CK1 EQU H'0006' DT1 EQU H'0007' P2A_PORTC EQU H'0001' P1A EQU H'0002' SCK1 EQU H'0003' SDI1 EQU H'0004' SDO1 EQU H'0005' TX1 EQU H'0006' RX1 EQU H'0007' ;----- PORTD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' PSP0 EQU H'0000' PSP1 EQU H'0001' PSP2 EQU H'0002' PSP3 EQU H'0003' PSP4 EQU H'0004' PSP5 EQU H'0005' PSP6 EQU H'0006' PSP7 EQU H'0007' AD0 EQU H'0000' AD1 EQU H'0001' AD2 EQU H'0002' AD3 EQU H'0003' AD4 EQU H'0004' AD5 EQU H'0005' AD6 EQU H'0006' AD7 EQU H'0007' SDA2 EQU H'0005' SCL2 EQU H'0006' SS2 EQU H'0007' SDO2 EQU H'0004' SDI2 EQU H'0005' SCK2 EQU H'0006' NOT_SS2 EQU H'0007' ;----- PORTE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' RD EQU H'0000' WR EQU H'0001' CS EQU H'0002' ECCP2_PORTE EQU H'0007' NOT_RD EQU H'0000' NOT_WR EQU H'0001' NOT_CS EQU H'0002' AD8 EQU H'0000' AD9 EQU H'0001' AD10 EQU H'0002' AD11 EQU H'0003' AD12 EQU H'0004' AD13 EQU H'0005' AD14 EQU H'0006' AD15 EQU H'0007' P2D EQU H'0000' P2C EQU H'0001' P2B EQU H'0002' P3C_PORTE EQU H'0003' P3B_PORTE EQU H'0004' P1C_PORTE EQU H'0005' P1B_PORTE EQU H'0006' P2A_PORTE EQU H'0007' CCP2_PORTE EQU H'0007' ;----- PORTF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' AN5 EQU H'0000' AN6 EQU H'0001' AN7 EQU H'0002' AN8 EQU H'0003' AN9 EQU H'0004' AN10 EQU H'0005' AN11 EQU H'0006' SS1 EQU H'0007' C2OUT_PORTF EQU H'0001' C1OUT_PORTF EQU H'0002' CVREF EQU H'0005' NOT_SS1 EQU H'0007' ;----- PORTG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' RG5 EQU H'0005' ECCP3 EQU H'0000' TX2 EQU H'0001' RX2 EQU H'0002' CCP4 EQU H'0003' CCP5 EQU H'0004' MCLR EQU H'0005' P3A EQU H'0000' CK2 EQU H'0001' DT2 EQU H'0002' P3D EQU H'0003' P1D EQU H'0004' NOT_MCLR EQU H'0005' CCP3 EQU H'0000' ;----- PORTH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' A16 EQU H'0000' A17 EQU H'0001' A18 EQU H'0002' A19 EQU H'0003' AN12 EQU H'0004' AN13 EQU H'0005' AN14 EQU H'0006' AN15 EQU H'0007' P3C_PORTH EQU H'0004' P3B_PORTH EQU H'0005' P1C_PORTH EQU H'0006' P1B_PORTH EQU H'0007' ;----- PORTJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ALE EQU H'0000' OE EQU H'0001' WRL EQU H'0002' WRH EQU H'0003' BA0 EQU H'0004' CE EQU H'0005' LB EQU H'0006' UB EQU H'0007' NOT_OE EQU H'0001' NOT_WRL EQU H'0002' NOT_WRH EQU H'0003' NOT_CE EQU H'0005' NOT_LB EQU H'0006' NOT_UB EQU H'0007' ;----- LATA Bits ----------------------------------------------------- LATA0 EQU H'0000' LATA1 EQU H'0001' LATA2 EQU H'0002' LATA3 EQU H'0003' LATA4 EQU H'0004' LATA5 EQU H'0005' LATA6 EQU H'0006' LATA7 EQU H'0007' ;----- LATB Bits ----------------------------------------------------- LATB0 EQU H'0000' LATB1 EQU H'0001' LATB2 EQU H'0002' LATB3 EQU H'0003' LATB4 EQU H'0004' LATB5 EQU H'0005' LATB6 EQU H'0006' LATB7 EQU H'0007' ;----- LATC Bits ----------------------------------------------------- LATC0 EQU H'0000' LATC1 EQU H'0001' LATC2 EQU H'0002' LATC3 EQU H'0003' LATC4 EQU H'0004' LATC5 EQU H'0005' LATC6 EQU H'0006' LATC7 EQU H'0007' ;----- LATD Bits ----------------------------------------------------- LATD0 EQU H'0000' LATD1 EQU H'0001' LATD2 EQU H'0002' LATD3 EQU H'0003' LATD4 EQU H'0004' LATD5 EQU H'0005' LATD6 EQU H'0006' LATD7 EQU H'0007' ;----- LATE Bits ----------------------------------------------------- LATE0 EQU H'0000' LATE1 EQU H'0001' LATE2 EQU H'0002' LATE3 EQU H'0003' LATE4 EQU H'0004' LATE5 EQU H'0005' LATE6 EQU H'0006' LATE7 EQU H'0007' ;----- LATF Bits ----------------------------------------------------- LATF0 EQU H'0000' LATF1 EQU H'0001' LATF2 EQU H'0002' LATF3 EQU H'0003' LATF4 EQU H'0004' LATF5 EQU H'0005' LATF6 EQU H'0006' LATF7 EQU H'0007' ;----- LATG Bits ----------------------------------------------------- LATG0 EQU H'0000' LATG1 EQU H'0001' LATG2 EQU H'0002' LATG3 EQU H'0003' LATG4 EQU H'0004' LATG5 EQU H'0005' ;----- LATH Bits ----------------------------------------------------- LATH0 EQU H'0000' LATH1 EQU H'0001' LATH2 EQU H'0002' LATH3 EQU H'0003' LATH4 EQU H'0004' LATH5 EQU H'0005' LATH6 EQU H'0006' LATH7 EQU H'0007' ;----- LATJ Bits ----------------------------------------------------- LATJ0 EQU H'0000' LATJ1 EQU H'0001' LATJ2 EQU H'0002' LATJ3 EQU H'0003' LATJ4 EQU H'0004' LATJ5 EQU H'0005' LATJ6 EQU H'0006' LATJ7 EQU H'0007' ;----- DDRA Bits ----------------------------------------------------- RA0 EQU H'0000' RA1 EQU H'0001' RA2 EQU H'0002' RA3 EQU H'0003' RA4 EQU H'0004' RA5 EQU H'0005' RA6 EQU H'0006' RA7 EQU H'0007' ;----- TRISA Bits ----------------------------------------------------- TRISA0 EQU H'0000' TRISA1 EQU H'0001' TRISA2 EQU H'0002' TRISA3 EQU H'0003' TRISA4 EQU H'0004' TRISA5 EQU H'0005' TRISA6 EQU H'0006' TRISA7 EQU H'0007' ;----- DDRB Bits ----------------------------------------------------- RB0 EQU H'0000' RB1 EQU H'0001' RB2 EQU H'0002' RB3 EQU H'0003' RB4 EQU H'0004' RB5 EQU H'0005' RB6 EQU H'0006' RB7 EQU H'0007' ;----- TRISB Bits ----------------------------------------------------- TRISB0 EQU H'0000' TRISB1 EQU H'0001' TRISB2 EQU H'0002' TRISB3 EQU H'0003' TRISB4 EQU H'0004' TRISB5 EQU H'0005' TRISB6 EQU H'0006' TRISB7 EQU H'0007' ;----- DDRC Bits ----------------------------------------------------- RC0 EQU H'0000' RC1 EQU H'0001' RC2 EQU H'0002' RC3 EQU H'0003' RC4 EQU H'0004' RC5 EQU H'0005' RC6 EQU H'0006' RC7 EQU H'0007' ;----- TRISC Bits ----------------------------------------------------- TRISC0 EQU H'0000' TRISC1 EQU H'0001' TRISC2 EQU H'0002' TRISC3 EQU H'0003' TRISC4 EQU H'0004' TRISC5 EQU H'0005' TRISC6 EQU H'0006' TRISC7 EQU H'0007' ;----- DDRD Bits ----------------------------------------------------- RD0 EQU H'0000' RD1 EQU H'0001' RD2 EQU H'0002' RD3 EQU H'0003' RD4 EQU H'0004' RD5 EQU H'0005' RD6 EQU H'0006' RD7 EQU H'0007' ;----- TRISD Bits ----------------------------------------------------- TRISD0 EQU H'0000' TRISD1 EQU H'0001' TRISD2 EQU H'0002' TRISD3 EQU H'0003' TRISD4 EQU H'0004' TRISD5 EQU H'0005' TRISD6 EQU H'0006' TRISD7 EQU H'0007' ;----- DDRE Bits ----------------------------------------------------- RE0 EQU H'0000' RE1 EQU H'0001' RE2 EQU H'0002' RE3 EQU H'0003' RE4 EQU H'0004' RE5 EQU H'0005' RE6 EQU H'0006' RE7 EQU H'0007' ;----- TRISE Bits ----------------------------------------------------- TRISE0 EQU H'0000' TRISE1 EQU H'0001' TRISE2 EQU H'0002' TRISE3 EQU H'0003' TRISE4 EQU H'0004' TRISE5 EQU H'0005' TRISE6 EQU H'0006' TRISE7 EQU H'0007' ;----- DDRF Bits ----------------------------------------------------- RF0 EQU H'0000' RF1 EQU H'0001' RF2 EQU H'0002' RF3 EQU H'0003' RF4 EQU H'0004' RF5 EQU H'0005' RF6 EQU H'0006' RF7 EQU H'0007' ;----- TRISF Bits ----------------------------------------------------- TRISF0 EQU H'0000' TRISF1 EQU H'0001' TRISF2 EQU H'0002' TRISF3 EQU H'0003' TRISF4 EQU H'0004' TRISF5 EQU H'0005' TRISF6 EQU H'0006' TRISF7 EQU H'0007' ;----- DDRG Bits ----------------------------------------------------- RG0 EQU H'0000' RG1 EQU H'0001' RG2 EQU H'0002' RG3 EQU H'0003' RG4 EQU H'0004' ;----- TRISG Bits ----------------------------------------------------- TRISG0 EQU H'0000' TRISG1 EQU H'0001' TRISG2 EQU H'0002' TRISG3 EQU H'0003' TRISG4 EQU H'0004' ;----- DDRH Bits ----------------------------------------------------- RH0 EQU H'0000' RH1 EQU H'0001' RH2 EQU H'0002' RH3 EQU H'0003' RH4 EQU H'0004' RH5 EQU H'0005' RH6 EQU H'0006' RH7 EQU H'0007' ;----- TRISH Bits ----------------------------------------------------- TRISH0 EQU H'0000' TRISH1 EQU H'0001' TRISH2 EQU H'0002' TRISH3 EQU H'0003' TRISH4 EQU H'0004' TRISH5 EQU H'0005' TRISH6 EQU H'0006' TRISH7 EQU H'0007' ;----- DDRJ Bits ----------------------------------------------------- RJ0 EQU H'0000' RJ1 EQU H'0001' RJ2 EQU H'0002' RJ3 EQU H'0003' RJ4 EQU H'0004' RJ5 EQU H'0005' RJ6 EQU H'0006' RJ7 EQU H'0007' ;----- TRISJ Bits ----------------------------------------------------- TRISJ0 EQU H'0000' TRISJ1 EQU H'0001' TRISJ2 EQU H'0002' TRISJ3 EQU H'0003' TRISJ4 EQU H'0004' TRISJ5 EQU H'0005' TRISJ6 EQU H'0006' TRISJ7 EQU H'0007' ;----- OSCTUNE Bits ----------------------------------------------------- TUN0 EQU H'0000' TUN1 EQU H'0001' TUN2 EQU H'0002' TUN3 EQU H'0003' TUN4 EQU H'0004' PLLEN EQU H'0006' INTSRC EQU H'0007' ;----- MEMCON Bits ----------------------------------------------------- WM0 EQU H'0000' WM1 EQU H'0001' WAIT0 EQU H'0004' WAIT1 EQU H'0005' EBDIS EQU H'0007' ;----- PIE1 Bits ----------------------------------------------------- TMR1IE EQU H'0000' TMR2IE EQU H'0001' CCP1IE EQU H'0002' SSPIE EQU H'0003' TXIE EQU H'0004' RCIE EQU H'0005' ADIE EQU H'0006' PSPIE EQU H'0007' SSP1IE EQU H'0003' TX1IE EQU H'0004' RC1IE EQU H'0005' ;----- PIR1 Bits ----------------------------------------------------- TMR1IF EQU H'0000' TMR2IF EQU H'0001' CCP1IF EQU H'0002' SSPIF EQU H'0003' TXIF EQU H'0004' RCIF EQU H'0005' ADIF EQU H'0006' PSPIF EQU H'0007' SSP1IF EQU H'0003' TX1IF EQU H'0004' RC1IF EQU H'0005' ;----- IPR1 Bits ----------------------------------------------------- TMR1IP EQU H'0000' TMR2IP EQU H'0001' CCP1IP EQU H'0002' SSPIP EQU H'0003' TXIP EQU H'0004' RCIP EQU H'0005' ADIP EQU H'0006' PSPIP EQU H'0007' SSP1IP EQU H'0003' TX1IP EQU H'0004' RC1IP EQU H'0005' ;----- PIE2 Bits ----------------------------------------------------- CCP2IE EQU H'0000' TMR3IE EQU H'0001' LVDIE EQU H'0002' BCLIE EQU H'0003' EEIE EQU H'0004' CMIE EQU H'0006' OSCFIE EQU H'0007' HLVDIE EQU H'0002' BCL1IE EQU H'0003' ;----- PIR2 Bits ----------------------------------------------------- CCP2IF EQU H'0000' TMR3IF EQU H'0001' LVDIF EQU H'0002' BCLIF EQU H'0003' EEIF EQU H'0004' CMIF EQU H'0006' OSCFIF EQU H'0007' HLVDIF EQU H'0002' BCL1IF EQU H'0003' ;----- IPR2 Bits ----------------------------------------------------- CCP2IP EQU H'0000' TMR3IP EQU H'0001' LVDIP EQU H'0002' BCLIP EQU H'0003' EEIP EQU H'0004' CMIP EQU H'0006' OSCFIP EQU H'0007' HLVDIP EQU H'0002' BCL1IP EQU H'0003' ;----- PIE3 Bits ----------------------------------------------------- CCP3IE EQU H'0000' CCP4IE EQU H'0001' CCP5IE EQU H'0002' TMR4IE EQU H'0003' TX2IE EQU H'0004' RC2IE EQU H'0005' BCL2IE EQU H'0006' SSP2IE EQU H'0007' ;----- PIR3 Bits ----------------------------------------------------- CCP3IF EQU H'0000' CCP4IF EQU H'0001' CCP5IF EQU H'0002' TMR4IF EQU H'0003' TX2IF EQU H'0004' RC2IF EQU H'0005' BCL2IF EQU H'0006' SSP2IF EQU H'0007' ;----- IPR3 Bits ----------------------------------------------------- CCP3IP EQU H'0000' CCP4IP EQU H'0001' CCP5IP EQU H'0002' TMR4IP EQU H'0003' TX2IP EQU H'0004' RC2IP EQU H'0005' BCL2IP EQU H'0006' SSP2IP EQU H'0007' ;----- EECON1 Bits ----------------------------------------------------- RD EQU H'0000' WR EQU H'0001' WREN EQU H'0002' WRERR EQU H'0003' FREE EQU H'0004' CFGS EQU H'0006' EEPGD EQU H'0007' ;----- RCSTA Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- RCSTA1 Bits ----------------------------------------------------- RX9D EQU H'0000' OERR EQU H'0001' FERR EQU H'0002' ADDEN EQU H'0003' CREN EQU H'0004' SREN EQU H'0005' RX9 EQU H'0006' SPEN EQU H'0007' RCD8 EQU H'0000' RC9 EQU H'0006' NOT_RC8 EQU H'0006' RC8_9 EQU H'0006' ;----- TXSTA Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- TXSTA1 Bits ----------------------------------------------------- TX9D EQU H'0000' TRMT EQU H'0001' BRGH EQU H'0002' SENDB EQU H'0003' SYNC EQU H'0004' TXEN EQU H'0005' TX9 EQU H'0006' CSRC EQU H'0007' TXD8 EQU H'0000' TX8_9 EQU H'0006' NOT_TX8 EQU H'0006' ;----- PSPCON Bits ----------------------------------------------------- PSPMODE EQU H'0004' IBOV EQU H'0005' OBF EQU H'0006' IBF EQU H'0007' ;----- T3CON Bits ----------------------------------------------------- TMR3ON EQU H'0000' TMR3CS EQU H'0001' T3SYNC EQU H'0002' T3CCP1 EQU H'0003' T3CKPS0 EQU H'0004' T3CKPS1 EQU H'0005' T3CCP2 EQU H'0006' RD16 EQU H'0007' T3INSYNC EQU H'0002' NOT_T3SYNC EQU H'0002' ;----- CMCON Bits ----------------------------------------------------- CM0 EQU H'0000' CM1 EQU H'0001' CM2 EQU H'0002' CIS EQU H'0003' C1INV EQU H'0004' C2INV EQU H'0005' C1OUT_CMCON EQU H'0006' C2OUT_CMCON EQU H'0007' ;----- CVRCON Bits ----------------------------------------------------- CVR0 EQU H'0000' CVR1 EQU H'0001' CVR2 EQU H'0002' CVR3 EQU H'0003' CVRSS EQU H'0004' CVRR EQU H'0005' CVROE EQU H'0006' CVREN EQU H'0007' ;----- ECCP1AS Bits ----------------------------------------------------- PSS1BD0 EQU H'0000' PSS1BD1 EQU H'0001' PSS1AC0 EQU H'0002' PSS1AC1 EQU H'0003' ECCP1AS0 EQU H'0004' ECCP1AS1 EQU H'0005' ECCP1AS2 EQU H'0006' ECCP1ASE EQU H'0007' PSSBD0 EQU H'0000' PSSBD1 EQU H'0001' PSSAC0 EQU H'0002' PSSAC1 EQU H'0003' ECCPAS0 EQU H'0004' ECCPAS1 EQU H'0005' ECCPAS2 EQU H'0006' ECCPASE EQU H'0007' ;----- CCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- ECCP3CON Bits ----------------------------------------------------- CCP3M0 EQU H'0000' CCP3M1 EQU H'0001' CCP3M2 EQU H'0002' CCP3M3 EQU H'0003' DC3B0 EQU H'0004' DC3B1 EQU H'0005' P3M0 EQU H'0006' P3M1 EQU H'0007' CCP3Y EQU H'0004' CCP3X EQU H'0005' ;----- CCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- ECCP2CON Bits ----------------------------------------------------- CCP2M0 EQU H'0000' CCP2M1 EQU H'0001' CCP2M2 EQU H'0002' CCP2M3 EQU H'0003' DC2B0 EQU H'0004' DC2B1 EQU H'0005' P2M0 EQU H'0006' P2M1 EQU H'0007' CCP2Y EQU H'0004' CCP2X EQU H'0005' ;----- CCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ECCP1CON Bits ----------------------------------------------------- CCP1M0 EQU H'0000' CCP1M1 EQU H'0001' CCP1M2 EQU H'0002' CCP1M3 EQU H'0003' DC1B0 EQU H'0004' DC1B1 EQU H'0005' P1M0 EQU H'0006' P1M1 EQU H'0007' CCP1Y EQU H'0004' CCP1X EQU H'0005' ;----- ADCON2 Bits ----------------------------------------------------- ADCS0 EQU H'0000' ADCS1 EQU H'0001' ADCS2 EQU H'0002' ACQT0 EQU H'0003' ACQT1 EQU H'0004' ACQT2 EQU H'0005' ADFM EQU H'0007' ;----- ADCON1 Bits ----------------------------------------------------- PCFG0 EQU H'0000' PCFG1 EQU H'0001' PCFG2 EQU H'0002' PCFG3 EQU H'0003' VCFG0 EQU H'0004' VCFG1 EQU H'0005' ;----- ADCON0 Bits ----------------------------------------------------- DONE EQU H'0001' GO_DONE EQU H'0001' ADON EQU H'0000' GO EQU H'0001' CHS0 EQU H'0002' CHS1 EQU H'0003' CHS2 EQU H'0004' CHS3 EQU H'0005' NOT_DONE EQU H'0001' ;----- SSP1CON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSPCON2 Bits ----------------------------------------------------- SEN EQU H'0000' RSEN EQU H'0001' PEN EQU H'0002' RCEN EQU H'0003' ACKEN EQU H'0004' ACKDT EQU H'0005' ACKSTAT EQU H'0006' GCEN EQU H'0007' ;----- SSP1CON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSPCON1 Bits ----------------------------------------------------- SSPM0 EQU H'0000' SSPM1 EQU H'0001' SSPM2 EQU H'0002' SSPM3 EQU H'0003' CKP EQU H'0004' SSPEN EQU H'0005' SSPOV EQU H'0006' WCOL EQU H'0007' ;----- SSP1STAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- SSPSTAT Bits ----------------------------------------------------- BF EQU H'0000' UA EQU H'0001' R_W EQU H'0002' S EQU H'0003' P EQU H'0004' D_A EQU H'0005' CKE EQU H'0006' SMP EQU H'0007' I2C_READ EQU H'0002' I2C_START EQU H'0003' I2C_STOP EQU H'0004' I2C_DAT EQU H'0005' NOT_W EQU H'0002' NOT_A EQU H'0005' NOT_WRITE EQU H'0002' NOT_ADDRESS EQU H'0005' READ_WRITE EQU H'0002' DATA_ADDRESS EQU H'0005' R EQU H'0002' D EQU H'0005' ;----- T2CON Bits ----------------------------------------------------- T2CKPS0 EQU H'0000' T2CKPS1 EQU H'0001' TMR2ON EQU H'0002' T2OUTPS0 EQU H'0003' T2OUTPS1 EQU H'0004' T2OUTPS2 EQU H'0005' T2OUTPS3 EQU H'0006' ;----- T1CON Bits ----------------------------------------------------- TMR1ON EQU H'0000' TMR1CS EQU H'0001' T1SYNC EQU H'0002' T1OSCEN EQU H'0003' T1CKPS0 EQU H'0004' T1CKPS1 EQU H'0005' T1RUN EQU H'0006' RD16 EQU H'0007' T1INSYNC EQU H'0002' NOT_T1SYNC EQU H'0002' ;----- RCON Bits ----------------------------------------------------- NOT_BOR EQU H'0000' NOT_POR EQU H'0001' NOT_PD EQU H'0002' NOT_TO EQU H'0003' NOT_RI EQU H'0004' SBOREN EQU H'0006' IPEN EQU H'0007' BOR EQU H'0000' POR EQU H'0001' PD EQU H'0002' TO EQU H'0003' RI EQU H'0004' ;----- WDTCON Bits ----------------------------------------------------- SWDTE EQU H'0000' SWDTEN EQU H'0000' ;----- HLVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- LVDCON Bits ----------------------------------------------------- LVDL0 EQU H'0000' LVDL1 EQU H'0001' LVDL2 EQU H'0002' LVDL3 EQU H'0003' LVDEN EQU H'0004' IRVST EQU H'0005' LVV0 EQU H'0000' LVV1 EQU H'0001' LVV2 EQU H'0002' LVV3 EQU H'0003' BGST EQU H'0005' HLVDL0 EQU H'0000' HLVDL1 EQU H'0001' HLVDL2 EQU H'0002' HLVDL3 EQU H'0003' HLVDEN EQU H'0004' VDIRMAG EQU H'0007' IVRST EQU H'0005' ;----- OSCCON Bits ----------------------------------------------------- SCS0 EQU H'0000' SCS1 EQU H'0001' IOFS EQU H'0002' OSTS EQU H'0003' IRCF0 EQU H'0004' IRCF1 EQU H'0005' IRCF2 EQU H'0006' IDLEN EQU H'0007' FLTS EQU H'0002' ;----- T0CON Bits ----------------------------------------------------- T0PS0 EQU H'0000' T0PS1 EQU H'0001' T0PS2 EQU H'0002' PSA EQU H'0003' T0SE EQU H'0004' T0CS EQU H'0005' T08BIT EQU H'0006' TMR0ON EQU H'0007' T0PS3 EQU H'0003' ;----- STATUS Bits ----------------------------------------------------- C EQU H'0000' DC EQU H'0001' Z EQU H'0002' OV EQU H'0003' N EQU H'0004' ;----- INTCON3 Bits ----------------------------------------------------- INT1F EQU H'0000' INT2F EQU H'0001' INT3F EQU H'0002' INT1E EQU H'0003' INT2E EQU H'0004' INT3E EQU H'0005' INT1P EQU H'0006' INT2P EQU H'0007' INT1IF EQU H'0000' INT2IF EQU H'0001' INT3IF EQU H'0002' INT1IE EQU H'0003' INT2IE EQU H'0004' INT3IE EQU H'0005' INT1IP EQU H'0006' INT2IP EQU H'0007' ;----- INTCON2 Bits ----------------------------------------------------- RBIP EQU H'0000' INT3P EQU H'0001' T0IP EQU H'0002' INTEDG3 EQU H'0003' INTEDG2 EQU H'0004' INTEDG1 EQU H'0005' INTEDG0 EQU H'0006' NOT_RBPU EQU H'0007' INT3IP EQU H'0001' TMR0IP EQU H'0002' RBPU EQU H'0007' ;----- INTCON Bits ----------------------------------------------------- RBIF EQU H'0000' INT0F EQU H'0001' T0IF EQU H'0002' RBIE EQU H'0003' INT0E EQU H'0004' T0IE EQU H'0005' PEIE EQU H'0006' GIE EQU H'0007' INT0IF EQU H'0001' TMR0IF EQU H'0002' INT0IE EQU H'0004' TMR0IE EQU H'0005' GIEL EQU H'0006' GIEH EQU H'0007' ;----- STKPTR Bits ----------------------------------------------------- STKPTR0 EQU H'0000' STKPTR1 EQU H'0001' STKPTR2 EQU H'0002' STKPTR3 EQU H'0003' STKPTR4 EQU H'0004' STKUNF EQU H'0006' STKFUL EQU H'0007' SP0 EQU H'0000' SP1 EQU H'0001' SP2 EQU H'0002' SP3 EQU H'0003' SP4 EQU H'0004' STKOVF EQU H'0007' ;========================================================================== ; ; RAM Definitions ; ;========================================================================== __MAXRAM H'0FFF' __BADRAM H'0F7A'-H'0F7B' __BADRAM H'0FD4' ;========================================================================== ; ; IMPORTANT: For the PIC18 devices, the __CONFIG directive has been ; superseded by the CONFIG directive. The following settings ; are available for this device. ; ; Oscillator Selection bits: ; OSC = LP LP oscillator ; OSC = XT XT oscillator ; OSC = HS HS oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO6 EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO6 External RC oscillator, port function on RA6 ; OSC = INTIO67 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO7 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Two-Speed Start-up disabled ; IESO = ON Two-Speed Start-up enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOREN = OFF Brown-out Reset disabled in hardware and software ; BOREN = ON Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOREN = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOREN = SBORDIS Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Voltage bits: ; BORV = 0 Maximum setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; Processor Data Memory Mode Select bits: ; MODE = EM Extended Microcontroller mode ; MODE = MPB Microprocessor with Boot Block mode ; MODE = MP Microprocessor mode ; MODE = MC Microcontroller mode ; ; Address Bus Width Select bits: ; ADDRBW = ADDR8BIT 8-bit Address Bus ; ADDRBW = ADDR12BIT 12-bit Address Bus ; ADDRBW = ADDR16BIT 16-bit Address Bus ; ADDRBW = ADDR20BIT 20-bit Address Bus ; ; Data Bus Width Select bit: ; DATABW = DATA8BIT 8-bit External Bus mode ; DATABW = DATA16BIT 16-bit External Bus mode ; ; External Bus Data Wait Enable bit: ; WAIT = ON Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits ; WAIT = OFF Wait selections are unavailable for table reads and table writes ; ; MCLR Pin Enable bit: ; MCLRE = OFF RG5 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RG5 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; ECCP MUX bit: ; ECCPMX = PORTH ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively ; ECCPMX = PORTE ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively ; ; CCP2 MUX bit: ; CCP2MX = PORTBE ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. ; CCP2MX = PORTC ECCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB2K 1K word (2 Kbytes) Boot Block size ; BBSIZ = BB4K 2K words (4 Kbytes) Boot Block size ; BBSIZ = BB8K 4K words (8 Kbytes) Boot Block size ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 (000800, 001000 or 002000-003FFFh) code-protected ; CP0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 (004000-007FFFh) code-protected ; CP1 = OFF Block 1 (004000-007FFFh) not code-protected ; ; Code Protection bit Block 2: ; CP2 = ON Block 2 (008000-00BFFFh) code-protected ; CP2 = OFF Block 2 (008000-00BFFFh) not code-protected ; ; Code Protection bit Block 3: ; CP3 = ON Block 3 (00C000-00FFFFh) code-protected ; CP3 = OFF Block 3 (00C000-00FFFFh) not code-protected ; ; Code Protection bit Block 4: ; CP4 = ON Block 4 (010000-013FFFh) code-protected ; CP4 = OFF Block 4 (010000-013FFFh) not code-protected ; ; Code Protection bit Block 5: ; CP5 = ON Block 5 (014000-017FFFh) code-protected ; CP5 = OFF Block 5 (014000-017FFFh) not code-protected ; ; Code Protection bit Block 6: ; CP6 = ON Block 6 (01BFFF-018000h) code-protected ; CP6 = OFF Block 6 (01BFFF-018000h) not code-protected ; ; Code Protection bit Block 7: ; CP7 = ON Block 7 (01C000-01FFFFh) code-protected ; CP7 = OFF Block 7 (01C000-01FFFFh) not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot Block (000000-0007FFh) code-protected ; CPB = OFF Boot Block (000000-0007FFh) not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 (000800, 001000 or 002000-003FFFh) write-protected ; WRT0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 (004000-007FFFh) write-protected ; WRT1 = OFF Block 1 (004000-007FFFh) not write-protected ; ; Write Protection bit Block 2: ; WRT2 = ON Block 2 (008000-00BFFFh) write-protected ; WRT2 = OFF Block 2 (008000-00BFFFh) not write-protected ; ; Write Protection bit Block 3: ; WRT3 = ON Block 3 (00C000-00FFFFh) write-protected ; WRT3 = OFF Block 3 (00C000-00FFFFh) not write-protected ; ; Write Protection bit Block 4: ; WRT4 = ON Block 4 (010000-013FFFh) write-protected ; WRT4 = OFF Block 4 (010000-013FFFh) not write-protected ; ; Write Protection bit Block 5: ; WRT5 = ON Block 5 (014000-017FFFh) write-protected ; WRT5 = OFF Block 5 (014000-017FFFh) not write-protected ; ; Write Protection bit Block 6: ; WRT6 = ON Block 6 (01BFFF-018000h) write-protected ; WRT6 = OFF Block 6 (01BFFF-018000h) not write-protected ; ; Write Protection bit Block 7: ; WRT7 = ON Block 7 (01C000-01FFFFh) write-protected ; WRT7 = OFF Block 7 (01C000-01FFFFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected ; WRTB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 (004000-007FFFh) protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 (004000-007FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 2: ; EBTR2 = ON Block 2 (008000-00BFFFh) protected from table reads executed in other blocks ; EBTR2 = OFF Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 3: ; EBTR3 = ON Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks ; EBTR3 = OFF Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 4: ; EBTR4 = ON Block 4 (010000-013FFFh) protected from table reads executed in other blocks ; EBTR4 = OFF Block 4 (010000-013FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 5: ; EBTR5 = ON Block 5 (014000-017FFFh) protected from table reads executed in other blocks ; EBTR5 = OFF Block 5 (014000-017FFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 6: ; EBTR6 = ON Block 6 (018000-01BFFFh) protected from table reads executed in other blocks ; EBTR6 = OFF Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 7: ; EBTR7 = ON Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks ; EBTR7 = OFF Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks ; EBTRB = OFF Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks ; ;========================================================================== ;========================================================================== ; ; Configuration Bits ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3L 300004h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;========================================================================== ; The following is an assignment of address values for all of the ; configuration registers for the purpose of table reads _CONFIG1H EQU H'300001' _CONFIG2L EQU H'300002' _CONFIG2H EQU H'300003' _CONFIG3L EQU H'300004' _CONFIG3H EQU H'300005' _CONFIG4L EQU H'300006' _CONFIG5L EQU H'300008' _CONFIG5H EQU H'300009' _CONFIG6L EQU H'30000A' _CONFIG6H EQU H'30000B' _CONFIG7L EQU H'30000C' _CONFIG7H EQU H'30000D' ;----- CONFIG1H Options -------------------------------------------------- _OSC_LP_1H EQU H'F0' ; LP oscillator _OSC_XT_1H EQU H'F1' ; XT oscillator _OSC_HS_1H EQU H'F2' ; HS oscillator _OSC_RC_1H EQU H'F3' ; External RC oscillator, CLKO function on RA6 _OSC_EC_1H EQU H'F4' ; EC oscillator, CLKO function on RA6 _OSC_ECIO6_1H EQU H'F5' ; EC oscillator, port function on RA6 _OSC_HSPLL_1H EQU H'F6' ; HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) _OSC_RCIO6_1H EQU H'F7' ; External RC oscillator, port function on RA6 _OSC_INTIO67_1H EQU H'F8' ; Internal oscillator block, port function on RA6 and RA7 _OSC_INTIO7_1H EQU H'F9' ; Internal oscillator block, CLKO function on RA6, port function on RA7 _FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled _FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled _IESO_OFF_1H EQU H'7F' ; Two-Speed Start-up disabled _IESO_ON_1H EQU H'FF' ; Two-Speed Start-up enabled ;----- CONFIG2L Options -------------------------------------------------- _PWRT_ON_2L EQU H'FE' ; PWRT enabled _PWRT_OFF_2L EQU H'FF' ; PWRT disabled _BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software _BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled) _BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) _BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled) _BORV_0_2L EQU H'E7' ; Maximum setting _BORV_1_2L EQU H'EF' ; _BORV_2_2L EQU H'F7' ; _BORV_3_2L EQU H'FF' ; Minimum setting ;----- CONFIG2H Options -------------------------------------------------- _WDT_OFF_2H EQU H'FE' ; WDT disabled (control is placed on the SWDTEN bit) _WDT_ON_2H EQU H'FF' ; WDT enabled _WDTPS_1_2H EQU H'E1' ; 1:1 _WDTPS_2_2H EQU H'E3' ; 1:2 _WDTPS_4_2H EQU H'E5' ; 1:4 _WDTPS_8_2H EQU H'E7' ; 1:8 _WDTPS_16_2H EQU H'E9' ; 1:16 _WDTPS_32_2H EQU H'EB' ; 1:32 _WDTPS_64_2H EQU H'ED' ; 1:64 _WDTPS_128_2H EQU H'EF' ; 1:128 _WDTPS_256_2H EQU H'F1' ; 1:256 _WDTPS_512_2H EQU H'F3' ; 1:512 _WDTPS_1024_2H EQU H'F5' ; 1:1024 _WDTPS_2048_2H EQU H'F7' ; 1:2048 _WDTPS_4096_2H EQU H'F9' ; 1:4096 _WDTPS_8192_2H EQU H'FB' ; 1:8192 _WDTPS_16384_2H EQU H'FD' ; 1:16384 _WDTPS_32768_2H EQU H'FF' ; 1:32768 ;----- CONFIG3L Options -------------------------------------------------- _MODE_EM_3L EQU H'FC' ; Extended Microcontroller mode _MODE_MPB_3L EQU H'FD' ; Microprocessor with Boot Block mode _MODE_MP_3L EQU H'FE' ; Microprocessor mode _MODE_MC_3L EQU H'FF' ; Microcontroller mode _ADDRBW_ADDR8BIT_3L EQU H'CF' ; 8-bit Address Bus _ADDRBW_ADDR12BIT_3L EQU H'DF' ; 12-bit Address Bus _ADDRBW_ADDR16BIT_3L EQU H'EF' ; 16-bit Address Bus _ADDRBW_ADDR20BIT_3L EQU H'FF' ; 20-bit Address Bus _DATABW_DATA8BIT_3L EQU H'BF' ; 8-bit External Bus mode _DATABW_DATA16BIT_3L EQU H'FF' ; 16-bit External Bus mode _WAIT_ON_3L EQU H'7F' ; Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits _WAIT_OFF_3L EQU H'FF' ; Wait selections are unavailable for table reads and table writes ;----- CONFIG3H Options -------------------------------------------------- _MCLRE_OFF_3H EQU H'7F' ; RG5 input pin enabled; MCLR disabled _MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RG5 input pin disabled _LPT1OSC_OFF_3H EQU H'FB' ; Timer1 configured for higher power operation _LPT1OSC_ON_3H EQU H'FF' ; Timer1 configured for low-power operation _ECCPMX_PORTH_3H EQU H'FD' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RH7, RH6, RH5 and RH4 respectively _ECCPMX_PORTE_3H EQU H'FF' ; ECCP1/3 (P1B/P1C/P3B/P3C) are multiplexed onto RE6, RE5, RE4 and RE3 respectively _CCP2MX_PORTBE_3H EQU H'FE' ; ECCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode. _CCP2MX_PORTC_3H EQU H'FF' ; ECCP2 input/output is multiplexed with RC1 ;----- CONFIG4L Options -------------------------------------------------- _STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset _STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset _LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled _LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled _BBSIZ_BB2K_4L EQU H'CF' ; 1K word (2 Kbytes) Boot Block size _BBSIZ_BB4K_4L EQU H'DF' ; 2K words (4 Kbytes) Boot Block size _BBSIZ_BB8K_4L EQU H'FF' ; 4K words (8 Kbytes) Boot Block size _XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) _XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled _DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug _DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ;----- CONFIG5L Options -------------------------------------------------- _CP0_ON_5L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) code-protected _CP0_OFF_5L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not code-protected _CP1_ON_5L EQU H'FD' ; Block 1 (004000-007FFFh) code-protected _CP1_OFF_5L EQU H'FF' ; Block 1 (004000-007FFFh) not code-protected _CP2_ON_5L EQU H'FB' ; Block 2 (008000-00BFFFh) code-protected _CP2_OFF_5L EQU H'FF' ; Block 2 (008000-00BFFFh) not code-protected _CP3_ON_5L EQU H'F7' ; Block 3 (00C000-00FFFFh) code-protected _CP3_OFF_5L EQU H'FF' ; Block 3 (00C000-00FFFFh) not code-protected _CP4_ON_5L EQU H'EF' ; Block 4 (010000-013FFFh) code-protected _CP4_OFF_5L EQU H'FF' ; Block 4 (010000-013FFFh) not code-protected _CP5_ON_5L EQU H'DF' ; Block 5 (014000-017FFFh) code-protected _CP5_OFF_5L EQU H'FF' ; Block 5 (014000-017FFFh) not code-protected _CP6_ON_5L EQU H'BF' ; Block 6 (01BFFF-018000h) code-protected _CP6_OFF_5L EQU H'FF' ; Block 6 (01BFFF-018000h) not code-protected _CP7_ON_5L EQU H'7F' ; Block 7 (01C000-01FFFFh) code-protected _CP7_OFF_5L EQU H'FF' ; Block 7 (01C000-01FFFFh) not code-protected ;----- CONFIG5H Options -------------------------------------------------- _CPB_ON_5H EQU H'BF' ; Boot Block (000000-0007FFh) code-protected _CPB_OFF_5H EQU H'FF' ; Boot Block (000000-0007FFh) not code-protected _CPD_ON_5H EQU H'7F' ; Data EEPROM code-protected _CPD_OFF_5H EQU H'FF' ; Data EEPROM not code-protected ;----- CONFIG6L Options -------------------------------------------------- _WRT0_ON_6L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) write-protected _WRT0_OFF_6L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not write-protected _WRT1_ON_6L EQU H'FD' ; Block 1 (004000-007FFFh) write-protected _WRT1_OFF_6L EQU H'FF' ; Block 1 (004000-007FFFh) not write-protected _WRT2_ON_6L EQU H'FB' ; Block 2 (008000-00BFFFh) write-protected _WRT2_OFF_6L EQU H'FF' ; Block 2 (008000-00BFFFh) not write-protected _WRT3_ON_6L EQU H'F7' ; Block 3 (00C000-00FFFFh) write-protected _WRT3_OFF_6L EQU H'FF' ; Block 3 (00C000-00FFFFh) not write-protected _WRT4_ON_6L EQU H'EF' ; Block 4 (010000-013FFFh) write-protected _WRT4_OFF_6L EQU H'FF' ; Block 4 (010000-013FFFh) not write-protected _WRT5_ON_6L EQU H'DF' ; Block 5 (014000-017FFFh) write-protected _WRT5_OFF_6L EQU H'FF' ; Block 5 (014000-017FFFh) not write-protected _WRT6_ON_6L EQU H'BF' ; Block 6 (01BFFF-018000h) write-protected _WRT6_OFF_6L EQU H'FF' ; Block 6 (01BFFF-018000h) not write-protected _WRT7_ON_6L EQU H'7F' ; Block 7 (01C000-01FFFFh) write-protected _WRT7_OFF_6L EQU H'FF' ; Block 7 (01C000-01FFFFh) not write-protected ;----- CONFIG6H Options -------------------------------------------------- _WRTB_ON_6H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) write-protected _WRTB_OFF_6H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not write-protected _WRTC_ON_6H EQU H'DF' ; Configuration registers (300000-3000FFh) write-protected _WRTC_OFF_6H EQU H'FF' ; Configuration registers (300000-3000FFh) not write-protected _WRTD_ON_6H EQU H'7F' ; Data EEPROM write-protected _WRTD_OFF_6H EQU H'FF' ; Data EEPROM not write-protected ;----- CONFIG7L Options -------------------------------------------------- _EBTR0_ON_7L EQU H'FE' ; Block 0 (000800, 001000 or 002000-003FFFh) protected from table reads executed in other blocks _EBTR0_OFF_7L EQU H'FF' ; Block 0 (000800, 001000 or 002000-003FFFh) not protected from table reads executed in other blocks _EBTR1_ON_7L EQU H'FD' ; Block 1 (004000-007FFFh) protected from table reads executed in other blocks _EBTR1_OFF_7L EQU H'FF' ; Block 1 (004000-007FFFh) not protected from table reads executed in other blocks _EBTR2_ON_7L EQU H'FB' ; Block 2 (008000-00BFFFh) protected from table reads executed in other blocks _EBTR2_OFF_7L EQU H'FF' ; Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks _EBTR3_ON_7L EQU H'F7' ; Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks _EBTR3_OFF_7L EQU H'FF' ; Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks _EBTR4_ON_7L EQU H'EF' ; Block 4 (010000-013FFFh) protected from table reads executed in other blocks _EBTR4_OFF_7L EQU H'FF' ; Block 4 (010000-013FFFh) not protected from table reads executed in other blocks _EBTR5_ON_7L EQU H'DF' ; Block 5 (014000-017FFFh) protected from table reads executed in other blocks _EBTR5_OFF_7L EQU H'FF' ; Block 5 (014000-017FFFh) not protected from table reads executed in other blocks _EBTR6_ON_7L EQU H'BF' ; Block 6 (018000-01BFFFh) protected from table reads executed in other blocks _EBTR6_OFF_7L EQU H'FF' ; Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks _EBTR7_ON_7L EQU H'7F' ; Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks _EBTR7_OFF_7L EQU H'FF' ; Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks ;----- CONFIG7H Options -------------------------------------------------- _EBTRB_ON_7H EQU H'BF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) protected from table reads executed in other blocks _EBTRB_OFF_7H EQU H'FF' ; Boot Block (000000-007FFF, 000FFF or 001FFFh) not protected from table reads executed in other blocks _DEVID1 EQU H'3FFFFE' _DEVID2 EQU H'3FFFFF' _IDLOC0 EQU H'200000' _IDLOC1 EQU H'200001' _IDLOC2 EQU H'200002' _IDLOC3 EQU H'200003' _IDLOC4 EQU H'200004' _IDLOC5 EQU H'200005' _IDLOC6 EQU H'200006' _IDLOC7 EQU H'200007' LIST gputils-0.13.7/header/header_check.c0000644000175000017500000000224211156313161014171 00000000000000/* test for common problems in the header files Copyright (C) 2004 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" int main(int argc, char *argv[]) { FILE *f; if (argc != 2) { printf("usage: header_check filename\n"); return 1; } f = fopen(argv[1], "r"); if (f == NULL) { perror(argv[1]); return 1; } fseek(f, -1, SEEK_END); if (fgetc(f) != '\n') { printf("Missing newline before EOF in file \"%s\"\n", argv[1]); return 1; } return 0; } gputils-0.13.7/AUTHORS0000644000175000017500000000115011156521302011253 00000000000000The following people are gputils authors and contributors: James Bowman Craig Franklin Scott Dattalo James Cameron Stefan Petersen Eric Smith Alessandro Zummo Andrew Burgess Bruce Stough Tommy Thorn Charlie Krauter Carlos Nieves Salvador Tropea Marko Kohtala Have you been overlooked? gputils-0.13.7/libgputils/0000777000175000017500000000000011156521335012456 500000000000000gputils-0.13.7/libgputils/gpcod.h0000644000175000017500000002011411156313233013631 00000000000000/* .cod file support Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPCOD_H__ #define __GPCOD_H__ /* * .cod definitions * * A .cod file consists of an array of 512 byte blocks. There are two types * of blocks: a "directory" block and a "data" block. The directory block * describes the miscellaneous stuff like the compiler, the date, copy right * and it also describes the type of information that's available in the .cod * file. The "type of information" is specified by a range of blocks. For * example, if there are symbols in the .cod file then the directory block * tells the starting and ending blocks that contain the symbols. * * Types of data blocks: * short symbol table - a list of symbols in the "short format", which * means that the symbol name is restricted to 12 characters. This * is an old format and is not provided by gpasm. * long symbol table - a list of symbols in the "long format". Like the * short symbol table except the symbol names can be up to 255 chars. * list table - a cross reference between the source line numbers, list * line numbers, and the program memory. * Memory map table - describes the ranges of memory used in the processor. * Local variables table - [c files - not supported by gpasm] this describes * the memory locations used by functions. * Source file names - a list of the files used to assemble the source file. * Debug messages - [not supported by gpasm] this provides a list of messages * that can control the simulator or emulator. */ #define COD_BLOCK_BITS 9 /* COD_BLOCK_SIZE = 2^COD_BLOCK_BITS */ /* number of bytes in one cod block */ #define COD_BLOCK_SIZE (1<next; while (archive != NULL) { number++; archive = archive->next; } return number; } /* This function is unused */ char * gp_archive_member_name(gp_archive_type *archive) { char name[256]; char *end; sscanf(archive->header.ar_name, "%255s/", name); end = strchr(&name[0], '/'); if (end != NULL) *end = '\0'; return strdup(name); } void gp_archive_list_members(gp_archive_type *archive) { const char *format = "%-24s %06i bytes %s"; char name[256]; char *end; int date; time_t time; int size; /* If present, skip the symbol index. */ if (gp_archive_have_index(archive)) archive = archive->next; while (archive != NULL) { sscanf(archive->header.ar_name, "%255s/", name); sscanf(archive->header.ar_date, "%il", &date); sscanf(archive->header.ar_size, "%il", &size); end = strchr(&name[0], '/'); if (end != NULL) *end = '\0'; time = date; printf(format, name, size, ctime(&time)); archive = archive->next; } return; } gp_archive_type * gp_archive_find_member(gp_archive_type *archive, char *objectname) { char name[256]; char *end; gp_archive_type *found = NULL; /* If present, skip the symbol index. */ if (gp_archive_have_index(archive)) archive = archive->next; while (archive != NULL) { sscanf(archive->header.ar_name, "%255s/", name); end = strrchr(&name[0], '/'); if (end != NULL) *end = '\0'; if (strcmp(objectname, name) == 0) { found = archive; break; } archive = archive->next; } return found; } int gp_archive_free_member(gp_archive_type *archive) { if (archive->file != NULL) free(archive->file); if (archive != NULL) free(archive); return 0; } gp_archive_type * gp_archive_delete_member(gp_archive_type *archive, char *objectname) { gp_archive_type *object = NULL; gp_archive_type *list = NULL; object = gp_archive_find_member(archive, objectname); assert(object != NULL); if (object == archive) { /* the first object in the list is being deleted */ archive = archive->next; } else { /* locate and remove the member */ list = archive; while (list != NULL) { if (list->next == object) { list->next = object->next; break; } list = list->next; } } gp_archive_free_member(object); return archive; } gp_archive_type * gp_archive_add_member(gp_archive_type *archive, char *filename, char *objectname) { gp_archive_type *oldmember = NULL; gp_archive_type *newmember = NULL; gp_archive_type *list = NULL; gp_binary_type *newobject = NULL; char name[256]; char date[12]; char size[10]; int timer; newobject = gp_read_file(filename); newmember = (gp_archive_type *)malloc(sizeof(*newmember)); newmember->next = NULL; /* Point the archive member file to the object file. The object is never freed, so this is ok. It will be cleaned up later */ newmember->file = newobject->file; /* fill in the archive header */ memset(&newmember->header, 0x20, AR_HDR_SIZ); /* fill the header with space */ timer = (int)time(NULL); snprintf(name, sizeof(name), "%s/", objectname); snprintf(date, sizeof(date), "%il", timer); snprintf(size, sizeof(size), "%lil", newobject->size); /* FIXME: These functions overwrite the 0x20 that the header is filled with. */ strncpy(newmember->header.ar_name, &name[0], sizeof(newmember->header.ar_name)); strncpy(newmember->header.ar_date, &date[0], sizeof(newmember->header.ar_date)); strncpy(newmember->header.ar_size, &size[0], sizeof(newmember->header.ar_size)); strncpy(newmember->header.ar_fmag, ARMAG, sizeof(newmember->header.ar_fmag)); oldmember = gp_archive_find_member(archive, objectname); if (oldmember != NULL) { /* the object already exists, replace it */ archive = gp_archive_delete_member(archive, objectname); } if (archive == NULL) { /* the list is empty */ archive = newmember; } else { /* append the new object to the end of the list */ list = archive; while (list->next != NULL) { list = list->next; } list->next = newmember; } return archive; } int gp_archive_extract_member(gp_archive_type *archive, char *objectname) { gp_archive_type *object = NULL; char filename[256]; FILE *output_file; int size; object = gp_archive_find_member(archive, objectname); assert(object != NULL); /* if the object doesn't have an extension, add one. This is done for some libs generated with other tools. It should not be necessary for libs generated by gplib. */ strncpy(filename, objectname, sizeof(filename)); if (strrchr(filename, '.') == NULL) strncat(filename, ".o", sizeof(filename)); output_file = fopen(filename, "wb"); if (output_file == NULL) { perror(filename); exit(1); } sscanf(object->header.ar_size, "%il", &size); fwrite(object->file, 1, size, output_file); fclose(output_file); /* FIXME: put the proper date on the output file */ return 0; } int gp_archive_write(gp_archive_type *archive, char *archivename) { FILE *output_file; int size; assert(archive != NULL); output_file = fopen(archivename, "wb"); if (output_file == NULL) { perror(archivename); exit(1); } fputs(ARMAG, output_file); /* write the archive magic number */ while (archive != NULL) { fwrite(&archive->header, 1, AR_HDR_SIZ, output_file); sscanf(archive->header.ar_size, "%il", &size); fwrite(archive->file, 1, size, output_file); archive = archive->next; } fclose(output_file); return 0; } /* update the offset numbers for the archive, this is only required if a symbol index is created */ void gp_archive_update_offsets(gp_archive_type *archive) { unsigned int offset = SARMAG; int size = 0; while (archive != NULL) { archive->offset = offset; sscanf(archive->header.ar_size, "%il", &size); offset += AR_HDR_SIZ + size; archive = archive->next; } return; } /* read a coff archive and store it in memory */ gp_archive_type * gp_archive_read(char *filename) { FILE *infile; gp_archive_type *archive = NULL; gp_archive_type *list = NULL; gp_archive_type *new = NULL; struct ar_hdr tmpheader; fpos_t position; int object_size; char buffer[SARMAG + 1]; infile = fopen(filename,"rb"); if (infile == NULL) { perror(filename); exit(1); } fread(&buffer[0], 1, SARMAG, infile); /* read the magic number */ if (strncmp(buffer, ARMAG, SARMAG) != 0) { fclose(infile); return NULL; } while (feof(infile) == 0) { /* allocate space for the next archive member */ new = (gp_archive_type *)malloc(sizeof(*new)); new->next = NULL; /* read the archive header */ fread(&new->header, AR_HDR_SIZ, 1, infile); /* read the object file or symbol index into memory */ sscanf(new->header.ar_size, "%il", &object_size); new->file = (char *)malloc(sizeof(char)*object_size); fread(new->file, sizeof(char), object_size, infile); /* insert the new member in the archive list */ if (archive == NULL) { /* this is the first entry */ archive = new; list = new; } else { list->next = new; list = new; } /* Some malformed libs have a couple of extra bytes on the end. The while eof test passes, but there are no other members. Test for it. */ fgetpos(infile, &position); fread(&tmpheader, AR_HDR_SIZ, 1, infile); if (feof(infile)) break; fsetpos(infile, &position); } gp_archive_update_offsets(archive); fclose(infile); return archive; } /* Determine if the archive has a symbol index */ int gp_archive_have_index(gp_archive_type *archive) { if ((archive != NULL) && (archive->header.ar_name[0] == '/')) return 1; return 0; } /* Remove the symbol index if one exists */ gp_archive_type * gp_archive_remove_index(gp_archive_type *archive) { gp_archive_type *member = NULL; /* If present, remove the symbol index. */ if (gp_archive_have_index(archive)) { member = archive; archive = archive->next; gp_archive_free_member(member); } return archive; } /* Create a symbol index for the archive. This is always done to make sure duplicate symbols don't get into the library. This data can and should be stored in the file. The only reason not to is if you need compatibility with other tools. */ int gp_archive_make_index(gp_archive_type *archive, struct symbol_table *definition) { gp_object_type *object = NULL; char name[256]; char *end; /* If present, skip the symbol index. */ if (gp_archive_have_index(archive)) archive = archive->next; while (archive != NULL) { sscanf(archive->header.ar_name, "%255s/", name); end = strchr(&name[0], '/'); if (end != NULL) *end = '\0'; object = gp_convert_file(name, archive->file); assert(object != NULL); gp_link_add_symbols(definition, NULL, object); archive = archive->next; } return 0; } /* add the symbol index to the archive */ gp_archive_type * gp_archive_add_index(struct symbol_table *table, gp_archive_type *archive) { gp_archive_type *newmember = NULL; gp_archive_type *member = NULL; int i; struct symbol **lst, **ps, *s; gp_coffsymbol_type *var; char size[10]; char *ptr; long int indexsize = 0; char *symname; if ((archive == NULL) || (table == NULL)) return NULL; /* sort the index */ ps = lst = malloc(table->count * sizeof(lst[0])); for (i = 0; i < HASH_SIZE; i++) for (s = table->hash_table[i]; s; s = s->next) *ps++ = s; assert(ps == &lst[table->count]); qsort(lst, table->count, sizeof(lst[0]), symbol_compare); /* determine the symbol index size */ indexsize = AR_INDEX_NUMBER_SIZ; for (i = 0; i < table->count; i++) { symname = get_symbol_name(lst[i]); indexsize += strlen(symname) + 1 + AR_INDEX_OFFSET_SIZ; } /* create a new member for the index and place it in the archive */ newmember = (gp_archive_type *)malloc(sizeof(*newmember)); if (!newmember) { fprintf(stderr, " error allocating memory\n"); exit(1); } newmember->file = (char *)malloc(sizeof(char)*indexsize); if(!newmember->file) { fprintf(stderr, " error allocating memory\n"); exit(1); } newmember->next = NULL; /* fill in the archive header */ memset(&newmember->header, 0x20, AR_HDR_SIZ); /* fill the header with space */ newmember->header.ar_name[0] = '/'; snprintf(size, sizeof(size), "%lil", indexsize); strncpy(newmember->header.ar_size, &size[0], sizeof(newmember->header.ar_size)); strncpy(newmember->header.ar_fmag, ARMAG, sizeof(newmember->header.ar_fmag)); newmember->next = archive; archive = newmember; /* recalculate the file offsets for the symbol table */ gp_archive_update_offsets(archive); /* write the number of symbols to the member */ ptr = archive->file; gp_putl32(ptr, table->count); ptr += 4; /* write the offsets to the member */ for (i = 0; i < table->count; i++) { var = get_symbol_annotation(lst[i]); member = gp_archive_find_member(archive, var->file->filename); gp_putl32(ptr, member->offset); ptr += 4; } /* write the symbol names to the member */ for (i = 0; i < table->count; i++) { const char* symbol_name = get_symbol_name(lst[i]); const size_t symbol_len = strlen(symbol_name) + 1; memcpy(ptr, symbol_name, symbol_len); ptr += symbol_len; } return archive; } /* place the symbol from the archive symbol index in the archive symbol table */ int gp_archive_add_symbol(struct symbol_table *table, char *name, gp_archive_type *member) { struct symbol *sym; /* Search the for the symbol. If not found, then add it to the global symbol table. */ sym = get_symbol(table, name); if (sym != NULL) { return 1; } sym = add_symbol(table, name); annotate_symbol(sym, member); return 0; } /* This function reads the symbol index in the archive. The symbols are placed in the archive symbol table. This table stores the name of the symbol and the archive member that the symbol is defined in. */ void gp_archive_read_index(struct symbol_table *table, gp_archive_type *archive) { int number = 0; int i; char *name; char *offset; int offset_value = 0; gp_archive_type *list; char *file; assert(gp_archive_have_index(archive)); file = archive->file; /* read the number of symbols */ number = gp_getl32(file); /* set the pointers to the offsets and symbol names */ offset = &file[AR_INDEX_NUMBER_SIZ]; name = offset + (AR_INDEX_OFFSET_SIZ * number); for (i = 0; i < number; i++) { /* get the symbol offset from the symbol index */ offset_value = gp_getl32(offset); /* Locate the object file the symbol is defined in. The both should have the same offset */ list = archive; while (list != NULL) { if (list->offset == offset_value) break; list = list->next; } assert(list != NULL); /* add the symbol to the archive symbol table */ gp_archive_add_symbol(table, name, list); /* increment the pointers to the next symbol */ name += strlen(name) + 1; offset += AR_INDEX_OFFSET_SIZ; } return; } /* print the archive symbol table */ void gp_archive_print_table(struct symbol_table *table) { struct symbol **lst, **ps, *s; int i; const char *format = "%-32s %s\n"; gp_archive_type *member; char name[256]; char *end; assert(table != NULL); /* sort the index */ ps = lst = malloc(table->count * sizeof(lst[0])); for (i = 0; i < HASH_SIZE; i++) for (s = table->hash_table[i]; s; s = s->next) *ps++ = s; assert(ps == &lst[table->count]); qsort(lst, table->count, sizeof(lst[0]), symbol_compare); for (i = 0; i < table->count; i++) { /* determine the archive member the symbol is defined in */ member = get_symbol_annotation(lst[i]); assert(member != NULL); /* determine the archive member name */ sscanf(member->header.ar_name, "%255s/", name); end = strchr(&name[0], '/'); if (end != NULL) *end = '\0'; /* print it */ printf(format, get_symbol_name(lst[i]), name); } return; } gputils-0.13.7/libgputils/gpopcode.c0000644000175000017500000004102011156313233014327 00000000000000/* GNU PIC opcode definitions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* FIXME: use const struct */ /* PIC 12-bit instruction set */ struct insn op_12c5xx[] = { { "addwf", 0xfc0, 0x1c0, INSN_CLASS_OPWF5 }, { "andlw", 0xf00, 0xe00, INSN_CLASS_LIT8 }, { "andwf", 0xfc0, 0x140, INSN_CLASS_OPWF5 }, { "bcf", 0xf00, 0x400, INSN_CLASS_B5 }, { "bsf", 0xf00, 0x500, INSN_CLASS_B5 }, { "btfsc", 0xf00, 0x600, INSN_CLASS_B5 }, { "btfss", 0xf00, 0x700, INSN_CLASS_B5 }, { "call", 0xf00, 0x900, INSN_CLASS_LIT8C12 }, { "clrf", 0xfe0, 0x060, INSN_CLASS_OPF5 }, { "clrw", 0xfff, 0x040, INSN_CLASS_IMPLICIT }, { "clrwdt", 0xfff, 0x004, INSN_CLASS_IMPLICIT }, { "comf", 0xfc0, 0x240, INSN_CLASS_OPWF5 }, { "decf", 0xfc0, 0x0c0, INSN_CLASS_OPWF5 }, { "decfsz", 0xfc0, 0x2c0, INSN_CLASS_OPWF5 }, { "goto", 0xe00, 0xa00, INSN_CLASS_LIT9 }, { "incf", 0xfc0, 0x280, INSN_CLASS_OPWF5 }, { "incfsz", 0xfc0, 0x3c0, INSN_CLASS_OPWF5 }, { "iorlw", 0xf00, 0xd00, INSN_CLASS_LIT8 }, { "iorwf", 0xfc0, 0x100, INSN_CLASS_OPWF5 }, { "movf", 0xfc0, 0x200, INSN_CLASS_OPWF5 }, { "movlw", 0xf00, 0xc00, INSN_CLASS_LIT8 }, { "movwf", 0xfe0, 0x020, INSN_CLASS_OPF5 }, { "nop", 0xfff, 0x000, INSN_CLASS_IMPLICIT }, { "option", 0xfff, 0x002, INSN_CLASS_IMPLICIT }, { "retlw", 0xf00, 0x800, INSN_CLASS_LIT8 }, { "return", 0xfff, 0x800, INSN_CLASS_IMPLICIT }, /* FIXME: special mnemonic */ { "rlf", 0xfc0, 0x340, INSN_CLASS_OPWF5 }, { "rrf", 0xfc0, 0x300, INSN_CLASS_OPWF5 }, { "sleep", 0xfff, 0x003, INSN_CLASS_IMPLICIT }, { "subwf", 0xfc0, 0x080, INSN_CLASS_OPWF5 }, { "swapf", 0xfc0, 0x380, INSN_CLASS_OPWF5 }, { "tris", 0xff8, 0x000, INSN_CLASS_OPF5 }, { "xorlw", 0xf00, 0xf00, INSN_CLASS_LIT8 }, { "xorwf", 0xfc0, 0x180, INSN_CLASS_OPWF5 } }; const int num_op_12c5xx = TABLE_SIZE(op_12c5xx); /* Scenix SX has a superset of the PIC 12-bit instruction set */ /* * It would be nice if there was a more elegant way to do this, * either by adding a flags field to struct insn, or by allowing a * processor to have more than one associated table. */ struct insn op_sx[] = { { "addwf", 0xfc0, 0x1c0, INSN_CLASS_OPWF5 }, { "andlw", 0xf00, 0xe00, INSN_CLASS_LIT8 }, { "andwf", 0xfc0, 0x140, INSN_CLASS_OPWF5 }, { "bank", 0xff8, 0x018, INSN_CLASS_LIT3_BANK }, /* SX only */ { "bcf", 0xf00, 0x400, INSN_CLASS_B5 }, { "bsf", 0xf00, 0x500, INSN_CLASS_B5 }, { "btfsc", 0xf00, 0x600, INSN_CLASS_B5 }, { "btfss", 0xf00, 0x700, INSN_CLASS_B5 }, { "call", 0xf00, 0x900, INSN_CLASS_LIT8C12 }, { "clrf", 0xfe0, 0x060, INSN_CLASS_OPF5 }, { "clrw", 0xfff, 0x040, INSN_CLASS_IMPLICIT }, { "clrwdt", 0xfff, 0x004, INSN_CLASS_IMPLICIT }, { "comf", 0xfc0, 0x240, INSN_CLASS_OPWF5 }, { "decf", 0xfc0, 0x0c0, INSN_CLASS_OPWF5 }, { "decfsz", 0xfc0, 0x2c0, INSN_CLASS_OPWF5 }, { "goto", 0xe00, 0xa00, INSN_CLASS_LIT9 }, { "incf", 0xfc0, 0x280, INSN_CLASS_OPWF5 }, { "incfsz", 0xfc0, 0x3c0, INSN_CLASS_OPWF5 }, { "iorlw", 0xf00, 0xd00, INSN_CLASS_LIT8 }, { "iorwf", 0xfc0, 0x100, INSN_CLASS_OPWF5 }, { "iread", 0xfff, 0x041, INSN_CLASS_IMPLICIT }, /* SX only */ { "mode", 0xff0, 0x050, INSN_CLASS_LIT4 }, /* SX only */ { "movf", 0xfc0, 0x200, INSN_CLASS_OPWF5 }, { "movlw", 0xf00, 0xc00, INSN_CLASS_LIT8 }, { "movmw", 0xfff, 0x042, INSN_CLASS_IMPLICIT }, /* SX only */ { "movwf", 0xfe0, 0x020, INSN_CLASS_OPF5 }, { "movwm", 0xfff, 0x043, INSN_CLASS_IMPLICIT }, /* SX only */ { "nop", 0xfff, 0x000, INSN_CLASS_IMPLICIT }, { "option", 0xfff, 0x002, INSN_CLASS_IMPLICIT }, { "page", 0xff8, 0x010, INSN_CLASS_LIT3_PAGE }, /* SX only */ { "reti", 0xfff, 0x00e, INSN_CLASS_IMPLICIT }, /* SX only */ { "retiw", 0xfff, 0x00f, INSN_CLASS_IMPLICIT }, /* SX only */ { "retlw", 0xf00, 0x800, INSN_CLASS_LIT8 }, { "retp", 0xfff, 0x00d, INSN_CLASS_IMPLICIT }, /* SX only */ { "return", 0xfff, 0x00c, INSN_CLASS_IMPLICIT }, /* SX only */ { "rlf", 0xfc0, 0x340, INSN_CLASS_OPWF5 }, { "rrf", 0xfc0, 0x300, INSN_CLASS_OPWF5 }, { "sleep", 0xfff, 0x003, INSN_CLASS_IMPLICIT }, { "subwf", 0xfc0, 0x080, INSN_CLASS_OPWF5 }, { "swapf", 0xfc0, 0x380, INSN_CLASS_OPWF5 }, { "tris", 0xff8, 0x000, INSN_CLASS_OPF5 }, { "xorlw", 0xf00, 0xf00, INSN_CLASS_LIT8 }, { "xorwf", 0xfc0, 0x180, INSN_CLASS_OPWF5 } }; const int num_op_sx = TABLE_SIZE(op_sx); /* PIC 14-bit instruction set */ struct insn op_16cxx[] = { { "addlw", 0x3e00, 0x3e00, INSN_CLASS_LIT8 }, { "addwf", 0x3f00, 0x0700, INSN_CLASS_OPWF7 }, { "andlw", 0x3f00, 0x3900, INSN_CLASS_LIT8 }, { "andwf", 0x3f00, 0x0500, INSN_CLASS_OPWF7 }, { "bcf", 0x3c00, 0x1000, INSN_CLASS_B7 }, { "bsf", 0x3c00, 0x1400, INSN_CLASS_B7 }, { "btfsc", 0x3c00, 0x1800, INSN_CLASS_B7 }, { "btfss", 0x3c00, 0x1c00, INSN_CLASS_B7 }, { "call", 0x3800, 0x2000, INSN_CLASS_LIT11 }, { "clrf", 0x3f80, 0x0180, INSN_CLASS_OPF7 }, { "clrw", 0x3fff, 0x0103, INSN_CLASS_IMPLICIT }, { "clrwdt", 0x3fff, 0x0064, INSN_CLASS_IMPLICIT }, { "comf", 0x3f00, 0x0900, INSN_CLASS_OPWF7 }, { "decf", 0x3f00, 0x0300, INSN_CLASS_OPWF7 }, { "decfsz", 0x3f00, 0x0b00, INSN_CLASS_OPWF7 }, { "goto", 0x3800, 0x2800, INSN_CLASS_LIT11 }, { "incf", 0x3f00, 0x0a00, INSN_CLASS_OPWF7 }, { "incfsz", 0x3f00, 0x0f00, INSN_CLASS_OPWF7 }, { "iorlw", 0x3f00, 0x3800, INSN_CLASS_LIT8 }, { "iorwf", 0x3f00, 0x0400, INSN_CLASS_OPWF7 }, { "movf", 0x3f00, 0x0800, INSN_CLASS_OPWF7 }, { "movlw", 0x3c00, 0x3000, INSN_CLASS_LIT8 }, { "movwf", 0x3f80, 0x0080, INSN_CLASS_OPF7 }, { "nop", 0x3f9f, 0x0000, INSN_CLASS_IMPLICIT }, { "option", 0x3fff, 0x0062, INSN_CLASS_IMPLICIT }, { "retfie", 0x3fff, 0x0009, INSN_CLASS_IMPLICIT }, { "retlw", 0x3c00, 0x3400, INSN_CLASS_LIT8 }, { "return", 0x3fff, 0x0008, INSN_CLASS_IMPLICIT }, { "rlf", 0x3f00, 0x0d00, INSN_CLASS_OPWF7 }, { "rrf", 0x3f00, 0x0c00, INSN_CLASS_OPWF7 }, { "sleep", 0x3fff, 0x0063, INSN_CLASS_IMPLICIT }, { "sublw", 0x3e00, 0x3c00, INSN_CLASS_LIT8 }, { "subwf", 0x3f00, 0x0200, INSN_CLASS_OPWF7 }, { "swapf", 0x3f00, 0x0e00, INSN_CLASS_OPWF7 }, { "tris", 0x3ff8, 0x0060, INSN_CLASS_OPF7 }, { "xorlw", 0x3f00, 0x3a00, INSN_CLASS_LIT8 }, { "xorwf", 0x3f00, 0x0600, INSN_CLASS_OPWF7 } }; const int num_op_16cxx = TABLE_SIZE(op_16cxx); /* PIC 16-bit instruction set */ struct insn op_17cxx[] = { { "addlw", 0xff00, 0xb100, INSN_CLASS_LIT8 }, { "addwf", 0xfe00, 0x0e00, INSN_CLASS_OPWF8 }, { "addwfc", 0xfe00, 0x1000, INSN_CLASS_OPWF8 }, { "andlw", 0xff00, 0xb500, INSN_CLASS_LIT8 }, { "andwf", 0xfe00, 0x0a00, INSN_CLASS_OPWF8 }, { "bcf", 0xf800, 0x8800, INSN_CLASS_B8 }, { "bsf", 0xf800, 0x8000, INSN_CLASS_B8 }, { "btfsc", 0xf800, 0x9800, INSN_CLASS_B8 }, { "btfss", 0xf800, 0x9000, INSN_CLASS_B8 }, { "btg", 0xf800, 0x3800, INSN_CLASS_B8 }, { "call", 0xe000, 0xe000, INSN_CLASS_LIT13 }, { "clrf", 0xfe00, 0x2800, INSN_CLASS_OPWF8 }, { "clrwdt", 0xffff, 0x0004, INSN_CLASS_IMPLICIT }, { "comf", 0xfe00, 0x1200, INSN_CLASS_OPWF8 }, { "cpfseq", 0xff00, 0x3100, INSN_CLASS_OPF8 }, { "cpfsgt", 0xff00, 0x3200, INSN_CLASS_OPF8 }, { "cpfslt", 0xff00, 0x3000, INSN_CLASS_OPF8 }, { "daw", 0xfe00, 0x2e00, INSN_CLASS_OPWF8 }, { "decf", 0xfe00, 0x0600, INSN_CLASS_OPWF8 }, { "decfsz", 0xfe00, 0x1600, INSN_CLASS_OPWF8 }, { "dcfsnz", 0xfe00, 0x2600, INSN_CLASS_OPWF8 }, { "goto", 0xe000, 0xc000, INSN_CLASS_LIT13 }, { "incf", 0xfe00, 0x1400, INSN_CLASS_OPWF8 }, { "incfsz", 0xfe00, 0x1e00, INSN_CLASS_OPWF8 }, { "infsnz", 0xfe00, 0x2400, INSN_CLASS_OPWF8 }, { "iorlw", 0xff00, 0xb300, INSN_CLASS_LIT8 }, { "iorwf", 0xfe00, 0x0800, INSN_CLASS_OPWF8 }, { "lcall", 0xff00, 0xb700, INSN_CLASS_LIT8C16 }, { "movfp", 0xe000, 0x6000, INSN_CLASS_FP }, { "movpf", 0xe000, 0x4000, INSN_CLASS_PF }, { "movlb", 0xff00, 0xb800, INSN_CLASS_LIT8 }, { "movlr", 0xfe00, 0xba00, INSN_CLASS_LIT4S }, { "movlw", 0xff00, 0xb000, INSN_CLASS_LIT8 }, { "movwf", 0xff00, 0x0100, INSN_CLASS_OPF8 }, { "mullw", 0xff00, 0xbc00, INSN_CLASS_LIT8 }, { "mulwf", 0xff00, 0x3400, INSN_CLASS_OPF8 }, { "negw", 0xfe00, 0x2c00, INSN_CLASS_OPWF8 }, { "nop", 0xffff, 0x0000, INSN_CLASS_IMPLICIT }, { "retfie", 0xffff, 0x0005, INSN_CLASS_IMPLICIT }, { "retlw", 0xff00, 0xb600, INSN_CLASS_LIT8 }, { "return", 0xffff, 0x0002, INSN_CLASS_IMPLICIT }, { "rlcf", 0xfe00, 0x1a00, INSN_CLASS_OPWF8 }, { "rlncf", 0xfe00, 0x2200, INSN_CLASS_OPWF8 }, { "rrcf", 0xfe00, 0x1800, INSN_CLASS_OPWF8 }, { "rrncf", 0xfe00, 0x2000, INSN_CLASS_OPWF8 }, { "setf", 0xfe00, 0x2a00, INSN_CLASS_OPWF8 }, { "sleep", 0xffff, 0x0003, INSN_CLASS_IMPLICIT }, { "sublw", 0xff00, 0xb200, INSN_CLASS_LIT8 }, { "subwf", 0xfe00, 0x0400, INSN_CLASS_OPWF8 }, { "subwfb", 0xfe00, 0x0200, INSN_CLASS_OPWF8 }, { "swapf", 0xfe00, 0x1c00, INSN_CLASS_OPWF8 }, { "tablrd", 0xfc00, 0xa800, INSN_CLASS_TBL3 }, { "tablwt", 0xfc00, 0xac00, INSN_CLASS_TBL3 }, { "tlrd", 0xfc00, 0xa000, INSN_CLASS_TBL2 }, { "tlwt", 0xfc00, 0xa400, INSN_CLASS_TBL2 }, { "tstfsz", 0xff00, 0x3300, INSN_CLASS_OPF8 }, { "xorlw", 0xff00, 0xb400, INSN_CLASS_LIT8 }, { "xorwf", 0xfe00, 0x0c00, INSN_CLASS_OPWF8 } }; const int num_op_17cxx = TABLE_SIZE(op_17cxx); struct insn op_18cxx[] = { { "addlw", 0xff00, 0x0f00, INSN_CLASS_LIT8 }, { "addwf", 0xfc00, 0x2400, INSN_CLASS_OPWFA8 }, { "addwfc", 0xfc00, 0x2000, INSN_CLASS_OPWFA8 }, { "andlw", 0xff00, 0x0b00, INSN_CLASS_LIT8 }, { "andwf", 0xfc00, 0x1400, INSN_CLASS_OPWFA8 }, { "bc", 0xff00, 0xe200, INSN_CLASS_RBRA8 }, { "bcf", 0xf000, 0x9000, INSN_CLASS_BA8 }, { "bn", 0xff00, 0xe600, INSN_CLASS_RBRA8 }, { "bnc", 0xff00, 0xe300, INSN_CLASS_RBRA8 }, { "bnn", 0xff00, 0xe700, INSN_CLASS_RBRA8 }, { "bnov", 0xff00, 0xe500, INSN_CLASS_RBRA8 }, { "bnz", 0xff00, 0xe100, INSN_CLASS_RBRA8 }, { "bov", 0xff00, 0xe400, INSN_CLASS_RBRA8 }, { "bra", 0xf800, 0xd000, INSN_CLASS_RBRA11 }, { "bsf", 0xf000, 0x8000, INSN_CLASS_BA8 }, { "btfsc", 0xf000, 0xb000, INSN_CLASS_BA8 }, { "btfss", 0xf000, 0xa000, INSN_CLASS_BA8 }, { "btg", 0xf000, 0x7000, INSN_CLASS_BA8 }, { "bz", 0xff00, 0xe000, INSN_CLASS_RBRA8 }, { "call", 0xfe00, 0xec00, INSN_CLASS_CALL20 }, { "clrf", 0xfe00, 0x6a00, INSN_CLASS_OPFA8 }, { "clrwdt", 0xffff, 0x0004, INSN_CLASS_IMPLICIT }, { "comf", 0xfc00, 0x1c00, INSN_CLASS_OPWFA8 }, { "cpfseq", 0xfe00, 0x6200, INSN_CLASS_OPFA8 }, { "cpfsgt", 0xfe00, 0x6400, INSN_CLASS_OPFA8 }, { "cpfslt", 0xfe00, 0x6000, INSN_CLASS_OPFA8 }, { "daw", 0xffff, 0x0007, INSN_CLASS_IMPLICIT }, { "decf", 0xfc00, 0x0400, INSN_CLASS_OPWFA8 }, { "decfsz", 0xfc00, 0x2c00, INSN_CLASS_OPWFA8 }, { "dcfsnz", 0xfc00, 0x4c00, INSN_CLASS_OPWFA8 }, { "goto", 0xff00, 0xef00, INSN_CLASS_LIT20 }, { "incf", 0xfc00, 0x2800, INSN_CLASS_OPWFA8 }, { "incfsz", 0xfc00, 0x3c00, INSN_CLASS_OPWFA8 }, { "infsnz", 0xfc00, 0x4800, INSN_CLASS_OPWFA8 }, { "iorlw", 0xff00, 0x0900, INSN_CLASS_LIT8 }, { "iorwf", 0xfc00, 0x1000, INSN_CLASS_OPWFA8 }, { "lfsr", 0xffc0, 0xee00, INSN_CLASS_FLIT12 }, { "movf", 0xfc00, 0x5000, INSN_CLASS_OPWFA8 }, { "movff", 0xf000, 0xc000, INSN_CLASS_FF }, { "movlb", 0xff00, 0x0100, INSN_CLASS_LIT8 }, { "movlw", 0xff00, 0x0e00, INSN_CLASS_LIT8 }, { "movwf", 0xfe00, 0x6e00, INSN_CLASS_OPFA8 }, { "mullw", 0xff00, 0x0d00, INSN_CLASS_LIT8 }, { "mulwf", 0xfe00, 0x0200, INSN_CLASS_OPFA8 }, { "negf", 0xfe00, 0x6c00, INSN_CLASS_OPFA8 }, { "nop", 0xffff, 0x0000, INSN_CLASS_IMPLICIT }, { "pop", 0xffff, 0x0006, INSN_CLASS_IMPLICIT }, { "push", 0xffff, 0x0005, INSN_CLASS_IMPLICIT }, { "rcall", 0xf800, 0xd800, INSN_CLASS_RBRA11 }, { "reset", 0xffff, 0x00ff, INSN_CLASS_IMPLICIT }, { "retfie", 0xfffe, 0x0010, INSN_CLASS_LIT1 }, { "retlw", 0xff00, 0x0c00, INSN_CLASS_LIT8 }, { "return", 0xfffe, 0x0012, INSN_CLASS_LIT1 }, { "rlcf", 0xfc00, 0x3400, INSN_CLASS_OPWFA8 }, { "rlncf", 0xfc00, 0x4400, INSN_CLASS_OPWFA8 }, { "rrcf", 0xfc00, 0x3000, INSN_CLASS_OPWFA8 }, { "rrncf", 0xfc00, 0x4000, INSN_CLASS_OPWFA8 }, { "setf", 0xfe00, 0x6800, INSN_CLASS_OPFA8 }, { "sleep", 0xffff, 0x0003, INSN_CLASS_IMPLICIT }, { "subfwb", 0xfc00, 0x5400, INSN_CLASS_OPWFA8 }, { "sublw", 0xff00, 0x0800, INSN_CLASS_LIT8 }, { "subwf", 0xfc00, 0x5c00, INSN_CLASS_OPWFA8 }, { "subwfb", 0xfc00, 0x5800, INSN_CLASS_OPWFA8 }, { "swapf", 0xfc00, 0x3800, INSN_CLASS_OPWFA8 }, { "tblrd", 0xfffc, 0x0008, INSN_CLASS_TBL }, { "tblwt", 0xfffc, 0x000c, INSN_CLASS_TBL }, { "tstfsz", 0xfe00, 0x6600, INSN_CLASS_OPFA8 }, { "xorlw", 0xff00, 0x0a00, INSN_CLASS_LIT8 }, { "xorwf", 0xfc00, 0x1800, INSN_CLASS_OPWFA8 } }; const int num_op_18cxx = TABLE_SIZE(op_18cxx); /* PIC 16-bit "Special" instruction set */ struct insn op_18cxx_sp[] = { { "clrc", 0xffff, 0x90d8, INSN_CLASS_IMPLICIT }, { "clrdc", 0xffff, 0x92d8, INSN_CLASS_IMPLICIT }, { "clrn", 0xffff, 0x98d8, INSN_CLASS_IMPLICIT }, { "clrov", 0xffff, 0x96d8, INSN_CLASS_IMPLICIT }, { "clrw", 0xffff, 0x6ae8, INSN_CLASS_IMPLICIT }, { "clrz", 0xffff, 0x94d8, INSN_CLASS_IMPLICIT }, { "setc", 0xffff, 0x80d8, INSN_CLASS_IMPLICIT }, { "setdc", 0xffff, 0x82d8, INSN_CLASS_IMPLICIT }, { "setn", 0xffff, 0x88d8, INSN_CLASS_IMPLICIT }, { "setov", 0xffff, 0x86d8, INSN_CLASS_IMPLICIT }, { "setz", 0xffff, 0x84d8, INSN_CLASS_IMPLICIT }, { "skpc", 0xffff, 0xa0d8, INSN_CLASS_IMPLICIT }, { "skpdc", 0xffff, 0xa2d8, INSN_CLASS_IMPLICIT }, { "skpn", 0xffff, 0xa8d8, INSN_CLASS_IMPLICIT }, { "skpov", 0xffff, 0xa6d8, INSN_CLASS_IMPLICIT }, { "skpz", 0xffff, 0xa4d8, INSN_CLASS_IMPLICIT }, { "skpnc", 0xffff, 0xb0d8, INSN_CLASS_IMPLICIT }, { "skpndc", 0xffff, 0xb2d8, INSN_CLASS_IMPLICIT }, { "skpnn", 0xffff, 0xb8d8, INSN_CLASS_IMPLICIT }, { "skpnov", 0xffff, 0xb6d8, INSN_CLASS_IMPLICIT }, { "skpnz", 0xffff, 0xb4d8, INSN_CLASS_IMPLICIT }, { "tgc", 0xffff, 0x70d8, INSN_CLASS_IMPLICIT }, { "tgdc", 0xffff, 0x72d8, INSN_CLASS_IMPLICIT }, { "tgn", 0xffff, 0x78d8, INSN_CLASS_IMPLICIT }, { "tgov", 0xffff, 0x76d8, INSN_CLASS_IMPLICIT }, { "tgz", 0xffff, 0x74d8, INSN_CLASS_IMPLICIT } }; const int num_op_18cxx_sp = TABLE_SIZE(op_18cxx_sp); /* PIC 16-bit Extended instruction set */ struct insn op_18cxx_ext[] = { { "addfsr", 0xff00, 0xe800, INSN_CLASS_LITFSR }, { "addulnk", 0xffc0, 0xe8c0, INSN_CLASS_LIT6 }, { "callw", 0xffff, 0x0014, INSN_CLASS_IMPLICIT }, { "movsf", 0xff80, 0xeb00, INSN_CLASS_SF }, { "movss", 0xff80, 0xeb80, INSN_CLASS_SS }, { "pushl", 0xff00, 0xea00, INSN_CLASS_LIT8 }, { "subfsr", 0xff00, 0xe900, INSN_CLASS_LITFSR }, { "subulnk", 0xffc0, 0xe9c0, INSN_CLASS_LIT6 } }; const int num_op_18cxx_ext = TABLE_SIZE(op_18cxx_ext); gputils-0.13.7/libgputils/gpmemory.c0000644000175000017500000001413511156521302014373 00000000000000/* Supports instruction memory. Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /************************************************************************ gpmemory.c This file provides the functions used to manipulate the instruction memory. The instruction memory is stored in 'memory blocks' which are implemented with the 'MemBlock' structure: typedef struct MemBlock { unsigned int base; unsigned int *memory; struct MemBlock *next; } MemBlock; Each MemBlock can hold up to `MAX_I_MEM' (32k currently) words. The `base' is the base address of the memory block. If the instruction memory spans more than 32k, then additional memory blocks can be allocated and linked together in a singly linked list (`next'). The last memory block in a linked list of blocks has its next ptr set to NULL. 32k was chose because it corresponds to 64K bytes which is the upper limit on inhx8m files. ************************************************************************/ MemBlock *i_memory_create(void) { MemBlock *m; m = (MemBlock *)malloc(sizeof(MemBlock)); m->base = 0; m->memory = (unsigned int *)calloc(MAX_I_MEM, sizeof(unsigned int)); m->next = NULL; return m; } void i_memory_free(MemBlock *m) { MemBlock *n; do { if(m->memory) free(m->memory); n = m->next; free(m); m = n; } while(m); } /************************************************************************ * i_memory_new * * Create memory for a new memory block. * * Inputs: * m - start of the instruction memory * mpb - pointer to the memory block structure (MemBlock) * base_address - where this new block of memory is based * ************************************************************************/ MemBlock * i_memory_new(MemBlock *m, MemBlock *mbp, unsigned int base_address) { unsigned int base; base = (base_address >> I_MEM_BITS) & 0xFFFF; mbp->memory = (unsigned int *)calloc(MAX_I_MEM, sizeof(unsigned int)); mbp->base = base; do { if((m->next == NULL) || (m->next->base > base)) { /* Insert after this block */ mbp->next = m->next; m->next = mbp; return mbp; } m = m->next; } while(m); assert(0); return NULL; } /************************************************************************ * i_memory_get * * Fetch a word from the pic memory. This function will traverse through * the linked list of memory blocks searching for the address from the * word will be fetched. If the address is not found, then `0' will be * returned. * * Inputs: * address - * m - start of the instruction memory * Returns * the word from that address * ************************************************************************/ int i_memory_get(MemBlock *m, unsigned int address) { do { assert(m->memory != NULL); if( ((address >> I_MEM_BITS) & 0xFFFF) == m->base ) return m->memory[address & I_MEM_MASK]; m = m->next; } while(m); return 0; } /************************************************************************ * i_memory_put * * This function will write one word to a pic memory address. If the * destination memory block is non-existant, a new one will be created. * * inputs: * i_memory - start of the instruction memory * address - destination address of the write * value - the value to be written at that address * returns: * none * ************************************************************************/ void i_memory_put(MemBlock *i_memory, unsigned int address, unsigned int value) { MemBlock *m = NULL; do { if(m) m = m->next; else m = i_memory; if(m->memory == NULL) { i_memory_new(i_memory, m, address); } if( ((address >> I_MEM_BITS) & 0xFFFF) == m->base ) { m->memory[address & I_MEM_MASK] = value; return; } } while (m->next); /* Couldn't find an address to write this value. This must be the first time we've tried to write to high memory some place. */ m = i_memory_new(i_memory, (MemBlock *) malloc(sizeof(MemBlock)), address); m->memory[address & I_MEM_MASK] = value; } int i_memory_used(MemBlock *m) { int words=0; int i; int maximum; while(m) { i = m->base << I_MEM_BITS; maximum = i + MAX_I_MEM; while (i < maximum) { if ((i_memory_get(m, i) & MEM_USED_MASK)) { words++; } i++; } m = m->next; } return words; } /************************************************************************ * * * These two functions are used to read and write instruction memory. * * ************************************************************************/ void print_i_memory(MemBlock *m, int byte_addr) { int base,i,j,row_used; char c; #define WORDS_IN_ROW 8 do { assert(m->memory != NULL); base = m->base << I_MEM_BITS; for(i = 0; imemory[i+j] ) row_used = 1; if(row_used) { printf("%08X ",(base+i) << byte_addr ); for(j = 0; jmemory[i+j] & 0xffff ); for(j = 0; jmemory[i+j] & 0xff; putchar( (isprint(c)) ? c : '.'); c = (m->memory[i+j]>>8) & 0xff; putchar( (isprint(c)) ? c : '.'); } putchar('\n'); } } m = m->next; } while(m); } gputils-0.13.7/libgputils/gpsystem.c0000644000175000017500000001224511156313233014411 00000000000000/* General system functions Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #ifdef HAVE_WINDOWS_H #include #endif char *gp_header_path; char *gp_lkr_path; char *gp_lib_path; gp_boolean absolute_path_warning = true; /* initialize the library */ void gp_init(void) { #ifdef USE_DEFAULT_PATHS /* load the environmental variables */ gp_header_path = getenv("GPUTILS_HEADER_PATH"); gp_lkr_path = getenv("GPUTILS_LKR_PATH"); gp_lib_path = getenv("GPUTILS_LIB_PATH"); #ifndef HAVE_DOS_BASED_FILE_SYSTEM if (gp_header_path == NULL) { gp_header_path = strdup(HEADER_PATH); } if (gp_lkr_path == NULL) { gp_lkr_path = strdup(LKR_PATH); } if (gp_lib_path == NULL) { gp_lib_path = strdup(LIB_PATH); } #endif #else gp_header_path = NULL; gp_lkr_path = NULL; gp_lib_path = NULL; #endif } /* little endian functions */ void gp_fputl16(short data, FILE *fp) { fputc((int)(data & 255), fp); fputc((int)((data >> 8) & 255), fp); return; } void gp_fputl32(long data, FILE *fp) { fputc((int)(data & 255), fp); fputc((int)((data >> 8) & 255), fp); fputc((int)((data >> 16) & 255), fp); fputc((int)((data >> 24) & 255), fp); return; } void gp_fputvar(char *data, int number, FILE *fp) { int i; for(i = 0; i < number; i++) fputc(data[i], fp); return; } short gp_getl16(char *addr) { short value; value = (unsigned char)addr[0]; value |= (unsigned char)addr[1] << 8; return value; } unsigned short gp_getu16(char *addr) { return (unsigned short) gp_getl16(addr); } long gp_getl32(char *addr) { long value; value = (unsigned char)addr[0]; value |= (unsigned char)addr[1] << 8; value |= (unsigned char)addr[2] << 16; value |= (unsigned char)addr[3] << 24; return value; } void gp_putl16(char *addr, short data) { addr[1] = (data >> 8) & 0xff; addr[0] = data & 0xff; return; } void gp_putl32(char *addr, long data) { addr[0] = data & 0xff; addr[1] = (data >> 8) & 0xff; addr[2] = (data >> 16) & 0xff; addr[3] = (data >> 24) & 0xff; return; } /* big endian functions */ long gp_getb32(char *addr) { long value; value = (unsigned char)addr[0] << 24; value |= (unsigned char)addr[1] << 16; value |= (unsigned char)addr[2] << 8; value |= (unsigned char)addr[3]; return value; } void gp_putb32(char *addr, long data) { addr[0] = (data >> 24) & 0xff; addr[1] = (data >> 16) & 0xff; addr[2] = (data >> 8) & 0xff; addr[3] = data & 0xff; return; } void gp_date_string(char *buffer, size_t sizeof_buffer) { time_t now; struct tm *now_tm; time(&now); now_tm = localtime(&now); snprintf(buffer, sizeof_buffer, "%d-%d-%d %02d:%02d:%02d", now_tm->tm_mon + 1, now_tm->tm_mday, 1900 + now_tm->tm_year, now_tm->tm_hour, now_tm->tm_min, now_tm->tm_sec); return; } char * gp_lower_case(char *name) { char *new; char *ptr; ptr = new = strdup(name); while (*ptr != '\0') { *ptr = tolower(*ptr); ptr++; } return new; } char * gp_upper_case(char *name) { char *new; char *ptr; ptr = new = strdup(name); while (*ptr != '\0') { *ptr = toupper(*ptr); ptr++; } return new; } /* linked list functions */ gp_linked_list * gp_list_make(void) { gp_linked_list *new; new = malloc(sizeof(*new)); new->annotation = NULL; new->prev = NULL; new->next = NULL; return new; } void gp_list_annotate(gp_linked_list *link, void *a) { link->annotation = a; } void * gp_list_get(gp_linked_list *link) { return link->annotation; } /* fetch the absolute path of the filename */ char * gp_absolute_path(char *file_name) { #ifdef HAVE_WINDOWS_H /* It would be better to test for GetFullPathName, but the test won't work with a cross compiler. So if windows.h exists, we assume that GetFullPathName is available. */ #define FILE_BUFFER_SIZE 512 char file_buffer[FILE_BUFFER_SIZE]; char *file_ptr; int num_chars; num_chars = GetFullPathName(file_name, FILE_BUFFER_SIZE, file_buffer, &file_ptr); if (num_chars == 0) { gp_error("can't fetch full path of %s", file_name); return file_name; } else { return strdup(file_buffer); } #else if (absolute_path_warning) { gp_warning("host system does not support absolute paths"); absolute_path_warning = false; } return file_name; #endif } gputils-0.13.7/libgputils/gpcofflink.h0000644000175000017500000000677411156313233014677 00000000000000/* GNU PIC coff linker functions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPCOFFLINK_H__ #define __GPCOFFLINK_H__ /* accessbank - used for access registers in internal ram for 18CXX codepage - used for program code, initialized data values, and constants databank - used for banked registers in internal ram sharebank - used for unbanked registers in internal ram */ enum section_type { accessbank, codepage, databank, sharebank }; /* Section definitions from the linker script are stored in the following structure. These structures are placed in a symbol table. */ struct linker_section { enum section_type type; int start; int end; int fill; gp_boolean use_fill; gp_boolean protected; }; void gp_link_add_symbol(struct symbol_table *table, gp_symbol_type *symbol, gp_object_type *file); void gp_link_remove_symbol(struct symbol_table *table, char *name); int gp_link_add_symbols(struct symbol_table *, struct symbol_table *missing, gp_object_type *object); void gp_cofflink_combine_objects(gp_object_type *object); void gp_cofflink_clean_table(gp_object_type *object, struct symbol_table *symbols); void gp_cofflink_combine_overlay(gp_object_type *object, int remove_symbol); void gp_cofflink_make_stack(gp_object_type *object, int num_bytes); void gp_cofflink_merge_sections(gp_object_type *object, int byte_addr); void gp_cofflink_make_cinit(gp_object_type *object); void gp_cofflink_make_idata(gp_object_type *object); void gp_add_cinit_section(gp_object_type *object, int byte_addr); void gp_cofflink_reloc_abs(MemBlock *m, int byte_addr, gp_section_type *section, unsigned long flags); void gp_cofflink_reloc_assigned(MemBlock *m, int byte_addr, gp_section_type *section, unsigned long flags, struct symbol_table *sections, struct symbol_table *logical_sections); void gp_cofflink_reloc_unassigned(MemBlock *m, int byte_addr, gp_section_type *section, unsigned long flags, struct symbol_table *sections); void gp_cofflink_update_table(gp_object_type *object); void gp_cofflink_fill_pages(gp_object_type *object, MemBlock *m, int byte_addr, struct symbol_table *sections); void gp_cofflink_patch(gp_object_type *object); MemBlock *gp_cofflink_make_memory(gp_object_type *object); extern gp_boolean gp_relocate_to_shared; #endif gputils-0.13.7/libgputils/gpopcode.h0000644000175000017500000001101111156313233014331 00000000000000/* GNU PIC opcode definitions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPOPCODE_H__ #define __GPOPCODE_H__ enum insn_class { INSN_CLASS_LIT1, /* bit 0 contains a 1 bit literal */ INSN_CLASS_LIT4S, /* Bits 7:4 contain a 4 bit literal, bits 3:0 are unused */ INSN_CLASS_LIT6, /* bits 5:0 contain an 6 bit literal */ INSN_CLASS_LIT8, /* bits 7:0 contain an 8 bit literal */ INSN_CLASS_LIT8C12, /* bits 7:0 contain an 8 bit literal, 12 bit CALL */ INSN_CLASS_LIT8C16, /* bits 7:0 contain an 8 bit literal, 16 bit CALL */ INSN_CLASS_LIT9, /* bits 8:0 contain a 9 bit literal */ INSN_CLASS_LIT11, /* bits 10:0 contain an 11 bit literal */ INSN_CLASS_LIT13, /* bits 12:0 contain an 11 bit literal */ INSN_CLASS_LITFSR, /* bits 5:0 contain an 6 bit literal for fsr 7:6 */ INSN_CLASS_IMPLICIT, /* instruction has no variable bits at all */ INSN_CLASS_OPF5, /* bits 4:0 contain a register address */ INSN_CLASS_OPWF5, /* as above, but bit 5 has a destination flag */ INSN_CLASS_B5, /* as for OPF5, but bits 7:5 have bit number */ INSN_CLASS_OPF7, /* bits 6:0 contain a register address */ INSN_CLASS_OPWF7, /* as above, but bit 7 has destination flag */ INSN_CLASS_B7, /* as for OPF7, but bits 9:7 have bit number */ INSN_CLASS_OPF8, /* bits 7:0 contain a register address */ INSN_CLASS_OPFA8, /* bits 7:0 contain a register address & bit has access flag */ INSN_CLASS_OPWF8, /* as above, but bit 8 has dest flag */ INSN_CLASS_OPWFA8, /* as above, but bit 9 has dest flag & bit 8 has access flag */ INSN_CLASS_B8, /* like OPF7, but bits 9:11 have bit number */ INSN_CLASS_BA8, /* like OPF7, but bits 9:11 have bit number & bit 8 has access flag */ INSN_CLASS_LIT20, /* 20bit lit, bits 7:0 in first word bits 19:8 in second */ INSN_CLASS_CALL20, /* Like LIT20, but bit 8 has fast push flag */ INSN_CLASS_RBRA8, /* Bits 7:0 contain a relative branch address */ INSN_CLASS_RBRA11, /* Bits 10:0 contain a relative branch address */ INSN_CLASS_FLIT12, /* LFSR, 12bit lit loaded into 1 of 4 FSRs */ INSN_CLASS_FF, /* two 12bit file addresses */ INSN_CLASS_FP, /* Bits 7:0 contain a register address, bits 12:8 contains a peripheral address */ INSN_CLASS_PF, /* Bits 7:0 contain a register address, bits 12:8 contains a peripheral address */ INSN_CLASS_SF, /* 7 bit offset added to FSR2, fetched memory placed at 12 bit address */ INSN_CLASS_SS, /* two 7 bit offsets, memory moved using FSR2 */ INSN_CLASS_TBL, /* a table read or write instruction */ INSN_CLASS_TBL2, /* a table read or write instruction. Bits 7:0 contains a register address; Bit 8 is unused; Bit 9, table byte select. (0:lower ; 1:upper) */ INSN_CLASS_TBL3, /* a table read or write instruction. Bits 7:0 contains a register address; Bit 8, 1 if increment pointer, 0 otherwise; Bit 9, table byte select. (0:lower ; 1:upper) */ INSN_CLASS_FUNC, /* instruction is an assembler function */ INSN_CLASS_LIT3_BANK, /* SX: bits 3:0 contain a 3 bit literal, shifted 5 bits */ INSN_CLASS_LIT3_PAGE, /* SX: bits 3:0 contain a 3 bit literal, shifted 9 bits */ INSN_CLASS_LIT4 /* SX: bits 3:0 contain a 4 bit literal */ }; struct insn { char *name; long int mask; long int opcode; enum insn_class class; int attribs; }; #define TABLE_SIZE(X) (sizeof(X) / sizeof(X[0])) extern struct insn op_12c5xx[]; extern const int num_op_12c5xx; extern struct insn op_sx[]; extern const int num_op_sx; extern struct insn op_16cxx[]; extern const int num_op_16cxx; extern struct insn op_17cxx[]; extern const int num_op_17cxx; extern struct insn op_18cxx[]; extern const int num_op_18cxx; extern struct insn op_18cxx_sp[]; extern const int num_op_18cxx_sp; extern struct insn op_18cxx_ext[]; extern const int num_op_18cxx_ext; #endif gputils-0.13.7/libgputils/gpsymbol.h0000644000175000017500000000342111156313233014373 00000000000000/* Symbol table support Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPSYMBOL_H__ #define __GPSYMBOL_H__ #define HASH_SIZE 173 /* Too small and we get collisions. Too big * and we use up memory and run slow.. */ struct symbol { char *name; void *annotation; struct symbol *next; }; struct symbol_table { int count; gp_boolean case_insensitive; int (*compare)(const char *__s1, const char *__s2); struct symbol *hash_table[HASH_SIZE]; struct symbol_table *prev; }; struct symbol_table *push_symbol_table(struct symbol_table *, gp_boolean case_insensitive); struct symbol_table *pop_symbol_table(struct symbol_table *); struct symbol *add_symbol(struct symbol_table *, char *name); int remove_symbol(struct symbol_table *table, char *name); struct symbol *get_symbol(struct symbol_table *, char *name); void annotate_symbol(struct symbol *, void *); char *get_symbol_name(struct symbol *); void *get_symbol_annotation(struct symbol *); int symbol_compare(const void *p0, const void *p1); #endif gputils-0.13.7/libgputils/libgputils.h0000644000175000017500000000245211156313233014720 00000000000000/* libgputils header Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __LIBGPUTILS_H__ #define __LIBGPUTILS_H__ /* library files */ #include #include #include /* common files */ #include #include #include #include #include #include #include /* COFF files */ #include #include #include #include #include #include #include /* COD files */ #include #endif gputils-0.13.7/libgputils/gpmessage.c0000644000175000017500000000440511156313233014510 00000000000000/* messaging functions Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #ifdef STDC_HEADERS #include #endif gp_boolean gp_quiet = false; gp_boolean gp_message_disable = false; gp_boolean gp_debug_disable = true; int gp_num_errors = 0; int gp_num_warnings = 0; int gp_num_messages = 0; void gp_error(const char *format, ...) { va_list args; char buffer[BUFSIZ]; if (gp_message_disable) return; gp_num_errors++; if (gp_quiet) return; va_start(args, format); vsnprintf(buffer, sizeof(buffer), format, args); va_end(args); printf("%s %s\n", "error:", buffer); return; } void gp_warning(const char *format, ...) { va_list args; char buffer[BUFSIZ]; if (gp_message_disable) return; gp_num_warnings++; if (gp_quiet) return; va_start(args, format); vsnprintf(buffer, sizeof(buffer), format, args); va_end(args); printf("%s %s\n", "warning:", buffer); return; } void gp_message(const char *format, ...) { va_list args; char buffer[BUFSIZ]; if (gp_message_disable) return; gp_num_messages++; if (gp_quiet) return; va_start(args, format); vsnprintf(buffer, sizeof(buffer), format, args); va_end(args); printf("%s %s\n", "message:", buffer); return; } void gp_debug(const char *format, ...) { va_list args; char buffer[BUFSIZ]; if (gp_debug_disable) return; if (gp_quiet) return; va_start(args, format); vsnprintf(buffer, sizeof(buffer), format, args); va_end(args); printf("%s %s\n", "debug:", buffer); return; } gputils-0.13.7/libgputils/gpreadobj.c0000644000175000017500000003770611156521302014502 00000000000000/* Read coff objects Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" gp_coff_type gp_identify_coff_file(char *filename) { FILE *file; char magic[SARMAG + 1]; if ( (file = fopen(filename,"rb")) == NULL ) { return sys_err_file; } /* Read the magic number. Archive magic numbers are longest, so read their size */ fread(&magic[0], 1, SARMAG, file); fclose(file); if (((magic[1]<<8) + magic[0]) == MICROCHIP_MAGIC_v1) return object_file; if (((magic[1]<<8) + magic[0]) == MICROCHIP_MAGIC_v2) return object_file_v2; if (strncmp(magic, ARMAG, SARMAG) == 0) return archive_file; return unknown_file; } /* Read a binary file and store it in memory. */ gp_binary_type * gp_read_file(char *filename) { FILE *infile; gp_binary_type *file; infile = fopen(filename,"rb"); if (infile == NULL) { perror(filename); exit(1); } file = (gp_binary_type *)malloc(sizeof(*file)); /* determine the size of the file */ fseek(infile, 0, SEEK_END); file->size = ftell(infile); rewind(infile); /* read the object file into memory */ file->file = (char *)malloc(file->size); fread(file->file, 1, file->size, infile); fclose(infile); return file; } /* free a binary file. */ void gp_free_file(gp_binary_type *file) { if (file == NULL) return; free(file->file); free(file); return; } static void _read_file_header(gp_object_type *object, char *file) { int isnew = 0; if (gp_getl16(&file[0]) == MICROCHIP_MAGIC_v2) isnew = 1; else if (gp_getl16(&file[0]) != MICROCHIP_MAGIC_v1) gp_error("invalid magic number in \"%s\"", object->filename); object->isnew = isnew; object->version = gp_getl16(&file[0]); object->num_sections = gp_getl16(&file[2]); object->time = gp_getl32(&file[4]); object->symbol_ptr = gp_getl32(&file[8]); object->num_symbols = gp_getl32(&file[12]); if (gp_getl16(&file[16]) != (isnew ? OPT_HDR_SIZ_v2 : OPT_HDR_SIZ_v1) ) gp_error("incorrect optional header size in \"%s\"", object->filename); object->symbol_size = (object->version == MICROCHIP_MAGIC_v1 ? SYMBOL_SIZE_v1 : SYMBOL_SIZE_v2); object->flags = gp_getl16(&file[18]); } static void _read_opt_header(gp_object_type *object, char *file) { unsigned short optmagic; unsigned long vstamp, proc_code, rom_width, ram_width; size_t offset = 0; optmagic = gp_getl16(&file[0]); if (optmagic != (object->isnew ? OPTMAGIC_v2 : OPTMAGIC_v1)) gp_error("invalid optional magic number (%#04x) in \"%s\"", optmagic, object->filename); offset = 2; if (object->isnew) { vstamp = gp_getl32(&file[offset]); offset += 4; } else { vstamp = gp_getl16(&file[offset]); offset += 2; } if (!object->isnew && vstamp != 1) gp_error("invalid assembler version (%ld) in \"%s\"", vstamp, object->filename); proc_code = gp_getl32(&file[offset]); offset += 4; rom_width = gp_getl32(&file[offset]); offset += 4; object->processor = gp_processor_coff_proc(proc_code); if (object->processor == no_processor) { /* Fallback to a generic processor of matching rom width */ switch(rom_width) { case 8: object->processor = gp_find_processor("pic18cxx"); break; case 12: object->processor = gp_find_processor("pic16c5x"); break; case 14: object->processor = gp_find_processor("pic16cxx"); break; case 16: object->processor = gp_find_processor("pic17cxx"); break; } if (object->processor == no_processor) gp_error("invalid processor type (%#04lx) in \"%s\"", proc_code, object->filename); else gp_warning("unknown processor type (%#04lx) in \"%s\" defaulted to %s", proc_code, object->filename, gp_processor_name(object->processor, 0)); } object->class = gp_processor_class(object->processor); if (gp_processor_rom_width(object->class) != rom_width) gp_error("invalid rom width for selected processor (%ld) in \"%s\"", rom_width, object->filename); ram_width = gp_getl32(&file[offset]); if (ram_width != 8) gp_error("invalid ram width (%ld) in \"%s\"", ram_width, object->filename); offset += 4; } static void _read_section_header(gp_object_type *object, gp_section_type *section, char *file, char *string_table) { char buffer[9]; unsigned int offset; if (gp_getl32(&file[0]) == 0) { /* read name from the string table */ offset = gp_getl32(&file[4]); section->name = strdup(&string_table[offset]); } else { strncpy(buffer, &file[0], 8); /* the name can occupy all 8 chars without a null terminator */ buffer[8] = '\0'; section->name = strdup(buffer); } section->symbol = gp_coffgen_findsymbol(object, section->name); section->address = gp_getl32(&file[8]); if (section->address != gp_getl32(&file[12])) gp_error("virtual address does not equal physical address in \"%s\"", object->filename); section->size = gp_getl32(&file[16]); section->data_ptr = gp_getl32(&file[20]); section->reloc_ptr = gp_getl32(&file[24]); section->lineno_ptr = gp_getl32(&file[28]); section->num_reloc = gp_getl16(&file[32]); section->num_lineno = gp_getl16(&file[34]); section->flags = gp_getl32(&file[36]); section->data = i_memory_create(); section->relocations = NULL; section->relocations_tail = NULL; section->line_numbers = NULL; section->line_numbers_tail = NULL; section->is_used = false; } static void _read_reloc(gp_object_type *object, gp_section_type *section, gp_reloc_type *relocation, char *file) { relocation->address = gp_getl32(&file[0]); relocation->symbol = &object->symbols[gp_getl32(&file[4])]; relocation->offset = gp_getl16(&file[8]); relocation->type = gp_getl16(&file[10]); if (relocation->address > section->size) gp_error("relocation at address %#x in section \"%s\" of \"%s\" exceeds the section size", relocation->address, section->name, object->filename); } static void _read_lineno(gp_object_type *object, gp_linenum_type *line_number, char *file) { line_number->symbol = &object->symbols[gp_getl32(&file[0])]; line_number->line_number = gp_getl16(&file[4]); line_number->address = gp_getl32(&file[6]); /* FIXME: function index and flags are unused, so far. line_number->l_flags = gp_getl16(&file[10]); line_number->l_fcnndx = gp_getl32(&file[12]); */ } static void _read_sections(gp_object_type *object, char *file) { int i, j; char *section_ptr; char *string_table; char *loc; gp_section_type *current = NULL; gp_reloc_type *current_reloc = NULL; gp_linenum_type *current_linenum = NULL; unsigned int number; unsigned int value; int org; /* move to the start of the section headers */ section_ptr = file + (object->isnew ? (FILE_HDR_SIZ_v2 + OPT_HDR_SIZ_v2) : (FILE_HDR_SIZ_v1 + OPT_HDR_SIZ_v1)); /* setup pointer to string table */ string_table = &file[object->symbol_ptr + (object->symbol_size * object->num_symbols)]; object->sections = gp_coffgen_blocksec(object->num_sections); current = object->sections; for (i = 0; i < object->num_sections; i++) { _read_section_header(object, current, section_ptr, string_table); current->number = i + 1; section_ptr += (object->isnew ? SEC_HDR_SIZ_v2 : SEC_HDR_SIZ_v1); /* read the data */ if ((current->size) && (current->data_ptr)) { if ((object->class == PROC_CLASS_PIC16E) && ((current->flags & STYP_TEXT) || (current->flags & STYP_DATA_ROM))) org = current->address >> 1; else org = current->address; loc = &file[current->data_ptr]; if ((current->flags & STYP_TEXT) || (current->flags & STYP_DATA_ROM)) { /* * original comment: size is in bytes, but words are stored in memory * * this is true, but when using code_pack sections can have an odd * size. it looks like what MPLAB does is set the odd byte to 0xff in * program memory, and it doesn't seem to allow two code pack sections * to straddle a non-word boundary. */ number = (current->size + 1) / 2; } else { number = current->size; } for (j = 0; j < number; j++) { if ((current->flags & STYP_TEXT) || (current->flags & STYP_DATA_ROM)) { if (j + 1 == number && current->size % 2 != 0) { /* an odd byte - use 0xff for the lower half, ala MPLAB */ value = 0xff00 | loc[j * 2]; } else { value = (unsigned int)gp_getl16(&loc[j * 2]); } } else { value = (unsigned int)loc[j]; } i_memory_put(current->data, org + j, MEM_USED_MASK | value); } } /* read the relocations */ if ((current->num_reloc) && (current->reloc_ptr)) { loc = &file[current->reloc_ptr]; number = current->num_reloc; current->relocations = gp_coffgen_blockrel(number); current_reloc = current->relocations; for (j = 0; j < number; j++) { _read_reloc(object, current, current_reloc, loc); loc += RELOC_SIZ; current->relocations_tail = current_reloc; current_reloc = current_reloc->next; } } /* read the line numbers */ if ((current->num_lineno) && (current->lineno_ptr)) { loc = &file[current->lineno_ptr]; number = current->num_lineno; current->line_numbers = gp_coffgen_blockline(number); current_linenum = current->line_numbers; for (j = 0; j < number; j++) { _read_lineno(object, current_linenum, loc); loc += LINENO_SIZ; current->line_numbers_tail = current_linenum; current_linenum = current_linenum->next; } } object->sections_tail = current; current = current->next; } } static void _read_aux(gp_object_type *object, gp_aux_type *aux, int aux_type, char *file, char *string_table) { aux->type = aux_type; switch (aux_type) { case AUX_DIRECT: aux->_aux_symbol._aux_direct.command = file[0]; aux->_aux_symbol._aux_direct.string = strdup(&string_table[gp_getl32(&file[4])]); break; case AUX_FILE: aux->_aux_symbol._aux_file.filename = strdup(&string_table[gp_getl32(&file[0])]); aux->_aux_symbol._aux_file.line_number = gp_getl32(&file[4]); break; case AUX_IDENT: aux->_aux_symbol._aux_ident.string = strdup(&string_table[gp_getl32(&file[0])]); break; case AUX_SCN: aux->_aux_symbol._aux_scn.length = gp_getl32(&file[0]); aux->_aux_symbol._aux_scn.nreloc = gp_getl16(&file[4]); aux->_aux_symbol._aux_scn.nlineno = gp_getl16(&file[6]); break; default: memcpy(&aux->_aux_symbol.data[0], file, object->symbol_size); } } static void _read_symbol(gp_object_type *object, gp_symbol_type *symbol, char *file, char *string_table) { char buffer[9]; unsigned int offset; size_t file_off = 0; if (gp_getl32(&file[0]) == 0) { /* read name from the string table */ offset = gp_getl32(&file[4]); symbol->name = strdup(&string_table[offset]); } else { strncpy(buffer, &file[0], 8); /* the name can occupy all 8 chars without a null terminator */ buffer[8] = '\0'; symbol->name = strdup(buffer); } file_off = 8; symbol->value = gp_getl32(&file[file_off]); file_off += 4; symbol->section_number = gp_getl16(&file[file_off]); file_off += 2; if(object->isnew) { symbol->type = gp_getl32(&file[file_off]); file_off += 4; } else { symbol->type = gp_getl16(&file[file_off]); file_off += 2; } symbol->class = file[file_off]; file_off += 1; symbol->num_auxsym = file[file_off]; file_off += 1; symbol->section = NULL; symbol->aux_list = NULL; } static void _read_symtbl(gp_object_type *object, char *file) { int i; int j; int number = object->num_symbols; int num_auxsym; int aux_type; gp_symbol_type *current = NULL; gp_aux_type *current_aux = NULL; char *string_table; if (number != 0) { /* create a block of symbols */ object->symbols = gp_coffgen_blocksym(number); /* setup pointer to string table */ string_table = &file[object->symbol_ptr + (object->symbol_size * number)]; /* read the symbols */ file = &file[object->symbol_ptr]; current = object->symbols; for (i = 0; i < number; i++) { /* read the symbol */ _read_symbol(object, current, file, string_table); current->number = i; num_auxsym = current->num_auxsym; file += object->symbol_size; if (num_auxsym != 0) { current->aux_list = gp_coffgen_blockaux(current->num_auxsym); current_aux = current->aux_list; aux_type = gp_determine_aux(current); /* read the aux symbols */ for (j = 0; j < num_auxsym; j++) { _read_aux(object, current_aux, aux_type, file, string_table); current_aux = current_aux->next; file += object->symbol_size; i++; } /* advance the through the list */ for (j = 0; j < num_auxsym; j++) { /* COFF places all symbols inluding auxiliary, in the symbol table. However, in memory, gputils attaches auxiliary symbols to their associated primary symbol. When reading COFF, space is reserved for the auxiliary symbols but not used. Later the space is freed. This simplifies assigning the pointer in the relocations. */ current = current->next; } } current = current->next; } } } /* remove space reserved for auxiliary entries, add section pointers, and setup tail pointer */ static void _clean_symtbl(gp_object_type *object) { gp_symbol_type *current = NULL; gp_symbol_type *next_symbol = NULL; gp_symbol_type *old_symbol = NULL; unsigned int i; current = object->symbols; while (current != NULL) { /* assign section pointer, section numbers start at 1 not 0 */ if (current->section_number > 0) current->section = &object->sections[current->section_number - 1]; else current->section = NULL; if (current->num_auxsym != 0) { next_symbol = current->next; for (i = 0; i < current->num_auxsym; i++) { old_symbol = next_symbol; next_symbol = next_symbol->next; /* FIXME: Can't free the single symbols because they were allocated in blocks. This won't be a problem once obstacks are used. free(old_symbol); */ } current->next = next_symbol; } object->symbols_tail = current; current = current->next; } } gp_object_type * gp_convert_file(char *filename, char *file) { gp_object_type *object; /* initialize object file */ object = gp_coffgen_init(); object->filename = strdup(filename); /* read the object */ _read_file_header(object, file); _read_opt_header(object, file + (object->isnew ? FILE_HDR_SIZ_v2 : FILE_HDR_SIZ_v1)); _read_symtbl(object, file); _read_sections(object, file); _clean_symtbl(object); return object; } gp_object_type * gp_read_coff(char *filename) { gp_binary_type *file; gp_object_type *object; file = gp_read_file(filename); if (file == NULL) return NULL; object = gp_convert_file(filename, file->file); gp_free_file(file); return object; } gputils-0.13.7/libgputils/gpcoffopt.c0000644000175000017500000000552711156521302014530 00000000000000/* GNU PIC coff optimizing functions Copyright (C) 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* Remove any weak symbols in the object. */ void gp_coffopt_remove_weak(gp_object_type *object) { gp_symbol_type *symbol; gp_debug("removing weak symbols from %s", object->filename); /* Search the symbol table for extern symbols. */ symbol = object->symbols; while (symbol != NULL) { if ((symbol->class == C_EXT) && (symbol->section_number == N_UNDEF) && (!gp_coffgen_has_reloc(object, symbol))) { gp_debug(" removed weak symbol \"%s\"", symbol->name); gp_coffgen_delsymbol(object, symbol); } symbol = symbol->next; } return; } /* Remove any relocatable section that doesn't have a symbol pointed to by a relocation. */ void gp_coffopt_remove_dead_sections(gp_object_type *object, int pass) { gp_section_type *section; gp_reloc_type *relocation; gp_boolean section_removed = false; gp_debug("removing dead sections pass %i", pass); section = object->sections; while (section != NULL) { /* mark all sections as unused */ section->is_used = false; section = section->next; } section = object->sections; while (section != NULL) { /* mark all sections that relocations point to as unused */ relocation = section->relocations; while (relocation != NULL) { if (relocation->symbol->section) relocation->symbol->section->is_used = true; else gp_warning("relocation symbol %s has no section", relocation->symbol->name); relocation = relocation->next; } section = section->next; } section = object->sections; while (section != NULL) { /* FIXME: maybe don't remove if it is in protected memory */ if ((!section->is_used) && !(section->flags & STYP_ABS)) { gp_debug("removing section %s", section->name); gp_coffgen_delsectionsyms(object, section); gp_coffgen_delsection(object, section); section_removed = true; } section = section->next; } if (section_removed) { /* take another pass */ gp_coffopt_remove_dead_sections(object, pass++); } return; } gputils-0.13.7/libgputils/gpcofflink.c0000644000175000017500000013112011156313233014652 00000000000000/* GNU PIC coff linker functions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" gp_boolean gp_relocate_to_shared = false; /* Two symbol tables are constructed. The first contains the definitions of all external symbols in all the object files. This symbol table is used for relocation and linking. The second table contains all external symbols that do not yet have a definition. This table is used to determine which objects in a library are to be linked against. This table should be empty at the begining of the relocation process. */ void gp_link_add_symbol(struct symbol_table *table, gp_symbol_type *symbol, gp_object_type *file) { struct symbol *sym; gp_coffsymbol_type *var; /* Search the for the symbol. If not found, then add it to the global symbol table. */ sym = get_symbol(table, symbol->name); if (sym != NULL) return; sym = add_symbol(table, symbol->name); var = malloc(sizeof(*var)); var->symbol = symbol; var->file = file; annotate_symbol(sym, var); return; } void gp_link_remove_symbol(struct symbol_table *table, char *name) { struct symbol *sym; gp_coffsymbol_type *var; sym = get_symbol(table, name); if (sym == NULL) return; var = get_symbol_annotation(sym); free(var); remove_symbol(table, name); return; } /* Add the external symbols from an object file to the appropriate symbol tables. NOTE: The missing symbol table is optional. This feature is not used for generating symbol indexes for archives. */ int gp_link_add_symbols(struct symbol_table *definition, struct symbol_table *missing, gp_object_type *object) { gp_symbol_type *symbol = NULL; struct symbol *sym; gp_coffsymbol_type *var; if ((definition == NULL) || (object == NULL)) return 1; symbol = object->symbols; while (symbol != NULL ) { /* process all external symbols that are not directives */ if ((symbol->class == C_EXT) && (symbol->name[0] != '.')) { if (symbol->section_number == 0) { /* This symbol is defined elsewhere. Check for it in the symbol definitions. If it doesn't exist there, add it to the missing symbol table, if not already entered. */ sym = get_symbol(definition, symbol->name); if ((sym == NULL) && (missing != NULL)) gp_link_add_symbol(missing, symbol, object); } else { /* External symbol definition. See if it is already defined, it so it is an error. Add the symbol to the symbol definitions and remove it from the missing symbol table if it exists there */ sym = get_symbol(definition, symbol->name); if (sym != NULL) { /* duplicate symbol */ var = get_symbol_annotation(sym); gp_error("duplicate symbol \"%s\" defined in \"%s\" and \"%s\"", symbol->name, var->file->filename, object->filename); } else { gp_link_add_symbol(definition, symbol, object); } if (missing != NULL) gp_link_remove_symbol(missing, symbol->name); } } symbol = symbol->next; } return 0; } /* Combine all sections and symbols from all objects into one object file. */ void gp_cofflink_combine_objects(gp_object_type *object) { gp_object_type *list; /* assign the time the operation occured */ object->time = (long)time(NULL); /* combine the symbol tables */ list = object->next; while (list != NULL) { if (list->num_symbols != 0) { if (object->num_symbols == 0) { /* The object has no symbols */ object->symbols = list->symbols; } else { /* Append the symbols from the second object to the first */ object->symbols_tail->next = list->symbols; } object->symbols_tail = list->symbols_tail; object->num_symbols += list->num_symbols; } list = list->next; } /* append the sections onto the list */ list = object->next; while (list != NULL) { if (list->num_sections != 0) { if (object->num_sections == 0) { /* The object has no sections */ object->sections = list->sections; } else { /* Append the sections from the second object to the first */ object->sections_tail->next = list->sections; } object->sections_tail = list->sections_tail; object->num_sections += list->num_sections; } list = list->next; } /* FIXME: breaking the chain isn't good */ object->next = NULL; return; } /* Cleanup the symbol table after combining objects. */ void gp_cofflink_clean_table(gp_object_type *object, struct symbol_table *symbols) { gp_section_type *section = object->sections; gp_reloc_type *relocation; gp_symbol_type *symbol; gp_coffsymbol_type *var; struct symbol *sym; gp_symbol_type *previous = NULL; gp_debug("cleaning symbol table"); /* point all relocations to the symbol definitions */ while (section != NULL) { relocation = section->relocations; while (relocation != NULL) { symbol = relocation->symbol; if ((symbol->class == C_EXT) && (symbol->section_number == N_UNDEF)) { /* This is an external symbol defined elsewhere */ sym = get_symbol(symbols, symbol->name); assert(sym != NULL); var = get_symbol_annotation(sym); assert(var != NULL); relocation->symbol = var->symbol; } relocation = relocation->next; } section = section->next; } symbol = object->symbols; while (symbol != NULL) { if ((symbol->class == C_EXT) && (symbol->section_number == N_UNDEF)) { /* This is an external symbol defined elsewhere */ if (previous == NULL) { /* removing first symbol in the list */ object->symbols = object->symbols->next; } else { previous->next = symbol->next; } gp_debug(" removed symbol \"%s\"", symbol->name); object->num_symbols--; } else { previous = symbol; } symbol = symbol->next; } return; } /* Update the line number offsets */ static void _update_line_numbers(gp_linenum_type *line_number, int offset) { while (line_number != NULL) { line_number->address += offset; line_number = line_number->next; } } /* Combine overlay sections in an object file. */ void gp_cofflink_combine_overlay(gp_object_type *object, int remove_symbol) { gp_section_type *first = NULL; gp_section_type *second = NULL; gp_symbol_type *symbol = NULL; first = object->sections; while (first != NULL) { if (first->flags & STYP_OVERLAY) { second = gp_coffgen_findsection(object, first->next, first->name); if (second != NULL) { /* The sections must have the same properties or they can't be combined. */ if (first->flags != second->flags) { gp_error("section types for \"%s\" do not match", first->name); continue; } else if ((first->flags & STYP_ABS) && (first->address != second->address)) { gp_error("different addresses for absolute overlay sections \"%s\"", first->name); continue; } /* Set the size of the first section to the larger of the two */ if (second->size > first->size) { first->size = second->size; first->symbol->aux_list->_aux_symbol._aux_scn.length = second->size; } /* Remove the section symbol */ if (remove_symbol) { gp_coffgen_delsymbol(object, second->symbol); } /* Update the symbol table */ symbol = object->symbols; while (symbol != NULL) { if (symbol->section == second) { symbol->section = first; } symbol = symbol->next; } /* Remove the second section*/ gp_coffgen_delsection(object, second); /* Take another pass */ gp_cofflink_combine_overlay(object, remove_symbol); return; } } first = first->next; } return; } /* Allocate memory for a stack */ void gp_cofflink_make_stack(gp_object_type *object, int num_bytes) { gp_section_type *new = NULL; int i; gp_symbol_type *symbol; new = gp_coffgen_addsection(object, ".stack"); new->flags = STYP_BSS; new->size = num_bytes; gp_debug("allocating stack memory of size %#x", num_bytes); /* mark the memory locations as used */ for (i = 0; i < num_bytes; i++) { i_memory_put(new->data, i, MEM_USED_MASK); } /* create the symbol for the start address of the stack */ symbol = gp_coffgen_findsymbol(object, "_stack"); if ((symbol != NULL) && (symbol->section_number > 0)) { gp_error("_stack symbol already exists"); } else { symbol = gp_coffgen_addsymbol(object); symbol->name = strdup("_stack"); symbol->value = 0; symbol->section_number = 1; symbol->section = new; symbol->type = T_NULL; symbol->class = C_EXT; } /* create the symbol for the end of the stack */ symbol = gp_coffgen_findsymbol(object, "_stack_end"); if ((symbol != NULL) && (symbol->section_number > 0)) { gp_error("_stack_end symbol already exists"); } else { symbol = gp_coffgen_addsymbol(object); symbol->name = strdup("_stack_end"); symbol->value = num_bytes - 1; symbol->section_number = 1; symbol->section = new; symbol->type = T_NULL; symbol->class = C_EXT; } return; } /* Merge all sections in one object file with the same name. The overlayed sections must have been combined first. */ void gp_cofflink_merge_sections(gp_object_type *object, int byte_addr) { gp_section_type *first; gp_section_type *second; gp_symbol_type *symbol = NULL; gp_reloc_type *relocation = NULL; unsigned int org; unsigned int last; unsigned int offset; unsigned int line_offset; unsigned int data; first = object->sections; while (first != NULL) { second = gp_coffgen_findsection(object, first->next, first->name); if (second != NULL) { /* The sections must have the same properties or they can't be combined. */ if ((first->flags & STYP_ABS) || (second->flags & STYP_ABS) || (strcmp(first->name, ".config") == 0) || (strcmp(first->name, ".idlocs") == 0)) { gp_error("section \"%s\" is absolute but occurs in more than one file", first->name); exit(1); } gp_debug(" merging section \"%s\" with section \"%s\"", first->name, second->name); /* Update the addresses in the relocation table */ relocation = second->relocations; while (relocation != NULL) { relocation->address += first->size; relocation = relocation->next; } /* Update the section symbol for the section symbol */ second->symbol->value = first->size; /* Copy the section data */ if ((second->flags & STYP_TEXT) || (second->flags & STYP_DATA_ROM)) { /* the section is executable, so each word is two bytes */ last = second->size / 2; offset = first->size / 2; if (byte_addr) { line_offset = first->size; } else { line_offset = first->size / 2; } } else { /* the section is data, so each word is one byte */ last = second->size; offset = first->size; line_offset = first->size; } if(_has_data(second)) { for (org = 0; org < last; org++) { data = i_memory_get(second->data, org); assert((data & MEM_USED_MASK) != 0); i_memory_put(first->data, org + offset, data); } } /* Update the line number offsets */ _update_line_numbers(second->line_numbers, line_offset); /* Update the symbol table */ symbol = object->symbols; while (symbol != NULL) { if ((symbol->section_number > 0) && (symbol->section == second)) { symbol->section = first; symbol->value += line_offset; } symbol = symbol->next; } /* Add section sizes */ first->size += second->size; /* Append the relocations from the second section to the first */ if (second->num_reloc != 0) { if (first->num_reloc == 0) { first->relocations = second->relocations; } else { first->relocations_tail->next = second->relocations; } first->num_reloc += second->num_reloc; first->relocations_tail = second->relocations_tail; } /* Append the line numbers from the second section to the first. */ if (second->num_lineno != 0) { if (first->num_lineno == 0) { first->line_numbers = second->line_numbers; } else { first->line_numbers_tail->next = second->line_numbers; } first->num_lineno += second->num_lineno; first->line_numbers_tail = second->line_numbers_tail; } /* Remove the second section*/ gp_coffgen_delsection(object, second); /* Take another pass */ gp_cofflink_merge_sections(object, byte_addr); return; } first = first->next; } return; } /* copy data from idata section to the ROM section */ static void _copy_rom_section(gp_object_type *object, gp_section_type *idata, gp_section_type *rom) { int insn; int data; int from; int to; int last; if (object->class == PROC_CLASS_PIC16E) { to = rom->address >> 1; } else { to = rom->address; } last = idata->address + idata->size; if (object->class == PROC_CLASS_PIC16E) { insn = MEM_USED_MASK; for (from = idata->address; from < last; from += 2) { data = (i_memory_get(idata->data, from) & 0xff); data |= ((i_memory_get(idata->data, from + 1) & 0xff) << 8); i_memory_put(rom->data, to++, insn | data); } } else { /* select "retlw" instruction */ insn = MEM_USED_MASK | gp_processor_retlw(object->class); for (from = idata->address; from < last; from++) { data = (i_memory_get(idata->data, from) & 0xff); i_memory_put(rom->data, to++, insn | data); } } } /* create a program memory section to hold the data */ static void _create_rom_section(gp_object_type *object, gp_section_type *section) { gp_section_type *new = NULL; char name[BUFSIZ]; /* create the new section */ strncpy(name, section->name, sizeof(name)); strncat(name, "_i", sizeof(name)); new = gp_coffgen_newsection(name); if (object->class == PROC_CLASS_PIC16E) { new->size = section->size; /* force the section size to be an even number of bytes */ if (section->size & 1) { new->size++; } } else { new->size = section->size << 1; } new->flags = STYP_DATA_ROM; /* Copy the data to get the MEM_USED_MASK correct. It is copied again later to ensure that any patched data is updated in the ROM section */ _copy_rom_section(object, section, new); /* insert the new ROM section after the idata section */ if (section == object->sections_tail) { object->sections_tail = new; } new->next = section->next; section->next = new; object->num_sections++; return; } /* write a word into two bytes of memory */ static void _write_table_data(gp_section_type *section, int org, int insn, int data) { i_memory_put(section->data, org, insn | (data & 0xff)); i_memory_put(section->data, org + 1, insn | ((data & 0xff00) >> 8)); } /* write a long into four bytes of memory */ static void _write_table_long(gp_section_type *section, int org, int insn, int data) { i_memory_put(section->data, org, insn | (data & 0xffff)); i_memory_put(section->data, org + 1, insn | ((data & 0xffff0000) >> 16)); } /* read a word into two bytes of memory */ static int _read_table_data(gp_section_type *section, int org) { int data; data = i_memory_get(section->data, org) & 0xff; data |= ((i_memory_get(section->data, org + 1) & 0xff) << 8); return data; } /* create the symbol for the start address of the table */ void gp_cofflink_make_cinit(gp_object_type *object) { gp_symbol_type *symbol; /* create the symbol for the start address of the table */ symbol = gp_coffgen_findsymbol(object, "_cinit"); if ((symbol != NULL) && (symbol->section_number > 0)) { gp_error("_cinit symbol already exists"); } else { symbol = gp_coffgen_addsymbol(object); symbol->name = strdup("_cinit"); symbol->value = 0; symbol->section_number = 1; symbol->section = NULL; symbol->type = T_NULL; symbol->class = C_EXT; } return; } /* create ROM data for initialized data sections */ void gp_cofflink_make_idata(gp_object_type *object) { gp_section_type *section = object->sections; gp_section_type *new = NULL; int count = 0; int word_count; int i; int insn; gp_symbol_type *symbol; while (section != NULL) { if (section->flags & STYP_DATA) { _create_rom_section(object, section); count++; } section = section->next; } if (count) { new = gp_coffgen_addsection(object, ".cinit"); new->flags = STYP_DATA_ROM; word_count = (count * 6); if (object->class == PROC_CLASS_PIC16E) { word_count += 1; } else { /* retlw is used so the count is stored in 4 bytes not 2 */ word_count += 2; } new->size = word_count << 1; /* load the table with data */ for (i = 0; i < word_count; i++) { i_memory_put(new->data, i, MEM_USED_MASK); } if (object->class == PROC_CLASS_PIC16E) { i_memory_put(new->data, 0, MEM_USED_MASK | count); } else { insn = MEM_USED_MASK | gp_processor_retlw(object->class); _write_table_data(new, 0, insn, count); } /* update the section pointer in _cinit */ symbol = gp_coffgen_findsymbol(object, "_cinit"); assert(symbol != NULL); symbol->section = new; } return; } /* load the relocated sections addresses in the table */ void gp_add_cinit_section(gp_object_type *object, int byte_addr) { gp_section_type *section; gp_section_type *new = NULL; gp_section_type *prog_section = NULL; char prog_name[BUFSIZ]; int insn; int count; int base_org; int number; new = gp_coffgen_findsection(object, object->sections, ".cinit"); if (new != NULL) { /* scan through the sections to determine the addresses */ count = 0; base_org = new->address >> byte_addr; if (object->class == PROC_CLASS_PIC16E) { base_org += 1; insn = MEM_USED_MASK; } else { base_org += 2; insn = MEM_USED_MASK | gp_processor_retlw(object->class); } section = object->sections; while (section != NULL) { if (section->flags & STYP_DATA) { /* locate the rom table */ strncpy(prog_name, section->name, sizeof(prog_name)); strncat(prog_name, "_i", sizeof(prog_name)); prog_section = gp_coffgen_findsection(object, object->sections, prog_name); if (object->class == PROC_CLASS_PIC16E) { /* write program memory address */ _write_table_long(new, base_org, insn, prog_section->address); /* write data memory address */ _write_table_long(new, base_org + 2, insn, section->address); /* write the table size */ _write_table_long(new, base_org + 4, insn, section->size); } else { /* write program memory address */ _write_table_data(new, base_org, insn, prog_section->address); /* write data memory address */ _write_table_data(new, base_org + 2, insn, section->address); /* write the table size */ _write_table_data(new, base_org + 4, insn, section->size); } count++; base_org += 6; } section = section->next; } /* make sure the section count matches */ if (object->class == PROC_CLASS_PIC16E) { number = i_memory_get(new->data, new->address >> byte_addr) & 0xffff; } else { number = _read_table_data(new, new->address >> byte_addr); } assert(number == count); } return; } /* Set the memory used flags in a block of words */ static void _set_used(MemBlock *m, int byte_addr, unsigned int address, unsigned int size) { unsigned int org; unsigned int stop; unsigned int data; org = address >> byte_addr; stop = org + size; gp_debug(" marking %#x words from %#x to %#x as used", size, org, (stop - 1)); for ( ; org < stop; org++) { data = i_memory_get(m, org); if (data & MEM_USED_MASK) { gp_error("multiple sections using address %#lx", org << byte_addr); return; } else { i_memory_put(m, org, MEM_USED_MASK); } } return; } /* allocate space for the absolute sections */ void gp_cofflink_reloc_abs(MemBlock *m, int byte_addr, gp_section_type *section, unsigned long flags) { unsigned int size; while (section != NULL) { if ((section->flags & STYP_ABS) && (section->flags & flags)) { if ((section->flags & STYP_TEXT) || (section->flags & STYP_DATA_ROM)) { /* size is in bytes, but words are stored in memory */ size = section->size / 2; } else { size = section->size; } _set_used(m, byte_addr, section->address, size); /* Set the relocated flag */ section->flags |= STYP_RELOC; } section = section->next; } } /* Search through all the sections in the object list. Locate the biggest assigned section that has not been relocated. */ static gp_section_type * gp_cofflink_find_big_assigned(gp_section_type *section, unsigned long flags, struct symbol_table *logical_sections) { gp_section_type *biggest = NULL; struct symbol *sym; while (section != NULL) { sym = get_symbol(logical_sections, section->name); if ((sym != NULL) && (section->flags & flags) && !(section->flags & STYP_RELOC)) { /* This section has not been relocated */ if ((biggest == NULL) || (section->size > biggest->size)) { biggest = section; } } section = section->next; } return biggest; } /* Search through all the sections in the object list. Locate the biggest section that has not been relocated. */ static gp_section_type * gp_cofflink_find_big_section(gp_section_type *section, unsigned long flags) { gp_section_type *biggest = NULL; while (section != NULL) { if ((section->flags & flags) && !(section->flags & STYP_RELOC)) { /* This section has not been relocated */ if ((biggest == NULL) || (section->size > biggest->size)) { biggest = section; } } section = section->next; } if (biggest != NULL) { gp_debug(" biggest section = %s, section flags = %#x, flags = %#x", biggest->name, biggest->flags, flags); } return biggest; } /* Search through the target memory. Locate the smallest block of memory that is larger than the requested size. Return the address of that block */ static int _search_memory(MemBlock *m, int byte_addr, unsigned int start, unsigned int stop, unsigned int size, unsigned int *block_address, unsigned int *block_size) { unsigned int org; unsigned int current_address = 0; unsigned int current_size = 0; int mem_used; int in_block = 0; int end_block = 0; int success = 0; /* data is stored as words in memory */ start = start >> byte_addr; stop = stop >> byte_addr; /* set the size to max value */ *block_size = 0xffffffff; for (org = start; org <= stop; org++) { mem_used = i_memory_get(m, org) & MEM_USED_MASK; if (org == stop) { if (in_block == 1) { /* end of the section definition */ end_block = 1; /* increment for last address */ current_size++; } else if (start == stop) { /* special case, one word section */ if (!mem_used) { end_block = 1; current_address = start; current_size = 1; } } in_block = 0; } else if (mem_used) { if (in_block == 1) { /* end of an unused block of memory */ end_block = 1; } in_block = 0; } else { if (in_block == 0) { /* start of an unused block of memory */ gp_debug(" start unused block at %#x", org); current_address = org; current_size = 1; } else { /* continuation of an unused block of memory */ current_size++; } in_block = 1; } if (end_block == 1) { gp_debug(" end unused block at %#x with size %#x", org, current_size); if ((current_size >= size) && (current_size < *block_size)) { *block_size = current_size; *block_address = current_address; success = 1; } end_block = 0; } } return success; } /* Move data in i_memory. This function assumes the move will be towards a higher address. */ static void _move_data(MemBlock *m, unsigned int address, unsigned int size, unsigned int new_address) { int org; unsigned int data; if (address == new_address) return; gp_debug(" moving %#x words from %#x to %#x", size, address, new_address); for (org = address + size - 1; org >= 0; org--) { data = i_memory_get(m, org); gp_debug(" moving word %#x from %#x to %#x", data, org, new_address + org); assert(data & MEM_USED_MASK); i_memory_put(m, org, 0x0); i_memory_put(m, new_address + org, data); } return; } /* allocate memory for relocatable assigned sections */ void gp_cofflink_reloc_assigned(MemBlock *m, int byte_addr, gp_section_type *section, unsigned long flags, struct symbol_table *sections, struct symbol_table *logical_sections) { gp_section_type *current; unsigned int size; struct symbol *sym; char *section_name; struct linker_section *section_def; unsigned int current_address; unsigned int current_size; while (1) { current = gp_cofflink_find_big_assigned(section, flags, logical_sections); if (current == NULL) break; if ((current->flags & STYP_TEXT) || (current->flags & STYP_DATA_ROM)) { /* size is in bytes, but words are stored in memory */ size = current->size / 2; } else { size = current->size; } /* Fetch the logical section */ sym = get_symbol(logical_sections, current->name); assert(sym != NULL); /* Fetch the section definition */ section_name = get_symbol_annotation(sym); sym = get_symbol(sections, section_name); assert(sym != NULL); section_def = get_symbol_annotation(sym); assert(section_def != NULL); /* assign the address to this section */ if (_search_memory(m, byte_addr, section_def->start, section_def->end, size, ¤t_address, ¤t_size) == 1) { gp_debug(" successful relocation to %#x", current_address); if (_has_data(current)) { _move_data(current->data, current->address, size, current_address); } current->address = current_address << byte_addr; _set_used(m, 0, current_address, size); /* Update the line number offsets */ _update_line_numbers(current->line_numbers, current->address); /* Set the relocated flag */ current->flags |= STYP_RELOC; } else { gp_error("no target memory available for section \"%s\"", current->name); return; } } return; } /* allocate memory for relocatable unassigned sections */ void gp_cofflink_reloc_unassigned(MemBlock *m, int byte_addr, gp_section_type *section, unsigned long flags, struct symbol_table *sections) { gp_section_type *current; enum section_type type; unsigned int size; int first_time; int success; int type_avail; int i; struct symbol *sym; struct linker_section *section_def; unsigned int current_address; unsigned int current_size; unsigned int smallest_address; unsigned int smallest_size; while (1) { current = gp_cofflink_find_big_section(section, flags); if (current == NULL) break; if ((current->flags & STYP_TEXT) || (current->flags & STYP_DATA_ROM)) { /* size is in bytes, but words are stored in memory */ size = current->size / 2; } else { size = current->size; } /* determine what type of sections are being relocated */ if ((current->flags & STYP_TEXT) || (current->flags & STYP_DATA_ROM)) { type = codepage; gp_debug(" relocating code"); } else if (current->flags & STYP_ACCESS) { type = accessbank; gp_debug(" relocating accessbank"); } else if (current->flags & STYP_SHARED) { type = sharebank; gp_debug(" relocating sharebank"); } else { type = databank; gp_debug(" relocating data"); } first_time = 1; next_pass: success = 0; type_avail = 0; smallest_address = 0; smallest_size = 0xffffffff; /* search the section definitions for the smallest block of memory that the section will fit in */ for (i = 0; i < HASH_SIZE; i++) { for (sym = sections->hash_table[i]; sym; sym = sym->next) { section_def = get_symbol_annotation(sym); if ((section_def->type == type) && (!section_def->protected)) { gp_debug(" section = %s", current->name); gp_debug(" size = %#x", current->size); gp_debug(" def start = %#x", section_def->start); gp_debug(" def end = %#x", section_def->end); type_avail = 1; if (_search_memory(m, byte_addr, section_def->start, section_def->end, size, ¤t_address, ¤t_size) == 1) { success = 1; if (smallest_size > current_size) { smallest_size = current_size; smallest_address = current_address; } } } } } /* set the memory used flag for all words in the block */ if (success == 1) { gp_debug(" successful relocation to %#x", smallest_address); if (_has_data(current)) { _move_data(current->data, current->address, size, smallest_address); } current->address = smallest_address << byte_addr; _set_used(m, 0, smallest_address, size); /* Update the line number offsets */ _update_line_numbers(current->line_numbers, current->address); /* Set the relocated flag */ current->flags |= STYP_RELOC; } else if (gp_relocate_to_shared && (first_time == 1) && (type == databank)) { first_time = 0; type = sharebank; gp_warning("relocation of section \"%s\" failed, relocating to a shared memory location", current->name); goto next_pass; } else if (type_avail == 0) { gp_error("linker script has no definition that matches the type of section \"%s\"", current->name); return; } else { gp_error("no target memory available for section \"%s\"", current->name); return; } } return; } /* update all symbols with their new relocated values */ void gp_cofflink_update_table(gp_object_type *object) { gp_symbol_type *symbol = object->symbols; gp_section_type *section = object->sections; gp_debug("updating symbols with their new relocated values"); while (symbol != NULL) { if (symbol->section_number > 0) { assert(symbol->section != NULL); if (!(symbol->section->flags & STYP_ABS)) symbol->value += symbol->section->address; } symbol = symbol->next; } gp_debug("stripping section relocated flag"); while (section != NULL) { section->flags &= ~(STYP_RELOC); section = section->next; } } /* Create sections to fill unused memory in the pages with constant data. */ void gp_cofflink_fill_pages(gp_object_type *object, MemBlock *m, int byte_addr, struct symbol_table *sections) { struct linker_section *section_def; int i; struct symbol *sym; int found; char fill_name[BUFSIZ]; int fill_number = 1; gp_section_type *section = NULL; unsigned int current_address; unsigned int current_size; int org; int end; gp_debug("adding fill sections"); /* search for any section definitions that have a fill */ for (i = 0; i < HASH_SIZE; i++) { for (sym = sections->hash_table[i]; sym; sym = sym->next) { section_def = get_symbol_annotation(sym); if ((section_def->type == codepage) && (section_def->use_fill)) { while (1) { found = _search_memory(m, byte_addr, section_def->start, section_def->end, 1, ¤t_address, ¤t_size); if (found == 1) { snprintf(fill_name, sizeof(fill_name), ".fill_%i", fill_number++); gp_debug(" new section \"%s\" at %#x with size %#x and data %#x", fill_name, current_address, current_size, section_def->fill); section = gp_coffgen_findsection(object, object->sections, fill_name); if (section != NULL) { gp_error("fill section \"%s\" aready exists", fill_name); return; } else { /* create a new section for the fill data */ section = gp_coffgen_addsection(object, fill_name); section->address = current_address; section->size = current_size * 2; /* size in bytes */ section->flags = STYP_TEXT; /* FIXME: do we really need a section symbol? */ /* mark the memory as used */ _set_used(m, byte_addr, current_address, current_size); /* fill the section memory */ org = current_address >> byte_addr; end = org + current_size; for ( ; org <= end; org++) { i_memory_put(section->data, org, MEM_USED_MASK | section_def->fill); } } } else { break; } } } } } return; } static void check_relative(gp_section_type *section, int org, int argument, int range) { /* If the branch is too far then issue a warning */ if ((argument > range) || (argument < -(range+1))) { gp_warning("relative branch out of range in at %#x of section \"%s\"", org << 1, section->name); } return; } /* patch one word with the relocated address */ static void gp_cofflink_patch_addr(enum proc_class class, int num_pages, int num_banks, int bsr_boundary, gp_section_type *section, gp_symbol_type *symbol, gp_reloc_type *relocation) { int org; int upper_byte; int current_value; int data = 0; int value; int offset; int write_data = 1; if (section->flags & STYP_DATA) { /* It is an initialized data section, so everything is bytes */ org = section->address + relocation->address; upper_byte = 0; } else { /* section address are byte addresses */ if (class == PROC_CLASS_PIC16E) { org = section->address >> 1; } else { org = section->address; } /* the relocation address is always a byte address */ org += (relocation->address >> 1); /* the address is odd so put the data in upper byte */ upper_byte = relocation->address & 1; } value = symbol->value + relocation->offset; gp_debug(" patching %#x from %s with %#x", section->address + relocation->address, section->name, value); /* fetch the current contents of the memory */ current_value = i_memory_get(section->data, org); assert(current_value & MEM_USED_MASK); /* FIXME: Not sure if warnings should be generated for out of range arguments. The linker should make sure values are within ranges in the linker scripts. */ switch (relocation->type) { case RELOCT_CALL: switch(class) { case PROC_CLASS_PIC12: case PROC_CLASS_SX: data = value & 0xff; break; case PROC_CLASS_PIC14: data = value & 0x7ff; break; case PROC_CLASS_PIC16: data = value & 0x1fff; break; case PROC_CLASS_PIC16E: data = (value >> 1) & 0xff; break; default: assert(0); } break; case RELOCT_GOTO: switch(class) { case PROC_CLASS_PIC12: case PROC_CLASS_SX: data = value & 0x1ff; break; case PROC_CLASS_PIC14: data = value & 0x7ff; break; case PROC_CLASS_PIC16: data = value & 0x1fff; break; case PROC_CLASS_PIC16E: data = (value >> 1) & 0xff; break; default: assert(0); } break; case RELOCT_HIGH: data = (value >> 8) & 0xff; break; case RELOCT_LOW: data = value & 0xff; break; case RELOCT_P: data = (value & 0x1f) << 8; break; case RELOCT_BANKSEL: { int bank = gp_processor_check_bank(class, value); gp_processor_set_bank(class, num_banks, bank, section->data, org); write_data = 0; } break; case RELOCT_ALL: data = value & 0xffff; break; case RELOCT_IBANKSEL: switch(class) { case PROC_CLASS_PIC14: if (value < 0x100) { /* bcf 0x3, 0x7 */ data = MEM_USED_MASK | 0x1383; } else { /* bsf 0x3, 0x7 */ data = MEM_USED_MASK | 0x1783; } break; case PROC_CLASS_PIC16: /* movlb bank */ data = MEM_USED_MASK | 0xb800 | gp_processor_check_bank(class, value); break; default: assert(0); } break; case RELOCT_F: switch(class) { case PROC_CLASS_PIC12: case PROC_CLASS_SX: data = value & 0x1f; break; case PROC_CLASS_PIC14: data = value & 0x7f; break; case PROC_CLASS_PIC16: case PROC_CLASS_PIC16E: data = value & 0xff; break; default: assert(0); } break; case RELOCT_TRIS: switch(class) { case PROC_CLASS_PIC12: case PROC_CLASS_SX: data = value & 0x1f; break; case PROC_CLASS_PIC14: data = value & 0x7f; break; default: assert(0); } break; case RELOCT_MOVLR: data = (value << 4) & 0xf0; break; case RELOCT_MOVLB: /* The upper byte of the symbol is used for the BSR. This is inconsistent with the datasheet and the assembler, but is done to maintain compatibility with mplink. */ data = (value >> 8) & 0xff; break; case RELOCT_GOTO2: data = (value >> 9) & 0xfff; break; case RELOCT_FF1: data = value & 0xfff; break; case RELOCT_FF2: data = value & 0xfff; break; case RELOCT_LFSR1: data = (value >> 8) & 0xf; break; case RELOCT_LFSR2: data = value & 0xff; break; case RELOCT_BRA: offset = (value - ((org + 1) << 1)) >> 1; check_relative(section, org, offset, 0x3ff); data = offset & 0x7ff; break; case RELOCT_CONDBRA: offset = (value - ((org + 1) << 1)) >> 1; check_relative(section, org, offset, 0x7f); data = offset & 0xff; break; case RELOCT_UPPER: data = (value >> 16) & 0xff; break; case RELOCT_ACCESS: { int a; if ((value < bsr_boundary) || (value >= (0xf00 + bsr_boundary))) { a = 0; } else { a = 1; } data = a << 8; } break; case RELOCT_PAGESEL_WREG: { int page = gp_processor_check_page(class, value); gp_processor_set_page(class, num_pages, page, section->data, org, 1); write_data = 0; } break; case RELOCT_PAGESEL_BITS: { int page = gp_processor_check_page(class, value); gp_processor_set_page(class, num_pages, page, section->data, org, 0); write_data = 0; } break; /* unimplemented relocations */ case RELOCT_PAGESEL: case RELOCT_SCNSZ_LOW: case RELOCT_SCNSZ_HIGH: case RELOCT_SCNSZ_UPPER: case RELOCT_SCNEND_LOW: case RELOCT_SCNEND_HIGH: case RELOCT_SCNEND_UPPER: case RELOCT_SCNEND_LFSR1: case RELOCT_SCNEND_LFSR2: default: gp_error("unimplemented relocation = %i in section \"%s\"", relocation->type, section->name); assert(0); } if (upper_byte) data <<= 8; /* update memory with the new value */ if (write_data) i_memory_put(section->data, org, current_value | data); return; } /* Patch all addresses with the relocated symbols. The relocations are stripped from the sections. */ void gp_cofflink_patch(gp_object_type *object) { gp_section_type *section = object->sections; gp_reloc_type *relocation; gp_symbol_type *symbol; int num_pages; int num_banks; int bsr_boundary = 0; if (object->class == PROC_CLASS_PIC16E) bsr_boundary = gp_processor_bsr_boundary(object->processor); num_pages = gp_processor_num_pages(object->processor); num_banks = gp_processor_num_banks(object->processor); gp_debug("patching data with relocated symbols"); while (section != NULL) { if (_has_data(section)) { /* patch raw data with relocation entries */ relocation = section->relocations; while (relocation != NULL) { symbol = relocation->symbol; gp_cofflink_patch_addr(object->class, num_pages, num_banks, bsr_boundary, section, symbol, relocation); relocation = relocation->next; } /* update the rom with the patched idata sections */ if ((section->flags & STYP_DATA) && (section->num_reloc != 0)) { assert(section->next->flags & STYP_DATA_ROM); _copy_rom_section(object, section, section->next); } /* strip the relocations from the section */ section->num_reloc = 0; section->relocations = NULL; section->relocations_tail = NULL; } section = section->next; } return; } /* copy all executatable data to new memory */ MemBlock * gp_cofflink_make_memory(gp_object_type *object) { gp_section_type *section = object->sections; MemBlock *m; unsigned int org; unsigned int stop; unsigned int data; m = i_memory_create(); while (section != NULL) { if ((section->flags & STYP_TEXT) || (section->flags & STYP_DATA_ROM)) { if (object->class == PROC_CLASS_PIC16E) org = section->address >> 1; else org = section->address; stop = org + (section->size / 2); for ( ; org < stop; org++) { /* fetch the current contents of the memory */ data = i_memory_get(section->data, org); assert(data & MEM_USED_MASK); /* write data to new memory */ i_memory_put(m, org, data); } } section = section->next; } return m; } gputils-0.13.7/libgputils/gpwritehex.c0000644000175000017500000001302111156313233014715 00000000000000/* ".HEX" file output for gputils Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* mode flags */ #define all 0 #define low 1 #define high 2 #define swap 3 /* swap bytes for inhx16 format */ #define byte 4 /* write byte sized words */ static int sum; static char *newline; static FILE *hex; MemBlock *memory; static void new_record() { fprintf(hex, ":"); sum = 0; } static void write_byte(int b) { sum += b; assert((0 <= b) && (b <= 255)); fprintf(hex, "%02X", b); } /* Write big-endian word */ static void write_bg_word(int w) { write_byte((w >> 8) & 0xff); write_byte(w & 0xff); } /* Write little-endian word */ static void write_word(int w) { write_byte(w & 0xff); write_byte((w >> 8) & 0xff); } static void end_record() { write_byte((-sum) & 0xff); fprintf(hex, newline); } void data_line(int start, int stop, int mode) { new_record(); if (mode == all) { write_byte(2 * (stop - start)); write_bg_word(2 * start); write_byte(0); while (start < stop){ write_word(i_memory_get(memory, start++)); } } else if (mode == byte) { write_byte(stop - start); write_bg_word(start); write_byte(0); while (start < stop) { write_byte((i_memory_get(memory, start++)) & 0xff); } } else if (mode == swap) { write_byte(stop - start); write_bg_word(start); write_byte(0); while (start < stop){ write_bg_word(i_memory_get(memory, start++)); } } else { write_byte(stop - start); write_bg_word(start); write_byte(0); while (start < stop) { if (mode == low) { write_byte((i_memory_get(memory, start++)) & 0xff); } else { write_byte(((i_memory_get(memory, start++)) & 0xff00) >> 8); } } } end_record(); } void seg_address_line(int segment) { new_record(); write_byte(2); write_word(0); write_byte(4); write_bg_word(segment); end_record(); } void last_line() { new_record(); write_byte(0); write_word(0); write_byte(1); end_record(); } void write_i_mem(enum formats hex_format, int mode) { MemBlock *m = memory; int i, j, maximum; while(m) { i = m->base << I_MEM_BITS; maximum = i + MAX_I_MEM; if (hex_format == inhx32) { seg_address_line(m->base); } else { assert(m->base == 0); } while (i < maximum) { if ((i_memory_get(memory, i) & MEM_USED_MASK) == 0) { ++i; } else { j = i; while ((i_memory_get(memory, i) & MEM_USED_MASK)) { ++i; if (((mode == all) || (mode == swap)) && ((i & 0x7) == 0)) break; if ((i & 0xf) == 0) break; } /* Now we have a run of (i - j) occupied memory locations. */ /* Write the data to the file */ data_line(j, i, mode); } } m = m->next; } last_line(); } int writehex (char *basefilename, MemBlock *m, enum formats hex_format, int numerrors, int byte_words, int dos_newlines) { char hexfilename[BUFSIZ]; char lowhex[BUFSIZ]; char highhex[BUFSIZ]; memory = m; if (dos_newlines) { newline = "\r\n"; } else { newline = "\n"; } /* build file names */ strncpy(hexfilename, basefilename, sizeof(hexfilename)); strncat(hexfilename, ".hex", sizeof(hexfilename)); strncpy(lowhex, basefilename, sizeof(lowhex)); strncat(lowhex, ".hxl", sizeof(lowhex)); strncpy(highhex, basefilename, sizeof(highhex)); strncat(highhex, ".hxh", sizeof(highhex)); if (numerrors) { /* Remove the hex files (if any) */ unlink(hexfilename); unlink(lowhex); unlink(highhex); return 0; } /* No error: overwrite the hex file */ if (hex_format == inhx8s) { /* Write the low memory */ hex = fopen(lowhex, "wt"); if (hex == NULL) { perror(lowhex); exit(1); } write_i_mem(hex_format, low); fclose(hex); /* Write the high memory */ hex = fopen(highhex, "wt"); if (hex == NULL) { perror(highhex); exit(1); } write_i_mem(hex_format, high); fclose(hex); } else if (hex_format == inhx16) { hex = fopen(hexfilename, "wt"); if (hex == NULL) { perror(hexfilename); exit(1); } write_i_mem(hex_format, swap); fclose(hex); } else { hex = fopen(hexfilename, "wt"); if (hex == NULL) { perror(hexfilename); exit(1); } if (byte_words) write_i_mem(hex_format, byte); else write_i_mem(hex_format, all); fclose(hex); } return 0; } /* scan the memory to see if it exceeds 32K limit on inhx8m limit */ int check_writehex(MemBlock *m, enum formats hex_format) { int error = 0; if (hex_format != inhx32) { while(m) { if (m->base > 0) { error = 1; } m = m->next; } } return error; } gputils-0.13.7/libgputils/gpcoffopt.h0000644000175000017500000000170011156313233014524 00000000000000/* GNU PIC coff optimizing functions Copyright (C) 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPCOFFOPT_H__ #define __GPCOFFOPT_H__ void gp_coffopt_remove_weak(gp_object_type *object); void gp_coffopt_remove_dead_sections(gp_object_type *object, int pass); #endif gputils-0.13.7/libgputils/gpreadobj.h0000644000175000017500000000255211156313233014500 00000000000000/* Read coff objects Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPREADOBJ_H__ #define __GPREADOBJ_H__ typedef enum gp_coff_type { archive_file, object_file, object_file_v2, sys_err_file, unknown_file } gp_coff_type; typedef struct gp_binary_type { long int size; /* size of the file in bytes */ char *file; /* file contents */ } gp_binary_type; gp_coff_type gp_identify_coff_file(char *filename); gp_binary_type *gp_read_file(char *filename); void gp_free_file(gp_binary_type *file); gp_object_type *gp_convert_file(char *filename, char *file); gp_object_type *gp_read_coff(char *filename); #endif gputils-0.13.7/libgputils/gptypes.h0000644000175000017500000000161011156313233014230 00000000000000/* libgputils typedefs Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPTYPES_H__ #define __GPTYPES_H__ typedef enum { false = (0 == 1), true = (0 == 0) } gp_boolean; #endif gputils-0.13.7/libgputils/gpmessage.h0000644000175000017500000000223711156313233014516 00000000000000/* messaging functions Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPMESSAGE_H__ #define __GPMESSAGE_H__ extern gp_boolean gp_quiet; extern gp_boolean gp_message_disable; extern gp_boolean gp_debug_disable; extern int gp_num_errors; extern int gp_num_warnings; extern int gp_num_messages; void gp_error(const char *format, ...); void gp_warning(const char *format, ...); void gp_message(const char *format, ...); void gp_debug(const char *format, ...); #endif gputils-0.13.7/libgputils/gpdis.h0000644000175000017500000000216511156313233013651 00000000000000/* Convert one word from memory into an equivalent assembly instruction Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPDIS_H__ #define __GPDIS_H__ extern gp_boolean gp_decode_mnemonics; extern gp_boolean gp_decode_extended; int gp_disassemble(MemBlock *m, int org, enum proc_class class, char *buffer, size_t sizeof_buffer); #endif gputils-0.13.7/libgputils/gpcfg.h0000644000175000017500000000510611156313233013627 00000000000000/* gpcfg.h - header file for pic object files Copyright (C) 2006 Michael Ballbach This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPCFG_H__ #define __GPCFG_H__ /* a directive value */ struct gp_cfg_option { const char *name; /* name of the value */ unsigned char byte; /* it's data value */ }; /* a directive, i.e., FOSC */ struct gp_cfg_directive { const char *name; /* directive name */ unsigned char mask; /* mask of bytes in the config address that apply to its value */ unsigned char option_count; /* number of possible values */ struct gp_cfg_option *options; /* array of values */ }; /* one particular configuration address, i.e., 0x300001 */ struct gp_cfg_addr { int addr; /* the address */ unsigned char defval; /* its default */ unsigned char directive_count; /* count of relavent directives */ struct gp_cfg_directive *directives; /* array of directives */ }; /* a device - that is, a colllection of configuration addresses */ struct gp_cfg_device { const char *device; /* device name */ unsigned char addr_count; /* number of configuration addresses */ struct gp_cfg_addr *config_addrs; /* array of configuration addresses */ }; /* the big table */ extern struct gp_cfg_device gp_cfg_devices[]; extern int gp_cfg_device_count; /* helper API */ const struct gp_cfg_device *gp_cfg_find_pic(const char *pic); const struct gp_cfg_device *gp_cfg_find_pic_multi(int count, char **pics); const struct gp_cfg_directive *gp_cfg_find_directive(const struct gp_cfg_device *device, const char *directive, int *out_config_addr, unsigned char *out_def_value); const struct gp_cfg_option *gp_cfg_find_option(const struct gp_cfg_directive *directive, const char *option); unsigned char gp_cfg_get_default(const struct gp_cfg_device *dev, int address); #endif /* __GPCFG_H__ */ gputils-0.13.7/libgputils/gpwriteobj.h0000644000175000017500000000164511156313233014721 00000000000000/* Write coff objects Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPWRITEOBJ_H__ #define __GPWRITEOBJ_H__ int _has_data(gp_section_type *section); int gp_write_coff(gp_object_type *object, int numerrors); #endif gputils-0.13.7/libgputils/gparchive.h0000644000175000017500000001050411156313233014507 00000000000000/* GNU PIC archive functions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPARCHIVE_H__ #define __GPARCHIVE_H__ /* gputils uses Microchip's library file format. It is basically a coff archive with a few exceptions. - There are no user id and mode entries in the header. - The archive member name has been increased from 16 to 256 characters. - The strings for data and size are terminated with "l" - The first member in the archive is not a symbol table. The first 8 bytes in the archive are ARMAG. This is followed by the archive members. Each member starts with an ar_hdr. This is followed by the complete object file. gputils uses the complete object filename for the member name. The only intentional deviation from Microchip's format, is a symbol index. This index provides all global symbols names from the archive. This simplifies the task of determining which archive members are required for linking. The symbol index is always the first coff member in the archive. It can be identified because ar_name[0] == '/'. */ /* Note that the usual '\n' in magic strings may translate to different characters, as allowed by ANSI. '\012' has a fixed value. */ #define ARMAG "!\012" #define SARMAG 8 #define ARFMAG "`\012" /* archive file member header */ struct ar_hdr { char ar_name[256]; /* name of this member */ char ar_date[12]; /* file mtime */ char ar_size[10]; /* file size, printed as decimal */ char ar_fmag[2]; /* should contain ARFMAG */ }; #define AR_HDR_SIZ 280 typedef struct gp_archive_type { struct ar_hdr header; /* archive header file */ char *file; /* object file */ int offset; /* offset from the begining of the archive */ struct gp_archive_type *next; /* next file in linked list */ } gp_archive_type; /* symbol index data */ #define AR_INDEX_NUMBER_SIZ 4 /* number of symbols is 4 bytes long */ #define AR_INDEX_OFFSET_SIZ 4 /* symbol index offsets are 4 bytes long */ int gp_archive_count_members(gp_archive_type *archive); char *gp_archive_member_name(gp_archive_type *archive); void gp_archive_list_members(gp_archive_type *archive); gp_archive_type *gp_archive_find_member(gp_archive_type *archive, char *objectname); int gp_archive_free_member(gp_archive_type *archive); gp_archive_type *gp_archive_delete_member(gp_archive_type *archive, char *objectname); gp_archive_type *gp_archive_add_member(gp_archive_type *archive, char *filename, char *objectname); int gp_archive_extract_member(gp_archive_type *archive, char *objectname); int gp_archive_write(gp_archive_type *archive, char *archivename); void gp_archive_update_offsets(gp_archive_type *archive); gp_archive_type *gp_archive_read(char *filename); int gp_archive_have_index(gp_archive_type *archive); gp_archive_type *gp_archive_remove_index(gp_archive_type *archive); int gp_archive_make_index(gp_archive_type *archive, struct symbol_table *); gp_archive_type *gp_archive_add_index(struct symbol_table *table, gp_archive_type *archive); int gp_archive_add_symbol(struct symbol_table *table, char *name, gp_archive_type *member); void gp_archive_read_index(struct symbol_table *table, gp_archive_type *archive); void gp_archive_print_table(struct symbol_table *table); #endif gputils-0.13.7/libgputils/gpmemory.h0000644000175000017500000000321311156313233014375 00000000000000/* memory header file. Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Scott Dattalo This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPMEMORY_H__ #define __GPMEMORY_H__ #define MAX_RAM 0x1000 /* Maximum RAM */ #define I_MEM_BITS 15 #define MAX_I_MEM (1<name) #define DECODE_ARG1(ARG1) snprintf(buffer, sizeof_buffer, "%s\t%#lx", \ instruction->name,\ ARG1) #define DECODE_ARG1WF(ARG1, ARG2) snprintf(buffer, sizeof_buffer, "%s\t%#lx, %s", \ instruction->name,\ ARG1, \ (ARG2 ? "f" : "w")) #define DECODE_ARG2(ARG1, ARG2) snprintf(buffer, sizeof_buffer, "%s\t%#lx, %#lx", \ instruction->name,\ ARG1, \ ARG2) #define DECODE_ARG3(ARG1, ARG2, ARG3) snprintf(buffer, sizeof_buffer, "%s\t%#lx, %#lx, %#lx", \ instruction->name,\ ARG1, \ ARG2, \ ARG3) gp_boolean gp_decode_mnemonics = false; gp_boolean gp_decode_extended = false; int gp_disassemble(MemBlock *m, int org, enum proc_class class, char *buffer, size_t sizeof_buffer) { int i; int value; long int opcode; struct insn *instruction = NULL; int num_words = 1; opcode = i_memory_get(m, org) & 0xffff; switch (class) { case PROC_CLASS_EEPROM8: case PROC_CLASS_EEPROM16: case PROC_CLASS_GENERIC: snprintf(buffer, sizeof_buffer, "unsupported processor class"); return 0; case PROC_CLASS_PIC12: for(i = 0; i < num_op_12c5xx; i++) { if((op_12c5xx[i].mask & opcode) == op_12c5xx[i].opcode) { instruction = &op_12c5xx[i]; break; } } break; case PROC_CLASS_SX: for(i = 0; i < num_op_sx; i++) { if((op_sx[i].mask & opcode) == op_sx[i].opcode) { instruction = &op_sx[i]; break; } } break; case PROC_CLASS_PIC14: for(i = 0; i < num_op_16cxx; i++) { if((op_16cxx[i].mask & opcode) == op_16cxx[i].opcode) { instruction = &op_16cxx[i]; break; } } break; case PROC_CLASS_PIC16: for(i = 0; i < num_op_17cxx; i++) { if((op_17cxx[i].mask & opcode) == op_17cxx[i].opcode) { instruction = &op_17cxx[i]; break; } } break; case PROC_CLASS_PIC16E: if (gp_decode_mnemonics) { for(i = 0; i < num_op_18cxx_sp; i++) { if((op_18cxx_sp[i].mask & opcode) == op_18cxx_sp[i].opcode) { instruction = &op_18cxx_sp[i]; break; } } } if (instruction == NULL) { for(i = 0; i < num_op_18cxx; i++) { if((op_18cxx[i].mask & opcode) == op_18cxx[i].opcode) { instruction = &op_18cxx[i]; break; } } } if ((instruction == NULL) && (gp_decode_extended)) { /* might be from the extended instruction set */ for(i = 0; i < num_op_18cxx_ext; i++) { if((op_18cxx_ext[i].mask & opcode) == op_18cxx_ext[i].opcode) { instruction = &op_18cxx_ext[i]; break; } } } break; default: assert(0); } if (instruction == NULL) { snprintf(buffer, sizeof_buffer, "dw\t%#lx ;unknown opcode", opcode); return num_words; } switch (instruction->class) { case INSN_CLASS_LIT3_BANK: DECODE_ARG1((opcode & 0x7) << 5); break; case INSN_CLASS_LIT3_PAGE: DECODE_ARG1((opcode & 0x7) << 9); break; case INSN_CLASS_LIT1: DECODE_ARG1(opcode & 1); break; case INSN_CLASS_LIT4: DECODE_ARG1(opcode & 0xf); break; case INSN_CLASS_LIT4S: DECODE_ARG1((opcode & 0xf0) >> 4); break; case INSN_CLASS_LIT6: DECODE_ARG1(opcode & 0x3f); break; case INSN_CLASS_LIT8: case INSN_CLASS_LIT8C12: case INSN_CLASS_LIT8C16: DECODE_ARG1(opcode & 0xff); break; case INSN_CLASS_LIT9: DECODE_ARG1(opcode & 0x1ff); break; case INSN_CLASS_LIT11: DECODE_ARG1(opcode & 0x7ff); break; case INSN_CLASS_LIT13: DECODE_ARG1(opcode & 0x1fff); break; case INSN_CLASS_LITFSR: DECODE_ARG2(((opcode >> 6) & 0x3), (opcode & 0x3f)); break; case INSN_CLASS_RBRA8: value = opcode & 0xff; /* twos complement number */ if (value & 0x80) { value = -((value ^ 0xff) + 1); } DECODE_ARG1((unsigned long)(org + value + 1) * 2); break; case INSN_CLASS_RBRA11: value = opcode & 0x7ff; /* twos complement number */ if (value & 0x400) { value = -((value ^ 0x7ff) + 1); } DECODE_ARG1((unsigned long)(org + value + 1) * 2); break; case INSN_CLASS_LIT20: { long int dest; num_words = 2; dest = (i_memory_get(m, org + 1) & 0xfff) << 8; dest |= opcode & 0xff; DECODE_ARG1(dest * 2); } break; case INSN_CLASS_CALL20: { long int dest; num_words = 2; dest = (i_memory_get(m, org + 1) & 0xfff) << 8; dest |= opcode & 0xff; snprintf(buffer, sizeof_buffer, "%s\t%#lx, %#lx", instruction->name, dest * 2, (opcode >> 8) & 1); } break; case INSN_CLASS_FLIT12: { long int k; long int file; num_words = 2; k = i_memory_get(m, org + 1) & 0xff; k |= ((opcode & 0xf) << 8); file = (opcode >> 4) & 0x3; DECODE_ARG2(file, k); } break; case INSN_CLASS_FF: { long int file1; long int file2; num_words = 2; file1 = opcode & 0xfff; file2 = i_memory_get(m, org + 1) & 0xfff; DECODE_ARG2(file1, file2); } break; case INSN_CLASS_FP: DECODE_ARG2((opcode & 0xff), ((opcode >> 8) & 0x1f)); break; case INSN_CLASS_PF: DECODE_ARG2(((opcode >> 8) & 0x1f), (opcode & 0xff)); break; case INSN_CLASS_SF: { long int offset; long int file; num_words = 2; offset = opcode & 0x7f; file = i_memory_get(m, org + 1) & 0xfff; DECODE_ARG2(offset, file); } break; case INSN_CLASS_SS: { long int offset1; long int offset2; num_words = 2; offset1 = opcode & 0x7f; offset2 = i_memory_get(m, org + 1) & 0x7f; DECODE_ARG2(offset1, offset2); } break; case INSN_CLASS_OPF5: DECODE_ARG1(opcode & 0x1f); break; case INSN_CLASS_OPWF5: DECODE_ARG1WF((opcode & 0x1f), ((opcode >> 5) & 1)); break; case INSN_CLASS_B5: DECODE_ARG2((opcode & 0x1f), ((opcode >> 5) & 7)); break; case INSN_CLASS_B8: DECODE_ARG2((opcode & 0xff), ((opcode >> 8) & 7)); break; case INSN_CLASS_OPF7: DECODE_ARG1(opcode & 0x7f); break; case INSN_CLASS_OPF8: DECODE_ARG1(opcode & 0xff); break; case INSN_CLASS_OPWF7: DECODE_ARG1WF((opcode & 0x7f), ((opcode >> 7) & 1)); break; case INSN_CLASS_OPWF8: DECODE_ARG1WF((opcode & 0xff), ((opcode >> 8) & 1)); break; case INSN_CLASS_B7: DECODE_ARG2((opcode & 0x7f), ((opcode >> 7) & 7)); break; case INSN_CLASS_OPFA8: DECODE_ARG2((opcode & 0xff), ((opcode >> 8) & 1)); break; case INSN_CLASS_BA8: DECODE_ARG3((opcode & 0xff), ((opcode >> 9) & 7), ((opcode >> 8) & 1)); break; case INSN_CLASS_OPWFA8: DECODE_ARG3((opcode & 0xff), ((opcode >> 9) & 1), ((opcode >> 8) & 1)); break; case INSN_CLASS_IMPLICIT: DECODE_ARG0; break; case INSN_CLASS_TBL: { char operator[5]; switch(opcode & 0x3) { case 0: strncpy(operator, "*", sizeof(operator)); break; case 1: strncpy(operator, "*+", sizeof(operator)); break; case 2: strncpy(operator, "*-", sizeof(operator)); break; case 3: strncpy(operator, "+*", sizeof(operator)); break; default: assert(0); } snprintf(buffer, sizeof_buffer, "%s\t%s", instruction->name, operator); } break; case INSN_CLASS_TBL2: DECODE_ARG2(((opcode >> 9) & 1), (opcode & 0xff)); break; case INSN_CLASS_TBL3: DECODE_ARG3(((opcode >> 9) & 1), ((opcode >> 8) & 1), (opcode & 0xff)); break; default: assert(0); } return num_words; } gputils-0.13.7/libgputils/gpprocessor.h0000644000175000017500000001000411156521302015076 00000000000000/* GNU PIC processor definitions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPPROCESSOR_H__ #define __GPPROCESSOR_H__ enum proc_class { PROC_CLASS_UNKNOWN, /* Unknown device */ PROC_CLASS_EEPROM8, /* 8 bit EEPROM */ PROC_CLASS_EEPROM16, /* 16 bit EEPROM */ PROC_CLASS_GENERIC, /* 12 bit device */ PROC_CLASS_PIC12, /* 12 bit devices */ PROC_CLASS_SX, /* 12 bit devices */ PROC_CLASS_PIC14, /* 14 bit devices */ PROC_CLASS_PIC16, /* 16 bit devices */ PROC_CLASS_PIC16E /* enhanced 16 bit devices */ }; typedef struct px *pic_processor_t; #define no_processor ((struct px *)0) #define MAX_NAMES 3 /* Maximum number of names a processor can have */ #define MAX_BADROM 1*2 /* Maximum number of BADROM ranges a processor can be */ /* initialized with */ struct px { enum proc_class class; char *defined_as; char *names[MAX_NAMES]; unsigned long coff_type; int num_pages; int num_banks; long maxrom; long badrom[MAX_BADROM]; long config_addrs[2]; char *script; }; /* CONFIG addresses for the 18xx parts */ #define CONFIG1L 0x300000 #define CONFIG1H 0x300001 #define CONFIG2L 0x300002 #define CONFIG2H 0x300003 #define CONFIG3L 0x300004 #define CONFIG3H 0x300005 #define CONFIG4L 0x300006 #define CONFIG4H 0x300007 #define CONFIG5L 0x300008 #define CONFIG5H 0x300009 #define CONFIG6L 0x30000a #define CONFIG6H 0x30000b #define CONFIG7L 0x30000c #define CONFIG7H 0x30000d #define DEVID1 0x3ffffe #define DEVID2 0x3fffff /* ID Locations for the 18xx parts */ #define IDLOC0 0x200000 #define IDLOC1 0x200001 #define IDLOC2 0x200002 #define IDLOC3 0x200003 #define IDLOC4 0x200004 #define IDLOC5 0x200005 #define IDLOC6 0x200006 #define IDLOC7 0x200007 /* Config address for everything else */ #define CONFIG_17CXX 0xfe00 #define CONFIG_ADDRESS_14 0x2007 #define CONFIG_ADDRESS_12 0x0fff /* ID Locations */ #define IDLOC_ADDRESS_12 0x200 #define IDLOC_ADDRESS_14 0x2000 void gp_dump_processor_list(gp_boolean list_all, enum proc_class class); struct px *gp_find_processor(char *name); enum proc_class gp_processor_class(pic_processor_t); int gp_processor_bsr_boundary(pic_processor_t processor); unsigned long gp_processor_coff_type(pic_processor_t processor); int gp_processor_num_pages(pic_processor_t processor); int gp_processor_num_banks(pic_processor_t processor); pic_processor_t gp_processor_coff_proc(unsigned long coff_type); char *gp_processor_name(pic_processor_t processor, unsigned int choice); char *gp_processor_coff_name(unsigned long coff_type, unsigned int choice); char *gp_processor_script(pic_processor_t processor); int gp_processor_rom_width(enum proc_class class); int gp_processor_check_page(enum proc_class class, int address); int gp_processor_check_bank(enum proc_class class, int address); int gp_processor_set_page(enum proc_class class, int num_pages, int page, MemBlock *m, int address, int use_wreg); int gp_processor_set_bank(enum proc_class class, int num_banks, int bank, MemBlock *m, int address); int gp_processor_retlw(enum proc_class class); #endif gputils-0.13.7/libgputils/gpreadhex.h0000644000175000017500000000176511156313233014517 00000000000000/* Read ".HEX" files and store it in memory Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPREADHEX_H__ #define __GPREADHEX_H__ struct hex_data { enum formats hex_format; int size; int error; }; struct hex_data *readhex(char *filename, MemBlock *m); #endif gputils-0.13.7/libgputils/gpcoffgen.c0000644000175000017500000003456311156521302014501 00000000000000/* GNU PIC general coff functions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" gp_object_type * gp_coffgen_init(void) { gp_object_type *object = NULL; /* allocate memory for the object file */ object = (gp_object_type *)malloc(sizeof(*object)); /* initialize the object */ object->filename = NULL; object->processor = gp_find_processor("generic"); object->class = PROC_CLASS_GENERIC; object->time = (long)time(NULL); object->flags = 0; object->num_sections = 0; object->sections = NULL; object->sections_tail = NULL; object->num_symbols = 0; object->symbols = NULL; object->symbols_tail = NULL; object->next = NULL; return object; } gp_section_type * gp_coffgen_findsection(gp_object_type *object, gp_section_type *start, char *name) { gp_section_type *current = NULL; gp_section_type *found = NULL; if (object == NULL) return NULL; current = start; while (current != NULL) { if ((current->name != NULL) && (strcmp(current->name, name) == 0)) { found = current; break; } current = current->next; } return found; } gp_section_type * gp_coffgen_newsection(char *name) { gp_section_type *new = NULL; /* allocate memory for the section */ new = (gp_section_type *)malloc(sizeof(*new)); /* initialize section */ new->name = strdup(name); new->symbol = NULL; new->flags = 0; new->address = 0; new->size = 0; new->data = i_memory_create(); new->num_reloc = 0; new->relocations = NULL; new->relocations_tail = NULL; new->num_lineno = 0; new->line_numbers = NULL; new->line_numbers_tail = NULL; new->is_used = false; new->number = 0; new->data_ptr = 0; new->reloc_ptr = 0; new->lineno_ptr = 0; new->next = NULL; new->have_pack_byte = false; new->emitted_pack_byte = false; return new; } gp_section_type * gp_coffgen_addsection(gp_object_type *object, char *name) { gp_section_type *new = NULL; if (object == NULL) return NULL; new = gp_coffgen_newsection(name); if (object->sections == NULL) { /* the list is empty */ object->sections = new; } else { /* append the new object to the end of the list */ object->sections_tail->next = new; } object->sections_tail = new; object->num_sections++; return new; } void gp_coffgen_delsectionsyms(gp_object_type *object, gp_section_type *section) { gp_symbol_type *list; gp_symbol_type *symbol; /* remove all symbols for the section */ list = object->symbols; while (list != NULL) { /* advance the pointer so the symbol can be freed */ symbol = list; list = list->next; if (symbol->section == section) { gp_coffgen_delsymbol(object, symbol); } } return; } gp_section_type * gp_coffgen_delsection(gp_object_type *object, gp_section_type *section) { gp_section_type *list = NULL; gp_section_type *previous = NULL; gp_section_type *removed = NULL; if (object == NULL) return NULL; list = object->sections; while (list != NULL) { if (list == section) { removed = section; if (previous == NULL) { /* removing the first section in the list */ object->sections = list->next; if (object->sections == NULL) { /* there are no sections in the list */ object->sections_tail = NULL; } else if (object->sections->next == NULL) { /* there is one section in the list */ object->sections_tail = object->sections; } } else { previous->next = list->next; if (list->next == NULL) { /* The last section in the list is being removed, so update the tail. */ object->sections_tail = previous; } } break; } previous = list; list = list->next; } object->num_sections--; /* FIXME: gp_coffgen_free_section(second); */ return removed; } gp_reloc_type * gp_coffgen_addreloc(gp_section_type *section) { gp_reloc_type *new = NULL; /* allocate memory for the relocation */ new = (gp_reloc_type *)malloc(sizeof(*new)); new->address = 0; new->symbol = NULL; new->symbol_number = 0; new->offset = 0; new->type = 0; new->next = NULL; if (section->relocations == NULL) { /* the list is empty */ section->relocations = new; } else { section->relocations_tail->next = new; } section->relocations_tail = new; section->num_reloc++; return new; } gp_linenum_type * gp_coffgen_addlinenum(gp_section_type *section) { gp_linenum_type *new = NULL; /* allocate memory for the relocation */ new = (gp_linenum_type *)malloc(sizeof(*new)); new->symbol = NULL; new->line_number = 0; new->address = 0; new->next = NULL; if (section->line_numbers == NULL) { /* the list is empty */ section->line_numbers = new; } else { section->line_numbers_tail->next = new; } section->line_numbers_tail = new; section->num_lineno++; return new; } gp_symbol_type * gp_coffgen_findsymbol(gp_object_type *object, char *name) { gp_symbol_type *current = NULL; gp_symbol_type *found = NULL; if (object == NULL) return NULL; current = object->symbols; while (current != NULL) { if ((current->name != NULL) && (strcmp(current->name, name) == 0)) { found = current; break; } current = current->next; } return found; } gp_aux_type * gp_coffgen_addaux(gp_object_type *object, gp_symbol_type *symbol) { gp_aux_type *new = NULL; gp_aux_type *list = NULL; /* allocate memory for the auxiliary symbol */ new = (gp_aux_type *)malloc(sizeof(*new)); new->next = NULL; if (symbol->aux_list == NULL) { /* the list is empty */ symbol->aux_list = new; } else { /* append the new object to the end of the list */ list = symbol->aux_list; while (list->next != NULL) { list = list->next; } list->next = new; } symbol->num_auxsym += 1; object->num_symbols += 1; return new; } gp_symbol_type * gp_coffgen_addsymbol(gp_object_type *object) { gp_symbol_type *new = NULL; /* allocate memory for the symbol */ new = (gp_symbol_type *)malloc(sizeof(*new)); new->name = NULL; new->value = 0; new->section_number = 0; new->section = NULL; new->type = 0; new->class = 0; new->num_auxsym = 0; new->aux_list = NULL; new->number = object->num_symbols; new->next = NULL; if (object->symbols == NULL) { /* the list is empty */ object->symbols = new; } else { object->symbols_tail->next = new; } object->symbols_tail = new; object->num_symbols += 1; return new; } gp_symbol_type * gp_coffgen_delsymbol(gp_object_type *object, gp_symbol_type *symbol) { gp_symbol_type *list = NULL; gp_symbol_type *previous = NULL; gp_symbol_type *removed = NULL; if (object == NULL) return NULL; list = object->symbols; while (list != NULL) { if (list == symbol) { removed = symbol; if (previous == NULL) { /* removing the first symbol in the list */ object->symbols = list->next; if (object->symbols == NULL) { /* there are no symbols in the list */ object->symbols_tail = NULL; } else if (object->symbols->next == NULL) { /* there is one symbol in the list */ object->symbols_tail = object->symbols; } } else { previous->next = list->next; if (list->next == NULL) { /* The last symbol in the list is being removed, so update the tail. */ object->symbols_tail = previous; } } break; } previous = list; list = list->next; } object->num_symbols -= (symbol->num_auxsym + 1); /* FIXME: gp_coffgen_free_symbol(symbol); */ return removed; } /* Determine if any relocation uses the symbol. */ gp_boolean gp_coffgen_has_reloc(gp_object_type *object, gp_symbol_type *symbol) { gp_section_type *section; gp_reloc_type *relocation; section = object->sections; while (section != NULL) { relocation = section->relocations; while (relocation != NULL) { if (relocation->symbol == symbol) { return true; } relocation = relocation->next; } section = section->next; } return false; } /* Determine if the symbol is global */ gp_boolean gp_coffgen_is_global(gp_symbol_type *symbol) { if ((symbol->class == C_EXT) && (symbol->section_number == N_SCNUM)) { return true; } return false; } /* Determine if the symbol is external */ gp_boolean gp_coffgen_is_external(gp_symbol_type *symbol) { if ((symbol->class == C_EXT) && (symbol->section_number == N_UNDEF)) { return true; } return false; } /* Determine if the symbol is debug */ gp_boolean gp_coffgen_is_debug(gp_symbol_type *symbol) { if (symbol->class == N_DEBUG) { return true; } return false; } /* Determine if the symbol is absolute */ gp_boolean gp_coffgen_is_absolute(gp_symbol_type *symbol) { if (symbol->class == N_ABS) { return true; } return false; } /* allocate a block of section */ gp_section_type * gp_coffgen_blocksec(unsigned int number) { gp_section_type *new = NULL; unsigned int i; if (number == 0) return NULL; /* allocate memory for the sections */ new = (gp_section_type *)malloc(sizeof(*new) * number); /* don't process the last entry */ number--; /* initialize the pointers to create the linked list */ for(i = 0; i < number; i++) new[i].next = &new[i+1]; /* assign the tail of the list */ new[number].next = NULL; return new; } /* allocate a block of relocations */ gp_reloc_type * gp_coffgen_blockrel(unsigned int number) { gp_reloc_type *new = NULL; unsigned int i; if (number == 0) return NULL; /* allocate memory for the relocations */ new = (gp_reloc_type *)malloc(sizeof(*new) * number); /* don't process the last entry */ number--; /* initialize the pointers to create the linked list */ for(i = 0; i < number; i++) new[i].next = &new[i+1]; /* assign the tail of the list */ new[number].next = NULL; return new; } /* allocate a block of line numbers */ gp_linenum_type * gp_coffgen_blockline(unsigned int number) { gp_linenum_type *new = NULL; unsigned int i; if (number == 0) return NULL; /* allocate memory for the symbol */ new = (gp_linenum_type *)malloc(sizeof(*new) * number); /* don't process the last entry */ number--; /* initialize the pointers to create the linked list */ for(i = 0; i < number; i++) new[i].next = &new[i+1]; /* assign the tail of the list */ new[number].next = NULL; return new; } /* allocate a block of symbols */ gp_symbol_type * gp_coffgen_blocksym(unsigned int number) { gp_symbol_type *new = NULL; unsigned int i; if (number == 0) return NULL; /* allocate memory for the symbols */ new = (gp_symbol_type *)calloc(sizeof(*new) * number, sizeof(gp_symbol_type)); /* don't process the last entry */ number--; /* initialize the pointers to create the linked list */ for(i = 0; i < number; i++) { new[i].name = NULL; new[i].next = &new[i+1]; } /* assign the tail of the list */ new[number].name = NULL; new[number].next = NULL; return new; } /* allocate a block of auxiliary symbols */ gp_aux_type * gp_coffgen_blockaux(unsigned int number) { gp_aux_type *new = NULL; unsigned int i; if (number == 0) return NULL; /* allocate memory for the symbols */ new = (gp_aux_type *)calloc(sizeof(*new) * number, sizeof(gp_aux_type)); /* don't process the last entry */ number--; /* initialize the pointers to create the linked list */ for(i = 0; i < number; i++) { new[i].type = AUX_NONE; new[i].next = &new[i+1]; } /* assign the tail of the list */ new[number].next = NULL; return new; } int gp_coffgen_free_section(gp_section_type *section) { gp_reloc_type *relocation; gp_linenum_type *line_number; gp_reloc_type *old_relocation; gp_linenum_type *old_line_number; i_memory_free(section->data); relocation = section->relocations; while (relocation != NULL) { old_relocation = relocation; relocation = relocation->next; free(old_relocation); } line_number = section->line_numbers; while (line_number != NULL) { old_line_number = line_number; line_number = line_number->next; free(old_line_number); } free(section->name); free(section); return 0; } int gp_coffgen_free_symbol(gp_symbol_type *symbol) { gp_aux_type *aux; gp_aux_type *old_aux; int num_auxsym = symbol->num_auxsym; /* free the auxilary symbols */ aux = symbol->aux_list; while (aux != NULL) { old_aux = aux; aux = aux->next; free(old_aux); } free(symbol->name); free(symbol); return num_auxsym; } int gp_coffgen_free(gp_object_type *object) { gp_section_type *section; gp_symbol_type *symbol; gp_section_type *old_section; gp_symbol_type *old_symbol; if (object == NULL) return 1; free(object->filename); section = object->sections; while (section != NULL) { old_section = section; section = section->next; gp_coffgen_free_section(old_section); } symbol = object->symbols; while (symbol != NULL) { old_symbol = symbol; symbol = symbol->next; gp_coffgen_free_symbol(old_symbol); } free(object); return 0; } int gp_determine_aux(gp_symbol_type *symbol) { int aux_type = AUX_NONE; if (strcasecmp(".direct", symbol->name) == 0) { return AUX_DIRECT; } if (strcasecmp(".ident", symbol->name) == 0) { return AUX_IDENT; } switch (symbol->class) { case C_FILE: aux_type = AUX_FILE; break; case C_SECTION: aux_type = AUX_SCN; break; default: aux_type = AUX_NONE; } return aux_type; } gputils-0.13.7/libgputils/gpcfg-table.c0000644000175000017500000044212411156521302014712 00000000000000/* * This code is automatically generated from the MPASMWIN.EXE file. * This data is in the public domain. Use care in modifying. */ /* * since caches are enabled, directive and option structures may seem to include * references to other PICs. this is done by caching when two or more PICs contain * identical data. */ #include "stdhdr.h" #include "gpcfg.h" /* * PIC18F6410 */ static struct gp_cfg_option pic18f6410_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, { "INTIO67", 0x08 }, { "INTIO7", 0x09 }, }; static struct gp_cfg_option pic18f6410_fcmen_opts[] = { /* for FCMEN: */ { "OFF", 0x00 }, { "ON", 0x40 }, }; static struct gp_cfg_option pic18f6410_ieso_opts[] = { /* for IESO: */ { "OFF", 0x00 }, { "ON", 0x80 }, }; static struct gp_cfg_directive pic18f6410_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 10, pic18f6410_osc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f6410_pwrt_opts[] = { /* for PWRT: */ { "ON", 0x00 }, { "OFF", 0x01 }, }; static struct gp_cfg_option pic18f6410_boren_opts[] = { /* for BOREN: */ { "OFF", 0x00 }, { "ON", 0x02 }, { "NOSLP", 0x04 }, { "SBORDIS", 0x06 }, }; static struct gp_cfg_option pic18f6410_borv_opts[] = { /* for BORV: */ { "0", 0x00 }, { "1", 0x08 }, { "2", 0x10 }, { "3", 0x18 }, }; static struct gp_cfg_directive pic18f6410_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOREN", 0x06, 4, pic18f6410_boren_opts }, { "BORV", 0x18, 4, pic18f6410_borv_opts }, }; static struct gp_cfg_option pic18f6410_wdt_opts[] = { /* for WDT: */ { "OFF", 0x00 }, { "ON", 0x01 }, }; static struct gp_cfg_option pic18f6410_wdtps_opts[] = { /* for WDTPS: */ { "1", 0x00 }, { "2", 0x02 }, { "4", 0x04 }, { "8", 0x06 }, { "16", 0x08 }, { "32", 0x0a }, { "64", 0x0c }, { "128", 0x0e }, { "256", 0x10 }, { "512", 0x12 }, { "1024", 0x14 }, { "2048", 0x16 }, { "4096", 0x18 }, { "8192", 0x1a }, { "16384", 0x1c }, { "32768", 0x1e }, }; static struct gp_cfg_directive pic18f6410_300003[] = { /* for 0x300003 */ { "WDT", 0x01, 2, pic18f6410_wdt_opts }, { "WDTPS", 0x1e, 16, pic18f6410_wdtps_opts }, }; static struct gp_cfg_option pic18f6410_lpt1osc_opts[] = { /* for LPT1OSC: */ { "OFF", 0x00 }, { "ON", 0x04 }, }; static struct gp_cfg_option pic18f6410_ccp2mx_opts[] = { /* for CCP2MX: */ { "PORTE", 0x00 }, { "PORTC", 0x01 }, }; static struct gp_cfg_directive pic18f6410_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "CCP2MX", 0x01, 2, pic18f6410_ccp2mx_opts }, }; static struct gp_cfg_option pic18f6410_debug_opts[] = { /* for DEBUG: */ { "ON", 0x00 }, { "OFF", 0x80 }, }; static struct gp_cfg_directive pic18f6410_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f6410_300008[] = { /* for 0x300008 */ { "CP", 0x01, 2, pic18f6410_pwrt_opts }, }; /* config addresses for PIC18F6410: */ static struct gp_cfg_addr gp_cfg_pic18f6410_addrs[] = { { 0x300001, 0x07, 3, pic18f6410_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0xc3, 0, NULL }, { 0x300005, 0x81, 3, pic18f6410_300005 }, { 0x300006, 0x81, 3, pic18f6410_300006 }, { 0x300008, 0x01, 1, pic18f6410_300008 }, { 0x30000c, 0x01, 0, NULL }, }; /* * PIC18F2525 */ static struct gp_cfg_option pic18f2525_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, { "EC", 0x04 }, { "ECIO6", 0x05 }, { "HSPLL", 0x06 }, { "RCIO6", 0x07 }, { "INTIO67", 0x08 }, { "INTIO7", 0x09 }, }; static struct gp_cfg_directive pic18f2525_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 10, pic18f2525_osc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f2525_pbaden_opts[] = { /* for PBADEN: */ { "OFF", 0x00 }, { "ON", 0x02 }, }; static struct gp_cfg_option pic18f2525_ccp2mx_opts[] = { /* for CCP2MX: */ { "PORTBE", 0x00 }, { "PORTC", 0x01 }, }; static struct gp_cfg_directive pic18f2525_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "PBADEN", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f2525_ccp2mx_opts }, }; static struct gp_cfg_directive pic18f2525_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_option pic18f2525_cp1_opts[] = { /* for CP1: */ { "ON", 0x00 }, { "OFF", 0x02 }, }; static struct gp_cfg_option pic18f2525_cp2_opts[] = { /* for CP2: */ { "ON", 0x00 }, { "OFF", 0x04 }, }; static struct gp_cfg_directive pic18f2525_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_option pic18f2525_cpb_opts[] = { /* for CPB: */ { "ON", 0x00 }, { "OFF", 0x40 }, }; static struct gp_cfg_directive pic18f2525_300009[] = { /* for 0x300009 */ { "CPB", 0x40, 2, pic18f2525_cpb_opts }, { "CPD", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f2525_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_option pic18f2525_wrtc_opts[] = { /* for WRTC: */ { "ON", 0x00 }, { "OFF", 0x20 }, }; static struct gp_cfg_directive pic18f2525_30000b[] = { /* for 0x30000b */ { "WRTB", 0x40, 2, pic18f2525_cpb_opts }, { "WRTC", 0x20, 2, pic18f2525_wrtc_opts }, { "WRTD", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f2525_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f2525_30000d[] = { /* for 0x30000d */ { "EBTRB", 0x40, 2, pic18f2525_cpb_opts }, }; /* config addresses for PIC18F2525: */ static struct gp_cfg_addr gp_cfg_pic18f2525_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2525_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4450 */ static struct gp_cfg_option pic18f4450_plldiv_opts[] = { /* for PLLDIV: */ { "1", 0x00 }, { "2", 0x01 }, { "3", 0x02 }, { "4", 0x03 }, { "5", 0x04 }, { "6", 0x05 }, { "10", 0x06 }, { "12", 0x07 }, }; static struct gp_cfg_option pic18f4450_cpudiv_opts[] = { /* for CPUDIV: */ { "OSC1_PLL2", 0x00 }, { "OSC2_PLL3", 0x08 }, { "OSC3_PLL4", 0x10 }, { "OSC4_PLL6", 0x18 }, }; static struct gp_cfg_option pic18f4450_usbdiv_opts[] = { /* for USBDIV: */ { "1", 0x00 }, { "2", 0x20 }, }; static struct gp_cfg_directive pic18f4450_300000[] = { /* for 0x300000 */ { "PLLDIV", 0x07, 8, pic18f4450_plldiv_opts }, { "CPUDIV", 0x18, 4, pic18f4450_cpudiv_opts }, { "USBDIV", 0x20, 2, pic18f4450_usbdiv_opts }, }; static struct gp_cfg_option pic18f4450_fosc_opts[] = { /* for FOSC: */ { "XT_XT", 0x00 }, { "XTPLL_XT", 0x02 }, { "ECIO_EC", 0x04 }, { "EC_EC", 0x05 }, { "ECPLLIO_EC", 0x06 }, { "ECPLL_EC", 0x07 }, { "INTOSCIO_EC", 0x08 }, { "INTOSC_EC", 0x09 }, { "INTOSC_XT", 0x0a }, { "INTOSC_HS", 0x0b }, { "HS", 0x0c }, { "HSPLL_HS", 0x0e }, }; static struct gp_cfg_directive pic18f4450_300001[] = { /* for 0x300001 */ { "FOSC", 0x0f, 12, pic18f4450_fosc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f4450_bor_opts[] = { /* for BOR: */ { "OFF", 0x00 }, { "SOFT", 0x02 }, { "ON_ACTIVE", 0x04 }, { "ON", 0x06 }, }; static struct gp_cfg_option pic18f4450_borv_opts[] = { /* for BORV: */ { "46", 0x00 }, { "43", 0x08 }, { "28", 0x10 }, { "21", 0x18 }, }; static struct gp_cfg_option pic18f4450_vregen_opts[] = { /* for VREGEN: */ { "OFF", 0x00 }, { "ON", 0x20 }, }; static struct gp_cfg_directive pic18f4450_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x06, 4, pic18f4450_bor_opts }, { "BORV", 0x18, 4, pic18f4450_borv_opts }, { "VREGEN", 0x20, 2, pic18f4450_vregen_opts }, }; static struct gp_cfg_directive pic18f4450_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "PBADEN", 0x02, 2, pic18f2525_pbaden_opts }, }; static struct gp_cfg_option pic18f4450_bbsiz_opts[] = { /* for BBSIZ: */ { "BB1K", 0x00 }, { "BB2K", 0x08 }, }; static struct gp_cfg_directive pic18f4450_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "BBSIZ", 0x08, 2, pic18f4450_bbsiz_opts }, { "ICPRT", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f4450_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, }; static struct gp_cfg_directive pic18f4450_300009[] = { /* for 0x300009 */ { "CPB", 0x40, 2, pic18f2525_cpb_opts }, }; static struct gp_cfg_directive pic18f4450_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, }; static struct gp_cfg_directive pic18f4450_30000b[] = { /* for 0x30000b */ { "WRTB", 0x40, 2, pic18f2525_cpb_opts }, { "WRTC", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f4450_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, }; /* config addresses for PIC18F4450: */ static struct gp_cfg_addr gp_cfg_pic18f4450_addrs[] = { { 0x300000, 0x00, 3, pic18f4450_300000 }, { 0x300001, 0x05, 3, pic18f4450_300001 }, { 0x300002, 0x1f, 4, pic18f4450_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 6, pic18f4450_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0x40, 1, pic18f4450_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0x60, 2, pic18f4450_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18C858 */ static struct gp_cfg_option pic18c858_cp_opts[] = { /* for CP: */ { "ON", 0x00 }, { "OFF", 0xff }, }; static struct gp_cfg_directive pic18c858_300000[] = { /* for 0x300000 */ { "CP", 0xff, 2, pic18c858_cp_opts }, }; static struct gp_cfg_option pic18c858_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, }; static struct gp_cfg_directive pic18c858_300001[] = { /* for 0x300001 */ { "OSC", 0x07, 8, pic18c858_osc_opts }, { "OSCS", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_option pic18c858_borv_opts[] = { /* for BORV: */ { "45", 0x00 }, { "42", 0x04 }, { "27", 0x08 }, { "25", 0x0c }, }; static struct gp_cfg_directive pic18c858_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x02, 2, pic18f2525_pbaden_opts }, { "BORV", 0x0c, 4, pic18c858_borv_opts }, }; static struct gp_cfg_option pic18c858_wdtps_opts[] = { /* for WDTPS: */ { "1", 0x00 }, { "2", 0x02 }, { "4", 0x04 }, { "8", 0x06 }, { "16", 0x08 }, { "32", 0x0a }, { "64", 0x0c }, { "128", 0x0e }, }; static struct gp_cfg_directive pic18c858_300003[] = { /* for 0x300003 */ { "WDT", 0x01, 2, pic18f6410_wdt_opts }, { "WDTPS", 0x0e, 8, pic18c858_wdtps_opts }, }; static struct gp_cfg_directive pic18c858_300006[] = { /* for 0x300006 */ { "STVR", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18C858: */ static struct gp_cfg_addr gp_cfg_pic18c858_addrs[] = { { 0x300000, 0xff, 1, pic18c858_300000 }, { 0x300001, 0xe7, 2, pic18c858_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300006, 0x03, 1, pic18c858_300006 }, }; /* * PIC18F2523 */ static struct gp_cfg_option pic18f2523_ccp2mx_opts[] = { /* for CCP2MX: */ { "PORTB", 0x00 }, { "PORTC", 0x01 }, }; static struct gp_cfg_directive pic18f2523_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "PBADEN", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f2523_ccp2mx_opts }, }; static struct gp_cfg_option pic18f2523_cp3_opts[] = { /* for CP3: */ { "ON", 0x00 }, { "OFF", 0x08 }, }; static struct gp_cfg_directive pic18f2523_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, { "CP3", 0x08, 2, pic18f2523_cp3_opts }, }; static struct gp_cfg_directive pic18f2523_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, { "WRT3", 0x08, 2, pic18f2523_cp3_opts }, }; static struct gp_cfg_directive pic18f2523_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, { "EBTR3", 0x08, 2, pic18f2523_cp3_opts }, }; /* config addresses for PIC18F2523: */ static struct gp_cfg_addr gp_cfg_pic18f2523_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2523_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4610 */ /* config addresses for PIC18F4610: */ static struct gp_cfg_addr gp_cfg_pic18f4610_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2525_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0x40, 1, pic18f4450_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0x60, 2, pic18f4450_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F46K20 */ static struct gp_cfg_directive pic18f46k20_300001[] = { /* for 0x300001 */ { "FOSC", 0x0f, 10, pic18f2525_osc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f46k20_borv_opts[] = { /* for BORV: */ { "30", 0x00 }, { "27", 0x08 }, { "22", 0x10 }, { "18", 0x18 }, }; static struct gp_cfg_directive pic18f46k20_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOREN", 0x06, 4, pic18f6410_boren_opts }, { "BORV", 0x18, 4, pic18f46k20_borv_opts }, }; static struct gp_cfg_directive pic18f46k20_300003[] = { /* for 0x300003 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "WDTPS", 0x1e, 16, pic18f6410_wdtps_opts }, }; static struct gp_cfg_option pic18f46k20_hfofst_opts[] = { /* for HFOFST: */ { "OFF", 0x00 }, { "ON", 0x08 }, }; static struct gp_cfg_directive pic18f46k20_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "HFOFST", 0x08, 2, pic18f46k20_hfofst_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "PBADEN", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f2525_ccp2mx_opts }, }; /* config addresses for PIC18F46K20: */ static struct gp_cfg_addr gp_cfg_pic18f46k20_addrs[] = { { 0x300001, 0x07, 3, pic18f46k20_300001 }, { 0x300002, 0x1f, 3, pic18f46k20_300002 }, { 0x300003, 0x1f, 2, pic18f46k20_300003 }, { 0x300005, 0x8b, 5, pic18f46k20_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4458 */ static struct gp_cfg_directive pic18f4458_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x06, 4, pic18f4450_bor_opts }, { "BORV", 0x18, 4, pic18f6410_borv_opts }, { "VREGEN", 0x20, 2, pic18f4450_vregen_opts }, }; static struct gp_cfg_directive pic18f4458_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "PBADEN", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f4458_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ICPRT", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F4458: */ static struct gp_cfg_addr gp_cfg_pic18f4458_addrs[] = { { 0x300000, 0x00, 3, pic18f4450_300000 }, { 0x300001, 0x05, 3, pic18f4450_300001 }, { 0x300002, 0x1f, 4, pic18f4458_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4458_300005 }, { 0x300006, 0x85, 5, pic18f4458_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F65J50 */ static struct gp_cfg_option pic18f65j50_plldiv_opts[] = { /* for PLLDIV: */ { "12", 0x00 }, { "10", 0x02 }, { "6", 0x04 }, { "5", 0x06 }, { "4", 0x08 }, { "3", 0x0a }, { "2", 0x0c }, { "1", 0x0e }, }; static struct gp_cfg_directive pic18f65j50_007ff8[] = { /* for 0x007ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_option pic18f65j50_cpudiv_opts[] = { /* for CPUDIV: */ { "OSC4_PLL6", 0x00 }, { "OSC3_PLL3", 0x01 }, { "OSC2_PLL2", 0x02 }, { "OSC1", 0x03 }, }; static struct gp_cfg_directive pic18f65j50_007ff9[] = { /* for 0x007ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, }; static struct gp_cfg_option pic18f65j50_fosc_opts[] = { /* for FOSC: */ { "INTOSC", 0x00 }, { "INTOSCO", 0x01 }, { "INTOSCPLL", 0x02 }, { "INTOSCPLLO", 0x03 }, { "HS", 0x04 }, { "HSPLL", 0x05 }, { "EC", 0x06 }, { "ECPLL", 0x07 }, }; static struct gp_cfg_directive pic18f65j50_007ffa[] = { /* for 0x007ffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC", 0x07, 8, pic18f65j50_fosc_opts }, }; static struct gp_cfg_option pic18f65j50_wdtps_opts[] = { /* for WDTPS: */ { "1", 0x00 }, { "2", 0x01 }, { "4", 0x02 }, { "8", 0x03 }, { "16", 0x04 }, { "32", 0x05 }, { "64", 0x06 }, { "128", 0x07 }, { "256", 0x08 }, { "512", 0x09 }, { "1024", 0x0a }, { "2048", 0x0b }, { "4096", 0x0c }, { "8192", 0x0d }, { "16384", 0x0e }, { "32768", 0x0f }, }; static struct gp_cfg_directive pic18f65j50_007ffb[] = { /* for 0x007ffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_option pic18f65j50_msspmsk_opts[] = { /* for MSSPMSK: */ { "MSK5", 0x00 }, { "MSK7", 0x08 }, }; static struct gp_cfg_option pic18f65j50_ccp2mx_opts[] = { /* for CCP2MX: */ { "ALTERNATE", 0x00 }, { "DEFAULT", 0x01 }, }; static struct gp_cfg_directive pic18f65j50_007ffd[] = { /* for 0x007ffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F65J50: */ static struct gp_cfg_addr gp_cfg_pic18f65j50_addrs[] = { { 0x007ff8, 0xef, 5, pic18f65j50_007ff8 }, { 0x007ff9, 0xf7, 2, pic18f65j50_007ff9 }, { 0x007ffa, 0xc7, 3, pic18f65j50_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xf8, 0, NULL }, { 0x007ffd, 0xff, 2, pic18f65j50_007ffd }, }; /* * PIC18F8627 */ static struct gp_cfg_option pic18f8627_mode_opts[] = { /* for MODE: */ { "EM", 0x00 }, { "MPB", 0x01 }, { "MP", 0x02 }, { "MC", 0x03 }, }; static struct gp_cfg_option pic18f8627_addrbw_opts[] = { /* for ADDRBW: */ { "ADDR8BIT", 0x00 }, { "ADDR12BIT", 0x10 }, { "ADDR16BIT", 0x20 }, { "ADDR20BIT", 0x30 }, }; static struct gp_cfg_option pic18f8627_databw_opts[] = { /* for DATABW: */ { "DATA8BIT", 0x00 }, { "DATA16BIT", 0x40 }, }; static struct gp_cfg_directive pic18f8627_300004[] = { /* for 0x300004 */ { "MODE", 0x03, 4, pic18f8627_mode_opts }, { "ADDRBW", 0x30, 4, pic18f8627_addrbw_opts }, { "DATABW", 0x40, 2, pic18f8627_databw_opts }, { "WAIT", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_option pic18f8627_eccpmx_opts[] = { /* for ECCPMX: */ { "PORTH", 0x00 }, { "PORTE", 0x02 }, }; static struct gp_cfg_directive pic18f8627_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ECCPMX", 0x02, 2, pic18f8627_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f2525_ccp2mx_opts }, }; static struct gp_cfg_option pic18f8627_bbsiz_opts[] = { /* for BBSIZ: */ { "BB2K", 0x00 }, { "BB4K", 0x10 }, { "BB8K", 0x30 }, }; static struct gp_cfg_directive pic18f8627_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "BBSIZ", 0x30, 3, pic18f8627_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_option pic18f8627_cp4_opts[] = { /* for CP4: */ { "ON", 0x00 }, { "OFF", 0x10 }, }; static struct gp_cfg_directive pic18f8627_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, { "CP3", 0x08, 2, pic18f2523_cp3_opts }, { "CP4", 0x10, 2, pic18f8627_cp4_opts }, { "CP5", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f8627_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, { "WRT3", 0x08, 2, pic18f2523_cp3_opts }, { "WRT4", 0x10, 2, pic18f8627_cp4_opts }, { "WRT5", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f8627_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, { "EBTR3", 0x08, 2, pic18f2523_cp3_opts }, { "EBTR4", 0x10, 2, pic18f8627_cp4_opts }, { "EBTR5", 0x20, 2, pic18f2525_wrtc_opts }, }; /* config addresses for PIC18F8627: */ static struct gp_cfg_addr gp_cfg_pic18f8627_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0xf3, 4, pic18f8627_300004 }, { 0x300005, 0x83, 4, pic18f8627_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 6, pic18f8627_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 6, pic18f8627_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 6, pic18f8627_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4221 */ static struct gp_cfg_option pic18f4221_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, { "INTIO2", 0x08 }, { "INTIO1", 0x09 }, }; static struct gp_cfg_directive pic18f4221_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 10, pic18f4221_osc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f4221_bor_opts[] = { /* for BOR: */ { "OFF", 0x00 }, { "SOFT", 0x02 }, { "NOSLP", 0x04 }, { "ON", 0x06 }, }; static struct gp_cfg_directive pic18f4221_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x06, 4, pic18f4221_bor_opts }, { "BORV", 0x18, 4, pic18f6410_borv_opts }, }; static struct gp_cfg_option pic18f4221_pbaden_opts[] = { /* for PBADEN: */ { "DIG", 0x00 }, { "ANA", 0x02 }, }; static struct gp_cfg_option pic18f4221_ccp2mx_opts[] = { /* for CCP2MX: */ { "RB3", 0x00 }, { "RC1", 0x01 }, }; static struct gp_cfg_directive pic18f4221_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "PBADEN", 0x02, 2, pic18f4221_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f4221_ccp2mx_opts }, }; static struct gp_cfg_option pic18f4221_bbsiz_opts[] = { /* for BBSIZ: */ { "BB256", 0x00 }, { "BB512", 0x30 }, }; static struct gp_cfg_directive pic18f4221_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ICPORT", 0x08, 2, pic18f46k20_hfofst_opts }, { "BBSIZ", 0x30, 2, pic18f4221_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f4221_30000b[] = { /* for 0x30000b */ { "WRTC", 0x20, 2, pic18f2525_wrtc_opts }, { "WRTB", 0x40, 2, pic18f2525_cpb_opts }, { "WRTD", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F4221: */ static struct gp_cfg_addr gp_cfg_pic18f4221_addrs[] = { { 0x300001, 0x07, 3, pic18f4221_300001 }, { 0x300002, 0x1f, 3, pic18f4221_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4221_300005 }, { 0x300006, 0x85, 6, pic18f4221_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f4221_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4220 */ static struct gp_cfg_option pic18f4220_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, { "INTIO2", 0x08 }, { "INTIO1", 0x09 }, { "RC", 0x0f }, }; static struct gp_cfg_directive pic18f4220_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 10, pic18f4220_osc_opts }, { "FSCM", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f4220_borv_opts[] = { /* for BORV: */ { "45", 0x00 }, { "42", 0x04 }, { "27", 0x08 }, { "20", 0x0c }, }; static struct gp_cfg_directive pic18f4220_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x02, 2, pic18f2525_pbaden_opts }, { "BORV", 0x0c, 4, pic18f4220_borv_opts }, }; static struct gp_cfg_option pic18f4220_ccp2mx_opts[] = { /* for CCP2MX: */ { "B3", 0x00 }, { "OFF", 0x00 }, { "C1", 0x01 }, { "ON", 0x01 }, }; static struct gp_cfg_directive pic18f4220_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "PBAD", 0x02, 2, pic18f4221_pbaden_opts }, { "CCP2MX", 0x01, 4, pic18f4220_ccp2mx_opts }, }; static struct gp_cfg_directive pic18f4220_300006[] = { /* for 0x300006 */ { "STVR", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f4220_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, }; static struct gp_cfg_directive pic18f4220_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, }; static struct gp_cfg_directive pic18f4220_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, }; /* config addresses for PIC18F4220: */ static struct gp_cfg_addr gp_cfg_pic18f4220_addrs[] = { { 0x300001, 0xcf, 3, pic18f4220_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 3, pic18f4220_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F66J90 */ static struct gp_cfg_directive pic18f66j90_00fff8[] = { /* for 0x00fff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; static struct gp_cfg_directive pic18f66j90_00fff9[] = { /* for 0x00fff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f66j90_00fffa[] = { /* for 0x00fffa */ { "OSC", 0x07, 8, pic18f65j50_fosc_opts }, { "T1DIG", 0x08, 2, pic18f46k20_hfofst_opts }, { "LPT1OSC", 0x10, 2, pic18f8627_cp4_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18f66j90_00fffb[] = { /* for 0x00fffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_option pic18f66j90_rtcsosc_opts[] = { /* for RTCSOSC: */ { "INTOSCREF", 0x00 }, { "T1OSCREF", 0x02 }, }; static struct gp_cfg_directive pic18f66j90_00fffc[] = { /* for 0x00fffc */ { "RTCSOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, }; static struct gp_cfg_directive pic18f66j90_00fffd[] = { /* for 0x00fffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F66J90: */ static struct gp_cfg_addr gp_cfg_pic18f66j90_addrs[] = { { 0x00fff8, 0xe1, 3, pic18f66j90_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xdf, 5, pic18f66j90_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0x02, 1, pic18f66j90_00fffc }, { 0x00fffd, 0xf1, 1, pic18f66j90_00fffd }, }; /* * PIC18F6490 */ static struct gp_cfg_directive pic18f6490_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "CCP2MX", 0x01, 2, pic18f2525_ccp2mx_opts }, }; /* config addresses for PIC18F6490: */ static struct gp_cfg_addr gp_cfg_pic18f6490_addrs[] = { { 0x300001, 0x07, 3, pic18f6410_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x81, 3, pic18f6490_300005 }, { 0x300006, 0x81, 3, pic18f6410_300006 }, { 0x300008, 0x01, 1, pic18f6410_300008 }, }; /* * PIC18F2520 */ /* config addresses for PIC18F2520: */ static struct gp_cfg_addr gp_cfg_pic18f2520_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2525_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F8520 */ static struct gp_cfg_directive pic18f8520_300001[] = { /* for 0x300001 */ { "OSC", 0x07, 8, pic18c858_osc_opts }, { "OSCS", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f8520_300004[] = { /* for 0x300004 */ { "MODE", 0x03, 4, pic18f8627_mode_opts }, { "WAIT", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_option pic18f8520_ccp2mux_opts[] = { /* for CCP2MUX: */ { "OFF", 0x00 }, { "RE7", 0x00 }, { "ON", 0x01 }, { "RC1", 0x01 }, }; static struct gp_cfg_directive pic18f8520_300005[] = { /* for 0x300005 */ { "CCP2MUX", 0x01, 4, pic18f8520_ccp2mux_opts }, }; static struct gp_cfg_directive pic18f8520_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, { "CP3", 0x08, 2, pic18f2523_cp3_opts }, }; static struct gp_cfg_directive pic18f8520_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, { "WRT3", 0x08, 2, pic18f2523_cp3_opts }, }; static struct gp_cfg_directive pic18f8520_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, { "EBTR3", 0x08, 2, pic18f2523_cp3_opts }, }; /* config addresses for PIC18F8520: */ static struct gp_cfg_addr gp_cfg_pic18f8520_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x03, 1, pic18f8520_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0xff, 4, pic18f8520_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 4, pic18f8520_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 4, pic18f8520_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F242 */ static struct gp_cfg_directive pic18f242_300005[] = { /* for 0x300005 */ { "CCP2MUX", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F242: */ static struct gp_cfg_addr gp_cfg_pic18f242_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18LF45J50 */ static struct gp_cfg_directive pic18lf45j50_007ff8[] = { /* for 0x007ff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; static struct gp_cfg_directive pic18lf45j50_007ff9[] = { /* for 0x007ff9 */ { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18lf45j50_007ffa[] = { /* for 0x007ffa */ { "OSC", 0x07, 8, pic18f65j50_fosc_opts }, { "T1DIG", 0x08, 2, pic18f46k20_hfofst_opts }, { "LPT1OSC", 0x10, 2, pic18f8627_cp4_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18lf45j50_007ffc[] = { /* for 0x007ffc */ { "RTCOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, }; static struct gp_cfg_directive pic18lf45j50_007ffd[] = { /* for 0x007ffd */ { "IOL1WAY", 0x01, 2, pic18f6410_wdt_opts }, { "MSSP7B_EN", 0x08, 2, pic18f65j50_msspmsk_opts }, }; static struct gp_cfg_option pic18lf45j50_wpfp_opts[] = { /* for WPFP: */ { "PAGE_0", 0x00 }, { "PAGE_1", 0x01 }, { "PAGE_2", 0x02 }, { "PAGE_3", 0x03 }, { "PAGE_4", 0x04 }, { "PAGE_5", 0x05 }, { "PAGE_6", 0x06 }, { "PAGE_7", 0x07 }, { "PAGE_8", 0x08 }, { "PAGE_9", 0x09 }, { "PAGE_10", 0x0a }, { "PAGE_11", 0x0b }, { "PAGE_12", 0x0c }, { "PAGE_13", 0x0d }, { "PAGE_14", 0x0e }, { "PAGE_15", 0x0f }, { "PAGE_16", 0x10 }, { "PAGE_17", 0x11 }, { "PAGE_18", 0x12 }, { "PAGE_19", 0x13 }, { "PAGE_20", 0x14 }, { "PAGE_21", 0x15 }, { "PAGE_22", 0x16 }, { "PAGE_23", 0x17 }, { "PAGE_24", 0x18 }, { "PAGE_25", 0x19 }, { "PAGE_26", 0x1a }, { "PAGE_27", 0x1b }, { "PAGE_28", 0x1c }, { "PAGE_29", 0x1d }, { "PAGE_30", 0x1e }, { "PAGE_31", 0x1f }, }; static struct gp_cfg_option pic18lf45j50_wpend_opts[] = { /* for WPEND: */ { "PAGE_0", 0x00 }, { "PAGE_WPFP", 0x40 }, }; static struct gp_cfg_directive pic18lf45j50_007ffe[] = { /* for 0x007ffe */ { "WPFP", 0x3f, 32, pic18lf45j50_wpfp_opts }, { "WPEND", 0x40, 2, pic18lf45j50_wpend_opts }, { "WPCFG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18lf45j50_007fff[] = { /* for 0x007fff */ { "WPDIS", 0x01, 2, pic18f6410_pwrt_opts }, }; /* config addresses for PIC18LF45J50: */ static struct gp_cfg_addr gp_cfg_pic18lf45j50_addrs[] = { { 0x007ff8, 0xef, 4, pic18lf45j50_007ff8 }, { 0x007ff9, 0xf7, 2, pic18lf45j50_007ff9 }, { 0x007ffa, 0xdf, 5, pic18lf45j50_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0x02, 1, pic18lf45j50_007ffc }, { 0x007ffd, 0xf9, 2, pic18lf45j50_007ffd }, { 0x007ffe, 0xff, 3, pic18lf45j50_007ffe }, { 0x007fff, 0xf1, 1, pic18lf45j50_007fff }, }; /* * PIC18F8720 */ static struct gp_cfg_directive pic18f8720_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, { "CP3", 0x08, 2, pic18f2523_cp3_opts }, { "CP4", 0x10, 2, pic18f8627_cp4_opts }, { "CP5", 0x20, 2, pic18f2525_wrtc_opts }, { "CP6", 0x40, 2, pic18f2525_cpb_opts }, { "CP7", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f8720_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, { "WRT3", 0x08, 2, pic18f2523_cp3_opts }, { "WRT4", 0x10, 2, pic18f8627_cp4_opts }, { "WRT5", 0x20, 2, pic18f2525_wrtc_opts }, { "WRT6", 0x40, 2, pic18f2525_cpb_opts }, { "WRT7", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f8720_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, { "EBTR3", 0x08, 2, pic18f2523_cp3_opts }, { "EBTR4", 0x10, 2, pic18f8627_cp4_opts }, { "EBTR5", 0x20, 2, pic18f2525_wrtc_opts }, { "EBTR6", 0x40, 2, pic18f2525_cpb_opts }, { "EBTR7", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F8720: */ static struct gp_cfg_addr gp_cfg_pic18f8720_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0xff, 8, pic18f8720_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 8, pic18f8720_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 8, pic18f8720_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F8722 */ /* config addresses for PIC18F8722: */ static struct gp_cfg_addr gp_cfg_pic18f8722_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0xf3, 4, pic18f8627_300004 }, { 0x300005, 0x83, 4, pic18f8627_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 8, pic18f8720_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 8, pic18f8720_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 8, pic18f8720_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F26J50 */ static struct gp_cfg_directive pic18f26j50_00fff8[] = { /* for 0x00fff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; static struct gp_cfg_directive pic18f26j50_00fff9[] = { /* for 0x00fff9 */ { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_option pic18f26j50_dswdtosc_opts[] = { /* for DSWDTOSC: */ { "T1OSCREF", 0x00 }, { "INTOSCREF", 0x01 }, }; static struct gp_cfg_option pic18f26j50_dswdtps_opts[] = { /* for DSWDTPS: */ { "2", 0x00 }, { "8", 0x10 }, { "32", 0x20 }, { "128", 0x30 }, { "512", 0x40 }, { "2048", 0x50 }, { "8192", 0x60 }, { "K32", 0x70 }, { "K131", 0x80 }, { "K524", 0x90 }, { "M2", 0xa0 }, { "M8", 0xb0 }, { "M33", 0xc0 }, { "M134", 0xd0 }, { "M536", 0xe0 }, { "G2", 0xf0 }, }; static struct gp_cfg_directive pic18f26j50_00fffc[] = { /* for 0x00fffc */ { "DSWDTOSC", 0x01, 2, pic18f26j50_dswdtosc_opts }, { "RTCOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, { "DSBOREN", 0x04, 2, pic18f6410_lpt1osc_opts }, { "DSWDTEN", 0x08, 2, pic18f46k20_hfofst_opts }, { "DSWDTPS", 0xf0, 16, pic18f26j50_dswdtps_opts }, }; static struct gp_cfg_directive pic18f26j50_00fffd[] = { /* for 0x00fffd */ { "IOL1WAY", 0x01, 2, pic18f6410_wdt_opts }, { "MSSP7B_EN", 0x08, 2, pic18f65j50_msspmsk_opts }, }; static struct gp_cfg_option pic18f26j50_wpfp_opts[] = { /* for WPFP: */ { "PAGE_0", 0x00 }, { "PAGE_1", 0x01 }, { "PAGE_2", 0x02 }, { "PAGE_3", 0x03 }, { "PAGE_4", 0x04 }, { "PAGE_5", 0x05 }, { "PAGE_6", 0x06 }, { "PAGE_7", 0x07 }, { "PAGE_8", 0x08 }, { "PAGE_9", 0x09 }, { "PAGE_10", 0x0a }, { "PAGE_11", 0x0b }, { "PAGE_12", 0x0c }, { "PAGE_13", 0x0d }, { "PAGE_14", 0x0e }, { "PAGE_15", 0x0f }, { "PAGE_16", 0x10 }, { "PAGE_17", 0x11 }, { "PAGE_18", 0x12 }, { "PAGE_19", 0x13 }, { "PAGE_20", 0x14 }, { "PAGE_21", 0x15 }, { "PAGE_22", 0x16 }, { "PAGE_23", 0x17 }, { "PAGE_24", 0x18 }, { "PAGE_25", 0x19 }, { "PAGE_26", 0x1a }, { "PAGE_27", 0x1b }, { "PAGE_28", 0x1c }, { "PAGE_29", 0x1d }, { "PAGE_30", 0x1e }, { "PAGE_31", 0x1f }, { "PAGE_32", 0x20 }, { "PAGE_33", 0x21 }, { "PAGE_34", 0x22 }, { "PAGE_35", 0x23 }, { "PAGE_36", 0x24 }, { "PAGE_37", 0x25 }, { "PAGE_38", 0x26 }, { "PAGE_39", 0x27 }, { "PAGE_40", 0x28 }, { "PAGE_41", 0x29 }, { "PAGE_42", 0x2a }, { "PAGE_43", 0x2b }, { "PAGE_44", 0x2c }, { "PAGE_45", 0x2d }, { "PAGE_46", 0x2e }, { "PAGE_47", 0x2f }, { "PAGE_48", 0x30 }, { "PAGE_49", 0x31 }, { "PAGE_50", 0x32 }, { "PAGE_51", 0x33 }, { "PAGE_52", 0x34 }, { "PAGE_53", 0x35 }, { "PAGE_54", 0x36 }, { "PAGE_55", 0x37 }, { "PAGE_56", 0x38 }, { "PAGE_57", 0x39 }, { "PAGE_58", 0x3a }, { "PAGE_59", 0x3b }, { "PAGE_60", 0x3c }, { "PAGE_61", 0x3d }, { "PAGE_62", 0x3e }, { "PAGE_63", 0x3f }, }; static struct gp_cfg_directive pic18f26j50_00fffe[] = { /* for 0x00fffe */ { "WPFP", 0x3f, 64, pic18f26j50_wpfp_opts }, { "WPEND", 0x40, 2, pic18lf45j50_wpend_opts }, { "WPCFG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f26j50_00ffff[] = { /* for 0x00ffff */ { "WPDIS", 0x01, 2, pic18f6410_pwrt_opts }, }; /* config addresses for PIC18F26J50: */ static struct gp_cfg_addr gp_cfg_pic18f26j50_addrs[] = { { 0x00fff8, 0xef, 4, pic18f26j50_00fff8 }, { 0x00fff9, 0xf7, 2, pic18f26j50_00fff9 }, { 0x00fffa, 0xdf, 5, pic18f66j90_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xff, 5, pic18f26j50_00fffc }, { 0x00fffd, 0xf9, 2, pic18f26j50_00fffd }, { 0x00fffe, 0xff, 3, pic18f26j50_00fffe }, { 0x00ffff, 0xf1, 1, pic18f26j50_00ffff }, }; /* * PIC18F83J11 */ static struct gp_cfg_directive pic18f83j11_001ff8[] = { /* for 0x001ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f83j11_001ff9[] = { /* for 0x001ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_option pic18f83j11_fosc_opts[] = { /* for FOSC: */ { "HS", 0x00 }, { "HSPLL", 0x01 }, { "EC", 0x02 }, { "ECPLL", 0x03 }, }; static struct gp_cfg_directive pic18f83j11_001ffa[] = { /* for 0x001ffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f83j11_001ffb[] = { /* for 0x001ffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_option pic18f83j11_bw_opts[] = { /* for BW: */ { "8", 0x00 }, { "16", 0x40 }, }; static struct gp_cfg_option pic18f83j11_mode_opts[] = { /* for MODE: */ { "XM20", 0x00 }, { "XM16", 0x10 }, { "XM12", 0x20 }, { "MM", 0x30 }, }; static struct gp_cfg_directive pic18f83j11_001ffc[] = { /* for 0x001ffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18f83j11_001ffd[] = { /* for 0x001ffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F83J11: */ static struct gp_cfg_addr gp_cfg_pic18f83j11_addrs[] = { { 0x001ff8, 0xe1, 4, pic18f83j11_001ff8 }, { 0x001ff9, 0xf4, 1, pic18f83j11_001ff9 }, { 0x001ffa, 0xc7, 4, pic18f83j11_001ffa }, { 0x001ffb, 0xff, 1, pic18f83j11_001ffb }, { 0x001ffc, 0xf8, 4, pic18f83j11_001ffc }, { 0x001ffd, 0xf1, 1, pic18f83j11_001ffd }, }; /* * PIC18F248 */ /* config addresses for PIC18F248: */ static struct gp_cfg_addr gp_cfg_pic18f248_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4685 */ static struct gp_cfg_option pic18f4685_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, { "IRCIO67", 0x08 }, { "IRCIO7", 0x09 }, }; static struct gp_cfg_directive pic18f4685_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 10, pic18f4685_osc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18f4685_boren_opts[] = { /* for BOREN: */ { "OFF", 0x00 }, { "SBORENCTRL", 0x02 }, { "BOACTIVE", 0x04 }, { "BOHW", 0x06 }, }; static struct gp_cfg_directive pic18f4685_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOREN", 0x06, 4, pic18f4685_boren_opts }, { "BORV", 0x18, 4, pic18f6410_borv_opts }, }; static struct gp_cfg_option pic18f4685_bbsiz_opts[] = { /* for BBSIZ: */ { "1024", 0x00 }, { "2048", 0x10 }, { "4096", 0x20 }, }; static struct gp_cfg_directive pic18f4685_300006[] = { /* for 0x300006 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "BBSIZ", 0x30, 3, pic18f4685_bbsiz_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f4685_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, { "CP3", 0x08, 2, pic18f2523_cp3_opts }, { "CP4", 0x10, 2, pic18f8627_cp4_opts }, { "CP5", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f4685_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, { "WRT3", 0x08, 2, pic18f2523_cp3_opts }, { "WRT4", 0x10, 2, pic18f8627_cp4_opts }, { "WRT5", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f4685_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, { "EBTR3", 0x08, 2, pic18f2523_cp3_opts }, { "EBTR4", 0x10, 2, pic18f8627_cp4_opts }, { "EBTR5", 0x20, 2, pic18f2525_wrtc_opts }, }; /* config addresses for PIC18F4685: */ static struct gp_cfg_addr gp_cfg_pic18f4685_addrs[] = { { 0x300001, 0x07, 3, pic18f4685_300001 }, { 0x300002, 0x1f, 3, pic18f4685_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 5, pic18f4685_300006 }, { 0x300008, 0x3f, 6, pic18f4685_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x3f, 6, pic18f4685_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x3f, 6, pic18f4685_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2680 */ /* config addresses for PIC18F2680: */ static struct gp_cfg_addr gp_cfg_pic18f2680_addrs[] = { { 0x300001, 0x07, 3, pic18f4685_300001 }, { 0x300002, 0x1f, 3, pic18f4685_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 5, pic18f4685_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2320 */ /* config addresses for PIC18F2320: */ static struct gp_cfg_addr gp_cfg_pic18f2320_addrs[] = { { 0x300001, 0xcf, 3, pic18f4220_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 3, pic18f4220_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2321 */ static struct gp_cfg_option pic18f2321_bbsiz_opts[] = { /* for BBSIZ: */ { "BB256", 0x00 }, { "BB512", 0x10 }, { "BB1K", 0x30 }, }; static struct gp_cfg_directive pic18f2321_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "BBSIZ", 0x30, 3, pic18f2321_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F2321: */ static struct gp_cfg_addr gp_cfg_pic18f2321_addrs[] = { { 0x300001, 0x07, 3, pic18f4221_300001 }, { 0x300002, 0x1f, 3, pic18f4221_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4221_300005 }, { 0x300006, 0x85, 5, pic18f2321_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f4221_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2455 */ /* config addresses for PIC18F2455: */ static struct gp_cfg_addr gp_cfg_pic18f2455_addrs[] = { { 0x300000, 0x00, 3, pic18f4450_300000 }, { 0x300001, 0x05, 3, pic18f4450_300001 }, { 0x300002, 0x1f, 4, pic18f4458_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4458_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F87J90 */ static struct gp_cfg_directive pic18f87j90_01fff8[] = { /* for 0x01fff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; static struct gp_cfg_directive pic18f87j90_01fff9[] = { /* for 0x01fff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f87j90_01fffa[] = { /* for 0x01fffa */ { "OSC", 0x07, 8, pic18f65j50_fosc_opts }, { "T1DIG", 0x08, 2, pic18f46k20_hfofst_opts }, { "LPT1OSC", 0x10, 2, pic18f8627_cp4_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18f87j90_01fffb[] = { /* for 0x01fffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_directive pic18f87j90_01fffc[] = { /* for 0x01fffc */ { "RTCSOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, }; static struct gp_cfg_directive pic18f87j90_01fffd[] = { /* for 0x01fffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F87J90: */ static struct gp_cfg_addr gp_cfg_pic18f87j90_addrs[] = { { 0x01fff8, 0xe1, 3, pic18f87j90_01fff8 }, { 0x01fff9, 0xf4, 1, pic18f87j90_01fff9 }, { 0x01fffa, 0xdf, 5, pic18f87j90_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0x02, 1, pic18f87j90_01fffc }, { 0x01fffd, 0xf1, 1, pic18f87j90_01fffd }, }; /* * PIC18F4420 */ /* config addresses for PIC18F4420: */ static struct gp_cfg_addr gp_cfg_pic18f4420_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2525_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F66J60 */ static struct gp_cfg_directive pic18f66j60_00fff8[] = { /* for 0x00fff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVR", 0x20, 2, pic18f4450_vregen_opts }, { "WDT", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f66j60_00fffa[] = { /* for 0x00fffa */ { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f66j60_00fffd[] = { /* for 0x00fffd */ { "ETHLED", 0x04, 2, pic18f6410_lpt1osc_opts }, }; /* config addresses for PIC18F66J60: */ static struct gp_cfg_addr gp_cfg_pic18f66j60_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j60_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xc7, 4, pic18f66j60_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffd, 0xf7, 1, pic18f66j60_00fffd }, }; /* * PIC18F8410 */ static struct gp_cfg_directive pic18f8410_300004[] = { /* for 0x300004 */ { "PM", 0x03, 4, pic18f8627_mode_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "WAIT", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f8410_30000c[] = { /* for 0x30000c */ { "EBTR", 0x01, 2, pic18f6410_pwrt_opts }, }; /* config addresses for PIC18F8410: */ static struct gp_cfg_addr gp_cfg_pic18f8410_addrs[] = { { 0x300001, 0x07, 3, pic18f6410_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0xc3, 3, pic18f8410_300004 }, { 0x300005, 0x81, 3, pic18f6490_300005 }, { 0x300006, 0x81, 3, pic18f6410_300006 }, { 0x300008, 0x01, 1, pic18f6410_300008 }, { 0x30000c, 0x01, 1, pic18f8410_30000c }, }; /* * PIC18F84J11 */ static struct gp_cfg_directive pic18f84j11_003ff8[] = { /* for 0x003ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f84j11_003ff9[] = { /* for 0x003ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f84j11_003ffa[] = { /* for 0x003ffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f84j11_003ffb[] = { /* for 0x003ffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_directive pic18f84j11_003ffc[] = { /* for 0x003ffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18f84j11_003ffd[] = { /* for 0x003ffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F84J11: */ static struct gp_cfg_addr gp_cfg_pic18f84j11_addrs[] = { { 0x003ff8, 0xe1, 4, pic18f84j11_003ff8 }, { 0x003ff9, 0xf4, 1, pic18f84j11_003ff9 }, { 0x003ffa, 0xc7, 4, pic18f84j11_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0xf8, 4, pic18f84j11_003ffc }, { 0x003ffd, 0xf1, 1, pic18f84j11_003ffd }, }; /* * PIC18F66J65 */ static struct gp_cfg_directive pic18f66j65_017ff8[] = { /* for 0x017ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVR", 0x20, 2, pic18f4450_vregen_opts }, { "WDT", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f66j65_017ff9[] = { /* for 0x017ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f66j65_017ffa[] = { /* for 0x017ffa */ { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f66j65_017ffb[] = { /* for 0x017ffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_directive pic18f66j65_017ffd[] = { /* for 0x017ffd */ { "ETHLED", 0x04, 2, pic18f6410_lpt1osc_opts }, }; /* config addresses for PIC18F66J65: */ static struct gp_cfg_addr gp_cfg_pic18f66j65_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j65_017ff8 }, { 0x017ff9, 0xf4, 1, pic18f66j65_017ff9 }, { 0x017ffa, 0xc7, 4, pic18f66j65_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffd, 0xf7, 1, pic18f66j65_017ffd }, }; /* * PIC18F85J50 */ static struct gp_cfg_directive pic18f85j50_007ffc[] = { /* for 0x007ffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_option pic18f85j50_pmpmx_opts[] = { /* for PMPMX: */ { "ALTERNATE", 0x00 }, { "DEFAULT", 0x04 }, }; static struct gp_cfg_option pic18f85j50_eccpmx_opts[] = { /* for ECCPMX: */ { "ALTERNATE", 0x00 }, { "DEFAULT", 0x02 }, }; static struct gp_cfg_directive pic18f85j50_007ffd[] = { /* for 0x007ffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "PMPMX", 0x04, 2, pic18f85j50_pmpmx_opts }, { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F85J50: */ static struct gp_cfg_addr gp_cfg_pic18f85j50_addrs[] = { { 0x007ff8, 0xef, 5, pic18f65j50_007ff8 }, { 0x007ff9, 0xf7, 2, pic18f65j50_007ff9 }, { 0x007ffa, 0xc7, 3, pic18f65j50_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xf8, 4, pic18f85j50_007ffc }, { 0x007ffd, 0xff, 4, pic18f85j50_007ffd }, }; /* * PIC18F86J55 */ static struct gp_cfg_directive pic18f86j55_017ff8[] = { /* for 0x017ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f86j55_017ff9[] = { /* for 0x017ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, }; static struct gp_cfg_directive pic18f86j55_017ffa[] = { /* for 0x017ffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC", 0x07, 8, pic18f65j50_fosc_opts }, }; static struct gp_cfg_directive pic18f86j55_017ffc[] = { /* for 0x017ffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18f86j55_017ffd[] = { /* for 0x017ffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "PMPMX", 0x04, 2, pic18f85j50_pmpmx_opts }, { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F86J55: */ static struct gp_cfg_addr gp_cfg_pic18f86j55_addrs[] = { { 0x017ff8, 0xef, 5, pic18f86j55_017ff8 }, { 0x017ff9, 0xf7, 2, pic18f86j55_017ff9 }, { 0x017ffa, 0xc7, 3, pic18f86j55_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 4, pic18f86j55_017ffc }, { 0x017ffd, 0xff, 4, pic18f86j55_017ffd }, }; /* * PIC18LF14K22 */ static struct gp_cfg_option pic18lf14k22_fosc_opts[] = { /* for FOSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "ERCCLKOUT", 0x03 }, { "ECCLKOUTH", 0x04 }, { "ECH", 0x05 }, { "ERC", 0x07 }, { "IRC", 0x08 }, { "IRCCLKOUT", 0x09 }, { "ECCLKOUTM", 0x0a }, { "ECM", 0x0b }, { "ECCLKOUTL", 0x0c }, { "ECL", 0x0d }, }; static struct gp_cfg_option pic18lf14k22_pllen_opts[] = { /* for PLLEN: */ { "OFF", 0x00 }, { "ON", 0x10 }, }; static struct gp_cfg_directive pic18lf14k22_300001[] = { /* for 0x300001 */ { "FOSC", 0x0f, 13, pic18lf14k22_fosc_opts }, { "PLLEN", 0x10, 2, pic18lf14k22_pllen_opts }, { "PCLKEN", 0x20, 2, pic18f4450_vregen_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_option pic18lf14k22_borv_opts[] = { /* for BORV: */ { "30", 0x00 }, { "27", 0x08 }, { "22", 0x10 }, { "19", 0x18 }, }; static struct gp_cfg_directive pic18lf14k22_300002[] = { /* for 0x300002 */ { "PWRTEN", 0x01, 2, pic18f6410_pwrt_opts }, { "BOREN", 0x06, 4, pic18f6410_boren_opts }, { "BORV", 0x18, 4, pic18lf14k22_borv_opts }, }; static struct gp_cfg_directive pic18lf14k22_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "HFOFST", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18lf14k22_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "BBSIZ", 0x08, 2, pic18f46k20_hfofst_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; /* config addresses for PIC18LF14K22: */ static struct gp_cfg_addr gp_cfg_pic18lf14k22_addrs[] = { { 0x300001, 0x27, 5, pic18lf14k22_300001 }, { 0x300002, 0x1f, 3, pic18lf14k22_300002 }, { 0x300003, 0x1f, 2, pic18f46k20_300003 }, { 0x300005, 0x88, 2, pic18lf14k22_300005 }, { 0x300006, 0x05, 4, pic18lf14k22_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2439 */ static struct gp_cfg_directive pic18f2439_300001[] = { /* for 0x300001 */ { "OSC", 0x07, 8, pic18c858_osc_opts }, }; /* config addresses for PIC18F2439: */ static struct gp_cfg_addr gp_cfg_pic18f2439_addrs[] = { { 0x300001, 0x22, 1, pic18f2439_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F86J65 */ static struct gp_cfg_directive pic18f86j65_017ffd[] = { /* for 0x017ffd */ { "ETHLED", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ECCPMX", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F86J65: */ static struct gp_cfg_addr gp_cfg_pic18f86j65_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j65_017ff8 }, { 0x017ff9, 0xf4, 1, pic18f66j65_017ff9 }, { 0x017ffa, 0xc7, 4, pic18f66j65_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffd, 0xf7, 3, pic18f86j65_017ffd }, }; /* * PIC18F86J60 */ static struct gp_cfg_directive pic18f86j60_00fffd[] = { /* for 0x00fffd */ { "ETHLED", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ECCPMX", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F86J60: */ static struct gp_cfg_addr gp_cfg_pic18f86j60_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j60_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xc7, 4, pic18f66j60_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffd, 0xf7, 3, pic18f86j60_00fffd }, }; /* * PIC18F85J15 */ static struct gp_cfg_directive pic18f85j15_00bff8[] = { /* for 0x00bff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f85j15_00bff9[] = { /* for 0x00bff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f85j15_00bffa[] = { /* for 0x00bffa */ { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f85j15_00bffb[] = { /* for 0x00bffb */ { "WDTPS", 0x0f, 16, pic18f65j50_wdtps_opts }, }; static struct gp_cfg_directive pic18f85j15_00bffc[] = { /* for 0x00bffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18f85j15_00bffd[] = { /* for 0x00bffd */ { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F85J15: */ static struct gp_cfg_addr gp_cfg_pic18f85j15_addrs[] = { { 0x00bff8, 0xe1, 4, pic18f85j15_00bff8 }, { 0x00bff9, 0xf4, 1, pic18f85j15_00bff9 }, { 0x00bffa, 0xc7, 4, pic18f85j15_00bffa }, { 0x00bffb, 0xff, 1, pic18f85j15_00bffb }, { 0x00bffc, 0xf8, 4, pic18f85j15_00bffc }, { 0x00bffd, 0xf3, 2, pic18f85j15_00bffd }, }; /* * PIC18F85J10 */ static struct gp_cfg_directive pic18f85j10_007ff8[] = { /* for 0x007ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f85j10_007ff9[] = { /* for 0x007ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f85j10_007ffa[] = { /* for 0x007ffa */ { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f85j10_007ffd[] = { /* for 0x007ffd */ { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F85J10: */ static struct gp_cfg_addr gp_cfg_pic18f85j10_addrs[] = { { 0x007ff8, 0xe1, 4, pic18f85j10_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xc7, 4, pic18f85j10_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xf8, 4, pic18f85j50_007ffc }, { 0x007ffd, 0xf3, 2, pic18f85j10_007ffd }, }; /* * PIC18F85J11 */ static struct gp_cfg_directive pic18f85j11_007ffa[] = { /* for 0x007ffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f85j11_007ffd[] = { /* for 0x007ffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F85J11: */ static struct gp_cfg_addr gp_cfg_pic18f85j11_addrs[] = { { 0x007ff8, 0xe1, 4, pic18f85j10_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xc7, 4, pic18f85j11_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xf8, 4, pic18f85j50_007ffc }, { 0x007ffd, 0xf1, 1, pic18f85j11_007ffd }, }; /* * PIC18F2331 */ static struct gp_cfg_option pic18f2331_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC2", 0x03 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, { "IRCIO", 0x08 }, { "IRC", 0x09 }, { "RC1", 0x0b }, { "RC", 0x0f }, }; static struct gp_cfg_directive pic18f2331_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 12, pic18f2331_osc_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18f2331_300002[] = { /* for 0x300002 */ { "PWRTEN", 0x01, 2, pic18f6410_pwrt_opts }, { "BOREN", 0x02, 2, pic18f2525_pbaden_opts }, { "BORV", 0x0c, 4, pic18f4220_borv_opts }, }; static struct gp_cfg_directive pic18f2331_300003[] = { /* for 0x300003 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "WINEN", 0x20, 2, pic18f2525_wrtc_opts }, { "WDPS", 0x1e, 16, pic18f6410_wdtps_opts }, }; static struct gp_cfg_option pic18f2331_hpol_opts[] = { /* for HPOL: */ { "LOW", 0x00 }, { "HIGH", 0x10 }, }; static struct gp_cfg_option pic18f2331_lpol_opts[] = { /* for LPOL: */ { "LOW", 0x00 }, { "HIGH", 0x08 }, }; static struct gp_cfg_directive pic18f2331_300004[] = { /* for 0x300004 */ { "T1OSCMX", 0x20, 2, pic18f4450_vregen_opts }, { "HPOL", 0x10, 2, pic18f2331_hpol_opts }, { "LPOL", 0x08, 2, pic18f2331_lpol_opts }, { "PWMPIN", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f2331_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18f2331_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F2331: */ static struct gp_cfg_addr gp_cfg_pic18f2331_addrs[] = { { 0x300001, 0xcf, 3, pic18f2331_300001 }, { 0x300002, 0x0f, 3, pic18f2331_300002 }, { 0x300003, 0x3f, 3, pic18f2331_300003 }, { 0x300004, 0x3c, 4, pic18f2331_300004 }, { 0x300005, 0x9d, 1, pic18f2331_300005 }, { 0x300006, 0x85, 3, pic18f2331_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F65J11 */ /* config addresses for PIC18F65J11: */ static struct gp_cfg_addr gp_cfg_pic18f65j11_addrs[] = { { 0x007ff8, 0xe1, 4, pic18f85j10_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xc7, 4, pic18f85j11_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xf8, 0, NULL }, { 0x007ffd, 0xf1, 1, pic18f85j11_007ffd }, }; /* * PIC18F8527 */ static struct gp_cfg_directive pic18f8527_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f8527_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f8527_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, }; /* config addresses for PIC18F8527: */ static struct gp_cfg_addr gp_cfg_pic18f8527_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0xf3, 4, pic18f8627_300004 }, { 0x300005, 0x83, 4, pic18f8627_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 3, pic18f8527_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 3, pic18f8527_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 3, pic18f8527_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F67J50 */ static struct gp_cfg_directive pic18f67j50_01fff8[] = { /* for 0x01fff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f67j50_01fff9[] = { /* for 0x01fff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, }; static struct gp_cfg_directive pic18f67j50_01fffa[] = { /* for 0x01fffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC", 0x07, 8, pic18f65j50_fosc_opts }, }; static struct gp_cfg_directive pic18f67j50_01fffd[] = { /* for 0x01fffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F67J50: */ static struct gp_cfg_addr gp_cfg_pic18f67j50_addrs[] = { { 0x01fff8, 0xef, 5, pic18f67j50_01fff8 }, { 0x01fff9, 0xf7, 2, pic18f67j50_01fff9 }, { 0x01fffa, 0xc7, 3, pic18f67j50_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 0, NULL }, { 0x01fffd, 0xff, 2, pic18f67j50_01fffd }, }; /* * PIC18F66J16 */ static struct gp_cfg_directive pic18f66j16_017ff8[] = { /* for 0x017ff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f66j16_017ff9[] = { /* for 0x017ff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f66j16_017ffd[] = { /* for 0x017ffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F66J16: */ static struct gp_cfg_addr gp_cfg_pic18f66j16_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j16_017ff8 }, { 0x017ff9, 0xf7, 1, pic18f66j16_017ff9 }, { 0x017ffa, 0xc7, 3, pic18f86j55_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 0, NULL }, { 0x017ffd, 0xff, 2, pic18f66j16_017ffd }, }; /* * PIC18C452 */ /* config addresses for PIC18C452: */ static struct gp_cfg_addr gp_cfg_pic18c452_addrs[] = { { 0x300000, 0xff, 1, pic18c858_300000 }, { 0x300001, 0xe7, 2, pic18c858_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x03, 1, pic18c858_300006 }, }; /* * PIC18F4515 */ /* config addresses for PIC18F4515: */ static struct gp_cfg_addr gp_cfg_pic18f4515_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2525_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0x40, 1, pic18f4450_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0x60, 2, pic18f4450_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F66J10 */ static struct gp_cfg_directive pic18f66j10_00fff8[] = { /* for 0x00fff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f66j10_00fffd[] = { /* for 0x00fffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F66J10: */ static struct gp_cfg_addr gp_cfg_pic18f66j10_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j10_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xc7, 4, pic18f66j60_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 0, NULL }, { 0x00fffd, 0xf3, 1, pic18f66j10_00fffd }, }; /* * PIC18F2423 */ /* config addresses for PIC18F2423: */ static struct gp_cfg_addr gp_cfg_pic18f2423_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2523_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F86J50 */ static struct gp_cfg_directive pic18f86j50_00fff8[] = { /* for 0x00fff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f86j50_00fff9[] = { /* for 0x00fff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, }; static struct gp_cfg_directive pic18f86j50_00fffa[] = { /* for 0x00fffa */ { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "FOSC", 0x07, 8, pic18f65j50_fosc_opts }, }; static struct gp_cfg_directive pic18f86j50_00fffc[] = { /* for 0x00fffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18f86j50_00fffd[] = { /* for 0x00fffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "PMPMX", 0x04, 2, pic18f85j50_pmpmx_opts }, { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F86J50: */ static struct gp_cfg_addr gp_cfg_pic18f86j50_addrs[] = { { 0x00fff8, 0xef, 5, pic18f86j50_00fff8 }, { 0x00fff9, 0xf7, 2, pic18f86j50_00fff9 }, { 0x00fffa, 0xc7, 3, pic18f86j50_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 4, pic18f86j50_00fffc }, { 0x00fffd, 0xff, 4, pic18f86j50_00fffd }, }; /* * PIC18F46J11 */ /* config addresses for PIC18F46J11: */ static struct gp_cfg_addr gp_cfg_pic18f46j11_addrs[] = { { 0x00fff8, 0xe1, 3, pic18f66j90_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xdf, 5, pic18f66j90_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xff, 5, pic18f26j50_00fffc }, { 0x00fffd, 0xf9, 2, pic18f26j50_00fffd }, { 0x00fffe, 0xff, 3, pic18f26j50_00fffe }, { 0x00ffff, 0xf1, 1, pic18f26j50_00ffff }, }; /* * PIC18LF45J11 */ static struct gp_cfg_directive pic18lf45j11_007ff8[] = { /* for 0x007ff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; /* config addresses for PIC18LF45J11: */ static struct gp_cfg_addr gp_cfg_pic18lf45j11_addrs[] = { { 0x007ff8, 0xe1, 3, pic18lf45j11_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xdf, 5, pic18lf45j50_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0x02, 1, pic18lf45j50_007ffc }, { 0x007ffd, 0xf9, 2, pic18lf45j50_007ffd }, { 0x007ffe, 0xff, 3, pic18lf45j50_007ffe }, { 0x007fff, 0xf1, 1, pic18lf45j50_007fff }, }; /* * PIC18F96J60 */ /* config addresses for PIC18F96J60: */ static struct gp_cfg_addr gp_cfg_pic18f96j60_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j60_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xc7, 4, pic18f66j60_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 4, pic18f86j50_00fffc }, { 0x00fffd, 0xf7, 3, pic18f86j60_00fffd }, }; /* * PIC18F64J90 */ /* config addresses for PIC18F64J90: */ static struct gp_cfg_addr gp_cfg_pic18f64j90_addrs[] = { { 0x003ff8, 0xe1, 4, pic18f84j11_003ff8 }, { 0x003ff9, 0xf4, 1, pic18f84j11_003ff9 }, { 0x003ffa, 0xc7, 4, pic18f84j11_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0x00, 0, NULL }, { 0x003ffd, 0xf1, 1, pic18f84j11_003ffd }, }; /* * PIC18F8621 */ static struct gp_cfg_option pic18f8621_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "XT", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, { "EC", 0x04 }, { "ECIO", 0x05 }, { "HSPLL", 0x06 }, { "RCIO", 0x07 }, { "ECIOPLL", 0x0c }, { "ECIOSWPLL", 0x0d }, { "HSSWPLL", 0x0e }, }; static struct gp_cfg_directive pic18f8621_300001[] = { /* for 0x300001 */ { "OSC", 0x0f, 11, pic18f8621_osc_opts }, { "OSCS", 0x20, 2, pic18f2525_wrtc_opts }, }; static struct gp_cfg_directive pic18f8621_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "ECCPMX", 0x02, 2, pic18f8627_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f2525_ccp2mx_opts }, }; /* config addresses for PIC18F8621: */ static struct gp_cfg_addr gp_cfg_pic18f8621_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x83, 3, pic18f8621_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F8620 */ /* config addresses for PIC18F8620: */ static struct gp_cfg_addr gp_cfg_pic18f8620_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0xff, 4, pic18f8520_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 4, pic18f8520_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 4, pic18f8520_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F8525 */ /* config addresses for PIC18F8525: */ static struct gp_cfg_addr gp_cfg_pic18f8525_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x83, 3, pic18f8621_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2221 */ static struct gp_cfg_directive pic18f2221_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "BBSIZ", 0x30, 2, pic18f4221_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F2221: */ static struct gp_cfg_addr gp_cfg_pic18f2221_addrs[] = { { 0x300001, 0x07, 3, pic18f4221_300001 }, { 0x300002, 0x1f, 3, pic18f4221_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4221_300005 }, { 0x300006, 0x85, 5, pic18f2221_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f4221_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F24J50 */ static struct gp_cfg_directive pic18f24j50_003ff8[] = { /* for 0x003ff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "PLLDIV", 0x0e, 8, pic18f65j50_plldiv_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; static struct gp_cfg_directive pic18f24j50_003ff9[] = { /* for 0x003ff9 */ { "CPUDIV", 0x03, 4, pic18f65j50_cpudiv_opts }, { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f24j50_003ffa[] = { /* for 0x003ffa */ { "OSC", 0x07, 8, pic18f65j50_fosc_opts }, { "T1DIG", 0x08, 2, pic18f46k20_hfofst_opts }, { "LPT1OSC", 0x10, 2, pic18f8627_cp4_opts }, { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18f24j50_003ffc[] = { /* for 0x003ffc */ { "DSWDTOSC", 0x01, 2, pic18f26j50_dswdtosc_opts }, { "RTCOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, { "DSBOREN", 0x04, 2, pic18f6410_lpt1osc_opts }, { "DSWDTEN", 0x08, 2, pic18f46k20_hfofst_opts }, { "DSWDTPS", 0xf0, 16, pic18f26j50_dswdtps_opts }, }; static struct gp_cfg_directive pic18f24j50_003ffd[] = { /* for 0x003ffd */ { "IOL1WAY", 0x01, 2, pic18f6410_wdt_opts }, { "MSSP7B_EN", 0x08, 2, pic18f65j50_msspmsk_opts }, }; static struct gp_cfg_option pic18f24j50_wpfp_opts[] = { /* for WPFP: */ { "PAGE_0", 0x00 }, { "PAGE_1", 0x01 }, { "PAGE_2", 0x02 }, { "PAGE_3", 0x03 }, { "PAGE_4", 0x04 }, { "PAGE_5", 0x05 }, { "PAGE_6", 0x06 }, { "PAGE_7", 0x07 }, { "PAGE_8", 0x08 }, { "PAGE_9", 0x09 }, { "PAGE_10", 0x0a }, { "PAGE_11", 0x0b }, { "PAGE_12", 0x0c }, { "PAGE_13", 0x0d }, { "PAGE_14", 0x0e }, { "PAGE_15", 0x0f }, }; static struct gp_cfg_directive pic18f24j50_003ffe[] = { /* for 0x003ffe */ { "WPFP", 0x3f, 16, pic18f24j50_wpfp_opts }, { "WPEND", 0x40, 2, pic18lf45j50_wpend_opts }, { "WPCFG", 0x80, 2, pic18f6410_debug_opts }, }; static struct gp_cfg_directive pic18f24j50_003fff[] = { /* for 0x003fff */ { "WPDIS", 0x01, 2, pic18f6410_pwrt_opts }, }; /* config addresses for PIC18F24J50: */ static struct gp_cfg_addr gp_cfg_pic18f24j50_addrs[] = { { 0x003ff8, 0xef, 4, pic18f24j50_003ff8 }, { 0x003ff9, 0xf7, 2, pic18f24j50_003ff9 }, { 0x003ffa, 0xdf, 5, pic18f24j50_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0xff, 5, pic18f24j50_003ffc }, { 0x003ffd, 0xf9, 2, pic18f24j50_003ffd }, { 0x003ffe, 0xff, 3, pic18f24j50_003ffe }, { 0x003fff, 0xf1, 1, pic18f24j50_003fff }, }; /* * PIC18F8585 */ static struct gp_cfg_directive pic18f8585_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "ECCPMX", 0x02, 2, pic18f8627_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F8585: */ static struct gp_cfg_addr gp_cfg_pic18f8585_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x83, 3, pic18f8585_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2539 */ /* config addresses for PIC18F2539: */ static struct gp_cfg_addr gp_cfg_pic18f2539_addrs[] = { { 0x300001, 0x22, 1, pic18f2439_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F45J50 */ static struct gp_cfg_directive pic18f45j50_007ffc[] = { /* for 0x007ffc */ { "DSWDTOSC", 0x01, 2, pic18f26j50_dswdtosc_opts }, { "RTCOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, { "DSBOREN", 0x04, 2, pic18f6410_lpt1osc_opts }, { "DSWDTEN", 0x08, 2, pic18f46k20_hfofst_opts }, { "DSWDTPS", 0xf0, 16, pic18f26j50_dswdtps_opts }, }; /* config addresses for PIC18F45J50: */ static struct gp_cfg_addr gp_cfg_pic18f45j50_addrs[] = { { 0x007ff8, 0xef, 4, pic18lf45j50_007ff8 }, { 0x007ff9, 0xf7, 2, pic18lf45j50_007ff9 }, { 0x007ffa, 0xdf, 5, pic18lf45j50_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xff, 5, pic18f45j50_007ffc }, { 0x007ffd, 0xf9, 2, pic18lf45j50_007ffd }, { 0x007ffe, 0xff, 3, pic18lf45j50_007ffe }, { 0x007fff, 0xf1, 1, pic18lf45j50_007fff }, }; /* * PIC18F4682 */ static struct gp_cfg_directive pic18f4682_300008[] = { /* for 0x300008 */ { "CP0", 0x01, 2, pic18f6410_pwrt_opts }, { "CP1", 0x02, 2, pic18f2525_cp1_opts }, { "CP2", 0x04, 2, pic18f2525_cp2_opts }, { "CP3", 0x08, 2, pic18f2523_cp3_opts }, { "CP4", 0x10, 2, pic18f8627_cp4_opts }, }; static struct gp_cfg_directive pic18f4682_30000a[] = { /* for 0x30000a */ { "WRT0", 0x01, 2, pic18f6410_pwrt_opts }, { "WRT1", 0x02, 2, pic18f2525_cp1_opts }, { "WRT2", 0x04, 2, pic18f2525_cp2_opts }, { "WRT3", 0x08, 2, pic18f2523_cp3_opts }, { "WRT4", 0x10, 2, pic18f8627_cp4_opts }, }; static struct gp_cfg_directive pic18f4682_30000c[] = { /* for 0x30000c */ { "EBTR0", 0x01, 2, pic18f6410_pwrt_opts }, { "EBTR1", 0x02, 2, pic18f2525_cp1_opts }, { "EBTR2", 0x04, 2, pic18f2525_cp2_opts }, { "EBTR3", 0x08, 2, pic18f2523_cp3_opts }, { "EBTR4", 0x10, 2, pic18f8627_cp4_opts }, }; /* config addresses for PIC18F4682: */ static struct gp_cfg_addr gp_cfg_pic18f4682_addrs[] = { { 0x300001, 0x07, 3, pic18f4685_300001 }, { 0x300002, 0x1f, 3, pic18f4685_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 5, pic18f4685_300006 }, { 0x300008, 0x3f, 5, pic18f4682_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x3f, 5, pic18f4682_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x3f, 5, pic18f4682_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F13K50 */ static struct gp_cfg_option pic18f13k50_cpudiv_opts[] = { /* for CPUDIV: */ { "NOCLKDIV", 0x00 }, { "CLKDIV2", 0x08 }, { "CLKDIV3", 0x10 }, { "CLKDIV4", 0x18 }, }; static struct gp_cfg_directive pic18f13k50_300000[] = { /* for 0x300000 */ { "CPUDIV", 0x18, 4, pic18f13k50_cpudiv_opts }, { "USBDIV", 0x20, 2, pic18f4450_vregen_opts }, }; /* config addresses for PIC18F13K50: */ static struct gp_cfg_addr gp_cfg_pic18f13k50_addrs[] = { { 0x300000, 0x00, 2, pic18f13k50_300000 }, { 0x300001, 0x27, 5, pic18lf14k22_300001 }, { 0x300002, 0x1f, 3, pic18lf14k22_300002 }, { 0x300003, 0x1f, 2, pic18f46k20_300003 }, { 0x300005, 0x88, 2, pic18lf14k22_300005 }, { 0x300006, 0x05, 4, pic18lf14k22_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F67J60 */ static struct gp_cfg_directive pic18f67j60_01fff8[] = { /* for 0x01fff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVR", 0x20, 2, pic18f4450_vregen_opts }, { "WDT", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f67j60_01fffa[] = { /* for 0x01fffa */ { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; static struct gp_cfg_directive pic18f67j60_01fffd[] = { /* for 0x01fffd */ { "ETHLED", 0x04, 2, pic18f6410_lpt1osc_opts }, }; /* config addresses for PIC18F67J60: */ static struct gp_cfg_addr gp_cfg_pic18f67j60_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f67j60_01fff8 }, { 0x01fff9, 0xf4, 1, pic18f87j90_01fff9 }, { 0x01fffa, 0xc7, 4, pic18f67j60_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffd, 0xf7, 1, pic18f67j60_01fffd }, }; /* * PIC18F83J90 */ /* config addresses for PIC18F83J90: */ static struct gp_cfg_addr gp_cfg_pic18f83j90_addrs[] = { { 0x001ff8, 0xe1, 4, pic18f83j11_001ff8 }, { 0x001ff9, 0xf4, 1, pic18f83j11_001ff9 }, { 0x001ffa, 0xc7, 4, pic18f83j11_001ffa }, { 0x001ffb, 0xff, 1, pic18f83j11_001ffb }, { 0x001ffc, 0x00, 0, NULL }, { 0x001ffd, 0xf1, 1, pic18f83j11_001ffd }, }; /* * PIC18F2410 */ /* config addresses for PIC18F2410: */ static struct gp_cfg_addr gp_cfg_pic18f2410_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f2525_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0x40, 1, pic18f4450_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0x60, 2, pic18f4450_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F23K20 */ /* config addresses for PIC18F23K20: */ static struct gp_cfg_addr gp_cfg_pic18f23k20_addrs[] = { { 0x300001, 0x07, 3, pic18f46k20_300001 }, { 0x300002, 0x1f, 3, pic18f46k20_300002 }, { 0x300003, 0x1f, 2, pic18f46k20_300003 }, { 0x300005, 0x8b, 5, pic18f46k20_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18LF46J50 */ static struct gp_cfg_directive pic18lf46j50_00fffc[] = { /* for 0x00fffc */ { "RTCOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, }; /* config addresses for PIC18LF46J50: */ static struct gp_cfg_addr gp_cfg_pic18lf46j50_addrs[] = { { 0x00fff8, 0xef, 4, pic18f26j50_00fff8 }, { 0x00fff9, 0xf7, 2, pic18f26j50_00fff9 }, { 0x00fffa, 0xdf, 5, pic18f66j90_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0x02, 1, pic18lf46j50_00fffc }, { 0x00fffd, 0xf9, 2, pic18f26j50_00fffd }, { 0x00fffe, 0xff, 3, pic18f26j50_00fffe }, { 0x00ffff, 0xf1, 1, pic18f26j50_00ffff }, }; /* * PIC18F87J50 */ static struct gp_cfg_directive pic18f87j50_01fffc[] = { /* for 0x01fffc */ { "WAIT", 0x80, 2, pic18f6410_debug_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, { "MODE", 0x30, 4, pic18f83j11_mode_opts }, { "EASHFT", 0x08, 2, pic18f46k20_hfofst_opts }, }; static struct gp_cfg_directive pic18f87j50_01fffd[] = { /* for 0x01fffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "PMPMX", 0x04, 2, pic18f85j50_pmpmx_opts }, { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F87J50: */ static struct gp_cfg_addr gp_cfg_pic18f87j50_addrs[] = { { 0x01fff8, 0xef, 5, pic18f67j50_01fff8 }, { 0x01fff9, 0xf7, 2, pic18f67j50_01fff9 }, { 0x01fffa, 0xc7, 3, pic18f67j50_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 4, pic18f87j50_01fffc }, { 0x01fffd, 0xff, 4, pic18f87j50_01fffd }, }; /* * PIC18F87J11 */ static struct gp_cfg_directive pic18f87j11_01fff8[] = { /* for 0x01fff8 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, }; static struct gp_cfg_directive pic18f87j11_01fff9[] = { /* for 0x01fff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; /* config addresses for PIC18F87J11: */ static struct gp_cfg_addr gp_cfg_pic18f87j11_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f87j11_01fff8 }, { 0x01fff9, 0xf7, 1, pic18f87j11_01fff9 }, { 0x01fffa, 0xc7, 3, pic18f67j50_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 4, pic18f87j50_01fffc }, { 0x01fffd, 0xff, 4, pic18f87j50_01fffd }, }; /* * PIC18F66J15 */ static struct gp_cfg_directive pic18f66j15_017ffd[] = { /* for 0x017ffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F66J15: */ static struct gp_cfg_addr gp_cfg_pic18f66j15_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j16_017ff8 }, { 0x017ff9, 0xf4, 1, pic18f66j65_017ff9 }, { 0x017ffa, 0xc7, 4, pic18f66j65_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 0, NULL }, { 0x017ffd, 0xf3, 1, pic18f66j15_017ffd }, }; /* * PIC18C801 */ static struct gp_cfg_option pic18c801_osc_opts[] = { /* for OSC: */ { "LP", 0x00 }, { "EC", 0x01 }, { "HS", 0x02 }, { "RC", 0x03 }, }; static struct gp_cfg_directive pic18c801_300001[] = { /* for 0x300001 */ { "OSC", 0x03, 4, pic18c801_osc_opts }, }; static struct gp_cfg_directive pic18c801_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BW", 0x40, 2, pic18f83j11_bw_opts }, }; static struct gp_cfg_directive pic18c801_300003[] = { /* for 0x300003 */ { "WDT", 0x01, 2, pic18f6410_wdt_opts }, { "WDTPS", 0x0e, 8, pic18c858_wdtps_opts }, }; static struct gp_cfg_directive pic18c801_300006[] = { /* for 0x300006 */ { "STVR", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18C801: */ static struct gp_cfg_addr gp_cfg_pic18c801_addrs[] = { { 0x300001, 0x03, 1, pic18c801_300001 }, { 0x300002, 0x41, 2, pic18c801_300002 }, { 0x300003, 0x0e, 2, pic18c801_300003 }, { 0x300006, 0x81, 1, pic18c801_300006 }, }; /* * PIC18F8680 */ /* config addresses for PIC18F8680: */ static struct gp_cfg_addr gp_cfg_pic18f8680_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 2, pic18f8520_300004 }, { 0x300005, 0x83, 3, pic18f8585_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6585 */ static struct gp_cfg_directive pic18f6585_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "CCP2MX", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F6585: */ static struct gp_cfg_addr gp_cfg_pic18f6585_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 0, NULL }, { 0x300005, 0x83, 2, pic18f6585_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F25J10 */ /* config addresses for PIC18F25J10: */ static struct gp_cfg_addr gp_cfg_pic18f25j10_addrs[] = { { 0x007ff8, 0xe1, 4, pic18f85j10_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xc7, 4, pic18f85j10_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffd, 0xf1, 1, pic18f85j11_007ffd }, }; /* * PIC18F25J11 */ /* config addresses for PIC18F25J11: */ static struct gp_cfg_addr gp_cfg_pic18f25j11_addrs[] = { { 0x007ff8, 0xe1, 3, pic18lf45j11_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xdf, 5, pic18lf45j50_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xff, 5, pic18f45j50_007ffc }, { 0x007ffd, 0xf9, 2, pic18lf45j50_007ffd }, { 0x007ffe, 0xff, 3, pic18lf45j50_007ffe }, { 0x007fff, 0xf1, 1, pic18lf45j50_007fff }, }; /* * PIC18F66J11 */ static struct gp_cfg_directive pic18f66j11_00fff9[] = { /* for 0x00fff9 */ { "CP0", 0x04, 2, pic18f2525_cp2_opts }, }; static struct gp_cfg_directive pic18f66j11_00fffd[] = { /* for 0x00fffd */ { "MSSPMSK", 0x08, 2, pic18f65j50_msspmsk_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F66J11: */ static struct gp_cfg_addr gp_cfg_pic18f66j11_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j10_00fff8 }, { 0x00fff9, 0xf7, 1, pic18f66j11_00fff9 }, { 0x00fffa, 0xc7, 3, pic18f86j50_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 0, NULL }, { 0x00fffd, 0xff, 2, pic18f66j11_00fffd }, }; /* * PIC18F97J60 */ static struct gp_cfg_directive pic18f97j60_01fffd[] = { /* for 0x01fffd */ { "ETHLED", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ECCPMX", 0x02, 2, pic18f2525_pbaden_opts }, { "CCP2MX", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F97J60: */ static struct gp_cfg_addr gp_cfg_pic18f97j60_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f67j60_01fff8 }, { 0x01fff9, 0xf4, 1, pic18f87j90_01fff9 }, { 0x01fffa, 0xc7, 4, pic18f67j60_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 4, pic18f87j50_01fffc }, { 0x01fffd, 0xf7, 3, pic18f97j60_01fffd }, }; /* * PIC18LF26J11 */ /* config addresses for PIC18LF26J11: */ static struct gp_cfg_addr gp_cfg_pic18lf26j11_addrs[] = { { 0x00fff8, 0xe1, 3, pic18f66j90_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xdf, 5, pic18f66j90_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0x02, 1, pic18lf46j50_00fffc }, { 0x00fffd, 0xf9, 2, pic18f26j50_00fffd }, { 0x00fffe, 0xff, 3, pic18f26j50_00fffe }, { 0x00ffff, 0xf1, 1, pic18f26j50_00ffff }, }; /* * PIC18F66J50 */ /* config addresses for PIC18F66J50: */ static struct gp_cfg_addr gp_cfg_pic18f66j50_addrs[] = { { 0x00fff8, 0xef, 5, pic18f86j50_00fff8 }, { 0x00fff9, 0xf7, 2, pic18f86j50_00fff9 }, { 0x00fffa, 0xc7, 3, pic18f86j50_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 0, NULL }, { 0x00fffd, 0xff, 2, pic18f66j11_00fffd }, }; /* * PIC18F66J55 */ /* config addresses for PIC18F66J55: */ static struct gp_cfg_addr gp_cfg_pic18f66j55_addrs[] = { { 0x017ff8, 0xef, 5, pic18f86j55_017ff8 }, { 0x017ff9, 0xf7, 2, pic18f86j55_017ff9 }, { 0x017ffa, 0xc7, 3, pic18f86j55_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 0, NULL }, { 0x017ffd, 0xff, 2, pic18f66j16_017ffd }, }; /* * PIC18F65J10 */ static struct gp_cfg_directive pic18f65j10_007ffd[] = { /* for 0x007ffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F65J10: */ static struct gp_cfg_addr gp_cfg_pic18f65j10_addrs[] = { { 0x007ff8, 0xe1, 4, pic18f85j10_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xc7, 4, pic18f85j10_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0xf8, 0, NULL }, { 0x007ffd, 0xf3, 1, pic18f65j10_007ffd }, }; /* * PIC18F2480 */ static struct gp_cfg_option pic18f2480_bbsiz_opts[] = { /* for BBSIZ: */ { "1024", 0x00 }, { "2048", 0x10 }, }; static struct gp_cfg_directive pic18f2480_300006[] = { /* for 0x300006 */ { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "BBSIZ", 0x10, 2, pic18f2480_bbsiz_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, }; /* config addresses for PIC18F2480: */ static struct gp_cfg_addr gp_cfg_pic18f2480_addrs[] = { { 0x300001, 0x07, 3, pic18f4685_300001 }, { 0x300002, 0x1f, 3, pic18f4685_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 5, pic18f2480_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F65J15 */ static struct gp_cfg_directive pic18f65j15_00bffd[] = { /* for 0x00bffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F65J15: */ static struct gp_cfg_addr gp_cfg_pic18f65j15_addrs[] = { { 0x00bff8, 0xe1, 4, pic18f85j15_00bff8 }, { 0x00bff9, 0xf4, 1, pic18f85j15_00bff9 }, { 0x00bffa, 0xc7, 4, pic18f85j15_00bffa }, { 0x00bffb, 0xff, 1, pic18f85j15_00bffb }, { 0x00bffc, 0xf8, 0, NULL }, { 0x00bffd, 0xf3, 1, pic18f65j15_00bffd }, }; /* * PIC18F6722 */ static struct gp_cfg_directive pic18f6722_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "LPT1OSC", 0x04, 2, pic18f6410_lpt1osc_opts }, { "CCP2MX", 0x01, 2, pic18f6410_ccp2mx_opts }, }; /* config addresses for PIC18F6722: */ static struct gp_cfg_addr gp_cfg_pic18f6722_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 3, pic18f6722_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 8, pic18f8720_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 8, pic18f8720_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 8, pic18f8720_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6720 */ /* config addresses for PIC18F6720: */ static struct gp_cfg_addr gp_cfg_pic18f6720_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300004, 0x03, 0, NULL }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0xff, 8, pic18f8720_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 8, pic18f8720_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 8, pic18f8720_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F452 */ /* config addresses for PIC18F452: */ static struct gp_cfg_addr gp_cfg_pic18f452_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F458 */ /* config addresses for PIC18F458: */ static struct gp_cfg_addr gp_cfg_pic18f458_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18LF44J50 */ static struct gp_cfg_directive pic18lf44j50_003ffc[] = { /* for 0x003ffc */ { "RTCOSC", 0x02, 2, pic18f66j90_rtcsosc_opts }, }; /* config addresses for PIC18LF44J50: */ static struct gp_cfg_addr gp_cfg_pic18lf44j50_addrs[] = { { 0x003ff8, 0xef, 4, pic18f24j50_003ff8 }, { 0x003ff9, 0xf7, 2, pic18f24j50_003ff9 }, { 0x003ffa, 0xdf, 5, pic18f24j50_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0x02, 1, pic18lf44j50_003ffc }, { 0x003ffd, 0xf9, 2, pic18f24j50_003ffd }, { 0x003ffe, 0xff, 3, pic18f24j50_003ffe }, { 0x003fff, 0xf1, 1, pic18f24j50_003fff }, }; /* * PIC18F2550 */ /* config addresses for PIC18F2550: */ static struct gp_cfg_addr gp_cfg_pic18f2550_addrs[] = { { 0x300000, 0x00, 3, pic18f4450_300000 }, { 0x300001, 0x05, 3, pic18f4450_300001 }, { 0x300002, 0x1f, 4, pic18f4458_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4458_300005 }, { 0x300006, 0x85, 4, pic18f2525_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6520 */ /* config addresses for PIC18F6520: */ static struct gp_cfg_addr gp_cfg_pic18f6520_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300004, 0x03, 0, NULL }, { 0x300005, 0x03, 1, pic18f8520_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0xff, 4, pic18f8520_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 4, pic18f8520_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 4, pic18f8520_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F63J11 */ /* config addresses for PIC18F63J11: */ static struct gp_cfg_addr gp_cfg_pic18f63j11_addrs[] = { { 0x001ff8, 0xe1, 4, pic18f83j11_001ff8 }, { 0x001ff9, 0xf4, 1, pic18f83j11_001ff9 }, { 0x001ffa, 0xc7, 4, pic18f83j11_001ffa }, { 0x001ffb, 0xff, 1, pic18f83j11_001ffb }, { 0x001ffc, 0xf8, 0, NULL }, { 0x001ffd, 0xf1, 1, pic18f83j11_001ffd }, }; /* * PIC18F6525 */ static struct gp_cfg_directive pic18f6525_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "CCP2MX", 0x01, 2, pic18f2525_ccp2mx_opts }, }; /* config addresses for PIC18F6525: */ static struct gp_cfg_addr gp_cfg_pic18f6525_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 0, NULL }, { 0x300005, 0x83, 2, pic18f6525_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F85J90 */ /* config addresses for PIC18F85J90: */ static struct gp_cfg_addr gp_cfg_pic18f85j90_addrs[] = { { 0x007ff8, 0xe1, 4, pic18f85j10_007ff8 }, { 0x007ff9, 0xf4, 1, pic18f85j10_007ff9 }, { 0x007ffa, 0xc7, 4, pic18f85j11_007ffa }, { 0x007ffb, 0xff, 1, pic18f65j50_007ffb }, { 0x007ffc, 0x00, 0, NULL }, { 0x007ffd, 0xf1, 1, pic18f85j11_007ffd }, }; /* * PIC18F1220 */ static struct gp_cfg_option pic18f1220_borv_opts[] = { /* for BORV: */ { "45", 0x00 }, { "42", 0x04 }, { "27", 0x08 }, }; static struct gp_cfg_directive pic18f1220_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x02, 2, pic18f2525_pbaden_opts }, { "BORV", 0x0c, 3, pic18f1220_borv_opts }, }; static struct gp_cfg_directive pic18f1220_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, }; /* config addresses for PIC18F1220: */ static struct gp_cfg_addr gp_cfg_pic18f1220_addrs[] = { { 0x300001, 0xcf, 3, pic18f4220_300001 }, { 0x300002, 0x0f, 3, pic18f1220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x80, 1, pic18f1220_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4553 */ /* config addresses for PIC18F4553: */ static struct gp_cfg_addr gp_cfg_pic18f4553_addrs[] = { { 0x300000, 0x00, 3, pic18f4450_300000 }, { 0x300001, 0x05, 3, pic18f4450_300001 }, { 0x300002, 0x1f, 4, pic18f4458_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4458_300005 }, { 0x300006, 0x85, 5, pic18f4458_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6680 */ /* config addresses for PIC18F6680: */ static struct gp_cfg_addr gp_cfg_pic18f6680_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 0, NULL }, { 0x300005, 0x83, 2, pic18f6585_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F96J65 */ /* config addresses for PIC18F96J65: */ static struct gp_cfg_addr gp_cfg_pic18f96j65_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j65_017ff8 }, { 0x017ff9, 0xf4, 1, pic18f66j65_017ff9 }, { 0x017ffa, 0xc7, 4, pic18f66j65_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 4, pic18f86j55_017ffc }, { 0x017ffd, 0xf7, 3, pic18f86j65_017ffd }, }; /* * PIC18LF44J11 */ static struct gp_cfg_directive pic18lf44j11_003ff8[] = { /* for 0x003ff8 */ { "WDTEN", 0x01, 2, pic18f6410_wdt_opts }, { "STVREN", 0x20, 2, pic18f4450_vregen_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, }; /* config addresses for PIC18LF44J11: */ static struct gp_cfg_addr gp_cfg_pic18lf44j11_addrs[] = { { 0x003ff8, 0xe1, 3, pic18lf44j11_003ff8 }, { 0x003ff9, 0xf4, 1, pic18f84j11_003ff9 }, { 0x003ffa, 0xdf, 5, pic18f24j50_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0x02, 1, pic18lf44j50_003ffc }, { 0x003ffd, 0xf9, 2, pic18f24j50_003ffd }, { 0x003ffe, 0xff, 3, pic18f24j50_003ffe }, { 0x003fff, 0xf1, 1, pic18f24j50_003fff }, }; /* * PIC18F6628 */ /* config addresses for PIC18F6628: */ static struct gp_cfg_addr gp_cfg_pic18f6628_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 3, pic18f6722_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 6, pic18f8627_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 6, pic18f8627_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 6, pic18f8627_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F1330 */ static struct gp_cfg_option pic18f1330_borv_opts[] = { /* for BORV: */ { "0", 0x00 }, { "1", 0x04 }, { "2", 0x08 }, { "3", 0x0c }, }; static struct gp_cfg_directive pic18f1330_300002[] = { /* for 0x300002 */ { "PWRT", 0x01, 2, pic18f6410_pwrt_opts }, { "BOR", 0x06, 4, pic18f4685_boren_opts }, { "BORV", 0x0c, 4, pic18f1330_borv_opts }, }; static struct gp_cfg_option pic18f1330_lpol_opts[] = { /* for LPOL: */ { "LOW", 0x00 }, { "HIGH", 0x04 }, }; static struct gp_cfg_directive pic18f1330_300004[] = { /* for 0x300004 */ { "HPOL", 0x08, 2, pic18f2331_lpol_opts }, { "LPOL", 0x04, 2, pic18f1330_lpol_opts }, { "PWMPIN", 0x02, 2, pic18f2525_cp1_opts }, }; static struct gp_cfg_option pic18f1330_fltamx_opts[] = { /* for FLTAMX: */ { "RA7", 0x00 }, { "RA5", 0x01 }, }; static struct gp_cfg_directive pic18f1330_300005[] = { /* for 0x300005 */ { "FLTAMX", 0x01, 2, pic18f1330_fltamx_opts }, { "T1OSCMX", 0x08, 2, pic18f2331_lpol_opts }, { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, }; static struct gp_cfg_directive pic18f1330_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "BBSIZ", 0x30, 3, pic18f2321_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F1330: */ static struct gp_cfg_addr gp_cfg_pic18f1330_addrs[] = { { 0x300001, 0x07, 3, pic18f4221_300001 }, { 0x300002, 0x1f, 3, pic18f1330_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x0e, 3, pic18f1330_300004 }, { 0x300005, 0x81, 3, pic18f1330_300005 }, { 0x300006, 0x81, 4, pic18f1330_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6622 */ /* config addresses for PIC18F6622: */ static struct gp_cfg_addr gp_cfg_pic18f6622_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x81, 3, pic18f6410_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 4, pic18f8520_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 4, pic18f8520_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 4, pic18f8520_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6621 */ /* config addresses for PIC18F6621: */ static struct gp_cfg_addr gp_cfg_pic18f6621_addrs[] = { { 0x300001, 0x2f, 2, pic18f8621_300001 }, { 0x300002, 0x0f, 3, pic18f4220_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x83, 0, NULL }, { 0x300005, 0x83, 2, pic18f6525_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6620 */ /* config addresses for PIC18F6620: */ static struct gp_cfg_addr gp_cfg_pic18f6620_addrs[] = { { 0x300001, 0x27, 2, pic18f8520_300001 }, { 0x300002, 0x0f, 3, pic18c858_300002 }, { 0x300003, 0x0f, 2, pic18c858_300003 }, { 0x300004, 0x03, 0, NULL }, { 0x300005, 0x01, 1, pic18f242_300005 }, { 0x300006, 0x85, 3, pic18f4220_300006 }, { 0x300008, 0xff, 4, pic18f8520_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 4, pic18f8520_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 4, pic18f8520_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F67J10 */ static struct gp_cfg_directive pic18f67j10_01fffd[] = { /* for 0x01fffd */ { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F67J10: */ static struct gp_cfg_addr gp_cfg_pic18f67j10_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f87j11_01fff8 }, { 0x01fff9, 0xf4, 1, pic18f87j90_01fff9 }, { 0x01fffa, 0xc7, 4, pic18f67j60_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 0, NULL }, { 0x01fffd, 0xf3, 1, pic18f67j10_01fffd }, }; /* * PIC18F67J11 */ /* config addresses for PIC18F67J11: */ static struct gp_cfg_addr gp_cfg_pic18f67j11_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f87j11_01fff8 }, { 0x01fff9, 0xf7, 1, pic18f87j11_01fff9 }, { 0x01fffa, 0xc7, 3, pic18f67j50_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 0, NULL }, { 0x01fffd, 0xff, 2, pic18f67j50_01fffd }, }; /* * PIC18F2431 */ /* config addresses for PIC18F2431: */ static struct gp_cfg_addr gp_cfg_pic18f2431_addrs[] = { { 0x300001, 0xcf, 3, pic18f2331_300001 }, { 0x300002, 0x0f, 3, pic18f2331_300002 }, { 0x300003, 0x3f, 3, pic18f2331_300003 }, { 0x300004, 0x3c, 4, pic18f2331_300004 }, { 0x300005, 0x9d, 1, pic18f2331_300005 }, { 0x300006, 0x85, 3, pic18f2331_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 2, pic18f4220_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 2, pic18f4220_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F4321 */ static struct gp_cfg_directive pic18f4321_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "LVP", 0x04, 2, pic18f6410_lpt1osc_opts }, { "ICPORT", 0x08, 2, pic18f46k20_hfofst_opts }, { "BBSIZ", 0x30, 3, pic18f2321_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F4321: */ static struct gp_cfg_addr gp_cfg_pic18f4321_addrs[] = { { 0x300001, 0x07, 3, pic18f4221_300001 }, { 0x300002, 0x1f, 3, pic18f4221_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x83, 4, pic18f4221_300005 }, { 0x300006, 0x85, 6, pic18f4321_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f4221_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F86J15 */ static struct gp_cfg_directive pic18f86j15_017ffd[] = { /* for 0x017ffd */ { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F86J15: */ static struct gp_cfg_addr gp_cfg_pic18f86j15_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j16_017ff8 }, { 0x017ff9, 0xf4, 1, pic18f66j65_017ff9 }, { 0x017ffa, 0xc7, 4, pic18f66j65_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 4, pic18f86j55_017ffc }, { 0x017ffd, 0xf3, 2, pic18f86j15_017ffd }, }; /* * PIC18F1230 */ static struct gp_cfg_directive pic18f1230_300006[] = { /* for 0x300006 */ { "STVREN", 0x01, 2, pic18f6410_wdt_opts }, { "BBSIZ", 0x30, 2, pic18f4221_bbsiz_opts }, { "XINST", 0x40, 2, pic18f6410_fcmen_opts }, { "DEBUG", 0x80, 2, pic18f6410_debug_opts }, }; /* config addresses for PIC18F1230: */ static struct gp_cfg_addr gp_cfg_pic18f1230_addrs[] = { { 0x300001, 0x07, 3, pic18f4221_300001 }, { 0x300002, 0x1f, 3, pic18f1330_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0x0e, 3, pic18f1330_300004 }, { 0x300005, 0x81, 3, pic18f1330_300005 }, { 0x300006, 0x81, 4, pic18f1230_300006 }, { 0x300008, 0x03, 2, pic18f4450_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x03, 2, pic18f4450_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x03, 2, pic18f4450_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F2580 */ /* config addresses for PIC18F2580: */ static struct gp_cfg_addr gp_cfg_pic18f2580_addrs[] = { { 0x300001, 0x07, 3, pic18f4685_300001 }, { 0x300002, 0x1f, 3, pic18f4685_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 5, pic18f2480_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F86J16 */ /* config addresses for PIC18F86J16: */ static struct gp_cfg_addr gp_cfg_pic18f86j16_addrs[] = { { 0x017ff8, 0xe1, 4, pic18f66j16_017ff8 }, { 0x017ff9, 0xf7, 1, pic18f66j16_017ff9 }, { 0x017ffa, 0xc7, 3, pic18f86j55_017ffa }, { 0x017ffb, 0xff, 1, pic18f66j65_017ffb }, { 0x017ffc, 0xf8, 4, pic18f86j55_017ffc }, { 0x017ffd, 0xff, 4, pic18f86j55_017ffd }, }; /* * PIC18F86J11 */ /* config addresses for PIC18F86J11: */ static struct gp_cfg_addr gp_cfg_pic18f86j11_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j10_00fff8 }, { 0x00fff9, 0xf7, 1, pic18f66j11_00fff9 }, { 0x00fffa, 0xc7, 3, pic18f86j50_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 4, pic18f86j50_00fffc }, { 0x00fffd, 0xff, 4, pic18f86j50_00fffd }, }; /* * PIC18F86J10 */ static struct gp_cfg_directive pic18f86j10_00fffd[] = { /* for 0x00fffd */ { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F86J10: */ static struct gp_cfg_addr gp_cfg_pic18f86j10_addrs[] = { { 0x00fff8, 0xe1, 4, pic18f66j10_00fff8 }, { 0x00fff9, 0xf4, 1, pic18f66j90_00fff9 }, { 0x00fffa, 0xc7, 4, pic18f66j60_00fffa }, { 0x00fffb, 0xff, 1, pic18f66j90_00fffb }, { 0x00fffc, 0xf8, 4, pic18f86j50_00fffc }, { 0x00fffd, 0xf3, 2, pic18f86j10_00fffd }, }; /* * PIC18F2585 */ /* config addresses for PIC18F2585: */ static struct gp_cfg_addr gp_cfg_pic18f2585_addrs[] = { { 0x300001, 0x07, 3, pic18f4685_300001 }, { 0x300002, 0x1f, 3, pic18f4685_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x82, 3, pic18f4450_300005 }, { 0x300006, 0x85, 5, pic18f4685_300006 }, { 0x300008, 0x0f, 3, pic18f2525_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 3, pic18f2525_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 3, pic18f2525_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F6527 */ /* config addresses for PIC18F6527: */ static struct gp_cfg_addr gp_cfg_pic18f6527_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300005, 0x81, 3, pic18f6410_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 3, pic18f8527_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 3, pic18f8527_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 3, pic18f8527_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F24J11 */ /* config addresses for PIC18F24J11: */ static struct gp_cfg_addr gp_cfg_pic18f24j11_addrs[] = { { 0x003ff8, 0xe1, 3, pic18lf44j11_003ff8 }, { 0x003ff9, 0xf4, 1, pic18f84j11_003ff9 }, { 0x003ffa, 0xdf, 5, pic18f24j50_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0xff, 5, pic18f24j50_003ffc }, { 0x003ffd, 0xf9, 2, pic18f24j50_003ffd }, { 0x003ffe, 0xff, 3, pic18f24j50_003ffe }, { 0x003fff, 0xf1, 1, pic18f24j50_003fff }, }; /* * PIC18F24J10 */ static struct gp_cfg_directive pic18f24j10_003ffa[] = { /* for 0x003ffa */ { "FCMEN", 0x40, 2, pic18f6410_fcmen_opts }, { "IESO", 0x80, 2, pic18f6410_ieso_opts }, { "FOSC2", 0x04, 2, pic18f6410_lpt1osc_opts }, { "FOSC", 0x03, 4, pic18f83j11_fosc_opts }, }; /* config addresses for PIC18F24J10: */ static struct gp_cfg_addr gp_cfg_pic18f24j10_addrs[] = { { 0x003ff8, 0xe1, 4, pic18f84j11_003ff8 }, { 0x003ff9, 0xf4, 1, pic18f84j11_003ff9 }, { 0x003ffa, 0xc7, 4, pic18f24j10_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffd, 0xf1, 1, pic18f84j11_003ffd }, }; /* * PIC18F4331 */ static struct gp_cfg_option pic18f4331_exclkmx_opts[] = { /* for EXCLKMX: */ { "RD0", 0x00 }, { "RC3", 0x10 }, }; static struct gp_cfg_option pic18f4331_pwm4mx_opts[] = { /* for PWM4MX: */ { "RD5", 0x00 }, { "RB5", 0x08 }, }; static struct gp_cfg_option pic18f4331_sspmx_opts[] = { /* for SSPMX: */ { "RD1", 0x00 }, { "RC7", 0x04 }, }; static struct gp_cfg_option pic18f4331_fltamx_opts[] = { /* for FLTAMX: */ { "RD4", 0x00 }, { "RC1", 0x01 }, }; static struct gp_cfg_directive pic18f4331_300005[] = { /* for 0x300005 */ { "MCLRE", 0x80, 2, pic18f6410_ieso_opts }, { "EXCLKMX", 0x10, 2, pic18f4331_exclkmx_opts }, { "PWM4MX", 0x08, 2, pic18f4331_pwm4mx_opts }, { "SSPMX", 0x04, 2, pic18f4331_sspmx_opts }, { "FLTAMX", 0x01, 2, pic18f4331_fltamx_opts }, }; /* config addresses for PIC18F4331: */ static struct gp_cfg_addr gp_cfg_pic18f4331_addrs[] = { { 0x300001, 0xcf, 3, pic18f2331_300001 }, { 0x300002, 0x0f, 3, pic18f2331_300002 }, { 0x300003, 0x3f, 3, pic18f2331_300003 }, { 0x300004, 0x3c, 4, pic18f2331_300004 }, { 0x300005, 0x9d, 5, pic18f4331_300005 }, { 0x300006, 0x85, 3, pic18f2331_300006 }, { 0x300008, 0x0f, 2, pic18f4220_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F87J10 */ static struct gp_cfg_directive pic18f87j10_01fffd[] = { /* for 0x01fffd */ { "ECCPMX", 0x02, 2, pic18f85j50_eccpmx_opts }, { "CCP2MX", 0x01, 2, pic18f65j50_ccp2mx_opts }, }; /* config addresses for PIC18F87J10: */ static struct gp_cfg_addr gp_cfg_pic18f87j10_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f87j11_01fff8 }, { 0x01fff9, 0xf4, 1, pic18f87j90_01fff9 }, { 0x01fffa, 0xc7, 4, pic18f67j60_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffc, 0xf8, 4, pic18f87j50_01fffc }, { 0x01fffd, 0xf3, 2, pic18f87j10_01fffd }, }; /* * PIC18F87J60 */ /* config addresses for PIC18F87J60: */ static struct gp_cfg_addr gp_cfg_pic18f87j60_addrs[] = { { 0x01fff8, 0xe1, 4, pic18f67j60_01fff8 }, { 0x01fff9, 0xf4, 1, pic18f87j90_01fff9 }, { 0x01fffa, 0xc7, 4, pic18f67j60_01fffa }, { 0x01fffb, 0xff, 1, pic18f87j90_01fffb }, { 0x01fffd, 0xf7, 3, pic18f97j60_01fffd }, }; /* * PIC18F8622 */ /* config addresses for PIC18F8622: */ static struct gp_cfg_addr gp_cfg_pic18f8622_addrs[] = { { 0x300001, 0x07, 3, pic18f2525_300001 }, { 0x300002, 0x1f, 3, pic18f6410_300002 }, { 0x300003, 0x1f, 2, pic18f6410_300003 }, { 0x300004, 0xf3, 4, pic18f8627_300004 }, { 0x300005, 0x83, 4, pic18f8627_300005 }, { 0x300006, 0x85, 5, pic18f8627_300006 }, { 0x300008, 0xff, 4, pic18f8520_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0xff, 4, pic18f8520_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0xff, 4, pic18f8520_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * PIC18F64J11 */ /* config addresses for PIC18F64J11: */ static struct gp_cfg_addr gp_cfg_pic18f64j11_addrs[] = { { 0x003ff8, 0xe1, 4, pic18f84j11_003ff8 }, { 0x003ff9, 0xf4, 1, pic18f84j11_003ff9 }, { 0x003ffa, 0xc7, 4, pic18f84j11_003ffa }, { 0x003ffb, 0xff, 1, pic18f84j11_003ffb }, { 0x003ffc, 0xf8, 0, NULL }, { 0x003ffd, 0xf1, 1, pic18f84j11_003ffd }, }; /* * PIC18F4431 */ /* config addresses for PIC18F4431: */ static struct gp_cfg_addr gp_cfg_pic18f4431_addrs[] = { { 0x300001, 0xcf, 3, pic18f2331_300001 }, { 0x300002, 0x0f, 3, pic18f2331_300002 }, { 0x300003, 0x3f, 3, pic18f2331_300003 }, { 0x300004, 0x3c, 4, pic18f2331_300004 }, { 0x300005, 0x9d, 5, pic18f4331_300005 }, { 0x300006, 0x85, 3, pic18f2331_300006 }, { 0x300008, 0x0f, 4, pic18f2523_300008 }, { 0x300009, 0xc0, 2, pic18f2525_300009 }, { 0x30000a, 0x0f, 4, pic18f2523_30000a }, { 0x30000b, 0xe0, 3, pic18f2525_30000b }, { 0x30000c, 0x0f, 4, pic18f2523_30000c }, { 0x30000d, 0x40, 1, pic18f2525_30000d }, }; /* * Devices Table */ int gp_cfg_device_count = 209; struct gp_cfg_device gp_cfg_devices[] = { { "PIC18C242", 6, gp_cfg_pic18c452_addrs }, { "PIC18C252", 6, gp_cfg_pic18c452_addrs }, { "PIC18C442", 6, gp_cfg_pic18c452_addrs }, { "PIC18C452", 6, gp_cfg_pic18c452_addrs }, { "PIC18C601", 4, gp_cfg_pic18c801_addrs }, { "PIC18C658", 5, gp_cfg_pic18c858_addrs }, { "PIC18C801", 4, gp_cfg_pic18c801_addrs }, { "PIC18C858", 5, gp_cfg_pic18c858_addrs }, { "PIC18F1220", 11, gp_cfg_pic18f1220_addrs }, { "PIC18F1230", 12, gp_cfg_pic18f1230_addrs }, { "PIC18F1320", 11, gp_cfg_pic18f1220_addrs }, { "PIC18F1330", 12, gp_cfg_pic18f1330_addrs }, { "PIC18F13K22", 11, gp_cfg_pic18lf14k22_addrs }, { "PIC18F13K50", 12, gp_cfg_pic18f13k50_addrs }, { "PIC18F14K22", 11, gp_cfg_pic18lf14k22_addrs }, { "PIC18F14K50", 12, gp_cfg_pic18f13k50_addrs }, { "PIC18F2220", 11, gp_cfg_pic18f4220_addrs }, { "PIC18F2221", 11, gp_cfg_pic18f2221_addrs }, { "PIC18F2320", 11, gp_cfg_pic18f2320_addrs }, { "PIC18F2321", 11, gp_cfg_pic18f2321_addrs }, { "PIC18F2331", 12, gp_cfg_pic18f2331_addrs }, { "PIC18F23K20", 11, gp_cfg_pic18f23k20_addrs }, { "PIC18F2410", 11, gp_cfg_pic18f2410_addrs }, { "PIC18F242", 11, gp_cfg_pic18f242_addrs }, { "PIC18F2420", 11, gp_cfg_pic18f4420_addrs }, { "PIC18F2423", 11, gp_cfg_pic18f2423_addrs }, { "PIC18F2431", 12, gp_cfg_pic18f2431_addrs }, { "PIC18F2439", 10, gp_cfg_pic18f2439_addrs }, { "PIC18F2450", 12, gp_cfg_pic18f4450_addrs }, { "PIC18F2455", 12, gp_cfg_pic18f2455_addrs }, { "PIC18F2458", 12, gp_cfg_pic18f2455_addrs }, { "PIC18F248", 10, gp_cfg_pic18f248_addrs }, { "PIC18F2480", 11, gp_cfg_pic18f2480_addrs }, { "PIC18F24J10", 5, gp_cfg_pic18f24j10_addrs }, { "PIC18F24J11", 8, gp_cfg_pic18f24j11_addrs }, { "PIC18F24J50", 8, gp_cfg_pic18f24j50_addrs }, { "PIC18F24K20", 11, gp_cfg_pic18f23k20_addrs }, { "PIC18F2510", 11, gp_cfg_pic18f4610_addrs }, { "PIC18F2515", 11, gp_cfg_pic18f4515_addrs }, { "PIC18F252", 11, gp_cfg_pic18f452_addrs }, { "PIC18F2520", 11, gp_cfg_pic18f2520_addrs }, { "PIC18F2523", 11, gp_cfg_pic18f2523_addrs }, { "PIC18F2525", 11, gp_cfg_pic18f2525_addrs }, { "PIC18F2539", 10, gp_cfg_pic18f2539_addrs }, { "PIC18F2550", 12, gp_cfg_pic18f2550_addrs }, { "PIC18F2553", 12, gp_cfg_pic18f2550_addrs }, { "PIC18F258", 10, gp_cfg_pic18f458_addrs }, { "PIC18F2580", 11, gp_cfg_pic18f2580_addrs }, { "PIC18F2585", 11, gp_cfg_pic18f2585_addrs }, { "PIC18F25J10", 5, gp_cfg_pic18f25j10_addrs }, { "PIC18F25J11", 8, gp_cfg_pic18f25j11_addrs }, { "PIC18F25J50", 8, gp_cfg_pic18f45j50_addrs }, { "PIC18F25K20", 11, gp_cfg_pic18f46k20_addrs }, { "PIC18F2610", 11, gp_cfg_pic18f4610_addrs }, { "PIC18F2620", 11, gp_cfg_pic18f2520_addrs }, { "PIC18F2680", 11, gp_cfg_pic18f2680_addrs }, { "PIC18F2682", 11, gp_cfg_pic18f4682_addrs }, { "PIC18F2685", 11, gp_cfg_pic18f4685_addrs }, { "PIC18F26J11", 8, gp_cfg_pic18f46j11_addrs }, { "PIC18F26J50", 8, gp_cfg_pic18f26j50_addrs }, { "PIC18F26K20", 11, gp_cfg_pic18f46k20_addrs }, { "PIC18F4220", 11, gp_cfg_pic18f4220_addrs }, { "PIC18F4221", 11, gp_cfg_pic18f4221_addrs }, { "PIC18F4320", 11, gp_cfg_pic18f2320_addrs }, { "PIC18F4321", 11, gp_cfg_pic18f4321_addrs }, { "PIC18F4331", 12, gp_cfg_pic18f4331_addrs }, { "PIC18F43K20", 11, gp_cfg_pic18f23k20_addrs }, { "PIC18F4410", 11, gp_cfg_pic18f2410_addrs }, { "PIC18F442", 11, gp_cfg_pic18f242_addrs }, { "PIC18F4420", 11, gp_cfg_pic18f4420_addrs }, { "PIC18F4423", 11, gp_cfg_pic18f2423_addrs }, { "PIC18F4431", 12, gp_cfg_pic18f4431_addrs }, { "PIC18F4439", 10, gp_cfg_pic18f2439_addrs }, { "PIC18F4450", 12, gp_cfg_pic18f4450_addrs }, { "PIC18F4455", 12, gp_cfg_pic18f4458_addrs }, { "PIC18F4458", 12, gp_cfg_pic18f4458_addrs }, { "PIC18F448", 10, gp_cfg_pic18f248_addrs }, { "PIC18F4480", 11, gp_cfg_pic18f2480_addrs }, { "PIC18F44J10", 5, gp_cfg_pic18f24j10_addrs }, { "PIC18F44J11", 8, gp_cfg_pic18f24j11_addrs }, { "PIC18F44J50", 8, gp_cfg_pic18f24j50_addrs }, { "PIC18F44K20", 11, gp_cfg_pic18f23k20_addrs }, { "PIC18F4510", 11, gp_cfg_pic18f4610_addrs }, { "PIC18F4515", 11, gp_cfg_pic18f4515_addrs }, { "PIC18F452", 11, gp_cfg_pic18f452_addrs }, { "PIC18F4520", 11, gp_cfg_pic18f2520_addrs }, { "PIC18F4523", 11, gp_cfg_pic18f2523_addrs }, { "PIC18F4525", 11, gp_cfg_pic18f2525_addrs }, { "PIC18F4539", 10, gp_cfg_pic18f2539_addrs }, { "PIC18F4550", 12, gp_cfg_pic18f4553_addrs }, { "PIC18F4553", 12, gp_cfg_pic18f4553_addrs }, { "PIC18F458", 10, gp_cfg_pic18f458_addrs }, { "PIC18F4580", 11, gp_cfg_pic18f2580_addrs }, { "PIC18F4585", 11, gp_cfg_pic18f2585_addrs }, { "PIC18F45J10", 5, gp_cfg_pic18f25j10_addrs }, { "PIC18F45J11", 8, gp_cfg_pic18f25j11_addrs }, { "PIC18F45J50", 8, gp_cfg_pic18f45j50_addrs }, { "PIC18F45K20", 11, gp_cfg_pic18f46k20_addrs }, { "PIC18F4610", 11, gp_cfg_pic18f4610_addrs }, { "PIC18F4620", 11, gp_cfg_pic18f2520_addrs }, { "PIC18F4680", 11, gp_cfg_pic18f2680_addrs }, { "PIC18F4682", 11, gp_cfg_pic18f4682_addrs }, { "PIC18F4685", 11, gp_cfg_pic18f4685_addrs }, { "PIC18F46J11", 8, gp_cfg_pic18f46j11_addrs }, { "PIC18F46J50", 8, gp_cfg_pic18f26j50_addrs }, { "PIC18F46K20", 11, gp_cfg_pic18f46k20_addrs }, { "PIC18F6310", 8, gp_cfg_pic18f6410_addrs }, { "PIC18F6390", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F6393", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F63J11", 6, gp_cfg_pic18f63j11_addrs }, { "PIC18F63J90", 6, gp_cfg_pic18f83j90_addrs }, { "PIC18F6410", 8, gp_cfg_pic18f6410_addrs }, { "PIC18F6490", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F6493", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F64J11", 6, gp_cfg_pic18f64j11_addrs }, { "PIC18F64J90", 6, gp_cfg_pic18f64j90_addrs }, { "PIC18F6520", 12, gp_cfg_pic18f6520_addrs }, { "PIC18F6525", 12, gp_cfg_pic18f6525_addrs }, { "PIC18F6527", 11, gp_cfg_pic18f6527_addrs }, { "PIC18F6585", 12, gp_cfg_pic18f6585_addrs }, { "PIC18F65J10", 6, gp_cfg_pic18f65j10_addrs }, { "PIC18F65J11", 6, gp_cfg_pic18f65j11_addrs }, { "PIC18F65J15", 6, gp_cfg_pic18f65j15_addrs }, { "PIC18F65J50", 6, gp_cfg_pic18f65j50_addrs }, { "PIC18F65J90", 6, gp_cfg_pic18f85j90_addrs }, { "PIC18F6620", 12, gp_cfg_pic18f6620_addrs }, { "PIC18F6621", 12, gp_cfg_pic18f6621_addrs }, { "PIC18F6622", 11, gp_cfg_pic18f6622_addrs }, { "PIC18F6627", 11, gp_cfg_pic18f6628_addrs }, { "PIC18F6628", 11, gp_cfg_pic18f6628_addrs }, { "PIC18F6680", 12, gp_cfg_pic18f6680_addrs }, { "PIC18F66J10", 6, gp_cfg_pic18f66j10_addrs }, { "PIC18F66J11", 6, gp_cfg_pic18f66j11_addrs }, { "PIC18F66J15", 6, gp_cfg_pic18f66j15_addrs }, { "PIC18F66J16", 6, gp_cfg_pic18f66j16_addrs }, { "PIC18F66J50", 6, gp_cfg_pic18f66j50_addrs }, { "PIC18F66J55", 6, gp_cfg_pic18f66j55_addrs }, { "PIC18F66J60", 5, gp_cfg_pic18f66j60_addrs }, { "PIC18F66J65", 5, gp_cfg_pic18f66j65_addrs }, { "PIC18F66J90", 6, gp_cfg_pic18f66j90_addrs }, { "PIC18F6720", 12, gp_cfg_pic18f6720_addrs }, { "PIC18F6722", 11, gp_cfg_pic18f6722_addrs }, { "PIC18F6723", 11, gp_cfg_pic18f6722_addrs }, { "PIC18F67J10", 6, gp_cfg_pic18f67j10_addrs }, { "PIC18F67J11", 6, gp_cfg_pic18f67j11_addrs }, { "PIC18F67J50", 6, gp_cfg_pic18f67j50_addrs }, { "PIC18F67J60", 5, gp_cfg_pic18f67j60_addrs }, { "PIC18F67J90", 6, gp_cfg_pic18f87j90_addrs }, { "PIC18F8310", 8, gp_cfg_pic18f8410_addrs }, { "PIC18F8390", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F8393", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F83J11", 6, gp_cfg_pic18f83j11_addrs }, { "PIC18F83J90", 6, gp_cfg_pic18f83j90_addrs }, { "PIC18F8410", 8, gp_cfg_pic18f8410_addrs }, { "PIC18F8490", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F8493", 6, gp_cfg_pic18f6490_addrs }, { "PIC18F84J11", 6, gp_cfg_pic18f84j11_addrs }, { "PIC18F84J90", 6, gp_cfg_pic18f64j90_addrs }, { "PIC18F8520", 12, gp_cfg_pic18f8520_addrs }, { "PIC18F8525", 12, gp_cfg_pic18f8525_addrs }, { "PIC18F8527", 12, gp_cfg_pic18f8527_addrs }, { "PIC18F8585", 12, gp_cfg_pic18f8585_addrs }, { "PIC18F85J10", 6, gp_cfg_pic18f85j10_addrs }, { "PIC18F85J11", 6, gp_cfg_pic18f85j11_addrs }, { "PIC18F85J15", 6, gp_cfg_pic18f85j15_addrs }, { "PIC18F85J50", 6, gp_cfg_pic18f85j50_addrs }, { "PIC18F85J90", 6, gp_cfg_pic18f85j90_addrs }, { "PIC18F8620", 12, gp_cfg_pic18f8620_addrs }, { "PIC18F8621", 12, gp_cfg_pic18f8621_addrs }, { "PIC18F8622", 12, gp_cfg_pic18f8622_addrs }, { "PIC18F8627", 12, gp_cfg_pic18f8627_addrs }, { "PIC18F8628", 12, gp_cfg_pic18f8627_addrs }, { "PIC18F8680", 12, gp_cfg_pic18f8680_addrs }, { "PIC18F86J10", 6, gp_cfg_pic18f86j10_addrs }, { "PIC18F86J11", 6, gp_cfg_pic18f86j11_addrs }, { "PIC18F86J15", 6, gp_cfg_pic18f86j15_addrs }, { "PIC18F86J16", 6, gp_cfg_pic18f86j16_addrs }, { "PIC18F86J50", 6, gp_cfg_pic18f86j50_addrs }, { "PIC18F86J55", 6, gp_cfg_pic18f86j55_addrs }, { "PIC18F86J60", 5, gp_cfg_pic18f86j60_addrs }, { "PIC18F86J65", 5, gp_cfg_pic18f86j65_addrs }, { "PIC18F86J90", 6, gp_cfg_pic18f66j90_addrs }, { "PIC18F8720", 12, gp_cfg_pic18f8720_addrs }, { "PIC18F8722", 12, gp_cfg_pic18f8722_addrs }, { "PIC18F8723", 12, gp_cfg_pic18f8722_addrs }, { "PIC18F87J10", 6, gp_cfg_pic18f87j10_addrs }, { "PIC18F87J11", 6, gp_cfg_pic18f87j11_addrs }, { "PIC18F87J50", 6, gp_cfg_pic18f87j50_addrs }, { "PIC18F87J60", 5, gp_cfg_pic18f87j60_addrs }, { "PIC18F87J90", 6, gp_cfg_pic18f87j90_addrs }, { "PIC18F96J60", 6, gp_cfg_pic18f96j60_addrs }, { "PIC18F96J65", 6, gp_cfg_pic18f96j65_addrs }, { "PIC18F97J60", 6, gp_cfg_pic18f97j60_addrs }, { "PIC18LF13K22", 11, gp_cfg_pic18lf14k22_addrs }, { "PIC18LF13K50", 12, gp_cfg_pic18f13k50_addrs }, { "PIC18LF14K22", 11, gp_cfg_pic18lf14k22_addrs }, { "PIC18LF14K50", 12, gp_cfg_pic18f13k50_addrs }, { "PIC18LF24J11", 8, gp_cfg_pic18lf44j11_addrs }, { "PIC18LF24J50", 8, gp_cfg_pic18lf44j50_addrs }, { "PIC18LF25J11", 8, gp_cfg_pic18lf45j11_addrs }, { "PIC18LF25J50", 8, gp_cfg_pic18lf45j50_addrs }, { "PIC18LF26J11", 8, gp_cfg_pic18lf26j11_addrs }, { "PIC18LF26J50", 8, gp_cfg_pic18lf46j50_addrs }, { "PIC18LF44J11", 8, gp_cfg_pic18lf44j11_addrs }, { "PIC18LF44J50", 8, gp_cfg_pic18lf44j50_addrs }, { "PIC18LF45J11", 8, gp_cfg_pic18lf45j11_addrs }, { "PIC18LF45J50", 8, gp_cfg_pic18lf45j50_addrs }, { "PIC18LF46J11", 8, gp_cfg_pic18lf26j11_addrs }, { "PIC18LF46J50", 8, gp_cfg_pic18lf46j50_addrs }, }; gputils-0.13.7/libgputils/gpwritehex.h0000644000175000017500000000225311156313233014727 00000000000000/* ".HEX" file output for gputils Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman, Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPWRITEHEX_H__ #define __GPWRITEHEX_H__ enum formats { inhx8m, inhx8s, inhx16, inhx32 }; int writehex (char *basefilename, MemBlock *m, enum formats hex_format, int numerrors, int byte_words, int dos_newlines); int check_writehex(MemBlock *m, enum formats hex_format); #endif gputils-0.13.7/libgputils/Makefile.am0000644000175000017500000000153611156313233014427 00000000000000## Process this file with automake to produce Makefile.in AM_CPPFLAGS =\ -I${top_srcdir}/include \ -DHEADER_PATH=\"@GPUTILS_HEADER_PATH@\" \ -DLKR_PATH=\"@GPUTILS_LKR_PATH@\" \ -DLIB_PATH=\"@GPUTILS_LIB_PATH@\" \ -DPUB_PATH=\"@GPUTILS_PUB_PATH@\" noinst_LIBRARIES = libgputils.a libgputils_a_SOURCES =\ gparchive.c \ gpcod.c \ gpcoffgen.c \ gpcofflink.c \ gpcoffopt.c \ gpdis.c \ gpmemory.c \ gpmessage.c \ gpopcode.c \ gpprocessor.c \ gpreadhex.c \ gpreadobj.c \ gpsymbol.c \ gpsystem.c \ gpwritehex.c \ gpwriteobj.c \ gparchive.h \ gpcfg.c \ gpcfg.h \ gpcfg-table.c \ gpcod.h \ gpcoff.h \ gpcoffgen.h \ gpcofflink.h \ gpcoffopt.h \ gpdis.h \ gpmemory.h \ gpmessage.h \ gpopcode.h \ gpprocessor.h \ gpreadhex.h \ gpreadobj.h \ gpsymbol.h \ gpsystem.h \ gptypes.h \ gpwritehex.h \ gpwriteobj.h \ libgputils.h gputils-0.13.7/libgputils/gpreadhex.c0000644000175000017500000001203211156521302014475 00000000000000/* Read ".HEX" files and store it in memory Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" #define LINESIZ 520 char linebuf[LINESIZ]; char *linept; int checksum; FILE *infile; /* Converts a single ASCII character into a number */ unsigned int a2n(char character) { unsigned int number; if(character < 0x3A) { number = character-0x30; } else { /* convert lower case to upper */ character &= 0xDF; number = character-0x37; } return number; } unsigned int readbyte() { unsigned int number; linept++; number = a2n(*linept) << 4; linept++; number |= a2n(*linept); checksum += number; return number; } unsigned int readword() { unsigned int number; number = readbyte(); number = (readbyte() << 8) | number; return number; } unsigned int swapword(unsigned int input) { unsigned int number; number = ((input & 0xFF) << 8) | ((input & 0xFF00) >> 8); return number; } struct hex_data * readhex(char *filename, MemBlock *m) { struct hex_data *info = malloc(sizeof(*info)); int length, address, type, data; int i; int page = 0; int length_step; info->hex_format = inhx8m; info->size = 0; info->error = 0; /* Open the input file */ if ( (infile = fopen(filename,"rt")) == NULL ){ perror(filename); exit(1); } /* go to the beginning of the file */ fseek(infile, 0L, 0); /* set the line pointer to the beginning of the line buffer */ linept = linebuf; /* read a line of data from the file, if NULL stop */ while(fgets(linept, LINESIZ, infile)) { /* set the line pointer to the beginning of the line buffer */ linept = linebuf; checksum = 0; /* fetch the number of bytes */ length = readbyte(); if (length == 0) { fclose(infile); return info; } if (info->hex_format != inhx16) { length_step = 2; } else { length_step = 1; } /* fetch the address */ address = readword(); address = swapword(address); if (info->hex_format == inhx16) { address = address * 2; } /* read the type of record */ type = readbyte(); if (type == 4) { if (info->hex_format == inhx16) { printf("\nhex format error\n"); fclose(infile); info->error = 1; return info; } /* inhx32 segment line*/ page = readword(); info->hex_format = inhx32; } else { if ((length_step == 2) && ((address % 2) != 0)) { /* we're starting in the middle of a word */ /* merge this byte with word already in memory */ data = i_memory_get(m, ((page << 16) | (address >> 1))) & 0xFF; data |= (readbyte() << 8); i_memory_put(m, ((page << 16) | (address >> 1)), data | MEM_USED_MASK); ++address; --length; } /* read the data (skipping last byte if at odd address) */ for (i = 0; i < (length & ~0x1); i += length_step) { data = readword(); if (info->hex_format == inhx16) { data = swapword(data); } i_memory_put(m, ((page << 16) | (address + i)>>1), data | MEM_USED_MASK); } if ((length_step == 2) && ((length % 2) != 0)) { /* we're ending in the middle of a word */ /* merge this byte with word already in memory */ unsigned int word_address = (page << 16) | ((address+length) >> 1); data = i_memory_get(m, word_address) & 0xFF00; data |= readbyte(); i_memory_put(m, word_address, data | MEM_USED_MASK); } info->size += (length * length_step); } /* read the checksum, data is thrown away*/ data = readbyte(); if ((checksum & 0xFF) != 0) { if (info->hex_format == inhx8m) { /* first attempt at inhx8m failed, try inhx16 */ fseek(infile, 0L, 0); info->hex_format = inhx16; info->size = 0; /* data in i_memory is trash */ i_memory_free(m); m = i_memory_create(); } else { printf("\nChecksum Error\n"); fclose(infile); info->error = 1; return info; } } /* set the line pointer to the beginning of the line buffer */ linept = linebuf; } fclose(infile); return info; } gputils-0.13.7/libgputils/gpsymbol.c0000644000175000017500000000771511156313233014400 00000000000000/* Symbol table support Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 James Bowman This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* Base the hash func on the 1st, 2nd, 3rd and last characters of the string, and its length. */ static int hashfunc(struct symbol_table *t, char *s) { union { char b[4]; unsigned long ul; } change; int len; change.ul = 0; len = strlen(s); change.b[0] = s[0]; if (len > 1) { change.b[1] = s[1]; change.b[3] = s[len - 1]; if (len > 2) change.b[2] = s[2]; } if (t->case_insensitive) { change.ul &= 0x1f1f1f1f; } change.ul += (len << 3); return (change.ul % HASH_SIZE); } struct symbol_table *push_symbol_table(struct symbol_table * table, gp_boolean case_insensitive) { struct symbol_table *new = calloc(sizeof(*new), 1); new->case_insensitive = case_insensitive; if (case_insensitive) new->compare = strcasecmp; else new->compare = strcmp; new->prev = table; return new; } struct symbol_table *pop_symbol_table(struct symbol_table *table) { struct symbol_table *prev; prev = table->prev; return prev; } struct symbol *add_symbol(struct symbol_table *table, char *name) { struct symbol *r; int index; assert(name != NULL); assert(table != NULL); index = hashfunc(table, name); r = table->hash_table[index]; while (r && ((*table->compare)(name, r->name) != 0)) r = r->next; if (!r) { /* No match */ r = malloc(sizeof(*r)); r->name = strdup(name); r->next = table->hash_table[index]; r->annotation = NULL; table->hash_table[index] = r; table->count++; } return r; } /* FIXME: remove_symbol does not search all of the symbol tables in the stack. Maybe this is ok, but it seems wrong. */ int remove_symbol(struct symbol_table *table, char *name) { struct symbol *r = NULL; struct symbol *last = NULL; int index; int found_symbol = 0; assert(name != NULL); assert(table != NULL); index = hashfunc(table, name); /* Search for the symbol */ if (table != NULL) { r = table->hash_table[index]; while (r && ((*table->compare)(name, r->name) != 0)) { last = r; r = r->next; } } if (r != NULL) { /* remove the symbol */ if (last) { last->next = r->next; } else { /* r was first in the list */ table->hash_table[index] = r->next; } table->count--; found_symbol = 1; free(r); } return found_symbol; } struct symbol *get_symbol(struct symbol_table *table, char *name) { struct symbol *r = NULL; assert(name != NULL); if (table != NULL) { int index = hashfunc(table, name); r = table->hash_table[index]; while (r && ((*table->compare)(name, r->name) != 0)) r = r->next; /* If r is still NULL, we didn't match. Try the prev table on the stack */ if (r == NULL) r = get_symbol(table->prev, name); } return r; } void annotate_symbol(struct symbol *s, void *a) { s->annotation = a; } char *get_symbol_name(struct symbol *s) { return s->name; } void *get_symbol_annotation(struct symbol *s) { return s->annotation; } int symbol_compare(const void *p0, const void *p1) { struct symbol *s0 = *(struct symbol **)p0, *s1 = *(struct symbol **)p1; return strcmp(s0->name, s1->name); } gputils-0.13.7/libgputils/gpcfg.c0000644000175000017500000000600511156521302013617 00000000000000/* gpcfg.c - header file for pic object files Copyright (C) 2006 Michael Ballbach This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "gpcfg.h" static int cb_find_pic(const void *p1, const void *p2) { const struct gp_cfg_device *d1 = p1; const struct gp_cfg_device *d2 = p2; return strcasecmp(d1->device, d2->device); } /* * Locate a PIC configuration device structure by name */ const struct gp_cfg_device *gp_cfg_find_pic(const char *pic) { struct gp_cfg_device fake_dev = { NULL, 0, NULL }; fake_dev.device = pic; return bsearch(&fake_dev, gp_cfg_devices, gp_cfg_device_count, sizeof(gp_cfg_devices[0]), cb_find_pic); } /* * Locate a PIC by name, pass a list of names to use, try each in order. */ const struct gp_cfg_device *gp_cfg_find_pic_multi(int count, char **pics) { int t; for(t=0; taddr_count; t++) { const struct gp_cfg_addr *addr = device->config_addrs + t; for(u=0; udirective_count; u++) { const struct gp_cfg_directive *directive = addr->directives + u; if(strcasecmp(dname, directive->name) == 0) { if(config_addr) *(config_addr) = addr->addr; if(def_value) *(def_value) = addr->defval; return directive; } } } return NULL; } /* * Locate an option for a directive. Return it or NULL. */ const struct gp_cfg_option *gp_cfg_find_option(const struct gp_cfg_directive *directive, const char *option) { size_t t; for(t=0; toption_count; t++) { const struct gp_cfg_option *p = directive->options + t; if(strcasecmp(p->name, option) == 0) return p; } return NULL; } /* * Return 0xff or the default for the address and device passed. */ unsigned char gp_cfg_get_default(const struct gp_cfg_device *device, int address) { size_t t; for(t=0; taddr_count; t++) { const struct gp_cfg_addr *addr = device->config_addrs + t; if(addr->addr == address) return addr->defval; } return 0xff; } gputils-0.13.7/libgputils/gpsystem.h0000644000175000017500000000335611156313233014421 00000000000000/* General system functions Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPSYSTEM_H__ #define __GPSYSTEM_H__ extern char *gp_header_path; extern char *gp_lkr_path; extern char *gp_lib_path; void gp_init(void); void gp_fputl16(short data, FILE *fp); void gp_fputl32(long data, FILE *fp); void gp_fputvar(char *data, int number, FILE *fp); short gp_getl16(char *addr); unsigned short gp_getu16(char *addr); long gp_getl32(char *addr); void gp_putl16(char *addr, short data); void gp_putl32(char *addr, long data); long gp_getb32(char *addr); void gp_putb32(char *addr, long data); void gp_date_string(char *buffer, size_t sizeof_buffer); char *gp_lower_case(char *name); char *gp_upper_case(char *name); typedef struct gp_list_struct gp_linked_list; struct gp_list_struct { void *annotation; struct gp_list_struct *prev; struct gp_list_struct *next; }; gp_linked_list *gp_list_make(void); void gp_list_annotate(gp_linked_list *link, void *a); void *gp_list_get(gp_linked_list *link); char *gp_absolute_path(char *filename); #endif gputils-0.13.7/libgputils/gpcoff.h0000644000175000017500000004671111156521302014012 00000000000000/* gpcoff.h - header file for pic object files Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef __GPCOFF_H__ #define __GPCOFF_H__ /* These definitions are for the COFF as stored in a file. */ /* define the typical values, if they aren't found warn the user */ #define MICROCHIP_MAGIC_v1 0x1234 #define MICROCHIP_MAGIC_v2 0x1240 #define OPTMAGIC_v1 0x5678 #define OPTMAGIC_v2 0x5678 /* coff file header format */ struct filehdr { unsigned short f_magic; /* magic number */ unsigned short f_nscns; /* number of sections */ unsigned long f_timdat; /* time and date stamp */ unsigned long f_symptr; /* file ptr to symtab */ unsigned long f_nsyms; /* # symtab entries */ unsigned short f_opthdr; /* sizeof(opt hdr) */ unsigned short f_flags; /* flags */ }; /* define the size in the file, don't use sizeof() !! */ #define FILE_HDR_SIZ_v1 20 #define FILE_HDR_SIZ_v2 20 /* relocation info has been stripped */ #define F_RELFLG 0x01 /* file is executable - has no unresolved external symbols */ #define F_EXEC 0x02 /* line numbers have been stripped */ #define F_LNNO 0x04 /* local symbols have been stripped */ #define L_SYMS 0x80 /* processor independent file for a core */ #define F_GENERIC 0x8000 /* optional header format */ struct opthdr { unsigned short opt_magic; unsigned long vstamp; /* version of the compiler assembler */ unsigned long proc_type; unsigned long rom_width_bits; unsigned long ram_width_bits; }; #define OPT_HDR_SIZ_v1 16 #define OPT_HDR_SIZ_v2 18 /* section header format */ struct scnhdr { union { char name[8]; /* section name if less then 8 characters */ struct { unsigned long s_zeros; /* first four characters are 0 */ unsigned long s_offset; /* pointer to the string table */ } ptr; } s_name; unsigned long s_paddr; /* physical address */ unsigned long s_vaddr; /* virtual address */ unsigned long s_size; /* section size */ unsigned long s_scnptr; /* file ptr to raw data */ unsigned long s_relptr; /* file ptr to relocation */ unsigned long s_lnnoptr; /* file ptr to line numbers */ unsigned short s_nreloc; /* # reloc entries */ unsigned short s_nlnno; /* # line number entries */ unsigned long s_flags; /* flags */ }; #define SEC_HDR_SIZ_v1 40 #define SEC_HDR_SIZ_v2 40 /* Section contains executable code */ #define STYP_TEXT 0x0020 /* Section contains initialized data */ #define STYP_DATA 0x0040 /* Section contains uninitialized data */ #define STYP_BSS 0x0080 /* Section contains initialized data for ROM */ #define STYP_DATA_ROM 0x0100 /* Section is absolute */ #define STYP_ABS 0x1000 /* Section is shared across banks */ #define STYP_SHARED 0x2000 /* Section is overlaid with other sections of the same name from different objects modules */ #define STYP_OVERLAY 0x4000 /* Section is available using access bit */ #define STYP_ACCESS 0x8000 /* Section contains the activation record for a function */ #define STYP_ACTREC 0x10000 /* Section has been relocated. This is a temporary flag used by the linker */ #define STYP_RELOC 0x20000 /* Section is byte packed on 16bit devices */ #define STYP_BPACK 0x40000 /* relocation entry */ struct reloc { unsigned long r_vaddr; /* entry relative virtual address */ unsigned long r_symndx; /* index into symbol table */ short r_offset; /* offset to be added to address of symbol 'r_symndx' */ unsigned short r_type; /* relocation type */ }; #define RELOC_SIZ 12 /* relocation for the CALL instruction (first word only on 18cxx) */ #define RELOCT_CALL 1 /* relocation for the GOTO instruction (first word only on 18cxx) */ #define RELOCT_GOTO 2 /* relocation for the second 8 bits of an address */ #define RELOCT_HIGH 3 /* relocation for the low order 8 bits of an address */ #define RELOCT_LOW 4 /* relocation for the 5 bits of address for the P operand of a 17cxx MOVFP or MOVPF instruction */ #define RELOCT_P 5 /* relocation to generate the appropriate instruction to bank switch for a symbol */ #define RELOCT_BANKSEL 6 /* relocation to generate the appropriate instruction to page switch for a symbol */ #define RELOCT_PAGESEL 7 /* FIXME */ #define RELOCT_ALL 8 /* FIXME */ #define RELOCT_IBANKSEL 9 /* relocation for the 8 bits of address for the F operand of a 17cxx MOVFP or MOVPF instruction */ #define RELOCT_F 10 /* FIXME */ #define RELOCT_TRIS 11 /* relocation for the MOVLR bank 17cxx banking instruction */ #define RELOCT_MOVLR 12 /* relocation for the MOVLB 17cxx and 18cxx banking instruction */ #define RELOCT_MOVLB 13 /* relocation for the second word of an 18cxx goto instruction */ #define RELOCT_GOTO2 14 /* relocation for the second word of an 18cxx call instruction */ #define RELOCT_CALL2 RELOCT_GOTO2 /* relocation for the source register of the 18cxx MOVFF instruction */ #define RELOCT_FF1 15 /* relocation for the destination register of the 18cxx MOVFF instruction */ #define RELOCT_FF2 16 /* relocation for the first word of the 18cxx LFSR instruction */ #define RELOCT_LFSR1 17 /* relocation for the second word of the 18cxx LFSR instruction */ #define RELOCT_LFSR2 18 /* relocation for the 18cxx BRA instruction */ #define RELOCT_BRA 19 /* relocation for the 18cxx RCALL instruction */ #define RELOCT_RCALL RELOCT_BRA /* relocation for the 18cxx relative conditional branch instructions */ #define RELOCT_CONDBRA 20 /* relocation for the highest order 8 bits of a 24-bit address */ #define RELOCT_UPPER 21 /* relocation for the 18cxx access bit */ #define RELOCT_ACCESS 22 /* relocation for selecting the correct page using WREG as scratch */ #define RELOCT_PAGESEL_WREG 23 /* relocation for selecting the correct page using bit set/clear instructions */ #define RELOCT_PAGESEL_BITS 24 /* relocation for the size of a section */ #define RELOCT_SCNSZ_LOW 25 #define RELOCT_SCNSZ_HIGH 26 #define RELOCT_SCNSZ_UPPER 27 /* relocation for the address of the end of a section */ #define RELOCT_SCNEND_LOW 28 #define RELOCT_SCNEND_HIGH 29 #define RELOCT_SCNEND_UPPER 30 /* relocation for the address of the end of a section on LFSR */ #define RELOCT_SCNEND_LFSR1 31 #define RELOCT_SCNEND_LFSR2 32 #define RELOCT_TRIS_4BIT 33 /* linenumber entry */ struct lineno { unsigned long l_srcndx; /* symbol table index of associated source file */ unsigned short l_lnno; /* line number */ unsigned long l_paddr; /* address of code for this lineno */ unsigned short l_flags; /* bit flags for the line number */ unsigned long l_fcnndx; /* symbol table index of associated function, if there is one */ }; #define LINENO_SIZ 16 /* Set if l_fcnndx is valid */ #define LINENO_HASFCN 0x01 /* symbol table entry */ struct syment { union { char name[8]; /* symbol name if less then 8 characters */ struct { unsigned long s_zeros; /* first four characters are 0 */ unsigned long s_offset; /* pointer to the string table */ } ptr; } sym_name; unsigned long value; /* symbol value */ short sec_num; /* section number */ unsigned long type; /* type */ char st_class; /* storage class */ unsigned char num_auxsym; /* number of auxiliary symbols */ }; #define SYMBOL_SIZE_v1 18 #define SYMBOL_SIZE_v2 20 /* Symbol section numbers */ #define N_DEBUG -2 #define N_ABS -1 #define N_UNDEF 0 #define N_SCNUM 1 /* Symbol types Type in an unsigned short (16 bits). The lowest nibble contains the basic type. The next higher three bits contain the derived symbol type. The rest of the bits are unused. */ /* Basic symbol types */ #define T_NULL 0 /* null */ #define T_VOID 1 /* void */ #define T_CHAR 2 /* character */ #define T_SHORT 3 /* short integer */ #define T_INT 4 /* integer */ #define T_LONG 5 /* long integer */ #define T_FLOAT 6 /* floating point */ #define T_DOUBLE 7 /* double length floating point */ #define T_STRUCT 8 /* structure */ #define T_UNION 9 /* union */ #define T_ENUM 10 /* enumeration */ #define T_MOE 11 /* member of enumeration */ #define T_UCHAR 12 /* unsigned character */ #define T_USHORT 13 /* unsigned short */ #define T_UINT 14 /* unsigned integer */ #define T_ULONG 15 /* unsigned long */ #define T_LNGDBL 16 /* long double floating point */ #define T_SLONG 17 /* short long */ #define T_USLONG 18 /* unsigned short long */ /* Derived types */ #define DT_NON 0 /* no derived type */ #define DT_PTR 1 /* pointer */ #define DT_FCN 2 /* function */ #define DT_ARY 3 /* array */ #define DT_ROMPTR 4 #define DT_FARROMPTR 5 /* Storage classes */ #define C_EFCN 0xff /* physical end of function */ #define C_NULL 0 /* null */ #define C_AUTO 1 /* automatic variable */ #define C_EXT 2 /* external symbol */ #define C_STAT 3 /* static */ #define C_REG 4 /* register variable */ #define C_EXTDEF 5 /* external definition */ #define C_LABEL 6 /* label */ #define C_ULABEL 7 /* undefined label */ #define C_MOS 8 /* member of structure */ #define C_ARG 9 /* function argument */ #define C_STRTAG 10 /* structure tag */ #define C_MOU 11 /* member of union */ #define C_UNTAG 12 /* union tag */ #define C_TPDEF 13 /* type definition */ #define C_USTATIC 14 /* undefined static */ #define C_ENTAG 15 /* enumeration tag */ #define C_MOE 16 /* member of enumeration */ #define C_REGPARM 17 /* register parameter */ #define C_FIELD 18 /* bit field */ #define C_AUTOARG 19 /* auto argument */ #define C_LASTENT 20 /* dummy entry (end of block) */ #define C_BLOCK 100 /* ".bb" or ".eb" */ #define C_FCN 101 /* ".bf" or ".ef" */ #define C_EOS 102 /* end of structure */ #define C_FILE 103 /* file name */ #define C_LINE 104 /* line number reformatted as symbol table entry */ #define C_ALIAS 105 /* duplicate tag */ #define C_HIDDEN 106 /* ext symbol in dmert public lib */ #define C_EOF 107 /* end of file */ #define C_LIST 108 /* absoulte listing on or off */ #define C_SECTION 109 /* section */ /* Auxiliary symbol table entry for a file */ struct aux_file { unsigned long x_offset; /* String table offset for filename */ unsigned long x_incline; /* Line number at which this file was included, 0->not included */ unsigned char x_flags; char _unused[11]; }; /* Auxiliary symbol table entry for a section */ struct aux_scn { unsigned long x_scnlen; /* Section Length */ unsigned short x_nreloc; /* Number of relocation entries */ unsigned short x_nlinno; /* Number of line numbers */ char _unused[12]; }; /* Auxiliary symbol table entry for the tagname of a struct/union/enum */ struct aux_tag { char _unused[6]; unsigned short x_size; /* Size of struct/union/enum */ char _unused2[4]; unsigned long x_endndx; /* Symbol index of next entry beyond this struct/union/enum */ char _unused3[4]; }; /* Auxiliary symbol table entry for an end of struct/union/enum */ struct aux_eos { unsigned long x_tagndx; /* Symbol index of struct/union/enum tag */ char _unused[2]; unsigned short x_size; /* Size of struct/union/enum */ char _unused2[12]; }; /* Auxiliary symbol table entry for a function name */ struct aux_fcn { unsigned long x_tagndx; /* Unused?? Tag Index */ unsigned long x_size; /* Unused?? Size of function in bits */ unsigned long x_lnnoptr; /* File pointer to line numbers for this function */ unsigned long x_endndx; /* Symbol Index of next entry beyond this function */ short x_actscnum; /* size of static activation record to allocate */ char _unused[2]; }; /* Auxiliary symbol table entry for an array */ struct aux_arr { unsigned long x_tagndx; /* Unused?? Tag Index */ unsigned short x_lnno; /* Unused?? Line number declaration */ unsigned short x_size; /* Size of array */ unsigned short x_dimen[4]; /* Size of first four dimensions */ char _unused[4]; }; /* Auxiliary symbol table entry for the end of a block or function */ struct aux_eobf { char _unused[4]; unsigned short x_lnno; /* C Source line number of the end, relative to start of block/func */ char _unused2[14]; }; /* Auxiliary symbol table entry for the beginning of a block or function */ struct aux_bobf { char _unused[4]; unsigned short x_lnno; /* C Source line number of the beginning, relative to start enclosing scope */ char _unused2[6]; unsigned long x_endndx; /* Symbol Index of next entry past this block/func */ char _unused3[4]; }; /* Auxiliary symbol table entry for a variable of type struct/union/enum */ struct aux_var { unsigned long x_tagndx; /* Symbol Index of struct/union/enum tagname */ char _unused[2]; unsigned short x_size; /* Size of the struct/union/enum */ char _unused2[12]; }; struct aux_field { char _unused[6]; unsigned short x_size; char _unused2[12]; }; struct aux_fcn_calls { unsigned long x_calleendx; unsigned long x_is_interrupt; char _unused[12]; }; /* Auxiliary entries */ #define X_DIMNUM 4 #define AUX_NONE 0 #define AUX_FILE 1 /* detail information for a source file */ #define AUX_SCN 2 /* detail information for a section */ #define AUX_TAG 3 /* detail informationfor a struct/union/enum tag */ #define AUX_EOS 4 /* end of struct/union/enum */ #define AUX_FCN 5 /* detail information for a function */ #define AUX_ARR 6 /* FIXME */ #define AUX_EOBF 7 /* end of block or function */ #define AUX_BOBF 8 /* beginning of block or function */ #define AUX_VAR 9 /* variable */ #define AUX_DIRECT 10 /* direct message */ #define AUX_IDENT 11 /* ident */ /* These definitions are for the COFF as stored in memory. */ /* relocation linked list */ typedef struct gp_reloc_type { /* entry relative address */ long address; /* symbol */ struct gp_symbol_type *symbol; /* symbol number, only valid when generating a coff file */ long symbol_number; /* offset added to address of symbol */ short offset; /* relocation type */ unsigned short type; struct gp_reloc_type *next; } gp_reloc_type; /* line number linked list */ typedef struct gp_linenum_type { /* source file symbol */ struct gp_symbol_type *symbol; /* line number */ unsigned short line_number; /* address of code for this line number */ unsigned long address; struct gp_linenum_type *next; } gp_linenum_type; /* auxiliary symbol linked list */ typedef struct gp_aux_type { /* auxiliary symbol type */ long type; /* FIXME: Finish the aux entries. */ union { struct { unsigned char command; char *string; } _aux_direct; struct { char *filename; unsigned long line_number; } _aux_file; struct { char *string; } _aux_ident; struct { unsigned long length; unsigned short nreloc; unsigned short nlineno; } _aux_scn; char data[SYMBOL_SIZE_v2]; } _aux_symbol; struct gp_aux_type *next; } gp_aux_type; /* symbol linked list */ typedef struct gp_symbol_type { /* symbol name */ char *name; /* symbol value */ long value; /* section number, only for used for determining symbol type: N_DEBUG = -2, N_ABS = -1, N_UNDEF = 0, or N_SCNUM = 1 if defined */ short section_number; /* defining section */ struct gp_section_type *section; /* type */ unsigned long type; /* storage class */ signed char class; /* number of auxiliary symbols */ char num_auxsym; /* auxiliary symbols */ struct gp_aux_type *aux_list; /* symbol number, only valid when writing coff or cod file */ unsigned long number; struct gp_symbol_type *next; } gp_symbol_type; /* section linked list */ typedef struct gp_section_type { /* section name */ char *name; /* section symbol */ struct gp_symbol_type *symbol; /* flags */ unsigned long flags; /* section address */ unsigned long address; /* section size in bytes */ unsigned long size; /* memory linked list */ MemBlock *data; /* number of relocations */ unsigned short num_reloc; /* head of relocations */ gp_reloc_type *relocations; /* tail of relocations */ gp_reloc_type *relocations_tail; /* number of line numbers */ unsigned short num_lineno; /* head of line numbers */ gp_linenum_type *line_numbers; /* tail of line numbers */ gp_linenum_type *line_numbers_tail; /* this section required for symbol resolution, only valid when linking */ gp_boolean is_used; /* section number, only valid when writing coff file */ unsigned long number; /* data pointer, only valid when writing coff file */ unsigned long data_ptr; /* relocations pointer, only valid when writing coff file */ unsigned long reloc_ptr; /* linenumber pointer, only valid when writing coff file */ unsigned long lineno_ptr; /* * when the section is STYP_BPACK, this contains the flag as to whether the * next byte would occupy part of the existing org address or start a new one */ gp_boolean have_pack_byte; /* * when the section is STYP_BPACK, this will be true when we've just emitted * a packed byte. (for synchronizing the listing) */ gp_boolean emitted_pack_byte; struct gp_section_type *next; } gp_section_type; typedef struct gp_object_type { /* object filename */ char *filename; /* format version/magic number */ int version; /* to reduce conditionals, store the size of symbols in this object */ size_t symbol_size; /* new style coff file? */ int isnew; /* processor */ pic_processor_t processor; /* processor class */ enum proc_class class; /* time object was created */ time_t time; /* flags */ unsigned short flags; /* number of sections */ long num_sections; /* head of sections */ gp_section_type *sections; /* tail of sections */ gp_section_type *sections_tail; /* number of symbols */ long num_symbols; /* head of symbols */ gp_symbol_type *symbols; /* tail of symbols */ gp_symbol_type *symbols_tail; /* symbol table pointer, only valid when writing coff file */ unsigned long symbol_ptr; /* next object in the linked list */ struct gp_object_type *next; } gp_object_type; #endif gputils-0.13.7/libgputils/Makefile.in0000644000175000017500000003433011156521302014434 00000000000000# Makefile.in generated by automake 1.9.6 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ srcdir = @srcdir@ top_srcdir = @top_srcdir@ VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ top_builddir = .. am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd INSTALL = @INSTALL@ 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installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-compile \ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ uninstall-am uninstall-info-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: gputils-0.13.7/libgputils/gpwriteobj.c0000644000175000017500000002720211156521302014707 00000000000000/* Write coff objects Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* String table offsets are 16 bits so this coff has a limit on the maximum string table size. */ #define MAX_STRING_TABLE 0xffff /* write the symbol or section name into the string table */ static int _gp_coffgen_addstring(char *name, char *table) { int nbytes; int offset; size_t sizeof_name = strlen(name) + 1; assert(name != NULL); /* read the number of bytes in the string table */ offset = nbytes = gp_getl32(&table[0]); /* check the length against the max string table size */ nbytes += sizeof_name; assert(!(nbytes > MAX_STRING_TABLE)); /* copy the string to the table */ memcpy(&table[offset], name, sizeof_name); /* write the new byte count */ gp_putl32(&table[0], nbytes); return offset; } static void _gp_coffgen_addname(char *name, char *ptr, size_t sizeof_ptr, char *table) { int length; int offset; if (name == NULL) return; length = strlen(name); if (length < 9) { /* The string will fit in the structure. */ strncpy(ptr, name, sizeof_ptr); } else { offset = _gp_coffgen_addstring(name, table); /* write zeros and offset */ gp_putl32(&ptr[0], 0); gp_putl32(&ptr[4], offset); } return; } /* write the file header */ static void _gp_coffgen_write_filehdr(gp_object_type *object, FILE *fp) { gp_fputl16((object->isnew ? MICROCHIP_MAGIC_v2 : MICROCHIP_MAGIC_v1), fp); gp_fputl16(object->num_sections, fp); gp_fputl32(object->time, fp); gp_fputl32(object->symbol_ptr, fp); gp_fputl32(object->num_symbols, fp); gp_fputl16((object->isnew ? OPT_HDR_SIZ_v2: OPT_HDR_SIZ_v1), fp); gp_fputl16(object->flags, fp); return; } /* write the optional header */ static void _gp_coffgen_write_opthdr(gp_object_type *object, FILE *fp) { unsigned long coff_type = gp_processor_coff_type(object->processor); /* make sure we catch unfinished processors */ assert(coff_type); /* write the data to file */ gp_fputl16(object->isnew ? OPTMAGIC_v2 : OPTMAGIC_v1, fp); if (object->isnew) gp_fputl32(1, fp); else gp_fputl16(1, fp); gp_fputl32(coff_type, fp); gp_fputl32(gp_processor_rom_width(object->class), fp); gp_fputl32(8, fp); return; } /* write the section header */ static void _gp_coffgen_write_scnhdr(gp_section_type *section, char *table, FILE *fp) { char name[8]; _gp_coffgen_addname(section->name, name, sizeof(name), table); gp_fputvar(&name[0], 8, fp); gp_fputl32(section->address, fp); gp_fputl32(section->address, fp); gp_fputl32(section->size, fp); gp_fputl32(section->data_ptr, fp); gp_fputl32(section->reloc_ptr, fp); gp_fputl32(section->lineno_ptr, fp); gp_fputl16(section->num_reloc, fp); gp_fputl16(section->num_lineno, fp); gp_fputl32(section->flags, fp); return; } /* write the section data */ static void _gp_coffgen_write_data(enum proc_class class, gp_section_type *section, FILE *fp) { unsigned int org; unsigned int last; unsigned int data; if ((class == PROC_CLASS_PIC16E) && ((section->flags & STYP_TEXT) || (section->flags & STYP_DATA_ROM))) org = section->address >> 1; else org = section->address; if ((section->flags & STYP_TEXT) || (section->flags & STYP_DATA_ROM)) { /* the section is executable, so each word is two bytes */ last = org + (section->size / 2); } else { /* the section is data, so each word is one byte */ last = org + section->size; } #ifdef GPUTILS_DEBUG printf("section \"%s\"\nsize= %i\ndata:\n", section->name, section->size); print_i_memory(section->data, class == PROC_CLASS_PIC16E ? 1 : 0); #endif for ( ; org < last; org++) { data = i_memory_get(section->data, org); assert(data & MEM_USED_MASK); if ((section->flags & STYP_TEXT) || (section->flags & STYP_DATA_ROM)) { gp_fputl16(data & 0xffff, fp); } else { fputc((int)(data & 0xff), fp); } } return; } /* write the section relocations */ static void _gp_coffgen_write_reloc(gp_section_type *section, FILE *fp) { gp_reloc_type *current = section->relocations; while (current != NULL) { gp_fputl32(current->address, fp); gp_fputl32(current->symbol->number, fp); gp_fputl16(current->offset, fp); gp_fputl16(current->type, fp); current = current->next; } return; } /* write the section linenumbers */ static void _gp_coffgen_write_linenum(gp_section_type *section, FILE *fp) { gp_linenum_type *current = section->line_numbers; while (current != NULL) { gp_fputl32(current->symbol->number, fp); gp_fputl16(current->line_number, fp); gp_fputl32(current->address, fp); gp_fputl16(0, fp); gp_fputl32(0, fp); current = current->next; } return; } /* write the auxiliary symbols */ static void _gp_coffgen_write_auxsymbols(gp_aux_type *aux, char *table, FILE *fp, int isnew) { unsigned int offset; while(aux != NULL) { switch (aux->type) { case AUX_DIRECT: /* add the direct string to the string table */ offset = _gp_coffgen_addstring(aux->_aux_symbol._aux_direct.string, table); gp_fputl32(aux->_aux_symbol._aux_direct.command, fp); gp_fputl32(offset, fp); gp_fputl32(0, fp); gp_fputl32(0, fp); if (isnew) gp_fputl32(0, fp); else gp_fputl16(0, fp); break; case AUX_FILE: /* add the filename to the string table */ offset = _gp_coffgen_addstring(aux->_aux_symbol._aux_file.filename, table); gp_fputl32(offset, fp); gp_fputl32(aux->_aux_symbol._aux_file.line_number, fp); gp_fputl32(0, fp); gp_fputl32(0, fp); if (isnew) gp_fputl32(0, fp); else gp_fputl16(0, fp); break; case AUX_IDENT: /* add the ident string to the string table */ offset = _gp_coffgen_addstring(aux->_aux_symbol._aux_ident.string, table); gp_fputl32(offset, fp); gp_fputl32(0, fp); gp_fputl32(0, fp); gp_fputl32(0, fp); if (isnew) gp_fputl32(0, fp); else gp_fputl16(0, fp); break; case AUX_SCN: /* write section auxiliary symbol */ gp_fputl32(aux->_aux_symbol._aux_scn.length, fp); gp_fputl16(aux->_aux_symbol._aux_scn.nreloc, fp); gp_fputl16(aux->_aux_symbol._aux_scn.nlineno, fp); gp_fputl32(0, fp); gp_fputl32(0, fp); if (isnew) gp_fputl32(0, fp); else gp_fputl16(0, fp); break; default: /* copy the data to the file */ gp_fputvar(&aux->_aux_symbol.data[0], isnew ? 20 : 18, fp); } aux = aux->next; } return; } /* write the symbol table */ static void _gp_coffgen_write_symbols(gp_object_type *object, char *table, FILE *fp) { gp_symbol_type *current; char name[8]; current = object->symbols; while(current != NULL) { _gp_coffgen_addname(current->name, name, sizeof(name), table); gp_fputvar(&name[0], 8, fp); gp_fputl32(current->value, fp); if (current->section_number < 1) { gp_fputl16(current->section_number, fp); } else { gp_fputl16(current->section->number, fp); } if (object->isnew) gp_fputl32(current->type, fp); else gp_fputl16(current->type, fp); fputc(current->class, fp); fputc(current->num_auxsym, fp); if (current->num_auxsym) _gp_coffgen_write_auxsymbols(current->aux_list, table, fp, object->isnew); current = current->next; } return; } int _has_data(gp_section_type *section) { if (section->size == 0) return 0; if (section->flags & STYP_TEXT) return 1; if (section->flags & STYP_DATA) return 1; if (section->flags & STYP_DATA_ROM) return 1; return 0; } /* update all the coff pointers */ static int _gp_updateptr(gp_object_type *object) { int loc = 0; gp_section_type *section = NULL; gp_symbol_type *symbol = NULL; int section_number = 1; int symbol_number = 0; loc = (object->isnew ? (FILE_HDR_SIZ_v2 + OPT_HDR_SIZ_v2 + (SEC_HDR_SIZ_v2 * object->num_sections)) : (FILE_HDR_SIZ_v1 + OPT_HDR_SIZ_v1 + (SEC_HDR_SIZ_v1 * object->num_sections))); /* update the data pointers in the section headers */ section = object->sections; while (section != NULL) { section->number = section_number; section_number++; section->data_ptr = 0; if (_has_data(section)) { section->data_ptr = loc; loc += section->size; } section = section->next; } /* update the relocation pointers in the section headers */ section = object->sections; while (section != NULL) { section->reloc_ptr = 0; if (section->num_reloc != 0) { section->reloc_ptr = loc; loc += (section->num_reloc * RELOC_SIZ); } section = section->next; } /* update the line number pointers in the section headers */ section = object->sections; while (section != NULL) { section->lineno_ptr = 0; if (section->num_lineno != 0) { section->lineno_ptr = loc; loc += (section->num_lineno * LINENO_SIZ); } section = section->next; } /* update symbol table pointer */ object->symbol_ptr = loc; /* update the symbol numbers */ symbol = object->symbols; while (symbol != NULL) { symbol->number = symbol_number; symbol_number += 1 + symbol->num_auxsym; symbol = symbol->next; } return 0; } /* write the coff file */ int gp_write_coff(gp_object_type *object, int numerrors) { FILE *coff; gp_section_type *section = NULL; char table[MAX_STRING_TABLE]; /* string table */ if (numerrors) { unlink(object->filename); return 0; } coff = fopen(object->filename, "wb"); if (coff == NULL) { perror(object->filename); exit(1); } /* update file pointers in the coff */ _gp_updateptr(object); /* initialize the string table byte count */ gp_putl32(&table[0], 4); /* write the data to the file */ _gp_coffgen_write_filehdr(object, coff); _gp_coffgen_write_opthdr(object, coff); section = object->sections; /* write section headers */ while (section != NULL) { _gp_coffgen_write_scnhdr(section, &table[0], coff); section = section->next; } /* write section data */ section = object->sections; while (section != NULL) { if (_has_data(section)) { _gp_coffgen_write_data(object->class, section, coff); } section = section->next; } /* write section relocations */ section = object->sections; while (section != NULL) { if (section->num_reloc != 0) { _gp_coffgen_write_reloc(section, coff); } section = section->next; } /* write section line numbers */ section = object->sections; while (section != NULL) { if (section->num_lineno != 0) { _gp_coffgen_write_linenum(section, coff); } section = section->next; } /* write symbols */ if (object->num_symbols != 0) { _gp_coffgen_write_symbols(object, &table[0], coff); } /* write string table */ fwrite(&table[0], 1, gp_getl32(&table[0]), coff); fclose(coff); return 0; } gputils-0.13.7/libgputils/gpprocessor.c0000644000175000017500000025626511156521302015116 00000000000000/* GNU PIC processor definitions Copyright (C) 2001, 2002, 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* XXXPRO: Need to add a line here for any extra processors. Please keep this list sorted primarily by number, secondarily sorting alphabetically. */ static struct px pics[] = { { PROC_CLASS_EEPROM8, "__EEPROM8", { "eeprom8", "eeprom8", "eeprom8" }, 0x1fff, 0, 0, 0x7f, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_GENERIC, "__GEN", { "generic", "gen", "unknown" }, 0x0000, 0, 0, -1, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_PIC12, "__HCS1365", { "hcs1365", "hcs1365", "hcs1365" }, 0xf365, 2, 4, 0x3ff, { -1, -1 }, { 0x7FF, 0x7FF }, "hcs1365.lkr" }, { PROC_CLASS_PIC12, "__HCS1370", { "hcs1370", "hcs1370", "hcs1370" }, 0xf370, 2, 4, 0x3ff, { -1, -1 }, { 0x7FF, 0x7FF }, "hcs1370.lkr" }, { PROC_CLASS_PIC12, "__MCV08A", { "mcv08a", "mcv08a", "mcv08a" }, 0xa510, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "mcv08a.lkr" }, { PROC_CLASS_PIC12, "__MCV14A", { "mcv14a", "mcv14a", "mcv14a" }, 0xc526, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "mcv14a.lkr" }, { PROC_CLASS_PIC12, "__MCV18A", { "mcv18a", "mcv18a", "mcv18a" }, 0xcf54, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "mcv18a.lkr" }, { PROC_CLASS_PIC12, "__MCV28A", { "mcv28a", "mcv28a", "mcv28a" }, 0xcf57, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "mcv28a.lkr" }, { PROC_CLASS_PIC12, "__10F200", { "pic10f200", "p10f200", "10f200" }, 0xf200, 1, 1, 0xff, { -1, -1 }, { 0xFFF, 0xFFF }, "10f200.lkr" }, { PROC_CLASS_PIC12, "__10F202", { "pic10f202", "p10f202", "10f202" }, 0xf202, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "10f202.lkr" }, { PROC_CLASS_PIC12, "__10F204", { "pic10f204", "p10f204", "10f204" }, 0xf204, 1, 1, 0xff, { -1, -1 }, { 0xFFF, 0xFFF }, "10f204.lkr" }, { PROC_CLASS_PIC12, "__10F206", { "pic10f206", "p10f206", "10f206" }, 0xf206, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "10f206.lkr" }, { PROC_CLASS_PIC12, "__10F220", { "pic10f220", "p10f220", "10f220" }, 0xf220, 1, 1, 0xff, { -1, -1 }, { 0xFFF, 0xFFF }, "10f220.lkr" }, { PROC_CLASS_PIC12, "__10F222", { "pic10f222", "p10f222", "10f222" }, 0xf222, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "10f222.lkr" }, { PROC_CLASS_PIC12, "__12C508", { "pic12c508", "p12c508", "12c508" }, 0x2508, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12c508.lkr" }, { PROC_CLASS_PIC12, "__12C508A", { "pic12c508a", "p12c508a", "12c508a" }, 0x508a, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12c508a.lkr" }, { PROC_CLASS_PIC12, "__12F508", { "pic12f508", "p12f508", "12f508" }, 0xf508, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12f508.lkr" }, { PROC_CLASS_PIC12, "__12C509", { "pic12c509", "p12c509", "12c509" }, 0x2509, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12c509.lkr" }, { PROC_CLASS_PIC12, "__12C509A", { "pic12c509a", "p12c509a", "12c509a" }, 0x509a, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12c509a.lkr" }, { PROC_CLASS_PIC12, "__12CR509A", { "pic12cr509a", "p12cr509a", "12cr509a" }, 0xd09a, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12cr509a.lkr" }, { PROC_CLASS_PIC12, "__12F509", { "pic12f509", "p12f509", "12f509" }, 0xf509, 2, 4, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12f509.lkr" }, { PROC_CLASS_PIC12, "__12F510", { "pic12f510", "p12f510", "12f510" }, 0xf510, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12f510.lkr" }, { PROC_CLASS_PIC12, "__12CE518", { "pic12ce518", "p12ce518", "12ce518" }, 0x2518, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12ce518.lkr" }, { PROC_CLASS_PIC12, "__12CE519", { "pic12ce519", "p12ce519", "12ce519" }, 0x2519, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "12ce519.lkr" }, { PROC_CLASS_PIC12, "__12F519", { "pic12f519", "p12f519", "12f519" }, 0xf519, 2, 4, 0x3fe, { -1, -1 }, { 0xFFF, 0xFFF }, "12f519.lkr" }, { PROC_CLASS_PIC14, "__12F609", { "pic12f609", "p12f609", "12f609" }, 0xf609, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "12f609.lkr" }, { PROC_CLASS_PIC14, "__12HV609", { "pic12hv609", "p12hv609", "12hv609" }, 0x6609, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "12hv609.lkr" }, { PROC_CLASS_PIC14, "__12F615", { "pic12f615", "p12f615", "12f615" }, 0xf615, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "12f615.lkr" }, { PROC_CLASS_PIC14, "__12HV615", { "pic12hv615", "p12hv615", "12hv615" }, 0x6615, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "12hv615.lkr" }, { PROC_CLASS_PIC14, "__12F629", { "pic12f629", "p12f629", "12f629" }, 0x2629, 1, 2, 0x217f, { 0x3ff, 0x20ff }, { 0x2007, 0x2007 }, "12f629.lkr" }, { PROC_CLASS_PIC14, "__12F635", { "pic12f635", "p12f635", "12f635" }, 0xf635, 1, 4, 0x217f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "12f635.lkr" }, { PROC_CLASS_PIC14, "__12C671", { "pic12c671", "p12c671", "12c671" }, 0x2671, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "12c671.lkr" }, { PROC_CLASS_PIC14, "__12C672", { "pic12c672", "p12c672", "12c672" }, 0x2672, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "12c672.lkr" }, { PROC_CLASS_PIC14, "__12CE673", { "pic12ce673", "p12ce673", "12ce673" }, 0x2673, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "12ce673.lkr" }, { PROC_CLASS_PIC14, "__12CE674", { "pic12ce674", "p12ce674", "12ce674" }, 0x2674, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "12ce674.lkr" }, { PROC_CLASS_PIC14, "__12F675", { "pic12f675", "p12f675", "12f675" }, 0x2675, 1, 2, 0x217f, { 0x3ff, 0x20ff }, { 0x2007, 0x2007 }, "12f675.lkr" }, { PROC_CLASS_PIC14, "__12F683", { "pic12f683", "p12f683", "12f683" }, 0xf683, 1, 2, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "12f683.lkr" }, { PROC_CLASS_PIC14, "__14000", { "pic14000", "p14000", "14000" }, 0x4000, 2, 2, 0xfbf, { -1, -1 }, { 0x2007, 0x2007 }, "14000.lkr" }, { PROC_CLASS_PIC14, "__16CXX", { "pic16cxx", "p16cxx", "16cxx" }, 0x6c77, 4, 4, -1, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_PIC14, "__16F1933", { "pic16f1933", "p16f1933", "16f1933" }, 0x1933, 2, 2, 0xf0ff, { 0x1000, 0xefff }, { 0x8007, 0x8008 }, "16f1933.lkr" }, { PROC_CLASS_PIC14, "__16LF1933", { "pic16lf1933", "p16lf1933", "16lf1933" }, 0xa933, 2, 2, 0xf0ff, { 0x1000, 0xefff }, { 0x8007, 0x8008 }, "16lf1933.lkr" }, { PROC_CLASS_PIC14, "__16F1934", { "pic16f1934", "p16f1934", "16f1934" }, 0x1934, 2, 2, 0xf0ff, { 0x1000, 0xefff }, { 0x8007, 0x8008 }, "16f1934.lkr" }, { PROC_CLASS_PIC14, "__16LF1934", { "pic16lf1934", "p16lf1934", "16lf1934" }, 0xa934, 2, 2, 0xf0ff, { 0x1000, 0xefff }, { 0x8007, 0x8008 }, "16lf1934.lkr" }, { PROC_CLASS_PIC14, "__16F1936", { "pic16f1936", "p16f1936", "16f1936" }, 0x1936, 2, 2, 0xf0ff, { 0x2000, 0xefff }, { 0x8007, 0x8008 }, "16f1936.lkr" }, { PROC_CLASS_PIC14, "__16LF1936", { "pic16lf1936", "p16lf1936", "16lf1936" }, 0xa936, 2, 2, 0xf0ff, { 0x2000, 0xefff }, { 0x8007, 0x8008 }, "16lf1936.lkr" }, { PROC_CLASS_PIC14, "__16F1937", { "pic16f1937", "p16f1937", "16f1937" }, 0x1937, 2, 2, 0xf0ff, { 0x2000, 0xefff }, { 0x8007, 0x8008 }, "16f1937.lkr" }, { PROC_CLASS_PIC14, "__16LF1937", { "pic16lf1937", "p16lf1937", "16lf1937" }, 0xa937, 2, 2, 0xf0ff, { 0x2000, 0xefff }, { 0x8007, 0x8008 }, "16lf1937.lkr" }, { PROC_CLASS_PIC14, "__16C432", { "pic16c432", "p16c432", "16c432" }, 0x6432, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c432.lkr" }, { PROC_CLASS_PIC14, "__16C433", { "pic16c433", "p16c433", "16c433" }, 0x6433, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c433.lkr" }, { PROC_CLASS_PIC12, "__16C5X", { "pic16c5x", "p16c5x", "16c5x" }, 0x658a, 4, 4, -1, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_PIC12, "__16C505", { "pic16c505", "p16c505", "16c505" }, 0x2505, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c505.lkr" }, { PROC_CLASS_PIC12, "__16F505", { "pic16f505", "p16f505", "16f505" }, 0xf505, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16f505.lkr" }, { PROC_CLASS_PIC12, "__16F506", { "pic16f506", "p16f506", "16f506" }, 0xf506, 2, 4, 0x3fe, { -1, -1 }, { 0xFFF, 0xFFF }, "16f506.lkr" }, { PROC_CLASS_PIC12, "__16C52", { "pic16c52", "p16c52", "16c52" }, 0x6c52, 1, 1, 0x17f, { -1, -1 }, { 0xFFF, 0xFFF }, "16c52.lkr" }, { PROC_CLASS_PIC12, "__16F526", { "pic16f526", "p16f526", "16f526" }, 0xf526, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16f526.lkr" }, { PROC_CLASS_PIC12, "__16C54", { "pic16c54", "p16c54", "16c54" }, 0x6c54, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c54.lkr" }, { PROC_CLASS_PIC12, "__16C54A", { "pic16c54a", "p16c54a", "16c54a" }, 0x654a, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c54a.lkr" }, { PROC_CLASS_PIC12, "__16C54B", { "pic16c54b", "p16c54b", "16c54b" }, 0x654b, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c54b.lkr" }, { PROC_CLASS_PIC12, "__16C54C", { "pic16c54c", "p16c54c", "16c54c" }, 0x654c, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c54c.lkr" }, { PROC_CLASS_PIC12, "__16CR54", { "pic16cr54", "p16cr54", "16cr54" }, 0xdc54, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr54.lkr" }, { PROC_CLASS_PIC12, "__16CR54A", { "pic16cr54a", "p16cr54a", "16cr54a" }, 0xd54a, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr54a.lkr" }, { PROC_CLASS_PIC12, "__16CR54B", { "pic16cr54b", "p16cr54b", "16cr54b" }, 0xd54b, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr54b.lkr" }, { PROC_CLASS_PIC12, "__16CR54C", { "pic16cr54c", "p16cr54c", "16cr54c" }, 0xdc54, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr54c.lkr" }, { PROC_CLASS_PIC12, "__16F54", { "pic16f54", "p16f54", "16f54" }, 0x6f54, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16f54.lkr" }, { PROC_CLASS_PIC12, "__16HV540", { "pic16hv540", "p16hv540", "16hv540" }, 0x6540, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16hv540.lkr" }, { PROC_CLASS_PIC12, "__16C55", { "pic16c55", "p16c55", "16c55" }, 0x6c55, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c55.lkr" }, { PROC_CLASS_PIC12, "__16C55A", { "pic16c55a", "p16c55a", "16c55a" }, 0x655a, 1, 1, 0x1ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c55a.lkr" }, { PROC_CLASS_PIC14, "__16C554", { "pic16c554", "p16c554", "16c554" }, 0x6554, 1, 2, 0x1ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c554.lkr" }, { PROC_CLASS_PIC14, "__16C557", { "pic16c557", "p16c557", "16c557" }, 0x6557, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c557.lkr" }, { PROC_CLASS_PIC14, "__16C558", { "pic16c558", "p16c558", "16c558" }, 0x6558, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c558.lkr" }, { PROC_CLASS_PIC12, "__16C56", { "pic16c56", "p16c56", "16c56" }, 0x6c56, 2, 1, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c56.lkr" }, { PROC_CLASS_PIC12, "__16C56A", { "pic16c56a", "p16c56a", "16c56a" }, 0x656a, 2, 1, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c56a.lkr" }, { PROC_CLASS_PIC12, "__16CR56A", { "pic16cr56a", "p16cr56a", "16cr56a" }, 0xd56a, 2, 1, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr56a.lkr" }, { PROC_CLASS_PIC12, "__16C57", { "pic16c57", "p16c57", "16c57" }, 0x6c57, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c57.lkr" }, { PROC_CLASS_PIC12, "__16C57C", { "pic16c57c", "p16c57c", "16c57c" }, 0x657c, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c57c.lkr" }, { PROC_CLASS_PIC12, "__16CR57A", { "pic16cr57a", "p16cr57a", "16cr57a" }, 0xd57a, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr57a.lkr" }, { PROC_CLASS_PIC12, "__16CR57B", { "pic16cr57b", "p16cr57b", "16cr57b" }, 0xd57b, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr57b.lkr" }, { PROC_CLASS_PIC12, "__16CR57C", { "pic16cr57c", "p16cr57c", "16cr57c" }, 0xd57c, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr57c.lkr" }, { PROC_CLASS_PIC12, "__16F57", { "pic16f57", "p16f57", "16f57" }, 0x6f57, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16f57.lkr" }, { PROC_CLASS_PIC12, "__16C58A", { "pic16c58a", "p16c58a", "16c58a" }, 0x658a, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c58a.lkr" }, { PROC_CLASS_PIC12, "__16C58B", { "pic16c58b", "p16c58b", "16c58b" }, 0x658b, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16c58b.lkr" }, { PROC_CLASS_PIC12, "__16CR58A", { "pic16cr58a", "p16cr58a", "16cr58a" }, 0xd58a, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr58a.lkr" }, { PROC_CLASS_PIC12, "__16CR58B", { "pic16cr58b", "p16cr58b", "16cr58b" }, 0xd58b, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16cr58b.lkr" }, { PROC_CLASS_PIC12, "__16F59", { "pic16f59", "p16f59", "16f59" }, 0x6f59, 4, 4, 0x7ff, { -1, -1 }, { 0xFFF, 0xFFF }, "16f59.lkr" }, { PROC_CLASS_PIC14, "__16C61", { "pic16c61", "p16c61", "16c61" }, 0x6c61, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c61.lkr" }, { PROC_CLASS_PIC14, "__16F610", { "pic16f610", "p16f610", "16f610" }, 0xf610, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f610.lkr" }, { PROC_CLASS_PIC14, "__16HV610", { "pic16hv610", "p16hv610", "16hv610" }, 0x6610, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16hv610.lkr" }, { PROC_CLASS_PIC14, "__16F616", { "pic16f616", "p16f616", "16f616" }, 0xf616, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f616.lkr" }, { PROC_CLASS_PIC14, "__16HV616", { "pic16hv616", "p16hv616", "16hv616" }, 0x6616, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16hv616.lkr" }, { PROC_CLASS_PIC14, "__16C62", { "pic16c62", "p16c62", "16c62" }, 0x6c62, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c62.lkr" }, { PROC_CLASS_PIC14, "__16C62A", { "pic16c62a", "p16c62a", "16c62a" }, 0x662a, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c62a.lkr" }, { PROC_CLASS_PIC14, "__16C62B", { "pic16c62b", "p16c62b", "16c62b" }, 0x662b, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c62b.lkr" }, { PROC_CLASS_PIC14, "__16CR62", { "pic16cr62", "p16cr62", "16cr62" }, 0xdc62, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16cr62.lkr" }, { PROC_CLASS_PIC14, "__16C620", { "pic16c620", "p16c620", "16c620" }, 0x6620, 1, 2, 0x1ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c620.lkr" }, { PROC_CLASS_PIC14, "__16C620A", { "pic16c620a", "p16c620a", "16c620a" }, 0x620a, 1, 2, 0x1ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c620a.lkr" }, { PROC_CLASS_PIC14, "__16CR620A", { "pic16cr620a", "p16cr620a", "16cr620a" }, 0xd20a, 1, 2, 0x1ff, { -1, -1 }, { 0x2007, 0x2007 }, "16cr620a.lkr" }, { PROC_CLASS_PIC14, "__16C621", { "pic16c621", "p16c621", "16c621" }, 0x6621, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c621.lkr" }, { PROC_CLASS_PIC14, "__16C621A", { "pic16c621a", "p16c621a", "16c621a" }, 0x621a, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c621a.lkr" }, { PROC_CLASS_PIC14, "__16C622", { "pic16c622", "p16c622", "16c622" }, 0x6622, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c622.lkr" }, { PROC_CLASS_PIC14, "__16C622A", { "pic16c622a", "p16c622a", "16c622a" }, 0x622a, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c622a.lkr" }, { PROC_CLASS_PIC14, "__16CE623", { "pic16ce623", "p16ce623", "16ce623" }, 0x6623, 1, 2, 0x1ff, { -1, -1 }, { 0x2007, 0x2007 }, "16ce623.lkr" }, { PROC_CLASS_PIC14, "__16CE624", { "pic16ce624", "p16ce624", "16ce624" }, 0x6624, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16ce624.lkr" }, { PROC_CLASS_PIC14, "__16CE625", { "pic16ce625", "p16ce625", "16ce625" }, 0x6625, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16ce625.lkr" }, { PROC_CLASS_PIC14, "__16F627", { "pic16f627", "p16f627", "16f627" }, 0x6627, 1, 4, 0x217f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "16f627.lkr" }, { PROC_CLASS_PIC14, "__16F627A", { "pic16f627a", "p16f627a", "16f627a" }, 0x627a, 1, 4, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f627a.lkr" }, { PROC_CLASS_PIC14, "__16F628", { "pic16f628", "p16f628", "16f628" }, 0x6628, 1, 4, 0x217f, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f628.lkr" }, { PROC_CLASS_PIC14, "__16F628A", { "pic16f628a", "p16f628a", "16f628a" }, 0x628a, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f628a.lkr" }, { PROC_CLASS_PIC14, "__16C63", { "pic16c63", "p16c63", "16c63" }, 0x6c63, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c63.lkr" }, { PROC_CLASS_PIC14, "__16C63A", { "pic16c63a", "p16c63a", "16c63a" }, 0x663a, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c63a.lkr" }, { PROC_CLASS_PIC14, "__16CR63", { "pic16cr63", "p16cr63", "16cr63" }, 0x6d63, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16cr63.lkr" }, { PROC_CLASS_PIC14, "__16F630", { "pic16f630", "p16f630", "16f630" }, 0x6630, 1, 4, 0x217f, { 0x3ff, 0x20ff }, { 0x2007, 0x2007 }, "16f630.lkr" }, { PROC_CLASS_PIC14, "__16F631", { "pic16f631", "p16f631", "16f631" }, 0x6631, 1, 4, 0x217f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "16f631.lkr" }, { PROC_CLASS_PIC14, "__16F636", { "pic16f636", "p16f636", "16f636" }, 0xf636, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f636.lkr" }, { PROC_CLASS_PIC14, "__16F639", { "pic16f639", "p16f639", "16f639" }, 0xf639, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f639.lkr" }, { PROC_CLASS_PIC14, "__16C64", { "pic16c64", "p16c64", "16c64" }, 0x6c64, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c64.lkr" }, { PROC_CLASS_PIC14, "__16C64A", { "pic16c64a", "p16c64a", "16c64a" }, 0x664a, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c64a.lkr" }, { PROC_CLASS_PIC14, "__16CR64", { "pic16cr64", "p16cr64", "16cr64" }, 0xdc64, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16cr64.lkr" }, { PROC_CLASS_PIC14, "__16C642", { "pic16c642", "p16c642", "16c642" }, 0x6642, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c642.lkr" }, { PROC_CLASS_PIC14, "__16F648A", { "pic16f648a", "p16f648a", "16f648a" }, 0x648a, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16f648a.lkr" }, { PROC_CLASS_PIC14, "__16C65", { "pic16c65", "p16c65", "16c65" }, 0x6c65, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c65.lkr" }, { PROC_CLASS_PIC14, "__16C65A", { "pic16c65a", "p16c65a", "16c65a" }, 0x665a, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c65a.lkr" }, { PROC_CLASS_PIC14, "__16C65B", { "pic16c65b", "p16c65b", "16c65b" }, 0x665b, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c65b.lkr" }, { PROC_CLASS_PIC14, "__16CR65", { "pic16cr65", "p16cr65", "16cr65" }, 0x6d65, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16cr65.lkr" }, { PROC_CLASS_PIC14, "__16C66", { "pic16c66", "p16c66", "16c66" }, 0x6c66, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c66.lkr" }, { PROC_CLASS_PIC14, "__16C662", { "pic16c662", "p16c662", "16c662" }, 0x6662, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c662.lkr" }, { PROC_CLASS_PIC14, "__16C67", { "pic16c67", "p16c67", "16c67" }, 0x6c67, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c67.lkr" }, { PROC_CLASS_PIC14, "__16F676", { "pic16f676", "p16f676", "16f676" }, 0x6676, 1, 4, 0x217f, { 0x3ff, 0x20ff }, { 0x2007, 0x2007 }, "16f676.lkr" }, { PROC_CLASS_PIC14, "__16F677", { "pic16f677", "p16f677", "16f677" }, 0x6677, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f677.lkr" }, { PROC_CLASS_PIC14, "__16F684", { "pic16f684", "p16f684", "16f684" }, 0x6684, 1, 2, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f684.lkr" }, { PROC_CLASS_PIC14, "__16F685", { "pic16f685", "p16f685", "16f685" }, 0x6685, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f685.lkr" }, { PROC_CLASS_PIC14, "__16F687", { "pic16f687", "p16f687", "16f687" }, 0x6687, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f687.lkr" }, { PROC_CLASS_PIC14, "__16F688", { "pic16f688", "p16f688", "16f688" }, 0x6688, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f688.lkr" }, { PROC_CLASS_PIC14, "__16F689", { "pic16f689", "p16f689", "16f689" }, 0x6689, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f689.lkr" }, { PROC_CLASS_PIC14, "__16F690", { "pic16f690", "p16f690", "16f690" }, 0x6690, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f690.lkr" }, { PROC_CLASS_PIC14, "__16C71", { "pic16c71", "p16c71", "16c71" }, 0x6c71, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c71.lkr" }, { PROC_CLASS_PIC14, "__16C710", { "pic16c710", "p16c710", "16c710" }, 0x6710, 1, 2, 0x1ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c710.lkr" }, { PROC_CLASS_PIC14, "__16C711", { "pic16c711", "p16c711", "16c711" }, 0x6711, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c711.lkr" }, { PROC_CLASS_PIC14, "__16C712", { "pic16c712", "p16c712", "16c712" }, 0x6712, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c712.lkr" }, { PROC_CLASS_PIC14, "__16C715", { "pic16c715", "p16c715", "16c715" }, 0x6715, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c715.lkr" }, { PROC_CLASS_PIC14, "__16C716", { "pic16c716", "p16c716", "16c716" }, 0x6716, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c716.lkr" }, { PROC_CLASS_PIC14, "__16F716", { "pic16f716", "p16f716", "16f716" }, 0xf716, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f716.lkr" }, { PROC_CLASS_PIC14, "__16C717", { "pic16c717", "p16c717", "16c717" }, 0x6717, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c717.lkr" }, { PROC_CLASS_PIC14, "__16C72", { "pic16c72", "p16c72", "16c72" }, 0x6c72, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c72.lkr" }, { PROC_CLASS_PIC14, "__16C72A", { "pic16c72a", "p16c72a", "16c72a" }, 0x672a, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c72a.lkr" }, { PROC_CLASS_PIC14, "__16CR72", { "pic16cr72", "p16cr72", "16cr72" }, 0x6d72, 1, 2, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16cr72.lkr" }, { PROC_CLASS_PIC14, "__16F72", { "pic16f72", "p16f72", "16f72" }, 0x672f, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f72.lkr" }, { PROC_CLASS_PIC14, "__16F722", { "pic16f722", "p16f722", "16f722" }, 0xf722, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2008 }, "16f722.lkr" }, { PROC_CLASS_PIC14, "__16LF722", { "pic16lf722", "p16lf722", "16lf722" }, 0xd722, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2008 }, "16lf722.lkr" }, { PROC_CLASS_PIC14, "__16F723", { "pic16f723", "p16f723", "16f723" }, 0xf723, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2008 }, "16f723.lkr" }, { PROC_CLASS_PIC14, "__16LF723", { "pic16lf723", "p16lf723", "16lf723" }, 0xd723, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2008 }, "16lf723.lkr" }, { PROC_CLASS_PIC14, "__16F724", { "pic16f724", "p16f724", "16f724" }, 0xf724, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2008 }, "16f724.lkr" }, { PROC_CLASS_PIC14, "__16LF724", { "pic16lf724", "p16lf724", "16lf724" }, 0xd724, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2008 }, "16lf724.lkr" }, { PROC_CLASS_PIC14, "__16F726", { "pic16f726", "p16f726", "16f726" }, 0xf726, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2008 }, "16f726.lkr" }, { PROC_CLASS_PIC14, "__16LF726", { "pic16lf726", "p16lf726", "16lf726" }, 0xd726, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2008 }, "16lf726.lkr" }, { PROC_CLASS_PIC14, "__16F727", { "pic16f727", "p16f727", "16f727" }, 0xf727, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2008 }, "16f727.lkr" }, { PROC_CLASS_PIC14, "__16LF727", { "pic16lf727", "p16lf727", "16lf727" }, 0xd727, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2008 }, "16lf727.lkr" }, { PROC_CLASS_PIC14, "__16C73", { "pic16c73", "p16c73", "16c73" }, 0x6c73, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c73.lkr" }, { PROC_CLASS_PIC14, "__16C73A", { "pic16c73a", "p16c73a", "16c73a" }, 0x673a, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c73a.lkr" }, { PROC_CLASS_PIC14, "__16C73B", { "pic16c73b", "p16c73b", "16c73b" }, 0x673b, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c73b.lkr" }, { PROC_CLASS_PIC14, "__16F73", { "pic16f73", "p16f73", "16f73" }, 0x673f, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16f73.lkr" }, { PROC_CLASS_PIC14, "__16F737", { "pic16f737", "p16f737", "16f737" }, 0x6737, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2008 }, "16f737.lkr" }, { PROC_CLASS_PIC14, "__16C74", { "pic16c74", "p16c74", "16c74" }, 0x6c74, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c74.lkr" }, { PROC_CLASS_PIC14, "__16C74A", { "pic16c74a", "p16c74a", "16c74a" }, 0x674a, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c74a.lkr" }, { PROC_CLASS_PIC14, "__16C74B", { "pic16c74b", "p16c74b", "16c74b" }, 0x674b, 2, 2, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c74b.lkr" }, { PROC_CLASS_PIC14, "__16F74", { "pic16f74", "p16f74", "16f74" }, 0x674f, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16f74.lkr" }, { PROC_CLASS_PIC14, "__16C745", { "pic16c745", "p16c745", "16c745" }, 0x6745, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c745.lkr" }, { PROC_CLASS_PIC14, "__16F747", { "pic16f747", "p16f747", "16f747" }, 0x6747, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2008 }, "16f747.lkr" }, { PROC_CLASS_PIC14, "__16C76", { "pic16c76", "p16c76", "16c76" }, 0x6c76, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c76.lkr" }, { PROC_CLASS_PIC14, "__16F76", { "pic16f76", "p16f76", "16f76" }, 0x676f, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16f76.lkr" }, { PROC_CLASS_PIC14, "__16C765", { "pic16c765", "p16c765", "16c765" }, 0x6765, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c765.lkr" }, { PROC_CLASS_PIC14, "__16F767", { "pic16f767", "p16f767", "16f767" }, 0x6767, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2008 }, "16f767.lkr" }, { PROC_CLASS_PIC14, "__16C77", { "pic16c77", "p16c77", "16c77" }, 0x6c77, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c77.lkr" }, { PROC_CLASS_PIC14, "__16F77", { "pic16f77", "p16f77", "16f77" }, 0x677f, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16f77.lkr" }, { PROC_CLASS_PIC14, "__16C770", { "pic16c770", "p16c770", "16c770" }, 0x6770, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c770.lkr" }, { PROC_CLASS_PIC14, "__16C771", { "pic16c771", "p16c771", "16c771" }, 0x6771, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c771.lkr" }, { PROC_CLASS_PIC14, "__16C773", { "pic16c773", "p16c773", "16c773" }, 0x6773, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c773.lkr" }, { PROC_CLASS_PIC14, "__16C774", { "pic16c774", "p16c774", "16c774" }, 0x6774, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c774.lkr" }, { PROC_CLASS_PIC14, "__16F777", { "pic16f777", "p16f777", "16f777" }, 0x6777, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2008 }, "16f777.lkr" }, { PROC_CLASS_PIC14, "__16C781", { "pic16c781", "p16c781", "16c781" }, 0x6781, 1, 4, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c781.lkr" }, { PROC_CLASS_PIC14, "__16C782", { "pic16c782", "p16c782", "16c782" }, 0x6782, 1, 4, 0x7ff, { -1, -1 }, { 0x2007, 0x2007 }, "16c782.lkr" }, { PROC_CLASS_PIC14, "__16F785", { "pic16f785", "p16f785", "16f785" }, 0xf785, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f785.lkr" }, { PROC_CLASS_PIC14, "__16HV785", { "pic16hv785", "p16hv785", "16hv785" }, 0x6785, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16hv785.lkr" }, { PROC_CLASS_PIC14, "__16F818", { "pic16f818", "p16f818", "16f818" }, 0x818f, 1, 4, 0x217f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "16f818.lkr" }, { PROC_CLASS_PIC14, "__16F819", { "pic16f819", "p16f819", "16f819" }, 0x819f, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f819.lkr" }, { PROC_CLASS_PIC14, "__16CR83", { "pic16cr83", "p16cr83", "16cr83" }, 0xdc83, 1, 2, 0x213f, { 0x200, 0x20ff }, { 0x2007, 0x2007 }, "16cr83.lkr" }, { PROC_CLASS_PIC14, "__16F83", { "pic16f83", "p16f83", "16f83" }, 0x6c83, 1, 2, 0x213f, { 0x200, 0x20ff }, { 0x2007, 0x2007 }, "16f83.lkr" }, { PROC_CLASS_PIC14, "__16C84", { "pic16c84", "p16c84", "16c84" }, 0x6c84, 1, 2, 0x213f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "16c84.lkr" }, { PROC_CLASS_PIC14, "__16CR84", { "pic16cr84", "p16cr84", "16cr84" }, 0xdc84, 1, 2, 0x213f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "16cr84.lkr" }, { PROC_CLASS_PIC14, "__16F84", { "pic16f84", "p16f84", "16f84" }, 0x684a, 1, 2, 0x213f, { 0x400, 0x20ff }, { 0x2007, 0x2007 }, "16f84.lkr" }, { PROC_CLASS_PIC14, "__16F84A", { "pic16f84a", "p16f84a", "16f84a" }, 0x6f84, 1, 2, 0x3ff, { -1, -1 }, { 0x2007, 0x2007 }, "16f84a.lkr" }, { PROC_CLASS_PIC14, "__16F87", { "pic16f87", "p16f87", "16f87" }, 0x687f, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2008 }, "16f87.lkr" }, { PROC_CLASS_PIC14, "__16F870", { "pic16f870", "p16f870", "16f870" }, 0x870f, 1, 4, 0x213f, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f870.lkr" }, { PROC_CLASS_PIC14, "__16F871", { "pic16f871", "p16f871", "16f871" }, 0x871f, 1, 4, 0x213f, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f871.lkr" }, { PROC_CLASS_PIC14, "__16F872", { "pic16f872", "p16f872", "16f872" }, 0x872f, 1, 4, 0x213f, { 0x800, 0x20ff }, { 0x2007, 0x2007 }, "16f872.lkr" }, { PROC_CLASS_PIC14, "__16F873", { "pic16f873", "p16f873", "16f873" }, 0x873f, 2, 4, 0x217f, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f873.lkr" }, { PROC_CLASS_PIC14, "__16F873A", { "pic16f873a", "p16f873a", "16f873a" }, 0x873a, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16f873a.lkr" }, { PROC_CLASS_PIC14, "__16F874", { "pic16f874", "p16f874", "16f874" }, 0x874f, 2, 4, 0x217f, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f874.lkr" }, { PROC_CLASS_PIC14, "__16F874A", { "pic16f874a", "p16f874a", "16f874a" }, 0x874a, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16f874a.lkr" }, { PROC_CLASS_PIC14, "__16F876", { "pic16f876", "p16f876", "16f876" }, 0x876f, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2007 }, "16f876.lkr" }, { PROC_CLASS_PIC14, "__16F876A", { "pic16f876a", "p16f876a", "16f876a" }, 0x876a, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16f876a.lkr" }, { PROC_CLASS_PIC14, "__16F877", { "pic16f877", "p16f877", "16f877" }, 0x877f, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2007 }, "16f877.lkr" }, { PROC_CLASS_PIC14, "__16F877A", { "pic16f877a", "p16f877a", "16f877a" }, 0x877a, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16f877a.lkr" }, { PROC_CLASS_PIC14, "__16F88", { "pic16f88", "p16f88", "16f88" }, 0x688f, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2008 }, "16f88.lkr" }, { PROC_CLASS_PIC14, "__16F882", { "pic16f882", "p16f882", "16f882" }, 0x882f, 1, 4, 0x21ff, { 0x800, 0x20ff }, { 0x2007, 0x2008 }, "16f882.lkr" }, { PROC_CLASS_PIC14, "__16F883", { "pic16f883", "p16f883", "16f883" }, 0x883f, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2008 }, "16f883.lkr" }, { PROC_CLASS_PIC14, "__16F884", { "pic16f884", "p16f884", "16f884" }, 0x884f, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2008 }, "16f884.lkr" }, { PROC_CLASS_PIC14, "__16F886", { "pic16f886", "p16f886", "16f886" }, 0x886f, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2008 }, "16f886.lkr" }, { PROC_CLASS_PIC14, "__16F887", { "pic16f887", "p16f887", "16f887" }, 0x887f, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2008 }, "16f887.lkr" }, { PROC_CLASS_PIC14, "__16F913", { "pic16f913", "p16f913", "16f913" }, 0xf913, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f913.lkr" }, { PROC_CLASS_PIC14, "__16F914", { "pic16f914", "p16f914", "16f914" }, 0xf914, 2, 4, 0x21ff, { 0x1000, 0x20ff }, { 0x2007, 0x2007 }, "16f914.lkr" }, { PROC_CLASS_PIC14, "__16F916", { "pic16f916", "p16f916", "16f916" }, 0xf916, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2007 }, "16f916.lkr" }, { PROC_CLASS_PIC14, "__16F917", { "pic16f917", "p16f917", "16f917" }, 0xf917, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2007 }, "16f917.lkr" }, { PROC_CLASS_PIC14, "__16C923", { "pic16c923", "p16c923", "16c923" }, 0x6923, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c923.lkr" }, { PROC_CLASS_PIC14, "__16C924", { "pic16c924", "p16c924", "16c924" }, 0x6924, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c924.lkr" }, { PROC_CLASS_PIC14, "__16C925", { "pic16c925", "p16c925", "16c925" }, 0x6925, 2, 4, 0xfff, { -1, -1 }, { 0x2007, 0x2007 }, "16c925.lkr" }, { PROC_CLASS_PIC14, "__16C926", { "pic16c926", "p16c926", "16c926" }, 0x6926, 4, 4, 0x1fff, { -1, -1 }, { 0x2007, 0x2007 }, "16c926.lkr" }, { PROC_CLASS_PIC14, "__16F946", { "pic16f946", "p16f946", "16f946" }, 0xf946, 4, 4, 0x21ff, { 0x2000, 0x20ff }, { 0x2007, 0x2007 }, "16f946.lkr" }, { PROC_CLASS_PIC16, "__17CXX", { "pic17cxx", "p17cxx", "17cxx" }, 0x7756, 0, 0, -1, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_PIC16, "__17C42", { "pic17c42", "p17c42", "17c42" }, 0x7c42, 0, 0, 0x7ff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c42.lkr" }, { PROC_CLASS_PIC16, "__17C42A", { "pic17c42a", "p17c42a", "17c42a" }, 0x742a, 0, 0, 0x7ff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c42a.lkr" }, { PROC_CLASS_PIC16, "__17CR42", { "pic17cr42", "p17cr42", "17cr42" }, 0xe42a, 0, 0, 0x7ff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17cr42.lkr" }, { PROC_CLASS_PIC16, "__17C43", { "pic17c43", "p17c43", "17c43" }, 0x7c43, 0, 0, 0xfff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c43.lkr" }, { PROC_CLASS_PIC16, "__17CR43", { "pic17cr43", "p17cr43", "17cr43" }, 0xec43, 0, 0, 0xfff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17cr43.lkr" }, { PROC_CLASS_PIC16, "__17C44", { "pic17c44", "p17c44", "17c44" }, 0x7c44, 0, 0, 0x1fff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c44.lkr" }, { PROC_CLASS_PIC16, "__17C752", { "pic17c752", "p17c752", "17c752" }, 0x7752, 0, 0, 0x1fff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c752.lkr" }, { PROC_CLASS_PIC16, "__17C756", { "pic17c756", "p17c756", "17c756" }, 0x7756, 0, 0, 0x3fff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c756.lkr" }, { PROC_CLASS_PIC16, "__17C756A", { "pic17c756a", "p17c756a", "17c756a" }, 0x756a, 0, 0, 0x3fff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c756a.lkr" }, { PROC_CLASS_PIC16, "__17C762", { "pic17c762", "p17c762", "17c762" }, 0x7762, 0, 0, 0x1fff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c762.lkr" }, { PROC_CLASS_PIC16, "__17C766", { "pic17c766", "p17c766", "17c766" }, 0x7766, 0, 0, 0x3fff, { -1, -1 }, { 0xFE00, 0xFE0F }, "17c766.lkr" }, { PROC_CLASS_PIC16E, "__18CXX", { "pic18cxx", "p18cxx", "18cxx" }, 0x8452, 0, 0x80, -1, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_PIC16E, "__18F1220", { "pic18f1220", "p18f1220", "18f1220" }, 0xa122, 0, 0x80, 0xf000ff, { 0x1000, 0xefffff }, { 0x300000, 0x30000D }, "18f1220.lkr" }, { PROC_CLASS_PIC16E, "__18F1230", { "pic18f1230", "p18f1230", "18f1230" }, 0x1230, 0, 0x80, 0xf0007f, { 0x1000, 0xefffff }, { 0x300000, 0x30000D }, "18f1230.lkr" }, { PROC_CLASS_PIC16E, "__18F1320", { "pic18f1320", "p18f1320", "18f1320" }, 0xa132, 0, 0x80, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f1320.lkr" }, { PROC_CLASS_PIC16E, "__18F13K22", { "pic18f13k22", "p18f13k22", "18f13k22" }, 0xb132, 0, 0x60, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f13k22.lkr" }, { PROC_CLASS_PIC16E, "__18LF13K22",{ "pic18lf13k22","p18lf13k22","18lf13k22"}, 0xa133, 0, 0x60, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18lf13k22.lkr"}, { PROC_CLASS_PIC16E, "__18F1330", { "pic18f1330", "p18f1330", "18f1330" }, 0x1330, 0, 0x80, 0xf0007f, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f1330.lkr" }, { PROC_CLASS_PIC16E, "__18F13K50", { "pic18f13k50", "p18f13k50", "18f13k50" }, 0xa135, 0, 0x60, 0xf0007f, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f13k50.lkr" }, { PROC_CLASS_PIC16E, "__18LF13K50",{ "pic18lf13k50","p18lf13k50","18lf13k50"}, 0xd135, 0, 0x60, 0xf0007f, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18lf13k50.lkr" }, { PROC_CLASS_PIC16E, "__18F14K22", { "pic18f14k22", "p18f14k22", "18f14k22" }, 0xb142, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f14k22.lkr" }, { PROC_CLASS_PIC16E, "__18LF14K22",{ "pic18lf14k22","p18lf14k22","18lf14k22"}, 0xa142, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18lf14k22.lkr"}, { PROC_CLASS_PIC16E, "__18F14K50", { "pic18f14k50", "p18f14k50", "18f14k50" }, 0xa145, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f14k50.lkr" }, { PROC_CLASS_PIC16E, "__18LF14K50",{ "pic18lf14k50","p18lf14k50","18lf14k50"}, 0xd145, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18lf14k50.lkr"}, { PROC_CLASS_PIC16E, "__18F2220", { "pic18f2220", "p18f2220", "18f2220" }, 0xa222, 0, 0x80, 0xf000ff, { 0x1000, 0xefffff }, { 0x300000, 0x30000D }, "18f2220.lkr" }, { PROC_CLASS_PIC16E, "__18F2221", { "pic18f2221", "p18f2221", "18f2221" }, 0x2221, 0, 0x80, 0xf000ff, { 0x1000, 0xefffff }, { 0x300000, 0x30000D }, "18f2221.lkr" }, { PROC_CLASS_PIC16E, "__18F2320", { "pic18f2320", "p18f2320", "18f2320" }, 0xa232, 0, 0x80, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f2320.lkr" }, { PROC_CLASS_PIC16E, "__18F23K20", { "pic18f23k20", "p18f23k20", "18f23k20" }, 0xd320, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f23k20.lkr" }, { PROC_CLASS_PIC16E, "__18F2321", { "pic18f2321", "p18f2321", "18f2321" }, 0x2321, 0, 0x80, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f2321.lkr" }, { PROC_CLASS_PIC16E, "__18F2331", { "pic18f2331", "p18f2331", "18f2331" }, 0x2331, 0, 0x60, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f2331.lkr" }, { PROC_CLASS_PIC16E, "__18F2410", { "pic18f2410", "p18f2410", "18f2410" }, 0x2410, 0, 0x80, 0x3fff, { -1, -1 }, { 0x300000, 0x30000D }, "18f2410.lkr" }, { PROC_CLASS_PIC16E, "__18F24J10", { "pic18f24j10", "p18f24j10", "18f24j10" }, 0xd410, 0, 0x80, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFD }, "18f24j10.lkr" }, { PROC_CLASS_PIC16E, "__18F24J11", { "pic18f24j11", "p18f24j11", "18f24j11" }, 0xd411, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18f24j11.lkr" }, { PROC_CLASS_PIC16E, "__18LF24J11",{ "pic18lf24j11","p18lf24j11","18lf24j11"}, 0xb411, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18lf24j11.lkr"}, { PROC_CLASS_PIC16E, "__18C242", { "pic18c242", "p18c242", "18c242" }, 0x8242, 0, 0x80, 0x3fff, { -1, -1 }, { 0x300000, 0x300006 }, "18c242.lkr" }, { PROC_CLASS_PIC16E, "__18F242", { "pic18f242", "p18f242", "18f242" }, 0x242f, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f242.lkr" }, { PROC_CLASS_PIC16E, "__18F2420", { "pic18f2420", "p18f2420", "18f2420" }, 0x2420, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f2420.lkr" }, { PROC_CLASS_PIC16E, "__18F24K20", { "pic18f24k20", "p18f24k20", "18f24k20" }, 0xd420, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f24k20.lkr" }, { PROC_CLASS_PIC16E, "__18F2423", { "pic18f2423", "p18f2423", "18f2423" }, 0x2423, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f2423.lkr" }, { PROC_CLASS_PIC16E, "__18F2431", { "pic18f2431", "p18f2431", "18f2431" }, 0x2431, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f2431.lkr" }, { PROC_CLASS_PIC16E, "__18F2439", { "pic18f2439", "p18f2439", "18f2439" }, 0x2439, 0, 0x80, 0xf000ff, { 0x3000, 0xefffff }, { 0x300000, 0x30000D }, "18f2439.lkr" }, { PROC_CLASS_PIC16E, "__18F2450", { "pic18f2450", "p18f2450", "18f2450" }, 0x2450, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f2450.lkr" }, { PROC_CLASS_PIC16E, "__18F24J50", { "pic18f24j50", "p18f24j50", "18f24j50" }, 0xd450, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18f24j50.lkr" }, { PROC_CLASS_PIC16E, "__18LF24J50",{ "pic18lf24j50","p18lf24j50","18lf24j50"}, 0xb450, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18lf24j50.lkr"}, { PROC_CLASS_PIC16E, "__18F2455", { "pic18f2455", "p18f2455", "18f2455" }, 0x2455, 0, 0x60, 0xf000ff, { 0x6000, 0xefffff }, { 0x300000, 0x30000D }, "18f2455.lkr" }, { PROC_CLASS_PIC16E, "__18F2458", { "pic18f2458", "p18f2458", "18f2458" }, 0x2458, 0, 0x60, 0xf000ff, { 0x6000, 0xefffff }, { 0x300000, 0x30000D }, "18f2458.lkr" }, { PROC_CLASS_PIC16E, "__18F248", { "pic18f248", "p18f248", "18f248" }, 0x8248, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f248.lkr" }, { PROC_CLASS_PIC16E, "__18F2480", { "pic18f2480", "p18f2480", "18f2480" }, 0x2480, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f2480.lkr" }, { PROC_CLASS_PIC16E, "__18F2510", { "pic18f2510", "p18f2510", "18f2510" }, 0x2510, 0, 0x80, 0x7fff, { -1, -1 }, { 0x300000, 0x30000D }, "18f2510.lkr" }, { PROC_CLASS_PIC16E, "__18F25J10", { "pic18f25j10", "p18f25j10", "18f25j10" }, 0xd510, 0, 0x80, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f25j10.lkr" }, { PROC_CLASS_PIC16E, "__18F25J11", { "pic18f25j11", "p18f25j11", "18f25j11" }, 0xd511, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18f25j11.lkr" }, { PROC_CLASS_PIC16E, "__18LF25J11",{ "pic18lf25j11","p18lf25j11","18lf25j11"}, 0xb511, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18lf25j11.lkr"}, { PROC_CLASS_PIC16E, "__18F2515", { "pic18f2515", "p18f2515", "18f2515" }, 0x2515, 0, 0x80, 0xbfff, { -1, -1 }, { 0x300000, 0x30000D }, "18f2515.lkr" }, { PROC_CLASS_PIC16E, "__18C252", { "pic18c252", "p18c252", "18c252" }, 0x8252, 0, 0x80, 0x7fff, { -1, -1 }, { 0x300000, 0x300006 }, "18c252.lkr" }, { PROC_CLASS_PIC16E, "__18F252", { "pic18f252", "p18f252", "18f252" }, 0x252f, 0, 0x80, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f252.lkr" }, { PROC_CLASS_PIC16E, "__18F2520", { "pic18f2520", "p18f2520", "18f2520" }, 0x2520, 0, 0x80, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f2520.lkr" }, { PROC_CLASS_PIC16E, "__18F25K20", { "pic18f25k20", "p18f25k20", "18f25k20" }, 0xd520, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f25k20.lkr" }, { PROC_CLASS_PIC16E, "__18F2523", { "pic18f2523", "p18f2523", "18f2523" }, 0x2523, 0, 0x80, 0x7fff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f2523.lkr" }, { PROC_CLASS_PIC16E, "__18F2525", { "pic18f2525", "p18f2525", "18f2525" }, 0x2525, 0, 0x80, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f2525.lkr" }, { PROC_CLASS_PIC16E, "__18F2539", { "pic18f2539", "p18f2539", "18f2539" }, 0x2539, 0, 0x80, 0xf000ff, { 0x6000, 0xefffff }, { 0x300000, 0x30000D }, "18f2539.lkr" }, { PROC_CLASS_PIC16E, "__18F2550", { "pic18f2550", "p18f2550", "18f2550" }, 0x2550, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f2550.lkr" }, { PROC_CLASS_PIC16E, "__18F25J50", { "pic18f25j50", "p18f25j50", "18f25j50" }, 0xd550, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18f25j50.lkr" }, { PROC_CLASS_PIC16E, "__18LF25J50",{ "pic18lf25j50","p18lf25j50","18lf25j50"}, 0xb551, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18lf25j50.lkr"}, { PROC_CLASS_PIC16E, "__18F2553", { "pic18f2553", "p18f2553", "18f2553" }, 0x2553, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f2553.lkr" }, { PROC_CLASS_PIC16E, "__18F258", { "pic18f258", "p18f258", "18f258" }, 0x8258, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f258.lkr" }, { PROC_CLASS_PIC16E, "__18F2580", { "pic18f2580", "p18f2580", "18f2580" }, 0x2580, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f2580.lkr" }, { PROC_CLASS_PIC16E, "__18F2585", { "pic18f2585", "p18f2585", "18f2585" }, 0x2585, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f2585.lkr" }, { PROC_CLASS_PIC16E, "__18F2610", { "pic18f2610", "p18f2610", "18f2610" }, 0x2610, 0, 0x80, 0xffff, { -1, -1 }, { 0x300000, 0x30000D }, "18f2610.lkr" }, { PROC_CLASS_PIC16E, "__18F26J11", { "pic18f26j11", "p18f26j11", "18f26j11" }, 0xd611, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18f26j11.lkr" }, { PROC_CLASS_PIC16E, "__18LF26J11",{ "pic18lf26j11","p18lf26j11","18lf26j11"}, 0xb612, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18lf26j11.lkr"}, { PROC_CLASS_PIC16E, "__18F2620", { "pic18f2620", "p18f2620", "18f2620" }, 0x2620, 0, 0x80, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f2620.lkr" }, { PROC_CLASS_PIC16E, "__18F26K20", { "pic18f26k20", "p18f26k20", "18f26k20" }, 0xd620, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f26k20.lkr" }, { PROC_CLASS_PIC16E, "__18F26J50", { "pic18f26j50", "p18f26j50", "18f26j50" }, 0xd650, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18f26j50.lkr" }, { PROC_CLASS_PIC16E, "__18LF26J50",{ "pic18lf26j50","p18lf26j50","18lf26j50"}, 0xb651, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18lf26j50.lkr"}, { PROC_CLASS_PIC16E, "__18F2680", { "pic18f2680", "p18f2680", "18f2680" }, 0x2680, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f2680.lkr" }, { PROC_CLASS_PIC16E, "__18F2681", { "pic18f2681", "p18f2681", "18f2681" }, 0x2681, 0, 0x60, -1, { -1, -1 }, { -1, -1 }, "18f2681.lkr" }, { PROC_CLASS_PIC16E, "__18F2682", { "pic18f2682", "p18f2682", "18f2682" }, 0x2682, 0, 0x60, 0xf003ff, { 0x14000, 0xefffff }, { 0x300000, 0x30000D }, "18f2682.lkr" }, { PROC_CLASS_PIC16E, "__18F2685", { "pic18f2685", "p18f2685", "18f2685" }, 0x2685, 0, 0x60, 0xf003ff, { 0x18000, 0xefffff }, { 0x300000, 0x30000D }, "18f2685.lkr" }, { PROC_CLASS_PIC16E, "__18F4220", { "pic18f4220", "p18f4220", "18f4220" }, 0xa422, 0, 0x80, 0xf000ff, { 0x1000, 0xefffff }, { 0x300000, 0x30000D }, "18f4220.lkr" }, { PROC_CLASS_PIC16E, "__18F4221", { "pic18f4221", "p18f4221", "18f4221" }, 0x4221, 0, 0x80, 0xf000ff, { 0x1000, 0xefffff }, { 0x300000, 0x30000D }, "18f4221.lkr" }, { PROC_CLASS_PIC16E, "__18F4320", { "pic18f4320", "p18f4320", "18f4320" }, 0xa432, 0, 0x80, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f4320.lkr" }, { PROC_CLASS_PIC16E, "__18F43K20", { "pic18f43k20", "p18f43k20", "18f43k20" }, 0xe320, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f43k20.lkr" }, { PROC_CLASS_PIC16E, "__18F4321", { "pic18f4321", "p18f4321", "18f4321" }, 0x4321, 0, 0x80, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f4321.lkr" }, { PROC_CLASS_PIC16E, "__18F4331", { "pic18f4331", "p18f4331", "18f4331" }, 0x4331, 0, 0x60, 0xf000ff, { 0x2000, 0xefffff }, { 0x300000, 0x30000D }, "18f4331.lkr" }, { PROC_CLASS_PIC16E, "__18F4410", { "pic18f4410", "p18f4410", "18f4410" }, 0x4410, 0, 0x80, 0x3fff, { -1, -1 }, { 0x300000, 0x30000D }, "18f4410.lkr" }, { PROC_CLASS_PIC16E, "__18F44J10", { "pic18f44j10", "p18f44j10", "18f44j10" }, 0xe410, 0, 0x80, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFD }, "18f44j10.lkr" }, { PROC_CLASS_PIC16E, "__18F44J11", { "pic18f44j11", "p18f44j11", "18f44j11" }, 0xe411, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18f44j11.lkr" }, { PROC_CLASS_PIC16E, "__18LF44J11",{ "pic18lf44j11","p18lf44j11","18lf44j11"}, 0xc411, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18lf44j11.lkr"}, { PROC_CLASS_PIC16E, "__18C442", { "pic18c442", "p18c442", "18c442" }, 0x8442, 0, 0x80, 0x3fff, { -1, -1 }, { 0x300000, 0x300006 }, "18c442.lkr" }, { PROC_CLASS_PIC16E, "__18F442", { "pic18f442", "p18f442", "18f442" }, 0x442f, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f442.lkr" }, { PROC_CLASS_PIC16E, "__18F4420", { "pic18f4420", "p18f4420", "18f4420" }, 0x4420, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f4420.lkr" }, { PROC_CLASS_PIC16E, "__18F44K20", { "pic18f44k20", "p18f44k20", "18f44k20" }, 0xe420, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f44k20.lkr" }, { PROC_CLASS_PIC16E, "__18F4423", { "pic18f4423", "p18f4423", "18f4423" }, 0x4423, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f4423.lkr" }, { PROC_CLASS_PIC16E, "__18F4431", { "pic18f4431", "p18f4431", "18f4431" }, 0x4431, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f4431.lkr" }, { PROC_CLASS_PIC16E, "__18F4439", { "pic18f4439", "p18f4439", "18f4439" }, 0x4439, 0, 0x80, 0xf000ff, { 0x3000, 0xefffff }, { 0x300000, 0x30000D }, "18f4439.lkr" }, { PROC_CLASS_PIC16E, "__18F4450", { "pic18f4450", "p18f4450", "18f4450" }, 0x4450, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f4450.lkr" }, { PROC_CLASS_PIC16E, "__18F44J50", { "pic18f44j50", "p18f44j50", "18f44j50" }, 0xe450, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18f44j50.lkr" }, { PROC_CLASS_PIC16E, "__18LF44J50",{ "pic18lf44j50","p18lf44j50","18lf44j50"}, 0xc450, 0, 0x60, 0x3ff7, { -1, -1 }, { 0x3FF8, 0x3FFF }, "18lf44j50.lkr"}, { PROC_CLASS_PIC16E, "__18F4455", { "pic18f4455", "p18f4455", "18f4455" }, 0x4455, 0, 0x60, 0xf000ff, { 0x6000, 0xefffff }, { 0x300000, 0x30000D }, "18f4455.lkr" }, { PROC_CLASS_PIC16E, "__18F4458", { "pic18f4458", "p18f4458", "18f4458" }, 0x4458, 0, 0x60, 0xf000ff, { 0x6000, 0xefffff }, { 0x300000, 0x30000D }, "18f4458.lkr" }, { PROC_CLASS_PIC16E, "__18F448", { "pic18f448", "p18f448", "18f448" }, 0x8448, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f448.lkr" }, { PROC_CLASS_PIC16E, "__18F4480", { "pic18f4480", "p18f4480", "18f4480" }, 0x4480, 0, 0x60, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "18f4480.lkr" }, { PROC_CLASS_PIC16E, "__18F4510", { "pic18f4510", "p18f4510", "18f4510" }, 0x4510, 0, 0x80, 0x7fff, { -1, -1 }, { 0x300000, 0x30000D }, "18f4510.lkr" }, { PROC_CLASS_PIC16E, "__18F45J10", { "pic18f45j10", "p18f45j10", "18f45j10" }, 0xe510, 0, 0x80, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f45j10.lkr" }, { PROC_CLASS_PIC16E, "__18F45J11", { "pic18f45j11", "p18f45j11", "18f45j11" }, 0xe511, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18f45j11.lkr" }, { PROC_CLASS_PIC16E, "__18LF45J11",{ "pic18lf45j11","p18lf45j11","18lf45j11"}, 0xc511, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18lf45j11.lkr"}, { PROC_CLASS_PIC16E, "__18F4515", { "pic18f4515", "p18f4515", "18f4515" }, 0x4515, 0, 0x80, 0xbfff, { -1, -1 }, { 0x300000, 0x30000D }, "18f4515.lkr" }, { PROC_CLASS_PIC16E, "__18C452", { "pic18c452", "p18c452", "18c452" }, 0x8452, 0, 0x80, 0x7fff, { -1, -1 }, { 0x300000, 0x300006 }, "18c452.lkr" }, { PROC_CLASS_PIC16E, "__18F452", { "pic18f452", "p18f452", "18f452" }, 0x452f, 0, 0x80, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f452.lkr" }, { PROC_CLASS_PIC16E, "__18F4520", { "pic18f4520", "p18f4520", "18f4520" }, 0x4520, 0, 0x80, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f4520.lkr" }, { PROC_CLASS_PIC16E, "__18F45K20", { "pic18f45k20", "p18f45k20", "18f45k20" }, 0xe520, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f45k20.lkr" }, { PROC_CLASS_PIC16E, "__18F4523", { "pic18f4523", "p18f4523", "18f4523" }, 0x4523, 0, 0x80, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f4523.lkr" }, { PROC_CLASS_PIC16E, "__18F4525", { "pic18f4525", "p18f4525", "18f4525" }, 0x4525, 0, 0x80, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f4525.lkr" }, { PROC_CLASS_PIC16E, "__18F4539", { "pic18f4539", "p18f4539", "18f4539" }, 0x4539, 0, 0x80, 0xf000ff, { 0x6000, 0xefffff }, { 0x300000, 0x30000D }, "18f4539.lkr" }, { PROC_CLASS_PIC16E, "__18F4550", { "pic18f4550", "p18f4550", "18f4550" }, 0x4550, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f4550.lkr" }, { PROC_CLASS_PIC16E, "__18F45J50", { "pic18f45j50", "p18f45j50", "18f45j50" }, 0xe550, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18f45j50.lkr" }, { PROC_CLASS_PIC16E, "__18LF45J50",{ "pic18lf45j50","p18lf45j50","18lf45j50"}, 0xc551, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFF }, "18lf45j50.lkr"}, { PROC_CLASS_PIC16E, "__18F4553", { "pic18f4553", "p18f4553", "18f4553" }, 0x4553, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f4553.lkr" }, { PROC_CLASS_PIC16E, "__18F458", { "pic18f458", "p18f458", "18f458" }, 0x8458, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f458.lkr" }, { PROC_CLASS_PIC16E, "__18F4580", { "pic18f4580", "p18f4580", "18f4580" }, 0x4580, 0, 0x60, 0xf000ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f4580.lkr" }, { PROC_CLASS_PIC16E, "__18F4585", { "pic18f4585", "p18f4585", "18f4585" }, 0x4585, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f4585.lkr" }, { PROC_CLASS_PIC16E, "__18F4610", { "pic18f4610", "p18f4610", "18f4610" }, 0x4610, 0, 0x80, 0xffff, { -1, -1 }, { 0x300000, 0x30000D }, "18f4610.lkr" }, { PROC_CLASS_PIC16E, "__18F46J11", { "pic18f46j11", "p18f46j11", "18f46j11" }, 0xe611, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18f46j11.lkr" }, { PROC_CLASS_PIC16E, "__18LF46J11",{ "pic18lf46j11","p18lf46j11","18lf46j11"}, 0xc612, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18lf46j11.lkr"}, { PROC_CLASS_PIC16E, "__18F4620", { "pic18f4620", "p18f4620", "18f4620" }, 0x4620, 0, 0x80, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f4620.lkr" }, { PROC_CLASS_PIC16E, "__18F46K20", { "pic18f46k20", "p18f46k20", "18f46k20" }, 0xe620, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f46k20.lkr" }, { PROC_CLASS_PIC16E, "__18F46J50", { "pic18f46j50", "p18f46j50", "18f46j50" }, 0xe650, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18f46j50.lkr" }, { PROC_CLASS_PIC16E, "__18LF46J50",{ "pic18lf46j50","p18lf46j50","18lf46j50"}, 0xc651, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFF }, "18lf46j50.lkr"}, { PROC_CLASS_PIC16E, "__18F4680", { "pic18f4680", "p18f4680", "18f4680" }, 0x4680, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f4680.lkr" }, { PROC_CLASS_PIC16E, "__18F4681", { "pic18f4681", "p18f4681", "18f4681" }, 0x4681, 0, 0x60, -1, { -1, -1 }, { -1, -1 }, "18f4681.lkr" }, { PROC_CLASS_PIC16E, "__18F4682", { "pic18f4682", "p18f4682", "18f4682" }, 0x4682, 0, 0x60, 0xf003ff, { 0x14000, 0xefffff }, { 0x300000, 0x30000D }, "18f4682.lkr" }, { PROC_CLASS_PIC16E, "__18F4685", { "pic18f4685", "p18f4685", "18f4685" }, 0x4685, 0, 0x60, 0xf003ff, { 0x18000, 0xefffff }, { 0x300000, 0x30000D }, "18f4685.lkr" }, { PROC_CLASS_PIC16E, "__18C601", { "pic18c601", "p18c601", "18c601" }, 0x8601, 0, 0x80, 0x3ffff, { -1, -1 }, { 0x300000, 0x300006 }, "18c601.lkr" }, { PROC_CLASS_PIC16E, "__18F6310", { "pic18f6310", "p18f6310", "18f6310" }, 0x6310, 0, 0x60, 0x1fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f6310.lkr" }, { PROC_CLASS_PIC16E, "__18F63J11", { "pic18f63j11", "p18f63j11", "18f63j11" }, 0x6311, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FF8, 0x1FFD }, "18f63j11.lkr" }, { PROC_CLASS_PIC16E, "__18F6390", { "pic18f6390", "p18f6390", "18f6390" }, 0x6390, 0, 0x60, 0x1fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f6390.lkr" }, { PROC_CLASS_PIC16E, "__18F63J90", { "pic18f63j90", "p18f63j90", "18f63j90" }, 0xb390, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FF8, 0x1FFD }, "18f63j90.lkr" }, { PROC_CLASS_PIC16E, "__18F6393", { "pic18f6393", "p18f6393", "18f6393" }, 0x6393, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x300000, 0x30000C }, "18f6393.lkr" }, { PROC_CLASS_PIC16E, "__18F6410", { "pic18f6410", "p18f6410", "18f6410" }, 0x6410, 0, 0x60, 0x3fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f6410.lkr" }, { PROC_CLASS_PIC16E, "__18F64J11", { "pic18f64j11", "p18f64j11", "18f64j11" }, 0x6411, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x3FF8, 0x3FFD }, "18f64j11.lkr" }, { PROC_CLASS_PIC16E, "__18F64J15", { "pic18f64j15", "p18f64j15", "18f64j15" }, 0xb415, 0, 0x60, -1, { -1, -1 }, { -1, -1 }, "18f64j15.lkr" }, { PROC_CLASS_PIC16E, "__18F6490", { "pic18f6490", "p18f6490", "18f6490" }, 0x6490, 0, 0x60, 0x3fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f6490.lkr" }, { PROC_CLASS_PIC16E, "__18F64J90", { "pic18f64j90", "p18f64j90", "18f64j90" }, 0xb490, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x3FF8, 0x3FFD }, "18f64j90.lkr" }, { PROC_CLASS_PIC16E, "__18F6493", { "pic18f6493", "p18f6493", "18f6493" }, 0x6493, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x300000, 0x30000C }, "18f6493.lkr" }, { PROC_CLASS_PIC16E, "__18F65J10", { "pic18f65j10", "p18f65j10", "18f65j10" }, 0xb510, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f65j10.lkr" }, { PROC_CLASS_PIC16E, "__18F65J11", { "pic18f65j11", "p18f65j11", "18f65j11" }, 0x6511, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f65j11.lkr" }, { PROC_CLASS_PIC16E, "__18F65J15", { "pic18f65j15", "p18f65j15", "18f65j15" }, 0xb515, 0, 0x60, 0xbff7, { -1, -1 }, { 0xBFF8, 0xBFFD }, "18f65j15.lkr" }, { PROC_CLASS_PIC16E, "__18F6520", { "pic18f6520", "p18f6520", "18f6520" }, 0xa652, 0, 0x60, 0xf003ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f6520.lkr" }, { PROC_CLASS_PIC16E, "__18F6525", { "pic18f6525", "p18f6525", "18f6525" }, 0x6525, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f6525.lkr" }, { PROC_CLASS_PIC16E, "__18F6527", { "pic18f6527", "p18f6527", "18f6527" }, 0x6527, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f6527.lkr" }, { PROC_CLASS_PIC16E, "__18F65J50", { "pic18f65j50", "p18f65j50", "18f65j50" }, 0xb550, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f65j50.lkr" }, { PROC_CLASS_PIC16E, "__18C658", { "pic18c658", "p18c658", "18c658" }, 0x8658, 0, 0x60, 0x7fff, { -1, -1 }, { 0x300000, 0x300006 }, "18c658.lkr" }, { PROC_CLASS_PIC16E, "__18F6585", { "pic18f6585", "p18f6585", "18f6585" }, 0x6585, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f6585.lkr" }, { PROC_CLASS_PIC16E, "__18F65J90", { "pic18f65j90", "p18f65j90", "18f65j90" }, 0xb590, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f65j90.lkr" }, { PROC_CLASS_PIC16E, "__18F66J10", { "pic18f66j10", "p18f66j10", "18f66j10" }, 0xb610, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f66j10.lkr" }, { PROC_CLASS_PIC16E, "__18F66J11", { "pic18f66j11", "p18f66j11", "18f66j11" }, 0xb611, 0, 0x60, 0x1fffff, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f66j11.lkr" }, { PROC_CLASS_PIC16E, "__18F66J15", { "pic18f66j15", "p18f66j15", "18f66j15" }, 0xb615, 0, 0x60, 0x17ff7, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f66j15.lkr" }, { PROC_CLASS_PIC16E, "__18F66J16", { "pic18f66j16", "p18f66j16", "18f66j16" }, 0xb616, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f66j16.lkr" }, { PROC_CLASS_PIC16E, "__18F6620", { "pic18f6620", "p18f6620", "18f6620" }, 0xa662, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f6620.lkr" }, { PROC_CLASS_PIC16E, "__18F6621", { "pic18f6621", "p18f6621", "18f6621" }, 0xa621, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f6621.lkr" }, { PROC_CLASS_PIC16E, "__18F6622", { "pic18f6622", "p18f6622", "18f6622" }, 0xf622, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f6622.lkr" }, { PROC_CLASS_PIC16E, "__18F6627", { "pic18f6627", "p18f6627", "18f6627" }, 0xf625, 0, 0x60, 0xf003ff, { 0x18000, 0xefffff }, { 0x300000, 0x30000D }, "18f6627.lkr" }, { PROC_CLASS_PIC16E, "__18F6628", { "pic18f6628", "p18f6628", "18f6628" }, 0xa628, 0, 0x60, 0xf003ff, { 0x18000, 0xefffff }, { 0x300000, 0x30000D }, "18f6628.lkr" }, { PROC_CLASS_PIC16E, "__18F66J50", { "pic18f66j50", "p18f66j50", "18f66j50" }, 0xb650, 0, 0x60, 0x1fffff, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f66j50.lkr" }, { PROC_CLASS_PIC16E, "__18F66J55", { "pic18f66j55", "p18f66j55", "18f66j55" }, 0xb655, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f66j55.lkr" }, { PROC_CLASS_PIC16E, "__18F66J60", { "pic18f66j60", "p18f66j60", "18f66j60" }, 0xb660, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f66j60.lkr" }, { PROC_CLASS_PIC16E, "__18F66J65", { "pic18f66j65", "p18f66j65", "18f66j65" }, 0xb665, 0, 0x60, 0x17ff7, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f66j65.lkr" }, { PROC_CLASS_PIC16E, "__18F6680", { "pic18f6680", "p18f6680", "18f6680" }, 0x6680, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f6680.lkr" }, { PROC_CLASS_PIC16E, "__18F66J90", { "pic18f66j90", "p18f66j90", "18f66j90" }, 0xb690, 0, 0x60, 0x1fffff, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f66j90.lkr" }, { PROC_CLASS_PIC16E, "__18F67J10", { "pic18f67j10", "p18f67j10", "18f67j10" }, 0xb710, 0, 0x60, 0x1fff7, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f67j10.lkr" }, { PROC_CLASS_PIC16E, "__18F67J11", { "pic18f67j11", "p18f67j11", "18f67j11" }, 0xb711, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f67j11.lkr" }, { PROC_CLASS_PIC16E, "__18F6720", { "pic18f6720", "p18f6720", "18f6720" }, 0xa672, 0, 0x60, 0xf003ff, { 0x20000, 0xefffff }, { 0x300000, 0x30000D }, "18f6720.lkr" }, { PROC_CLASS_PIC16E, "__18F6722", { "pic18f6722", "p18f6722", "18f6722" }, 0x6721, 0, 0x60, 0xf003ff, { 0x20000, 0xefffff }, { 0x300000, 0x30000D }, "18f6722.lkr" }, { PROC_CLASS_PIC16E, "__18F6723", { "pic18f6723", "p18f6723", "18f6723" }, 0x6723, 0, 0x60, 0xf003ff, { 0x20000, 0xefffff }, { 0x300000, 0x30000D }, "18f6723.lkr" }, { PROC_CLASS_PIC16E, "__18F67J50", { "pic18f67j50", "p18f67j50", "18f67j50" }, 0xb750, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f67j50.lkr" }, { PROC_CLASS_PIC16E, "__18F67J60", { "pic18f67j60", "p18f67j60", "18f67j60" }, 0xb760, 0, 0x60, 0x1fff7, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f67j60.lkr" }, { PROC_CLASS_PIC16E, "__18F67J90", { "pic18f67j90", "p18f67j90", "18f67j90" }, 0x6790, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f67j90.lkr" }, { PROC_CLASS_PIC16E, "__18C801", { "pic18c801", "p18c801", "18c801" }, 0x8801, 0, 0x80, 0x1fffff, { -1, -1 }, { 0x300000, 0x300006 }, "18c801.lkr" }, { PROC_CLASS_PIC16E, "__18F8310", { "pic18f8310", "p18f8310", "18f8310" }, 0x8310, 0, 0x60, 0x1fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f8310.lkr" }, { PROC_CLASS_PIC16E, "__18F83J11", { "pic18f83j11", "p18f83j11", "18f83j11" }, 0x8311, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FF8, 0x1FFD }, "18f83j11.lkr" }, { PROC_CLASS_PIC16E, "__18F8390", { "pic18f8390", "p18f8390", "18f8390" }, 0x8390, 0, 0x60, 0x1fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f8390.lkr" }, { PROC_CLASS_PIC16E, "__18F83J90", { "pic18f83j90", "p18f83j90", "18f83j90" }, 0xc390, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FF8, 0x1FFD }, "18f83j90.lkr" }, { PROC_CLASS_PIC16E, "__18F8393", { "pic18f8393", "p18f8393", "18f8393" }, 0x8393, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x300000, 0x30000C }, "18f8393.lkr" }, { PROC_CLASS_PIC16E, "__18F8410", { "pic18f8410", "p18f8410", "18f8410" }, 0x8410, 0, 0x60, 0x3fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f8410.lkr" }, { PROC_CLASS_PIC16E, "__18F84J11", { "pic18f84j11", "p18f84j11", "18f84j11" }, 0x8411, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x3FF8, 0x3FFD }, "18f84j11.lkr" }, { PROC_CLASS_PIC16E, "__18F84J15", { "pic18f84j15", "p18f84j15", "18f84j15" }, 0xc415, 0, 0x60, -1, { -1, -1 }, { -1, -1 }, "18f84j15.lkr" }, { PROC_CLASS_PIC16E, "__18F8490", { "pic18f8490", "p18f8490", "18f8490" }, 0x8490, 0, 0x60, 0x3fff, { -1, -1 }, { 0x300000, 0x30000C }, "18f8490.lkr" }, { PROC_CLASS_PIC16E, "__18F84J90", { "pic18f84j90", "p18f84j90", "18f84j90" }, 0xc490, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x3FF8, 0x3FFD }, "18f84j90.lkr" }, { PROC_CLASS_PIC16E, "__18F8493", { "pic18f8493", "p18f8493", "18f8493" }, 0x8493, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x300000, 0x30000C }, "18f8493.lkr" }, { PROC_CLASS_PIC16E, "__18F85J10", { "pic18f85j10", "p18f85j10", "18f85j10" }, 0xc510, 0, 0x60, 0x7ff7, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f85j10.lkr" }, { PROC_CLASS_PIC16E, "__18F85J11", { "pic18f85j11", "p18f85j11", "18f85j11" }, 0x8511, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f85j11.lkr" }, { PROC_CLASS_PIC16E, "__18F85J15", { "pic18f85j15", "p18f85j15", "18f85j15" }, 0xc515, 0, 0x60, 0xbff7, { -1, -1 }, { 0xBFF8, 0xBFFD }, "18f85j15.lkr" }, { PROC_CLASS_PIC16E, "__18F8520", { "pic18f8520", "p18f8520", "18f8520" }, 0xa852, 0, 0x60, 0xf003ff, { 0x8000, 0xefffff }, { 0x300000, 0x30000D }, "18f8520.lkr" }, { PROC_CLASS_PIC16E, "__18F8525", { "pic18f8525", "p18f8525", "18f8525" }, 0x8525, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f8525.lkr" }, { PROC_CLASS_PIC16E, "__18F8527", { "pic18f8527", "p18f8527", "18f8527" }, 0x8527, 0, 0x60, 0xf003ff, { 0x200000, 0xefffff },{ 0x300000, 0x30000D }, "18f8527.lkr" }, { PROC_CLASS_PIC16E, "__18F85J50", { "pic18f85j50", "p18f85j50", "18f85j50" }, 0xc550, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f85j50.lkr" }, { PROC_CLASS_PIC16E, "__18C858", { "pic18c858", "p18c858", "18c858" }, 0x8858, 0, 0x60, 0x7fff, { -1, -1 }, { 0x300000, 0x300006 }, "18c858.lkr" }, { PROC_CLASS_PIC16E, "__18F8585", { "pic18f8585", "p18f8585", "18f8585" }, 0x8585, 0, 0x60, 0xf003ff, { 0xc000, 0xefffff }, { 0x300000, 0x30000D }, "18f8585.lkr" }, { PROC_CLASS_PIC16E, "__18F85J90", { "pic18f85j90", "p18f85j90", "18f85j90" }, 0xc590, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x7FF8, 0x7FFD }, "18f85j90.lkr" }, { PROC_CLASS_PIC16E, "__18F86J10", { "pic18f86j10", "p18f86j10", "18f86j10" }, 0xc610, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f86j10.lkr" }, { PROC_CLASS_PIC16E, "__18F86J11", { "pic18f86j11", "p18f86j11", "18f86j11" }, 0xc611, 0, 0x60, 0x1fffff, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f86j11.lkr" }, { PROC_CLASS_PIC16E, "__18F86J15", { "pic18f86j15", "p18f86j15", "18f86j15" }, 0xc615, 0, 0x60, 0x17ff7, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f86j15.lkr" }, { PROC_CLASS_PIC16E, "__18F86J16", { "pic18f86j16", "p18f86j16", "18f86j16" }, 0xc616, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f86j16.lkr" }, { PROC_CLASS_PIC16E, "__18F8620", { "pic18f8620", "p18f8620", "18f8620" }, 0xa862, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f8620.lkr" }, { PROC_CLASS_PIC16E, "__18F8621", { "pic18f8621", "p18f8621", "18f8621" }, 0x8621, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f8621.lkr" }, { PROC_CLASS_PIC16E, "__18F8622", { "pic18f8622", "p18f8622", "18f8622" }, 0x8622, 0, 0x60, 0xf003ff, { 0x200000, 0xefffff },{ 0x300000, 0x30000D }, "18f8622.lkr" }, { PROC_CLASS_PIC16E, "__18F8627", { "pic18f8627", "p18f8627", "18f8627" }, 0x8625, 0, 0x60, 0xf003ff, { 0x18000, 0xefffff }, { 0x300000, 0x30000D }, "18f8627.lkr" }, { PROC_CLASS_PIC16E, "__18F8628", { "pic18f8628", "p18f8628", "18f8628" }, 0x8628, 0, 0x60, 0xf003ff, { 0x200000, 0xefffff },{ 0x300000, 0x30000D }, "18f8628.lkr" }, { PROC_CLASS_PIC16E, "__18F86J50", { "pic18f86j50", "p18f86j50", "18f86j50" }, 0xc650, 0, 0x60, 0x1fffff, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f86j50.lkr" }, { PROC_CLASS_PIC16E, "__18F86J55", { "pic18f86j55", "p18f86j55", "18f86j55" }, 0xc655, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f86j55.lkr" }, { PROC_CLASS_PIC16E, "__18F86J60", { "pic18f86j60", "p18f86j60", "18f86j60" }, 0xc660, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f86j60.lkr" }, { PROC_CLASS_PIC16E, "__18F86J65", { "pic18f86j65", "p18f86j65", "18f86j65" }, 0xc665, 0, 0x60, 0x17ff7, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f86j65.lkr" }, { PROC_CLASS_PIC16E, "__18F8680", { "pic18f8680", "p18f8680", "18f8680" }, 0x8680, 0, 0x60, 0xf003ff, { 0x10000, 0xefffff }, { 0x300000, 0x30000D }, "18f8680.lkr" }, { PROC_CLASS_PIC16E, "__18F86J90", { "pic18f86j90", "p18f86j90", "18f86j90" }, 0x8690, 0, 0x60, 0x1fffff, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f86j90.lkr" }, { PROC_CLASS_PIC16E, "__18F87J10", { "pic18f87j10", "p18f87j10", "18f87j10" }, 0xc710, 0, 0x60, 0x1fff7, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f87j10.lkr" }, { PROC_CLASS_PIC16E, "__18F87J11", { "pic18f87j11", "p18f87j11", "18f87j11" }, 0xc711, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f87j11.lkr" }, { PROC_CLASS_PIC16E, "__18F8720", { "pic18f8720", "p18f8720", "18f8720" }, 0xa872, 0, 0x60, 0xf003ff, { 0x20000, 0xefffff }, { 0x300000, 0x30000D }, "18f8720.lkr" }, { PROC_CLASS_PIC16E, "__18F8722", { "pic18f8722", "p18f8722", "18f8722" }, 0x8721, 0, 0x60, 0xf003ff, { 0x20000, 0xefffff }, { 0x300000, 0x30000D }, "18f8722.lkr" }, { PROC_CLASS_PIC16E, "__18F8723", { "pic18f8723", "p18f8723", "18f8723" }, 0x8723, 0, 0x60, 0xf003ff, { 0x200000, 0xefffff },{ 0x300000, 0x30000D }, "18f8723.lkr" }, { PROC_CLASS_PIC16E, "__18F87J50", { "pic18f87j50", "p18f87j50", "18f87j50" }, 0xc750, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f87j50.lkr" }, { PROC_CLASS_PIC16E, "__18F87J60", { "pic18f87j60", "p18f87j60", "18f87j60" }, 0xc760, 0, 0x60, 0x1fff7, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f87j60.lkr" }, { PROC_CLASS_PIC16E, "__18F87J90", { "pic18f87j90", "p18f87j90", "18f87j90" }, 0x8790, 0, 0x60, 0x1fffff, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f87j90.lkr" }, { PROC_CLASS_PIC16E, "__18F96J60", { "pic18f96j60", "p18f96j60", "18f96j60" }, 0xd660, 0, 0x60, 0xfff7, { -1, -1 }, { 0xFFF8, 0xFFFD }, "18f96j60.lkr" }, { PROC_CLASS_PIC16E, "__18F96J65", { "pic18f96j65", "p18f96j65", "18f96j65" }, 0xd665, 0, 0x60, 0x17ff7, { -1, -1 }, { 0x17FF8, 0x17FFD }, "18f96j65.lkr" }, { PROC_CLASS_PIC16E, "__18F97J60", { "pic18f97j60", "p18f97j60", "18f97j60" }, 0xd760, 0, 0x60, 0x1fff7, { -1, -1 }, { 0x1FFF8, 0x1FFFD }, "18f97j60.lkr" }, { PROC_CLASS_PIC16E, "__PS500", { "ps500", "ps500", "ps500" }, 0x0500, 0, 0x80, 0xf000ff, { 0x4000, 0xefffff }, { 0x300000, 0x30000D }, "ps500.lkr" }, { PROC_CLASS_PIC16E, "__PS810", { "ps810", "ps810", "ps810" }, 0x0810, 0, 0x80, 0x1fff, { -1, -1 }, { 0x300000, 0x30000D }, "ps810.lkr" }, { PROC_CLASS_PIC12, "__RF509AF", { "rf509af", "rf509af", "rf509af" }, 0x6509, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "rf509af.lkr" }, { PROC_CLASS_PIC12, "__RF509AG", { "rf509ag", "rf509ag", "rf509ag" }, 0x7509, 2, 4, 0x3ff, { -1, -1 }, { 0xFFF, 0xFFF }, "rf509ag.lkr" }, { PROC_CLASS_PIC14, "__RF675F", { "rf675f", "rf675f", "rf675f" }, 0x3675, 1, 2, 0x3fe, { -1, -1 }, { 0x2007, 0x2007 }, "rf675f.lkr" }, { PROC_CLASS_PIC14, "__RF675H", { "rf675h", "rf675h", "rf675h" }, 0x4675, 1, 2, 0x3fe, { -1, -1 }, { 0x2007, 0x2007 }, "rf675h.lkr" }, { PROC_CLASS_PIC14, "__RF675K", { "rf675k", "rf675k", "rf675k" }, 0x5675, 1, 2, 0x3fe, { -1, -1 }, { 0x2007, 0x2007 }, "rf675k.lkr" }, { PROC_CLASS_SX, "__SX18", { "sx18ac", "sx18", "sx18" }, 0x0018, 0, 0, 0x7ff, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_SX, "__SX20", { "sx20ac", "sx20", "sx20" }, 0x0020, 0, 0, 0x7ff, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_SX, "__SX28", { "sx28ac", "sx28", "sx28" }, 0x0028, 0, 0, 0x7ff, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_SX, "__SX48", { "sx48bd", "sx48", "sx48" }, 0x0048, 0, 0, 0xfff, { -1, -1 }, { -1, -1 }, NULL }, { PROC_CLASS_SX, "__SX52", { "sx52bd", "sx52", "sx52" }, 0x0052, 0, 0, 0xfff, { -1, -1 }, { -1, -1 }, NULL }, }; #define NUM_PICS (sizeof(pics) / sizeof(pics[0])) /* * Display a list of the processor names */ void gp_dump_processor_list(gp_boolean list_all, enum proc_class class) { #define COLUMNS 6 #define SPACE_BETWEEN 2 /* number of chars between columns */ #define FAVORITE 1 /* there are 3 names to choose from */ int i; int j; int length; int num = 0; int longest = 0; for(i = 0; i < NUM_PICS; i++) { length = strlen(pics[i].names[FAVORITE]); if (length > longest) longest = length; } for(i = 0; i < NUM_PICS; i++) { if (list_all || (pics[i].class == class)) { num++; printf("%s", pics[i].names[FAVORITE]); length = longest + SPACE_BETWEEN - strlen(pics[i].names[FAVORITE]); for(j = 0; j < length; j++) { putchar(' '); } if ((num % COLUMNS) == 0) { putchar('\n'); } } } if ((num % COLUMNS) != 0) { putchar('\n'); } } struct px * gp_find_processor(char *name) { int i, j; for (i = 0; i < NUM_PICS; i++) { for (j = 0; (j < MAX_NAMES) && (pics[i].names[j] != NULL); j++) { if (strcasecmp(name, pics[i].names[j]) == 0) { return &pics[i]; } } } return NULL; } enum proc_class gp_processor_class(pic_processor_t processor) { if (processor) return processor->class; return PROC_CLASS_UNKNOWN; } /* 18xx bsr boundary location */ int gp_processor_bsr_boundary(pic_processor_t processor) { assert(processor && processor->class == PROC_CLASS_PIC16E); return processor->num_banks; } unsigned long gp_processor_coff_type(pic_processor_t processor) { if (processor) return processor->coff_type; return 0; } int gp_processor_num_pages(pic_processor_t processor) { if (processor) return processor->num_pages; return 0; } int gp_processor_num_banks(pic_processor_t processor) { if (processor && processor->class != PROC_CLASS_PIC16E) return processor->num_banks; return 0; } pic_processor_t gp_processor_coff_proc(unsigned long coff_type) { int i; pic_processor_t processor = no_processor; for (i = 0; i < NUM_PICS; i++) { if (pics[i].coff_type == coff_type) { processor = &pics[i]; break; } } return processor; } char * gp_processor_name(pic_processor_t processor, unsigned int choice) { assert(!(choice > MAX_NAMES - 1)); if (processor) return processor->names[choice]; return NULL; } char * gp_processor_coff_name(unsigned long coff_type, unsigned int choice) { int i; if (coff_type == 0) return NULL; assert(!(choice > MAX_NAMES - 1)); for (i = 0; i < NUM_PICS; i++) { if (pics[i].coff_type == coff_type) { return pics[i].names[choice]; } } return NULL; } char * gp_processor_script(pic_processor_t processor) { if (processor) return processor->script; return NULL; } int gp_processor_rom_width(enum proc_class class) { int rom_width; switch (class) { case PROC_CLASS_GENERIC: case PROC_CLASS_PIC12: case PROC_CLASS_SX: rom_width = 12; break; case PROC_CLASS_PIC14: rom_width = 14; break; case PROC_CLASS_PIC16: case PROC_CLASS_EEPROM16: rom_width = 16; break; case PROC_CLASS_PIC16E: case PROC_CLASS_EEPROM8: rom_width = 8; break; default: assert(0); } return rom_width; } /* determine which page of program memory the address is located */ int gp_processor_check_page(enum proc_class class, int address) { int page; switch (class) { case PROC_CLASS_EEPROM8: case PROC_CLASS_EEPROM16: assert(0); break; case PROC_CLASS_GENERIC: case PROC_CLASS_PIC12: case PROC_CLASS_SX: if (address < 0x200) { page = 0; } else if (address < 0x400) { page = 1; } else if (address < 0x600) { page = 2; } else { page = 3; } break; case PROC_CLASS_PIC14: if (address < 0x800) { page = 0; } else if (address < 0x1000) { page = 1; } else if (address < 0x1800) { page = 2; } else { page = 3; } break; case PROC_CLASS_PIC16: page = (address >> 8) & 0xff; break; case PROC_CLASS_PIC16E: default: assert(0); } return page; } /* determine which bank of data memory the address is located */ int gp_processor_check_bank(enum proc_class class, int address) { int bank; switch (class) { case PROC_CLASS_EEPROM8: case PROC_CLASS_EEPROM16: assert(0); break; case PROC_CLASS_GENERIC: case PROC_CLASS_PIC12: case PROC_CLASS_SX: bank = (address >> 5) & 0x3; break; case PROC_CLASS_PIC14: bank = (address >> 7) & 0x3; break; case PROC_CLASS_PIC16: case PROC_CLASS_PIC16E: bank = (address >> 8) & 0xff; break; default: assert(0); } return bank; } /* Set the page bits, return the number of instructions required. */ int gp_processor_set_page(enum proc_class class, int num_pages, int page, MemBlock *m, int address, int use_wreg) { unsigned int data; int bcf_insn; int bsf_insn; int movlw_insn; int movwf_insn; int location; int page0; int page1; int count = 2; if ((class == PROC_CLASS_EEPROM8) || (class == PROC_CLASS_EEPROM16) || (class == PROC_CLASS_PIC16E)) { assert(0); } else if (class == PROC_CLASS_PIC16) { /* movlw */ data = MEM_USED_MASK | (0xb000 | (page & 0xff)); i_memory_put(m, address, data); /* movwf 0x3 */ data = MEM_USED_MASK | 0x0100 | 0x3; i_memory_put(m, address + 1, data); } else { if (num_pages == 1) { return 0; } if (class == PROC_CLASS_PIC14) { bcf_insn = MEM_USED_MASK | 0x1000; bsf_insn = MEM_USED_MASK | 0x1400; movlw_insn = MEM_USED_MASK | 0x3000; movwf_insn = MEM_USED_MASK | 0x0080; location = 0xa; page0 = 3 << 7; page1 = 4 << 7; } else { bcf_insn = MEM_USED_MASK | 0x400; bsf_insn = MEM_USED_MASK | 0x500; movlw_insn = MEM_USED_MASK | 0xc00; movwf_insn = MEM_USED_MASK | 0x020; location = 0x3; page0 = 5 << 5; page1 = 6 << 5; } if (use_wreg) { data = movlw_insn | page; i_memory_put(m, address, data); data = movwf_insn | location; i_memory_put(m, address + 1, data); } else { /* page low bit */ data = (page & 1 ? bsf_insn : bcf_insn) | page0 | location; i_memory_put(m, address, data); /* page high bit */ if (num_pages == 4) { data = (page & 2 ? bsf_insn : bcf_insn) | page1 | location; i_memory_put(m, address + 1, data); } if (num_pages == 2) { count = 1; } else { count = 2; } } } return count; } /* Set the bank bits, return the number of instructions required. */ int gp_processor_set_bank(enum proc_class class, int num_banks, int bank, MemBlock *m, int address) { unsigned int data; int bcf_insn; int bsf_insn; int location; int bank0; int bank1; int count; if (class == PROC_CLASS_EEPROM8 || class == PROC_CLASS_EEPROM16) { assert(0); } else if (class == PROC_CLASS_PIC16E) { /* movlb bank */ data = MEM_USED_MASK | 0x0100 | (bank & 0xff); i_memory_put(m, address, data); count = 1; } else if (class == PROC_CLASS_PIC16) { /* movlb bank */ data = MEM_USED_MASK | 0xb800 | (bank & 0xff); i_memory_put(m, address, data); count = 1; } else { if (num_banks == 1) { return 0; } if (class == PROC_CLASS_PIC14) { bcf_insn = MEM_USED_MASK | 0x1000; bsf_insn = MEM_USED_MASK | 0x1400; location = 0x3; bank0 = 5 << 7; bank1 = 6 << 7; } else { bcf_insn = MEM_USED_MASK | 0x400; bsf_insn = MEM_USED_MASK | 0x500; location = 0x4; bank0 = 5 << 5; bank1 = 6 << 5; } switch(bank) { case 0: /* bcf location, bank0 */ data = bcf_insn | bank0 | location; i_memory_put(m, address, data); if (num_banks == 4) { /* bcf location, bank1 */ data = bcf_insn | bank1 | location; i_memory_put(m, address + 1, data); } break; case 1: /* bsf location, bank0 */ data = bsf_insn | bank0 | location; i_memory_put(m, address, data); if (num_banks == 4) { /* bcf location, bank1 */ data = bcf_insn | bank1 | location; i_memory_put(m, address + 1, data); } break; case 2: /* bcf location, bank0 */ data = bcf_insn | bank0 | location; i_memory_put(m, address, data); if (num_banks == 4) { /* bsf location, bank1 */ data = bsf_insn | bank1 | location; i_memory_put(m, address + 1, data); } break; case 3: /* bcf location, bank0 */ data = bsf_insn | bank0 | location; i_memory_put(m, address, data); if (num_banks == 4) { /* bcf location, bank1 */ data = bsf_insn | bank1 | location; i_memory_put(m, address + 1, data); } break; default: assert(0); break; } if (num_banks == 2) { count = 1; } else { count = 2; } } return count; } /* determine the value for retlw */ int gp_processor_retlw(enum proc_class class) { int insn; switch(class) { case PROC_CLASS_PIC12: case PROC_CLASS_SX: insn = 0x800; break; case PROC_CLASS_PIC14: insn = 0x3400; break; case PROC_CLASS_PIC16: insn = 0xb600; break; case PROC_CLASS_PIC16E: insn = 0x0c00; break; default: assert(0); } return insn; } gputils-0.13.7/libgputils/gpcod.c0000644000175000017500000000535111156313233013632 00000000000000/* .cod file support Copyright (C) 2003, 2004, 2005 Craig Franklin This file is part of gputils. gputils is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. gputils is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with gputils; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "stdhdr.h" #include "libgputils.h" /* copy a string to a cod block using the pascal convention, i.e. the string length occupies the first string location */ void gp_cod_strncpy(char *dest, char *src, int max_len) { *(dest-1) = ( (max_len>strlen(src)) ? strlen(src) : max_len ); strncpy(dest, src, *(dest-1)); } /* gp_cod_clear - write zeroes to a code block, unless the code block ptr is null. */ void gp_cod_clear(Block *b) { int i; if(b && b->block) for(i=0; iblock[i] = 0; else assert(0); } void gp_cod_delete(Block *b) { if(b && b->block) { free(b->block); b->block = NULL; } else assert(0); } void gp_cod_next(Block *b, int *block_number) { assert(b != NULL); gp_cod_clear(b); b->block_number = *block_number; *block_number = *block_number + 1; } void gp_cod_create(Block *b, int *block_number) { assert(b != NULL); b->block = malloc(COD_BLOCK_SIZE); gp_cod_clear(b); b->block_number = *block_number; *block_number = *block_number + 1; } void gp_cod_date(char *buffer, size_t sizeof_buffer) { #define TEMP_SIZE 32 char temp[TEMP_SIZE]; int i; time_t now; struct tm *now_tm; static const char mon_name[12][4] = { "Jan\0", "Feb\0", "Mar\0", "Apr\0", "May\0", "Jun\0", "Jul\0", "Aug\0", "Sep\0", "Oct\0", "Nov\0", "Dec\0" }; time(&now); now_tm = localtime(&now); snprintf(temp, TEMP_SIZE, "%02d%3s%02d", now_tm->tm_mday, &mon_name[now_tm->tm_mon][0], now_tm->tm_year % 100); /* copy the temporary buffer to the output */ for (i = 0; i < sizeof_buffer; i++) { *buffer++ = temp[i]; } return; } void gp_cod_time(char *buffer, size_t sizeof_buffer) { time_t now; struct tm *now_tm; int value; time(&now); now_tm = localtime(&now); value = ((now_tm->tm_hour) * 100) + now_tm->tm_min; buffer[0] = value & 0xff; buffer[1] = (value >> 8) & 0xff; buffer[2] = now_tm->tm_sec & 0xff; return; } gputils-0.13.7/install-sh0000755000175000017500000002176611156313233012230 00000000000000#!/bin/sh # install - install a program, script, or datafile scriptversion=2004-09-10.20 # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the # following copyright and license. # # Copyright (C) 1994 X Consortium # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to # deal in the Software without restriction, including without limitation the # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or # sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN # AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- # TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # Except as contained in this notice, the name of the X Consortium shall not # be used in advertising or otherwise to promote the sale, use or other deal- # ings in this Software without prior written authorization from the X Consor- # tium. # # # FSF changes to this file are in the public domain. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. It can only install one file at a time, a restriction # shared with many OS's install programs. # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit="${DOITPROG-}" # put in absolute paths if you don't have them in your path; or use env. vars. mvprog="${MVPROG-mv}" cpprog="${CPPROG-cp}" chmodprog="${CHMODPROG-chmod}" chownprog="${CHOWNPROG-chown}" chgrpprog="${CHGRPPROG-chgrp}" stripprog="${STRIPPROG-strip}" rmprog="${RMPROG-rm}" mkdirprog="${MKDIRPROG-mkdir}" chmodcmd="$chmodprog 0755" chowncmd= chgrpcmd= stripcmd= rmcmd="$rmprog -f" mvcmd="$mvprog" src= dst= dir_arg= dstarg= no_target_directory= usage="Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE or: $0 [OPTION]... SRCFILES... DIRECTORY or: $0 [OPTION]... -t DIRECTORY SRCFILES... or: $0 [OPTION]... -d DIRECTORIES... In the 1st form, copy SRCFILE to DSTFILE. In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. In the 4th, create DIRECTORIES. Options: -c (ignored) -d create directories instead of installing files. -g GROUP $chgrpprog installed files to GROUP. -m MODE $chmodprog installed files to MODE. -o USER $chownprog installed files to USER. -s $stripprog installed files. -t DIRECTORY install into DIRECTORY. -T report an error if DSTFILE is a directory. --help display this help and exit. --version display version info and exit. Environment variables override the default commands: CHGRPPROG CHMODPROG CHOWNPROG CPPROG MKDIRPROG MVPROG RMPROG STRIPPROG " while test -n "$1"; do case $1 in -c) shift continue;; -d) dir_arg=true shift continue;; -g) chgrpcmd="$chgrpprog $2" shift shift continue;; --help) echo "$usage"; exit 0;; -m) chmodcmd="$chmodprog $2" shift shift continue;; -o) chowncmd="$chownprog $2" shift shift continue;; -s) stripcmd=$stripprog shift continue;; -t) dstarg=$2 shift shift continue;; -T) no_target_directory=true shift continue;; --version) echo "$0 $scriptversion"; exit 0;; *) # When -d is used, all remaining arguments are directories to create. # When -t is used, the destination is already specified. test -n "$dir_arg$dstarg" && break # Otherwise, the last argument is the destination. Remove it from $@. for arg do if test -n "$dstarg"; then # $@ is not empty: it contains at least $arg. set fnord "$@" "$dstarg" shift # fnord fi shift # arg dstarg=$arg done break;; esac done if test -z "$1"; then if test -z "$dir_arg"; then echo "$0: no input file specified." >&2 exit 1 fi # It's OK to call `install-sh -d' without argument. # This can happen when creating conditional directories. exit 0 fi for src do # Protect names starting with `-'. case $src in -*) src=./$src ;; esac if test -n "$dir_arg"; then dst=$src src= if test -d "$dst"; then mkdircmd=: chmodcmd= else mkdircmd=$mkdirprog fi else # Waiting for this to be detected by the "$cpprog $src $dsttmp" command # might cause directories to be created, which would be especially bad # if $src (and thus $dsttmp) contains '*'. if test ! -f "$src" && test ! -d "$src"; then echo "$0: $src does not exist." >&2 exit 1 fi if test -z "$dstarg"; then echo "$0: no destination specified." >&2 exit 1 fi dst=$dstarg # Protect names starting with `-'. case $dst in -*) dst=./$dst ;; esac # If destination is a directory, append the input filename; won't work # if double slashes aren't ignored. if test -d "$dst"; then if test -n "$no_target_directory"; then echo "$0: $dstarg: Is a directory" >&2 exit 1 fi dst=$dst/`basename "$src"` fi fi # This sed command emulates the dirname command. dstdir=`echo "$dst" | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'` # Make sure that the destination directory exists. # Skip lots of stat calls in the usual case. if test ! -d "$dstdir"; then defaultIFS=' ' IFS="${IFS-$defaultIFS}" oIFS=$IFS # Some sh's can't handle IFS=/ for some reason. IFS='%' set - `echo "$dstdir" | sed -e 's@/@%@g' -e 's@^%@/@'` IFS=$oIFS pathcomp= while test $# -ne 0 ; do pathcomp=$pathcomp$1 shift if test ! -d "$pathcomp"; then $mkdirprog "$pathcomp" # mkdir can fail with a `File exist' error in case several # install-sh are creating the directory concurrently. This # is OK. test -d "$pathcomp" || exit fi pathcomp=$pathcomp/ done fi if test -n "$dir_arg"; then $doit $mkdircmd "$dst" \ && { test -z "$chowncmd" || $doit $chowncmd "$dst"; } \ && { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } \ && { test -z "$stripcmd" || $doit $stripcmd "$dst"; } \ && { test -z "$chmodcmd" || $doit $chmodcmd "$dst"; } else dstfile=`basename "$dst"` # Make a couple of temp file names in the proper directory. dsttmp=$dstdir/_inst.$$_ rmtmp=$dstdir/_rm.$$_ # Trap to clean up those temp files at exit. trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 trap '(exit $?); exit' 1 2 13 15 # Copy the file name to the temp name. $doit $cpprog "$src" "$dsttmp" && # and set any options; do chmod last to preserve setuid bits. # # If any of these fail, we abort the whole thing. If we want to # ignore errors from any of these, just make sure not to ignore # errors from the above "$doit $cpprog $src $dsttmp" command. # { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } \ && { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } \ && { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } \ && { test -z "$chmodcmd" || $doit $chmodcmd "$dsttmp"; } && # Now rename the file to the real destination. { $doit $mvcmd -f "$dsttmp" "$dstdir/$dstfile" 2>/dev/null \ || { # The rename failed, perhaps because mv can't rename something else # to itself, or perhaps because mv is so ancient that it does not # support -f. # Now remove or move aside any old file at destination location. # We try this two ways since rm can't unlink itself on some # systems and the destination file might be busy for other # reasons. In this case, the final cleanup might fail but the new # file should still install successfully. { if test -f "$dstdir/$dstfile"; then $doit $rmcmd -f "$dstdir/$dstfile" 2>/dev/null \ || $doit $mvcmd -f "$dstdir/$dstfile" "$rmtmp" 2>/dev/null \ || { echo "$0: cannot unlink or rename $dstdir/$dstfile" >&2 (exit 1); exit } else : fi } && # Now rename the file to the real destination. $doit $mvcmd "$dsttmp" "$dstdir/$dstfile" } } fi || { (exit 1); exit; } done # The final little trick to "correctly" pass the exit status to the exit trap. { (exit 0); exit } # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: gputils-0.13.7/Makefile.am0000644000175000017500000000040611156313233012244 00000000000000## Process this file with automake to produce Makefile.in SUBDIRS = @MAKE_SUBDIRS@ dist-hook: cp gputils.spec $(distdir) EXTRA_DIST =\ ./include/ansidecl.h \ ./include/getopt.h \ ./include/libiberty.h \ ./include/stdhdr.h \ gputils.spec.in \ TODO gputils-0.13.7/ChangeLog0000644000175000017500000021714511156521302011772 000000000000002009-03-13 David Barnett * gputils-0.13.7 released 2009-03-13 David Barnett * Minor signed/unsigned cleanups from bug #2556391. 2009-03-12 Marko Kohtala * Add LIST M=??? support for EEPROM8. 2009-03-10 Marko Kohtala * configure script updated to only test for what is used. Fixes compilation problems due to unresolved rpl_malloc and others. * Some includes of stdlib.h and string.h fixed to take advice from configure. 2009-02-09 Marko Kohtala * gpasm/parse.y: Move use of token symbols after definition. This is needed to compile with bison 1.4.1. * gpasm/Makefile.am, gplink/Makefile.am: Separate AM_YFLAGS -d option to enable automake magic to make EXTRA_DIST and MAINTAINERCLEANFILES unnecessary. Use BUILT_SOURCES to have parse.h available for include in other files (namely gpasm/directive.c). 2009-02-06 Marko Kohtala * Synchronized device support with MPLAB IDE 8.20. Updated 82 devices. For some devices object files compiled with previous version will not link against object files from this version due to coff file type changes and memory size changes. Coff file type changed on pic12f508, pic12f509, pic12f635, pic12f683, pic16f505, pic16f54, pic16f57, pic16f59, pic16f610, pic16f636, pic16f639, pic16f716, pic16f737, pic16f767, pic16f777, pic16f785, pic16f84, pic16f84a, pic16f913, pic16f914, pic16f916, pic16f917, pic18f1230, pic18f1330, pic18f2610, pic18f2620, pic18f26k20, pic18f4610, pic18f4620, pic18f6310, pic18f6390, pic18f6410, pic18f6490, pic18f6627, pic18f66j60, pic18f66j65, pic18f6722, pic18f67j60, pic18f8627, pic18f86j60, pic18f86j65, pic18f87j60, pic18f96j60, pic18f96j65, pic18f97j60. Memory sizes fixed to match MPASM v5.30 for pic12c509, pic12c509a, pic12cr509a, pic12f509, pic12f510, pic12ce519, pic16c505, pic16f610, pic16f630, pic16f676, pic16f88, pic16f882, pic16f883, pic16f884, pic16f914, pic16f916, rf509af, rf509ag, rf675f, rf675h, rf675k. BSR position fixed on pic18f6525, pic18c658, pic18f6621, pic18c858, pic18f8621. Added 122 new devices from MPASM v5.30. * [gpasm] Updated config options with script by Michael Ballbach. 2009-1-30 David Barnett * Patch from Marko Kohtala to open COFF files with unknown device ID (using generic device of the same ROM width) 2008-12-15 David Barnett * Cleaned up processor definitions and updated from MPASM data (special thanks Marko Kohtala) 2008-12-03 David Barnett * [gpasm] Fixed warnings checking RAM against max ROM address (bug #2255225) 2008-12-02 David Barnett * Corrected COFF type for p12f510 (bug #2255399) 2008-12-02 David Barnett * [gpasm] Fixed infinite loop for odd addresses on 18F parts (bug #1988473) * [gpasm] Display code_pack sections byte-by-byte in listing file * Special thanks to Michael Ballbach 2008-12-02 David Barnett * Fixed filename expansion bug in regression test script 2008-12-02 David Barnett * Made regression tests Bourne shell compatible 2008-11-06 David Barnett * Added missing definitions for p18f23k20 and p18f43k20 (thanks Raphael Neider) 2008-08-19 David Barnett * Added header & LKR files for p18f23k20, p18f24k20, p18f25k20, p18f26k20, p18f43k20, p18f44k20, p18f45k20, p18f46k20 2008-07-08 David Barnett * Added support for p18f23k20, p18f24k20, p18f25k20, p18f26k20, p18f43k20, p18f44k20, p18f45k20, p18f46k20 (thanks Renato Caldas) 2008-06-06 David Barnett * Fixed segfault in gplink -O2 for symbols w/o sections (bug #1985543) 2008-06-06 David Barnett * Fixed CONFIG address range for 18f65j50 (bug #1986505) 2008-06-03 David Barnett * Fixed line number problems with CODE_PACK directive (bug #1972099) 2008-05-17 David Barnett * gputils-0.13.6 released 2008-05-17 David Barnett * Fixed bug in r528 (involving bug #1534641) 2008-05-16 David Barnett * Added support for p18f45k20 * Added this and previous few processors to processor list in documentation 2008-05-16 David Barnett * Added support for p18f65j50 2008-05-15 David Barnett * Added support for p18f4321 (thanks Rob Pearce) 2008-05-14 David Barnett * Updated CONFIG directive definitions to match MPASM 5.20 2008-05-14 David Barnett * [gpasm] Fixed segfault involving relocations on second pass of assembler (bug #1858537) 2008-05-13 David Barnett * [gpasm] Added support for p18f66j60, p18f66j65, p18f67j60, p18f86j60, p18f86j65, p18f87j60, p18f96j60, p18f96j65, and p18f97j60 (thanks Strobl Anton) * Added these and other added processors to processor list in documentation 2008-05-13 David Barnett * [gpasm] Updated French manpage for -C option (patch by Alain Portal) 2008-05-11 David Barnett * [gpasm] Added CONFIG start/end addresses into processor table (bugs #1831152, #1852585) 2008-05-11 David Barnett * [gputils] Updated p18f65j50.inc 2008-05-11 David Barnett * [gpasm] Fixed special-case default for PIC18 access bit (bug #1534641) 2008-05-11 David Barnett * [gputils] Fixed missing #include for Windows builds 2008-05-11 David Barnett * [gpasm] Fixed segfault on call w/ no args in PIC18's (bug #1943484) 2008-05-08 David Barnett * [gpdasm] Improved gpdasm to allow non-word-aligned byte addresses (bug #1917597) 2008-05-07 David Barnett * [gpasm] Fixed failed assertion for unreasonably high code addresses (bug #1741065) 2008-05-06 David Barnett * [gpasm] Fixed symbol problems for labels on blank lines in data sections (bug #1943487) 2008-05-05 David Barnett * [gpasm] Applied patch by Borut Razem to fix buffer overflow in LST file generation (bug #1922419) 2008-03-21 David Barnett * [gpasm] Added support for 18f2450, 18f4450, 18f2523 2008-03-21 David Barnett * Fixed bug with multiple spaces in #define directives (bug #1860881) 2007-11-22 David Barnett * Fix bug with #v substituted labels in code_pack sections 2007-11-21 David Barnett * Updated gputils manual (gputils.lyx) to LyX 1.5.1 and fixed outdated information 2007-11-20 David Barnett * Applied patch by Michael Ballbach to support code_pack directive 2007-11-19 David Barnett * Fixed endianness bugs in gpvc based on patch by Steve Tell (bug #803352) 2007-11-18 David Barnett * Changed "mode" directive on sx48/sx52 to support 5 bits (FR #835201) 2007-11-18 David Barnett * Changed COFF v2 optional magic number to 0x5678 (same as COFF v1) * Fixed strange errors in sx.asm and pageselw2.asm tests expected output 2007-11-18 David Barnett * Fixed COFF magic number regression 2007-11-17 David Barnett * Fixed CONFIG definitions for 16c54a and 16c715 (in PIC headers) 2007-11-14 David Barnett * Updated gpasm manpage for flag to output new COFF format (-C) 2007-11-13 David Barnett * Merged changes from patch by Andreas Kabel to support the new COFF format across all of gputils 2007-11-12 David Barnett * [gpasm] Fixed -g option to give meaningful error instead of failed assertion when missing .file directive (bug #1825940) 2007-11-11 David Barnett * [gpasm] Added support for 18f2321 2007-11-11 David Barnett * [gpasm] Fixed bad information on 12f509 and 18f6722 in processor data 2007-11-10 David Barnett * Fixed old version number to 0.13.5 (actually released 2007-10-27) 2007-11-08 David Barnett * [gpasm] Fixed gpasm absolute mode to give "maximum range" warnings between program memory and eeprom 2007-11-08 David Barnett * [gpasm] Fixed maxrom to respect max eeprom address (but temporarily removed warnings for addresses in between) 2007-11-05 David Barnett * [gplink] Applied patch from Robert Pearce to fix address/line mapping in COD files 2007-11-05 David Barnett * [gpasm] Updated gpcfg-table.c based on MPASMWIN 5.13 and script by Michael Ballbach 2007-11-05 David Barnett * Changed 'FCMEM' to 'FCMEN' in p18f4550.inc 2007-10-28 David Barnett * Applied patch from Alain Portal to fix French manpage 2007-10-28 David Barnett * Applied patch from Alain Portal to fix manpage formatting 2007-10-27 David Barnett * gputils 0.13.5 Released 2007-09-17 Scott Dattalo * [gpasm] Single character strings were not being interpreted correctly for the .direct macros. 2007-09-28 David Barnett * [gputils] Fixed bsr location for p18f6585, p18f6680, p18f8585 and p18f8680 2007-09-17 Scott Dattalo * [gputils] Added support for the p12f510. 2007-06-26 David Barnett * [gpasm] Report message when RES directive size evaluates to zero (or truncates on PIC18) * [gpasm] Report error when ORG has odd address on PIC18 2007-06-26 David Barnett * [gpasm] Fixed bug #1638506, where fixed idata addresses were divided by 2 2007-06-26 David Barnett * [gpasm] Added message when assuming first CBLOCK address 2007-06-25 David Barnett * [gpasm] Added support for pageselw directive * [gpasm] Added test cases for pageselw directive in gpasm.project directory 2007-06-25 David Barnett * [gputils] Patch by Michael Ballbach to add support for new COFF format 2007-06-25 David Barnett * [gpasm] Fixed bug #1466150, where gpasm produced bad HEX output (instead of an error) for addresses above 0xFFFF under some hex formats 2007-06-25 David Barnett * [gpasm] Reverted forward reference changes for RES directive (on 2007-6-19 & 6-20) since they affect the wrong value * [gpasm] Fixed potential uninitialized pointer access in do_define 2007-06-25 David Barnett * [gputils] Added support for p18f2682, p18f2685, p18f4682, and p18f4685 2007-06-22 David Barnett * Fixed bug in test scripts that prevented failures from being reported properly * [gpasm] Disabled reporting testing failed if tests in gpasm.mchip fail (several have never passed) * [gpasm] Added sx.o into test script directory, apparently forgotten * [gpvc] Changed 'gpdasm' to 'gpvc' in gpvc usage message 2007-06-22 David Barnett * [gpasm] Fixed token problem that caused some beginning-of-line directives (include, title, subtitle) to be accepted when not followed by whitespace or a delimiter 2007-06-21 David Barnett * [gpasm] Fixed bug #1335511, where redefining a symbol silently corrupts the COFF relocations 2007-06-21 David Barnett * [gpasm] Fixed to return non-zero for invalid command-line arguments 2007-06-20 David Barnett * [gpasm] Implemented warning for program code overflow * [gpasm] Implemented __maxrom directive (but not __badrom) * [gputils] Removed 16c747 (doesn't exist) and added 16f747 * [gputils] Fixed wrong address in 16c771.lkr 2007-06-20 David Barnett * [gpasm] Minor fix to previous update, assume 0 instead of 1 for "res" directive argument (size). 2007-06-19 David Barnett * [gpasm] Fixed behavior of undefined expressions on the first pass to assume 0 as in MPASM (affects strange "differ on second pass" cases like bug #1058509) 2007-06-18 David Barnett * [gpasm] Fixed to allow blank parameters on macro invocation, substituting nothing (not even empty quotes) as in MPASM 2007-06-18 David Barnett * [gplink] Fixed bug #1472396, error on empty comment line in LKR script 2007-06-17 David Barnett * [gpasm] Limited string->character coercion of 1-length string literals to contexts where syntax doesn't permit strings * [gpasm] Allowed special escape sequences (like hex codes) in character literals. Old behavior would silently return incorrect result. 2007-06-14 David Barnett * [gpasm] Fixed bug #897875, assertion failed instead of error for substitution of #define label without a value * [gpasm] Fixed minor bug with ignored parameter in check_defines 2007-06-12 David Barnett * [gpasm] Patch by Michael Ballbach to add support for CONFIG directive 2007-06-12 David Barnett * [gpasm] Fixed minor lexer error with title and subtitle directive involving whitespace after parameter * [gpasm] Fixed errors on misuse of #define directive 2007-06-11 David Barnett * [gpasm] Improved quote behavior on include, title, and subtitle directives and moved their logic into the parser grammar 2007-06-11 David Barnett * [gpasm] Corrected behavior for include directive with quoted, braced, and unquoted parameter 2007-06-07 David Barnett * [gputils] Added support for sx48 and sx52 * [gputils] Updated list of supported processors in gputils.lyx 2007-06-07 David Barnett * [gputils] Added support for p10f220 and p10f222 2007-06-07 David Barnett * [gputils] Added support for p16f610 * [gputils] Added support for p16f882, p16f883, p16f884, p16f886, and p16f887 * [gputils] Added support for p18f1230 and p18f1330 * [gputils] Added support for p18f24j10, p18f25j10, p18f44j10, and p18f45j10 2007-06-06 David Barnett * [gpasm] Corrected processor class and removed special-case missing instructions for p16f5x 2007-06-06 David Barnett * [gpasm] Fixed erroneous page count on p16f88 2007-06-06 David Barnett * [gpasm] Fixed missing warning for line ending in unpaired quote 2006-12-16 Scott Dattalo * [gpasm] Patch from David Barnett to fix 'Duplicate Label' bug. 2006-08-19 Craig Franklin * gputils 0.13.4 Released. * [gputils] Updated header files and linker scripts. * {gputils] Fixed UPPER to mask with 0xff instead of 0x3f. * [gpasm] Mask MOVLB with 0xf instead of 0xff. * [gpasm] Fixed default access bit for extended pic16e. 2005-12-19 Craig Franklin * [gpasm] Fixed 18xx config bug when config the last section. 2005-10-13 Craig Franklin * [gputils] Fixed bsr boundary for 18f2455/2550/4455/4550. 2005-08-18 Borut Razem * [gplib] Allow forward and back slashes as directory delimiters. 2005-08-03 Craig Franklin * gputils 0.13.3 Released. * [gpasm] Added more arity checks to bit special instruction mnemonics. 2005-08-03 Raphael Neider * [gplink] Allow processor mismatch warning to be disabled. 2005-07-25 Craig Franklin * [gplink] Changed order of stack and cinit functions to fix bugs. 2005-07-02 Scott Dattalo * [gpasm] Quoted strings can now be passed in a .direct directive. 2005-06-14 Alain Portal * [man] Updated French man pages. 2005-05-26 Alain Portal * [man] Updated French man pages. 2005-05-22 Craig Franklin * [gplink] Remove dead sections from the object files. * [gplink] Added default linker path to search paths. 2005-05-18 Craig Franklin * [gpasm] Check for divide by zero on modulo operator. 2005-05-11 Craig Franklin * [gpstrip] Allow multiple input files. 2005-05-07 Craig Franklin * [gpasm] Generate dependency file. 2005-05-06 Craig Franklin * [gpvo] Added symbol export feature. 2005-05-05 Craig Franklin * gputils 0.13.2 Released. * [gpal] Removed gpal until it reaches alpha status. * [libgputils] Fixed pointer bug in symbol removal function. * [gpasm] Use .org_{address} for ORG COFF section names. 2005-04-24 Craig Franklin * [gpstrip] Added new utility. 2005-04-15 Craig Franklin * gputils 0.13.1 Released. * [gpasm] Generate an error if config is placed in the middle of section. * [gplink] Generate an error if a relocation address is outside a section. 2005-04-13 Craig Franklin * [gplink] Fixed a bug in section merging. * [gpvo] Fixed a bug when disassembling multiword instructions. 2005-03-23 Craig Franklin * [gputils] Updated header files and linker scripts. 2005-03-11 Craig Franklin * [gplink] Fixed RELOCT_ALL relocation. 2005-01-27 Craig Franklin * [gpal] Updated pub files. 2005-01-22 Craig Franklin * [gplink] Remove weak symbols from input object files. 2005-01-17 Craig Franklin * [gplink] Scan archives for missing symbols multiple times if necessary. 2005-01-17 Craig Franklin * [gpasm] Fix relocation error with LCALL and LGOTO directives. 2005-01-14 Craig Franklin * [gpasm] Allow concatenation operators in extern and global directives. 2005-01-12 Craig Franklin * Updated config scripts. 2005-01-06 Alain Portal * Updated French man pages. 2005-01-03 Craig Franklin * gputils 0.13.0 Released. * [gpdasm] Fixed error in decoding two word instructions. 2004-12-31 Craig Franklin * [gputils] Added support for 18xx extended instruction set. * [gplink] Generate a warning if object processor names don't match. * [gpdasm] Decode 18xx instruction mnemonics. 2004-12-24 Craig Franklin * [gputils] Updated header files and linker scripts. * [gputils] Added new processors: p10f200, p10f202, p10f204, p10f206, p16f59, p16f639, p16f685, p16f687, p16f689, p16f690 p18f6310, p18f6390, p18f64j15, p18f65j10, p18f65j15, p18f6627, p18f66j10, p18f66j15, p18f6722, p18f67j10, p18f8310, p18f8390, p18f84j15, p18f85j10, p18f85j15, p18f8627, p18f86j10, p18f86j15, p18f8722, p18f87j10 2004-11-28 Robert Kaes * [gpal] Improved context save during isr. * [gpal] Simplified symbol offsets in the code generator. 2004-11-26 Craig Franklin * [gpal] Added symbol attributes. * [gpal] Added access types. * [gpal] Added volatile symbols. * [gpal] Added records. 2004-11-09 Craig Franklin * [gpal] Write a newline before eof in deps output. * [gpal] Require a public file for the module being compiled. 2004-11-09 Craig Franklin * [gpal] Generate Make compatible dependency lists. * [gpal] Attempt to open .pub file if isn't in memory. * [gpal] Use extended coff directives in gpal output files. * [gpasm] Fixed errors in new COFF directives. * [gplink] Sort sections in the map file. 2004-11-05 Craig Franklin * Moved gpal FSR code to device specific code generators. 2004-11-05 Robert Kaes * Improved gpal 16e code generator. 2004-10-29 Craig Franklin * Fixed bugs in gpal banksels, code generation, and optimizer. 2004-10-27 Robert Kaes * Moved gpal reset and interrupt vectors to device specific code generators. * Fixed gpal com operator. * Fixed gpal bug when function calls appear in test expressions. * Improved gpal 16e indirect accesses, indf accesses, and inc/dec functions. 2004-10-26 Craig Franklin * Allow conditionals in gpal subprogram declaration region. 2004-10-24 Craig Franklin * Allow complex alias expressions in gpal. * Allow pragmas in gpal subprograms. * Add second pass to gpal optimizer. 2004-10-21 Craig Franklin * Reduced number of gpal banksels. 2004-10-19 Craig Franklin * Fixed bug in new linker script option. * Use autoconf PACKAGE_BUGREPORT macro. * Improvements in gpal's 18xx code generator. 2004-10-17 Craig Franklin * Added absolute path option on win32 hosts. * Allow the linker script to be specified on as first item of the object list in gplink. 2004-10-15 Craig Franklin * Delete gplink output files when errors occur. * Use more boolean types. * Clean up top level of gplink. * Added French translation of gputils man pages. 2004-10-10 Craig Franklin * Merged changes from cod-branch: - Fixed stop location error in directory map of COD files. - Added time and date to COD files. - Fixed error in gpvc time reporting. - Changed to byte addressing for 18xx cod files. * Added direct messaging from COFF and COD files to simulator. * Added new COFF directives .ident and .type. * Allow expressions as arguments to banksel, bankisel, and pagesel. * Improved rpm spec file. 2004-10-02 Craig Franklin * Fixed error in disassembly of 18xx instuctions. 2004-09-26 Craig Franklin * Added directives to gpasm for directly modifying COFF symbol tables. * Changed the gpasm COFF debug directives to .file, .eof, and .line. 2004-09-24 Craig Franklin * gputils 0.12.4 Released. * Allow odd relocation addresses in gplink and gpasm. 2004-09-16 Craig Franklin * Improved banksel and pagesel directives. 2004-09-13 Craig Franklin * Remove processor name kludge in gpasm lexer. * Fixed bug in gpal indirect access banksel. * Fixed bug in gpal function return values. 2004-09-05 Craig Franklin * Added new error message to gplink to catch udata sections in devices with only shared memory definitions. * Allow udata sections to be relocated by gplink to shared sections if no space is available. 2004-08-29 Craig Franklin * Add 18xx support to gpal. * Fix disassembly of multi-word 18xx instructions. 2004-08-25 Craig Franklin * Allow "#" in gpasm labels. 2004-08-23 Craig Franklin * Fixed disassembly of clrwdt on 16xx processors. 2004-08-22 Craig Franklin * Fixed BSR location for 18f2331, 18f2431, 18f4331, and 18f4431 2004-07-25 Craig Franklin * gputils 0.12.3 Released. 2004-07-24 Craig Franklin * Merged patches from OpenBSD port. 2004-07-23 Craig Franklin * Added new processors: 12f508 12f509 12f635 12f683 16f505 16f636 16f785 16f913 16f914 16f916 16f917 18f2410 18f2420 18f2455 18f2480 18f2510 18f2515 18f2520 18f2525 18f2550 18f2580 18f2585 18f2610 18f2680 18f2681 18f4410 18f4420 18f4455 18f4480 18f4510 18f4515 18f4520 18f4525 18f4550 18f4580 18f4585 18f4610 18f4680 18f4681 18f6410 18f6490 18f8410 18f8490 * Updated header files and linker scripts. 2004-07-22 Craig Franklin * Define SFRs in pub files as uint8 instead of constant uint8. 2004-07-18 Craig Franklin * Allow multiple modules and publics in one gpal file. 2004-07-17 Craig Franklin * Added _stack_end symbol to gplink to simplify downward growing stacks. 2004-07-13 Craig Franklin * gputils 0.12.2 Released. 2004-07-08 Craig Franklin * Allow empty modules and publics in gpal. * Allow if statements in a module or public, but outside of subprograms in gpal. 2004-07-07 Craig Franklin * Added support for manually assigned data memory addresses in gpal. 2004-07-04 Craig Franklin * Added support for nested case statements in gpal. * Added support for multiple switch elements in gpal case statements. 2004-07-03 Craig Franklin * Added symbol alias feature to gpal. 2004-06-27 Craig Franklin * Added several new gpal optimizations. 2004-06-25 Craig Franklin * Fixed gpasm regression. Duplicate extern feature can cause assertions. * Allow cblocks in gpasm macros. 2004-06-16 Craig Franklin * Allow duplicate extern directives in gpasm. 2004-06-15 Craig Franklin * Fixed relocations in idata sections. 2004-05-05 Craig Franklin * Added labels and gotos to gpal. 2004-05-02 Craig Franklin * gputils 0.12.1 Released. 2004-04-22 Craig Franklin * Added processor pub file generation. * Added default search path to gpal. 2004-04-17 Craig Franklin * Added support for #if directive and allow else in column 1. * Fixed malformed header files. They were missing a NL before the EOF. * Added interrupt context save to gpal. 2004-03-13 Craig Franklin * Added gplink command line option to disable list file output. * Fixed gplink bug that caused an error to be generated if a source file wasn't found when generating a list file. * Fixed gplink 18xx initialized data sections so retlw isn't used. * Added support for stack sections in gplink. * Use section type to determine format for gpvo disassembly output. 2004-02-09 Craig Franklin * Fixed bug in gpdasm relative branches. 2004-02-07 Craig Franklin * Fixed uninitialized memory in escape character conversion. 2004-01-20 Craig Franklin * gputils 0.12.0 Released. * Fixed bug in gpdasm relative branches. * Force decimal interpretation of debug line number directive in gpasm. * Don't insert LIST or NOLIST symbols in gpasm COFF outputs if debug directives are used. * Fixed bug when concatenated symbols _#v is used as a macro argument. * Fill missing 18xx config words in gpasm relocatable objects with 0xff instead of generating an error. 2004-01-16 Craig Franklin * Use install path for default when environmental variable isn't set. * Added GPUTILS_LIB_PATH environmental variable for gplink. * Added list file output to gplink and fixed bugs in cod file output. * Added automake work around to fix compile order for bison outputs. * Switched to AM_ flags in automake so users can specify additional flags. 2004-01-09 Craig Franklin * Allow full path to object file in gplib when creating an archive. * Always generate a warning when a source is missing an endif. * Prevent #v label from being processed when assembly is disabled. * Force list file to print blank space when assembly is disabled. 2004-01-07 Craig Franklin * Use environmental variables GPUTILS_HEADER_PATH and GPUTILS_LKR_PATH for the default header and lkr paths. * Removed CFLAGS from mingw port. * Fixed COFF line number bugs in gplink. * Fixed 18xx symbol offset bug when merging sections in gplink. * Fixed segfault in gplink when sections missing relocations are merged. 2004-01-01 Scott Dattalo * libgputils/gpsystem.c - added unsigned short gp_getu16(char *addr) * gputils/dump.c - changed references of gp_getl16 to gp_getu16. Added new function fget_line() to read a line from a file. 2004-01-01 Craig Franklin * Allow multiple config words for all devices in gpasm. 2003-12-25 Craig Franklin * Use full symbol name in gpal at the base of symbol tables. * Add symbol alias at the top of symbol table stack. * Use full type name in types. 2003-12-23 Craig Franklin * Removed constant and variable keywords from gpal. Added constant type. * Removed header file scan from gpal. 2003-12-20 Craig Franklin * Fixed i_memory allocation so memory beyond 32k words is initialized to 0. * Fixed memory map in gpasm list files for 18xx devices. The map is now in byte format. 2003-12-18 Craig Franklin * Changed gpasm classification to beta, gpal to pre-alpha, and all others to alpha. * Updated gputils manual to include gpal. * Added gpal man page. * Fixed many gpal bugs. 2003-12-15 Craig Franklin * Added a new tool called gpal. * Added debug-info feature to gpasm, so HLL linenumbers can be inserted into COFF outputs. 2003-12-14 Craig Franklin * Fixed a bug in gpasm 18xx absolute data memory sections that caused the address to be wrong. 2003-12-01 Craig Franklin * Changed gpasm behavior so cblocks are only processed when assembly is enabled. 2003-11-30 Craig Franklin * Changed gpasm while loops to insert raw text instead of a parsed tree. 2003-11-29 Craig Franklin * Fixed gpasm bug that prevented some symbols from being substitued with macro parameters and #defines. 2003-11-23 Craig Franklin * Fixed gpasm bug that caused the relocation to be omitted if the macro argument is complex. * Fixed gpasm bug that could cause symbol offsets in relocations to be calculated incorrectly. 2003-11-22 Craig Franklin * gputils 0.11.8 Released. * Added new processors: 16f54, 16f57, 16f688 * Updated header files and linker scripts. * Updated libiberty from upstream sources. * Changed gpasm 18xx banksel from movlb relocation to banksel relocation. * Changed gplink movlb relocation to use the upper byte of symbol address. 2003-10-21 Craig Franklin * Fixed string to long conversion in gpasm so 32 bit numbers could be used. 2003-10-19 Craig Franklin * Updated documentation. 2003-10-18 Craig Franklin * Fixed a bug in 16xx special instruction mnemonics that could cause an incorrect branch calculation if a goto proceded the mnemonic. 2003-10-17 Craig Franklin * gputils 0.11.7 Released. 2003-10-09 Craig Franklin * Allow gplink to parse linker scripts with missing newlines before the EOF. 2003-10-08 Craig Franklin * Fixed an initialization problem that causes a segfault when the first line has a parse error. 2003-10-03 Craig Franklin * Added 18xx config and idlocs sections to gpasm coff outputs. * Cleaned up gplink script error reporting. 2003-09-28 Craig Franklin * Fixed gplink bug in 18xx absolute sections. * Fixed gplink memory allocation bug in 18xx devices. 2003-08-08 Craig Franklin * Fixed bug that could cause problems with comments on include directives. 2003-08-01 Craig Franklin * gputils 0.11.6 Released. * Added support for idata sections in gplink. * Changed extension of gplink object output from ".out" to ".cof" 2003-07-23 Craig Franklin * Fixed bsr boundary location for 18f248, 18f258,18f448, and 18f458. * Changed gpasm, gpdasm, and gpvo memory dump address format from word to byte for 18xx devices. * Changed gplink processor check to be processor family instead of processor name. * Changed gpdasm to display the second word of 18xx two word instructions. 2003-07-20 Craig Franklin * Added new processors: 16f716, 18f2620, 18f4620 * Update header files and linker scripts. * Fixed gplink error that caused the map file to always be generated. * Fixed bug in gpasm that caused 18xx access bank bit to be ignored if it was specified on some instructions. * Changed gpdasm 18xx address format from word to byte. 2003-07-07 Craig Franklin * Changed extension of gplink object output from ".o" to ".out" * Fixed error in RES directive when used for data sections. * Fixed typo in gp_date_string. 2003-06-28 Craig Franklin * gputils 0.11.5 Released. * Fixed byte count when RES directive is used in 18xx data sections. * Display help when multiple files are passed to gpasm, gpdasm, gpvo, and gpvc on the command line. * Check for lower case filename if include file is not found. 2003-06-23 Craig Franklin * Extended the legal syntax for difference of coff symbols within the same section. 2003-06-22 Craig Franklin * Changed coff to use byte addressing for program memory of 18xx devices. * Changed absolute coff sections generated with org directive to use org_"number" for a name instead of org_"address". * Added missing relocation for "$" symbol. * Fixed bug in gpvo which could cause section data to not be printed for 18xx devices. * Added range warning to gplink for 18xx relative branches. * Changed default behavior of the 18xx access bit in gplink to be like gpasm. * Changed build directory for rpms. 2003-06-14 Craig Franklin * Fixed error in the range check for 17xx movpf and movfp instructions. 2003-06-04 Craig Franklin * gputils 0.11.4 Released. * Replaced or removed obsolete macros in configure.ac. 2003-06-01 Craig Franklin * Added new processors: p16c557 p16c747 p16f648a p16f684 p16f737 p16f767 p16f777 p18f2331 p18f2431 p18f2439 p18f2539 p18f4331 p18f4431 p18f4439 p18f4539 p18f6520 p18f6525 p18f6585 p18f6621 p18f6680 p18f8520 p18f8525 p18f8585 p18f8621 p18f8680 rf675f rf675h rf675k * Updated header files and linker scripts. 2003-05-20 Craig Franklin * Updated scripts to automake-1.6 and autoconf-2.57. * Ran autoscan and fixed reported problems. * Added AM_MAINTAINER_MODE to autoconf. 2003-05-10 Craig Franklin * gputils 0.11.3 Released. * Fixed seg fault in gpasm when difference between coff symbols is calculated. * Fixed map file bug that caused the end section address to be reported incorrectly. * Added gplink command line option to fill unused unprotected program memory. * Added gplink testsuite. 2003-05-06 Craig Franklin * Fixed conditional assembly of INCLUDE directives in gpasm. * Fixed seg fault in gplink when object has no sections or symbols. * Fixed target memory allocation in gplink when section size = page size * Fixed target memory allocation in gplink when section size = 1 * Implemented section fill in gplink. 2003-05-03 Scott Dattalo * 18f Bit instructions were not handling the Access bit properly 2003-04-19 Craig Franklin * gputils 0.11.2 Released. * Fixed section size bug in org directives when used in gpasm coff outputs. * Fixed bug in cod file address size that confused MPLAB. * Fixed bug in lexer when < and > were used in the same expression. * Prevented symbols from absolute sections from being updated after relocation. * Added feature so gplink now loads a default linker script if one is not specified. * Updated header files. * Updated linker scripts. * Added configuration settings for OS/2 host. * Modified lexer to allow [.][a-z][a-z0-9]* labels. * Moved gpasm default header path to last in the search list. 2003-04-02 Craig Franklin * gputils 0.11.1 Released. 2003-03-23 Craig Franklin * Moved common cod functions into libgputils. * Added cod file output to gplink. * Updated config scripts. * Added variable bsr boundary location for default access bit on 18xx devices. 2003-03-21 Craig Franklin * Check status of all fopens to prevent file io problems. 2003-03-14 Craig Franklin * Specified fopen() mode to prevent CRLF conversion on binary files when using the mingw port. * Fixed gplink bug that causes some symbols to be incorrect after section merging. * Report symbol names when resolving external references in gplink fails. 2003-03-14 Craig Franklin * gputils 0.11.0 Released. * Fixed bug that caused amode stack to be incorrect when exitm was used. * The P value for movpf and movfp instructions is now checked. * Added check for invalid destinations with movff instructions. * Cleared defines table at the start of second pass. * Generate a warning for macros only invoked on pass 2. 2003-03-09 Craig Franklin * Fixed segmentation fault in gplink. * Fixed a parse error in the sharebank definitions in linker scripts. * Moved COFF definitions to gpcoff.h. 2003-03-03 Craig Franklin * Finished relocation patching. * Added map and hex file outputs to gplink. 2003-02-27 Craig Franklin * Added relocation and linking functions to gplink. 2003-02-22 Craig Franklin * Removed nuisance warning about malformed asm files. * Fixed errors when using escape characters in strings. 2003-02-17 Craig Franklin * Added auxiliary coff symbols. 2003-02-16 Craig Franklin * Added pointers in object files to simplify linking operations. * Added checks when reading object files. 2003-02-02 Craig Franklin * Combined overlayed sections in gpasm coff outputs. * Append prefix on local variables that end up in coff file. * Fixed error that prevented using $ with data directives. 2003-01-19 Craig Franklin * Added object test files. * Fixed errors found by running new test files. * Added bankisel directive. 2003-01-05 Craig Franklin * Converted to new object structures. * Fixed errors in gpasm, gplib, and gplink. * Changed gpvo output format. 2002-12-22 Craig Franklin * Added coff file support to gpasm. * Added UPPER operator. * Removed invalid parts. 2002-12-04 Craig Franklin * Fixed incorrect range warning on 18xx gotos. * Fixed parse error for << operators > in the comment. * Cleaned up parse debug output. 2002-11-22 Craig Franklin * gputils 0.10.6 Released. * Fixed behavior of de directive for 18xxx devices. Data is now packed. * Added new directives: banksel and pagesel * Fixed default BSR behavior for 18xxx devices. * Changed gpasm default hex file format to inhx32. 2002-11-09 Scott Dattalo * Invalid relative branches for 18xxx family were not generating errors. eg: bc $+258, bc $-256, rcall $-2048, rcall $+2050 all now generate appropriate errors. 2002-11-07 Craig Franklin * Added support for sx, 17xx, and 18xx devices in gpdasm. * Fixed config directive for 18xx devices with address > 0x300007 2002-10-27 Craig Franklin * gputils 0.10.5 Released. 2002-10-19 Craig Franklin * Added new processors: 12f629 12f675 16c557 16f627a 16f628a 16f630 16f676 16f72 16f76 16f77 16f818 16f819 16f87 16f873a 16f874a 16f876a 16f88 18f1220 18f1320 18f2220 18f2320 18f4220 18f4320 18f6620 18f6720 18f8620 18f8720 rf509af rf509ag * Updated header files 2002-10-12 Craig Franklin * gputils 0.10.4 Released. * Fixed bug that caused assertion when macro calls procede definition. * Fixed bug that required gpasm arguments be in a specific order. * Moved opcode definitions into libgputils for future gpdasm improvments. * Fixed bug that prevented conditional assembly directives in column 1 to be missed if assembly had been previously disabled. * Generate an error if endm is missing from a macro definition. * Increased gpvc file number limit from 20 to 100. 2002-08-18 Scott Dattalo * gpasm - arithmetic for negative relative branches on a 16bit core was loosing the sign bit. 2002-05-12 Craig Franklin * gputils 0.10.3 Released. 2002-04-27 Craig Franklin * Added Code Warrior changes. 2002-04-09 Craig Franklin * Updated header files and linker scripts. * Added manpages. 2002-04-08 Craig Franklin * Fixed error that could cause a seg fault on AmigaOS. 2002-04-03 Craig Franklin * gputils 0.10.2 Released. * Any argument to an instruction which exceeds its range will now generate at least a warning. * Bank warnings are now generated for access to register files that aren't in bank 0. * Any goto or call which is to a page other than the current page will now generate a page warning. * Added --force-list option, so gpasm will ignore nolist directives. * The default values for hex format, radix, and warning level are now displayed. * Added description of the alternative number formats to documents. 2002-02-28 Craig Franklin * Fixed a bug that inserted an extra NULL line in a macro definition when += type ops are used. The bug caused a seg fault. 2002-02-23 Craig Franklin * gputils 0.10.1 Released. 2002-02-23 Craig Franklin * Macros are now implemented as a text substitution at the input to the lexer. All macro arguments are preprocessor substitutions like #define. * Fixed a bug that caused i = i + 1 type expressions to be evaluated twice in macros. * Include statements now appear before the body of the file in the listing. * Macro calls now appear before the body of the macro in the listing. * Fixed a bug that allowed #defines in the body of a macro to be processed during the macro definition. * "fill (),number", equ, and various other commands now work in macros. * Fixed several bugs in the processing of numeric constants. For example, with a hex radix setting "100b" is now evaluated as 0x100b not 0x4. * #v() subsitutions will now work in cblocks and macros. * Fixed a bug that could cause a segmentation fault with a bad text substitution. 2002-01-27 Craig Franklin * added rpm spec file. 2002-01-20 Craig Franklin * gputils 0.10.0 Released. 2002-01-17 Craig Franklin * Removed target detection from configure. Target is always a PIC so it doesn't make any sense to run the test. * Removed unnecessary object extension from Makefiles. * Added bzero.c to libiberty for mingw32 port. 2002-01-16 Craig Franklin * Added missing () in gplink lexer. * Added a subset of libiberty so getopt_long is always available. 2002-01-15 Craig Franklin * Fixed a bug in gpasm that causes a nuisance warning when multiple macro definitions are selected using conditional assembly. 2002-01-13 Craig Franklin * Fixed a bug in gpvc that could cause a segmentation fault. 2002-01-10 Craig Franklin * Renamed gpasm package to gputils. * Changed library from libgpasm.a to libgputils.a * Renamed mem2asm.c to dis.c * Appended gp prefix to all library files. * Renamed /gpasm/opcode.c to /gpasm/directive.c. * Corrected and updated copyright notices. * Moved /gpasm/cod.h to library. Removed cod.h from gpvc. * Moved test files to tool subdir for future support of dejagnu. * Started updating users manual. * Moved examples to gputils-extra package. * Corrected many problems with gplib. * Continued work on gplink. 2001-12-07 Craig Franklin * Added linker scripts. 2001-12-06 Craig Franklin * Fixed cygwin warnings with -Wall -pedantic flags. * Updated maintainer information. 2001-11-26 Craig Franklin * Fixed a bug that could cause a core dump when expanding macros. * Fixed a bug that cause labels inside of macros for 18cxx devices to be off by 2X. * Removed unecessary -I /usr/local/share/gpasm/header from example1 Makefile. * Fixed a bug that causes command line radix to be overwritten on pass 2. * Moved symbol table functions to library for use with gplink. * Added extra warning flags to cygwin. 2001-11-24 Craig Franklin * Added new tool gplink. This tool is intended to be compatible with mplink. This is a development version. It is not complete. 2001-11-17 Craig Franklin * Added new tool gplib. This tool is intended to be compatible with mplib. This is a development version. It is not complete. 2001-10-31 Craig Franklin * gpasm 0.9.14 Released. * The path to the header files is now searched when including files. This means the "-I /usr/local/share/gpasm/header" argument to gpasm is no longer necessary. The path may be displayed by commanding "gpasm -h". This path may be disabled at compile time using the "--disable-path" configuration option. 2001-10-25 Craig Franklin * implemented "fill (),number", where is a line of assembly. example: "fill (goto start), 10" * fixed bug #423204, infinite loop when missing new line before EOF in a file without the END directive * parser debug is enabled when PARSE_DEBUG is defined 2001-10-09 Craig Franklin * removed all // comments to satisfy --pedantic flag * fixed several errors in gpvo 2001-10-06 Craig Franklin * gpasm 0.9.13 Released. * Added new processors: p16c432 p16c433 p16c781 p16c782 p16c925 p16c926 p16cr620a p16f73 p16f74 p16f85 p16f86 p16f877a p18f242 p18f248 p18f252 p18f258 p18f442 p18f448 p18f452 p18f458 * Corrected header file errors. * New header files added: p16c781.inc p16c782.inc p16f85.inc p16f86.inc p16f877a.inc p18c601.inc p18c801.inc p18f020.inc p18f242.inc p18f248.inc p18f252.inc p18f258.inc p18f442.inc p18f448.inc p18f452.inc p18f458.inc 2001-10-02 Craig Franklin * "list n=0" may now be used to prevent page breaks in the listing file. This feature was provided by Reto Felix . * All arguments to the list directive are now processed as decimal regardless of the current radix setting. * reformat ChangeLog 0.9.12 TSD for Craig Franklin 1. The preprocessor now supports #v(expression) substitution in labels and symbols. If symbol equals 4, then the label "mylabel_#v( (symbol * 3))_ok" is replaced with "mylabel_12_ok". 2. The error message "can't evaluate expression" has been replaced by more specific error messages. 3. eeprom8 device is now supported. 4. The DOS newlines option (-n) has been disabled on win32 systems. DOS newlines are already the default on these systems. 0.9.11 TSD for Craig Franklin 1. Labels are substituted when found on the #define table. 2. Labels are treated as macros when found on the macro table. 3. gpasm can now distinguish between directives and opcodes placed in the first column. 4. defines are now printing in the listing file symbol table. 5. #ifdef and #ifndef check the entire symbol table not just #define table. 6. Several processors had characters with the incorrect case in the defined_as section of their definition. This lead to incorrect warnings when using the Microchip header files. 7. Some changes have been incorporated for cross compiling to win32 systems. 0.9.10 TSD for Craig Franklin 1. The instruction set is now loaded when the processor is selected. Previously it was loaded when the first instruction is encountered. This resolves some old problems when the first instruction is incorrectly formatted. 0.9.9 TSD for Craig Franklin 1. Labels are now checked against the symbol tables. If the label is found on the instruction or the directive lists, a warning is generated and the text is treated accordingly. 2. Symbols may now be assigned values when declared using the local directive. As in "local i, j=15, k". 3. The extended ASCII character set (ü) may now be used for labels and symbols. 4. gpasm now tests for infinite while loops. In this condition, an error is generated and assembly continues. 5. Assembly will now stop upon encountering the first END statement. Regardless of location. 6. Flags have been added to the linker to warn when a common symbol is combined with another symbol. This condition could create porting issues. The warnings that resulted from this change were fixed. 0.9.8 TSD for Craig Franklin 1. Macros and While loops are now expanded in the listing file. Macro expansion can be disabled using "list e=OFF" in the source code or "-e OFF" as a gpasm argument. While loops are always expanded. 2. Macros and While loops are also expanded in the COD file. Now when you step through the source code in gpsim, the file viewer will jump to the macro or while loop definition. 3. New Processors added: 16c745, 16c765 4. Some users require dos style new lines (CRLF) in hex files for device programmers. gpasm will generate these by selecting -n or --dos. 5. The -Wall and -pedantic flags were added to gcc on linux systems. All warnings generated from this change were corrected. 6. Various configuration problems were fixed that caused "make distcheck" to fail. 7. getopt_long() has been added to gpvo. 8. A Makefile for generating rpms has been added. See the README in the rpm subdirectory for details. 9. BUG #433291. During macro innvocation, the list linetype was set to the value of the line before endm in the definition. This could result in a bad label error, if that line was a non code generating directive. The linetype is now "none" during expansion or "insn" during nonexpansion. 0.9.7 TSD for Craig Franklin 1. The i++ and i-- operators are now implemented. Note: the variable is a label and must appear in column 1. 2. +=, -=, *=, /=, %=, <<=, >>=, &=, |=, and ^= have all been implemented. Note: the variable is a label and must appear in column 1. 3. If a file ends during an IF statement, before an ENDIF found, a warning is now generated. 4. The conditional assembly directives IFDEF, IFNDEF, and ENDIF may now be proceeded by a "#". example: #ifdef 5. The SET directive may now be proceeded by "." 6. The header files have been updated. 7. A memory map is now generated as part of the listing file. The generation of the memory map is controlled by "list mm=[ON|OFF]". 8. The number of program words used by the program is now reported in the listing file. 9. Several users have had problems linking with libfl.a to get yywrap(). gpasm has been modified so that libfl.a is no longer needed. flex is still required. 10. The message generated whenever a special mneumonic was used has been disabled. This message was part of the test files provided by Microchip, but message is not yet part of the current mpasm releases. 11. The configure script now detects the host operating system. When using cc on SunOS the "-xCC" flag is used to allow "//" comments. 12. New processors added: 18c601, 18c801, 18f010, 18f012, 18f020, 18f022 0.9.6 TSD for Craig Franklin 1. A new utility, gpvo, GNU PIC View Object, was added. This tool displays the contents of Microchip's object files. The tool is in a very preliminary stage of development. To reflect this it is designated "pre-alpha". 2. BUG #426330. getopt_long() is not available on all systems. The configure script now detects the function. If it is not present gpasm uses getopt(). This does not change the features available, only the way they are commanded. 3. To make the error messages more readable the error codes are now enclosed in []. 4. BUG #423850. gpasm would hang on symbols defined incorrectly. #define foo foo. crash --> movlw foo An error is now generated each time foo is used in an expression and gpasm doesn't lockup. 5. 1/2 of BUG #423204. The top level assembly file must always end in "END". This condition is now tested for and an error is generated if it is not present. 6. BUG #422060. gpasm will now compile on a 64 bit machine (NetBSD/Alpha is the only one that has been tested). 7. gpvc header file had declarations that were getting instantiated multiple times. 0.9.5 TSD for Craig Franklin 1. gpasm, like mpasm, is now case sensitive by default. The -c parameter now makes gpasm case insensitive. 2. The macros in special.inc have been incorporated into the source code. This was done to solve a case sensitivity problem. 3. gpdasm can now read inhx16 format in addition to inhx8m and inhx32. 4. A new option, -i, has been added to gpdasm. This option returns data on the input hex file, like number of bytes and hex file format. 5. The format of error/warning/message has been changed. To standard output the new format is "filename":"line number": Error "number" "message" to the list file: Error ["number"] : "message" The list file output conforms with MPASM. The standard output conforms with most gnu tools. 6. GNU long options have been provided by Salvador Eduardo Tropea . 0.9.4 TSD for Craig Franklin 1. inhx16 hex format can now be generated by gpasm. 2. 17cxx devices are now checked for exceeding their 16 bit address range. If this happens an error is generated. 3. gpasm now checks to see if an address has been written to more than once. If it has an error is generated. 4. Previously, when an invalid data memory location is accessed, gpasm would generate a warning and not write the instruction to program memory. Now it will still generate the warning, but it also outputs the instruction. 5. __fuses is now equivalent to __config. 6. The 16c461 processor has been added. 7. When two different processors are selected in the source file an error, in addition to the duplicate processor warning, is generated. 8. The "#" symbol can now be prefixed to include directives. 9. If a source file ends during a while statement, before a endw is encountered, an error is generated. 10. Bug #413296. Numeric expressions followed by b, d, h, or o, are now interpretted according to the radix they represent (i.e. 144o = 144 octal = 100 decimal) 11. Labels are now checked to verify they are on a legal line. An example is shown below: Error radixerr.asm 16 : 121 Illegal label. 00016 Label RADIX OCTAL 0.9.3 TSD for Craig Franklin 1. The 17cxx processor family is now supported. Much of the work was completed by Carlos Nieves . 2. Macro name case sensitivity is now controlled by the -c option. 3. Values stored to program memory using the dt directive are now masked to ensure that a value over 0xff isn't stored. 4. The number of arguments passed to EXPAND and NOEXPAND are now checked. If any number other than 0 is passed a warning is generated. 5. If no arguments are passed to SPACE, it is now equivalent to SPACE 0. 6. 16cr56 and 14000 processors are now supported. 7. SUBTITL and STITLE are now equivalent to the SUBTITLE directive. 8. A single character enclosed by double quotes is now interpretted as the corresponding ASCII code (example: ANDLW "A" = 0x0E41 for 12 bit cores). 9. The header files have been updated. 10. The ram access bit "a" for 18cxx devices now defaults to "0" or Access RAM. 11. The AND operator now has a higher precedence then the OR operator. The following line from the preced.asm test file demonstrates this. 002D 0000 00067 DATA 2 == (2 && 0 + 1) ; 0 00068 --> 002E 0001 00069 DATA 1 || 0 && 0 ; 1 002F 0001 00070 DATA 1 || (0&&0) ; 1 0030 0000 00071 DATA (1||0) && 0 ; 0 12. A few changes were required to compile under Mac OS X. Some of these changes were incorporated. 0.9.2 TSD for Craig Franklin 1. Added many new processors. The new list is below: gen p12c508 p12c508a p12c509 p12c509a p12c671 p12c672 p12ce518 p12ce519 p12ce673 p12ce674 p12cr509a p16c5x p16cxx p16c505 p16c52 p16c54 p16c54a p16c54b p16c54c p16c55 p16c55a p16c554 p16c554a p16c558 p16c558a p16c56 p16c56a p16c57 p16c57c p16c58 p16c58a p16c58b p16c61 p16c62 p16c62a p16c62b p16c620 p16c620a p16c621 p16c621a p16c622 p16c622a p16c63 p16c63a p16c64 p16c64a p16c641 p16c642 p16c65 p16c65a p16c65b p16c66 p16c661 p16c662 p16c67 p16c70 p16c71 p16c71a p16c710 p16c711 p16c712 p16c715 p16c716 p16c717 p16c72 p16c72a p16c73 p16c73a p16c73b p16c74 p16c74a p16c74b p16c76 p16c77 p16c770 p16c771 p16c773 p16c774 p16c83 p16c84 p16c85 p16c86 p16c923 p16c924 p16ce623 p16ce624 p16ce625 p16cr54 p16cr54a p16cr54b p16cr54c p16cr56a p16cr57a p16cr57b p16cr57c p16cr58a p16cr58b p16cr62 p16cr63 p16cr64 p16cr65 p16cr72 p16cr83 p16cr84 p16f83 p16f84 p16f84a p16f627 p16f628 p16f870 p16f871 p16f872 p16f873 p16f874 p16f876 p16f877 p16hv540 p16lc74b p18cxx2 p18c242 p18c252 p18c442 p18c452 p18c658 p18c858 sx18 sx20 sx28 2. Bug #231274. Page directive conflicted with the Page instruction in sx devices. The result was a redefining symbol error when an SX device was selected. This has been fixed. The result is the PAGE directive is disabled for all SX devices. 3. Config data is now masked by the device core size. This prevents things like 0x1234 from being written into config memory for a 12 bit device. 4. "decimal" and "octal" are now valid arguments for the radix. This is a legacy feature of MPASM. It is not documented in their users manual. 5. In instances of "label org 100", label is added to the symbol table. Previously, it was ignored. 6. BUG #233207. Labels defined inside macros now work. 7. Microchip has provided the gpasm project with test files they use to test MPASM. The new test files have been added to CVS. These files required the use of their header files. These were added to the project. They are installed when "make install" is ran. 8. The distribution now includes an example located in ./examples/example1. 9. A few changes were required to compile under cygwin. Some of these changes were incorporated. 10. Cleaned up source code. (Missing comments, unused code, ...) 0.9.1 TSD for Craig Franklin 1. The project was reorganized to make room for some new tools. Each tool is now located in its own subdirectory. Common functions are located in libgpasm.a in the lib directory. 2. A new utility, gpdasm, GNU PIC Disassembler, was added. Details can be found in the project documentation. 3. A new utility, gpvc, GNU PIC View COD, was added. Details can be found in the project documentation. This is basically version 0.0.3 of Scott Dattalo's vc. It will be maintained as part of gpasm. 4. Documentation has been updated. The gpasm section includes changes made during the 0.8.x series. It still isn't perfect. It is missing information on the PIC18cxx series. New sections have been added for the new tools. 5. Previously, the ERRORLEVEL directive required the user to force interpretation of arguments as decimal using "." or "d". This is no longer required. The arguments are always interpreted as decimal regardless of the radix setting. 6. A debug message has been removed from the maybe_evaluate function in opcode.c. 0.9.0 TSD for Craig Franklin 1. A typo in the help listing for the usage of warning level was fixed. 2. The options for LIST are case sensitive when the -c option is used. Because of this, list p= works and list P= doesn't. This has been corrected. 3. The addition of the case sensitive defines broke the processor selection using -p . This has been fixed. 4. gpasm -q will now suppress the output from the gperror system to the screen. This doesn't effect the listing file. It doesn't currently make gpasm totally quiet. Some messages bypass the gperror system. They are not effected by -q. 5. gpasm reported an "Unknown Opcode" for each instruction whenever a processor wasn't selected. It now reports this error as "Processor type is undefined". 0.8.16 TSD for Craig Franklin 1. New directives: da __idlocs variable constant 2. The data and db directives generated incorrect values for 16 bit cores. This has been corrected. 3. The dw directive generated incorrect values for all devices. This as been corrected. 4. inhx8s hex format can now be generated. 5. EXPAND and NOEXPAND directives can now be called without generating an error. They will not, however, effect the listing file. Similarly, macro expansion can be selected on the command line with "gpasm -e [ON|OFF]" or using in the source file "list x=[ON|OFF]." They will not effect the listing file. 0.8.15 TSD for Craig Franklin 1. When numeric arguments were passed to a function that expects a symbol, GPASM reported the error as "Expression to Complex". This has been changed to illegal argument to conform with MPASM. 2. A previous patch always warned the user then option or tris was used. I have learned that MPASM doesn't warn the user on p16c5x devices. The behavior has been modified to conform with MPASM. 3. The -c option now makes the #defines case sensitive. 4. Command line setting of the warning level is supported. Like MPASM, command line arguments override settings in the source code. All command line settings now have flags indicating the value was set by the command line and it can't be overwritten by the asm source code. A warning or message is posted to the user. 5. Output hex file format can now be chose using LIST f=. 6. GPASM 0.8.14 has a bug were the org isn't reset after a config is called. This is normally not seen because most people place the config statements before their first org. This patch saves the org before the config is ran then restores it afterword. 7. GPASM 0.8.14 doesn't print the config information to the list file correctly for pic18cxx devices. 8. Several new codes have been added for new tests. 9. The FILL directive works. It works the same as MPASM with one important exception. It does't support the use of a line of assembly as an argument. That is not a problem because the while statement can do the same thing. 10. GPASM now generates inhx32 format. In adding this, a structural change had to be made. Previously, the MEMBLOCK segment size was 64K words. I changed this to 32K words. I did this because the 32K words (or 64K bytes) is equal to one segment. Which, conviently, is the maximum size for a inhx8m file and the size of one inhx32 segment. 11. The list file had some extra blanks. These were fixed. 12. All of the directives and instuctions now have the correct list linetype assignment. I abandoned the default method because of too many special cases. 13. The RADIX directive had a linetype assignment of ORG, it should be none. 14. The ORG directive originally had the correct line type assignment of ORG. It was changed to EQU in version 1.8 of opcode.c. I don't know the reason. This patch changes it back. 15. The PAGE directive had a linetype assignment of ORG, it should be NONE. 16. Directives in scan.l (include, define, ..) are now all case insensitive. There are many instances in microchips appnotes of SubTitle, Title, ... GPASM 0.8.14 dosesn't recognize them. The change was to add "-i" to flex when GPASM is compiled this makes the scan.l case insensitive. 17. #undefine now works. Previously symbols could be redefined by having another instance of #define. Doing so will now result in a warning. Symbols must be defined and undefined and defined again to be reassigned. 18. Previously, #define could only appear in column 1. Now it does not. This occurs in micorchip include files. 19. Previously, #defines were executed regardless of assembling being enabled. An example would be a set of defines inside an IF statement. This case occurs when Micorchip's include file for 16c5x devices is used. 0.8.14 TSD Yet another patch from Craig Franklin that improves gpasm error handling capabilities. Also, I added the 16f876 for Alex Holden. 0.8.13 ELS - Added gpasm.spec file to build RPMs under Red Hat Linux 7.0, use 'rpm -ta gpasm-0.8.13.tar.gz'. Added missing newline to gperror.h. 0.8.12 TSD Patch from Craig Franklin mailto:craigfranklin@users.sourceforge.net that implements the ERRORLEVEL directive. 0.8.11 TSD Patch from Craig Franklin mailto:craigfranklin@users.sourceforge.net to fix command line options (the -o option was missing, and the -e and -w options weren't being used). Also applied patch from Craig that implements the subtitle directive. 0.8.10 TSD added support for more than 8 files in one .cod file. 0.8.6 symbol information was not being written to the .cod file 0.8.5 added >64k file generation capability. added support for the __CONFIG address, config_bits directive (you used to couldn't specify the config address) added i_memory.c to handle the instruction memory. Previously, i_memory was a 64k, statically allocated array. Now it's a dynamically allocated linked list of 64k memory blocks. redesigned/rewrote major portions of cod.c to accomodate the greater than 64k code generation. Removed the unnecessary restriction that the miscellaneous code blocks had to be written in a specific order. Added multiple directories. Fixed the code range information (this specifies where there's valid code). 0.8.1 - 0.8.4 minor enhancements 0.8.0 - added a few more processors - the HIGH directive was always returning 0 - __CONFIG directive now supports an optional address - added support for >64k address space (this allows the 18cxxx config word to be handled properly, but at the same time the change is general enough to accomodate code generation at addresses above 64k - a feature gpsim will soon need). - Switched the Makefile to a more standard automake style. - Changed the number notation so that what was the micro version is now the minor version. Development releases will bump the micro version. (This means gpasm-0.0.8 is now expressed as gpasm-0.8.0). - renamed gpasm.y to parse.y so that the automake tools would be happy. - Enhanced the error message system. 0.0.8 Added SET opcode Supports '=' syntax for SET Added WHILE/WEND Added ERROR Added 'generic' processor type; needed for AVR support Support for .cod files added - added cod.c and cod.h - several small changes scattered through out all of the source some of the more significant changes: o modified the state structure to accomodate symbol files o gpasmVal now has typing information o cblock defined constant are given register typing o program labels are given typing info Added a few more pic processors __config now will display the config address and config value in the .lst file dt macro didn't ignore upper 8 bits of a literal added new macros: db byte packed data table dw same as data macro de like dw but upper nibble is zeroed Added support for the 18cxxx instruction set. Added the '-l' (dash ell) option for showing the list of supported processors 0.0.7 Tab-stops now expanded to spaces in listing, LIST b=NN supported Scenix processors added Changed sys_errlist[] to strerror() Manual update 0.0.6 Build using autoconf 0.0.5 Fixed bug where we always processed equ statements, even inside conditional assembly blocks. 0.0.4 Second invocation of macro actually runs the macro twice, so local forward definitions get resolved correctly. This means that macro bodies get 3 passes made on them. Far from pretty, but it does the job. See execute_macro(), and new function execute_body(). Restore cblock value to 0 at start of 2nd pass. Accept CBLOCK headers without an expression: continues at previous CBLOCK value. See gpasm.y. Accept CBLOCK values as labels, with or without an expression. See gpasm.y. Do #define substitution. Done in the lexical analyser, using the same stack that we use for include files. Still no support for parameters in #define. See scan.l. Evaluate '$' late, instead of at parse time. Missing parameter to bit operations was giving coredump instead of error message. Makefile now builds with "gcc -Wall --pedantic", had a general cleanup following this. Small fix to lexical analyser to make it cope with MSDOS '\r' characters. gputils-0.13.7/config.guess0000755000175000017500000012450411156313233012536 00000000000000#! /bin/sh # Attempt to guess a canonical system name. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. timestamp='2004-09-07' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Per Bothner . # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # This script attempts to guess a canonical system name similar to # config.sub. If it succeeds, it prints the system name on stdout, and # exits with 0. Otherwise, it exits with 1. # # The plan is that this can be called by configure scripts if you # don't specify an explicit build system type. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] Output the configuration name of the system \`$me' is run on. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.guess ($timestamp) Originally written by Per Bothner. Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit 0 ;; --version | -v ) echo "$version" ; exit 0 ;; --help | --h* | -h ) echo "$usage"; exit 0 ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" >&2 exit 1 ;; * ) break ;; esac done if test $# != 0; then echo "$me: too many arguments$help" >&2 exit 1 fi trap 'exit 1' 1 2 15 # CC_FOR_BUILD -- compiler used by this script. Note that the use of a # compiler to aid in system detection is discouraged as it requires # temporary files to be created and, as you can see below, it is a # headache to deal with in a portable fashion. # Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still # use `HOST_CC' if defined, but it is deprecated. # Portable tmp directory creation inspired by the Autoconf team. set_cc_for_build=' trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ; trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ; : ${TMPDIR=/tmp} ; { tmp=`(umask 077 && mktemp -d -q "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } || { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } || { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } || { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ; dummy=$tmp/dummy ; tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ; case $CC_FOR_BUILD,$HOST_CC,$CC in ,,) echo "int x;" > $dummy.c ; for c in cc gcc c89 c99 ; do if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then CC_FOR_BUILD="$c"; break ; fi ; done ; if test x"$CC_FOR_BUILD" = x ; then CC_FOR_BUILD=no_compiler_found ; fi ;; ,,*) CC_FOR_BUILD=$CC ;; ,*,*) CC_FOR_BUILD=$HOST_CC ;; esac ;' # This is needed to find uname on a Pyramid OSx when run in the BSD universe. # (ghazi@noc.rutgers.edu 1994-08-24) if (test -f /.attbin/uname) >/dev/null 2>&1 ; then PATH=$PATH:/.attbin ; export PATH fi UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown # Note: order is significant - the case branches are not exclusive. case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in *:NetBSD:*:*) # NetBSD (nbsd) targets should (where applicable) match one or # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently # switched to ELF, *-*-netbsd* would select the old # object file format. This provides both forward # compatibility and a consistent mechanism for selecting the # object file format. # # Note: NetBSD doesn't particularly care about the vendor # portion of the name. We always set it to "unknown". sysctl="sysctl -n hw.machine_arch" UNAME_MACHINE_ARCH=`(/sbin/$sysctl 2>/dev/null || \ /usr/sbin/$sysctl 2>/dev/null || echo unknown)` case "${UNAME_MACHINE_ARCH}" in armeb) machine=armeb-unknown ;; arm*) machine=arm-unknown ;; sh3el) machine=shl-unknown ;; sh3eb) machine=sh-unknown ;; *) machine=${UNAME_MACHINE_ARCH}-unknown ;; esac # The Operating System including object format, if it has switched # to ELF recently, or will in the future. case "${UNAME_MACHINE_ARCH}" in arm*|i386|m68k|ns32k|sh3*|sparc|vax) eval $set_cc_for_build if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep __ELF__ >/dev/null then # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). # Return netbsd for either. FIX? os=netbsd else os=netbsdelf fi ;; *) os=netbsd ;; esac # The OS release # Debian GNU/NetBSD machines have a different userland, and # thus, need a distinct triplet. However, they do not need # kernel version information, so it can be replaced with a # suitable tag, in the style of linux-gnu. case "${UNAME_VERSION}" in Debian*) release='-gnu' ;; *) release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` ;; esac # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: # contains redundant information, the shorter form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. echo "${machine}-${os}${release}" exit 0 ;; amd64:OpenBSD:*:*) echo x86_64-unknown-openbsd${UNAME_RELEASE} exit 0 ;; amiga:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; cats:OpenBSD:*:*) echo arm-unknown-openbsd${UNAME_RELEASE} exit 0 ;; hp300:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; luna88k:OpenBSD:*:*) echo m88k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mac68k:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; macppc:OpenBSD:*:*) echo powerpc-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mvme68k:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mvme88k:OpenBSD:*:*) echo m88k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; mvmeppc:OpenBSD:*:*) echo powerpc-unknown-openbsd${UNAME_RELEASE} exit 0 ;; sgi:OpenBSD:*:*) echo mips64-unknown-openbsd${UNAME_RELEASE} exit 0 ;; sun3:OpenBSD:*:*) echo m68k-unknown-openbsd${UNAME_RELEASE} exit 0 ;; *:OpenBSD:*:*) echo ${UNAME_MACHINE}-unknown-openbsd${UNAME_RELEASE} exit 0 ;; *:ekkoBSD:*:*) echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} exit 0 ;; macppc:MirBSD:*:*) echo powerppc-unknown-mirbsd${UNAME_RELEASE} exit 0 ;; *:MirBSD:*:*) echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} exit 0 ;; alpha:OSF1:*:*) case $UNAME_RELEASE in *4.0) UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` ;; *5.*) UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` ;; esac # According to Compaq, /usr/sbin/psrinfo has been available on # OSF/1 and Tru64 systems produced since 1995. I hope that # covers most systems running today. This code pipes the CPU # types through head -n 1, so we only detect the type of CPU 0. ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` case "$ALPHA_CPU_TYPE" in "EV4 (21064)") UNAME_MACHINE="alpha" ;; "EV4.5 (21064)") UNAME_MACHINE="alpha" ;; "LCA4 (21066/21068)") UNAME_MACHINE="alpha" ;; "EV5 (21164)") UNAME_MACHINE="alphaev5" ;; "EV5.6 (21164A)") UNAME_MACHINE="alphaev56" ;; "EV5.6 (21164PC)") UNAME_MACHINE="alphapca56" ;; "EV5.7 (21164PC)") UNAME_MACHINE="alphapca57" ;; "EV6 (21264)") UNAME_MACHINE="alphaev6" ;; "EV6.7 (21264A)") UNAME_MACHINE="alphaev67" ;; "EV6.8CB (21264C)") UNAME_MACHINE="alphaev68" ;; "EV6.8AL (21264B)") UNAME_MACHINE="alphaev68" ;; "EV6.8CX (21264D)") UNAME_MACHINE="alphaev68" ;; "EV6.9A (21264/EV69A)") UNAME_MACHINE="alphaev69" ;; "EV7 (21364)") UNAME_MACHINE="alphaev7" ;; "EV7.9 (21364A)") UNAME_MACHINE="alphaev79" ;; esac # A Pn.n version is a patched version. # A Vn.n version is a released version. # A Tn.n version is a released field test version. # A Xn.n version is an unreleased experimental baselevel. # 1.2 uses "1.2" for uname -r. echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` exit 0 ;; Alpha\ *:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # Should we change UNAME_MACHINE based on the output of uname instead # of the specific Alpha model? echo alpha-pc-interix exit 0 ;; 21064:Windows_NT:50:3) echo alpha-dec-winnt3.5 exit 0 ;; Amiga*:UNIX_System_V:4.0:*) echo m68k-unknown-sysv4 exit 0;; *:[Aa]miga[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-amigaos exit 0 ;; *:[Mm]orph[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-morphos exit 0 ;; *:OS/390:*:*) echo i370-ibm-openedition exit 0 ;; *:OS400:*:*) echo powerpc-ibm-os400 exit 0 ;; arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) echo arm-acorn-riscix${UNAME_RELEASE} exit 0;; SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) echo hppa1.1-hitachi-hiuxmpp exit 0;; Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. if test "`(/bin/universe) 2>/dev/null`" = att ; then echo pyramid-pyramid-sysv3 else echo pyramid-pyramid-bsd fi exit 0 ;; NILE*:*:*:dcosx) echo pyramid-pyramid-svr4 exit 0 ;; DRS?6000:unix:4.0:6*) echo sparc-icl-nx6 exit 0 ;; DRS?6000:UNIX_SV:4.2*:7*) case `/usr/bin/uname -p` in sparc) echo sparc-icl-nx7 && exit 0 ;; esac ;; sun4H:SunOS:5.*:*) echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; i86pc:SunOS:5.*:*) echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; sun4*:SunOS:6*:*) # According to config.sub, this is the proper way to canonicalize # SunOS6. Hard to guess exactly what SunOS6 will be like, but # it's likely to be more like Solaris than SunOS4. echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; sun4*:SunOS:*:*) case "`/usr/bin/arch -k`" in Series*|S4*) UNAME_RELEASE=`uname -v` ;; esac # Japanese Language versions have a version number like `4.1.3-JL'. echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` exit 0 ;; sun3*:SunOS:*:*) echo m68k-sun-sunos${UNAME_RELEASE} exit 0 ;; sun*:*:4.2BSD:*) UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 case "`/bin/arch`" in sun3) echo m68k-sun-sunos${UNAME_RELEASE} ;; sun4) echo sparc-sun-sunos${UNAME_RELEASE} ;; esac exit 0 ;; aushp:SunOS:*:*) echo sparc-auspex-sunos${UNAME_RELEASE} exit 0 ;; # The situation for MiNT is a little confusing. The machine name # can be virtually everything (everything which is not # "atarist" or "atariste" at least should have a processor # > m68000). The system name ranges from "MiNT" over "FreeMiNT" # to the lowercase version "mint" (or "freemint"). Finally # the system name "TOS" denotes a system which is actually not # MiNT. But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit 0 ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit 0 ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit 0 ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit 0 ;; m68k:machten:*:*) echo m68k-apple-machten${UNAME_RELEASE} exit 0 ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit 0 ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit 0 ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit 0 ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit 0 ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit 0 ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c \ && $dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \ && exit 0 echo mips-mips-riscos${UNAME_RELEASE} exit 0 ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit 0 ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax exit 0 ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax exit 0 ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit 0 ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit 0 ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit 0 ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit 0 ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit 0 ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit 0 ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit 0 ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit 0 ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit 0 ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit 0 ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit 0 ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 echo rs6000-ibm-aix3.2.5 elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit 0 ;; *:AIX:*:[45]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit 0 ;; *:AIX:*:*) echo rs6000-ibm-aix exit 0 ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit 0 ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit 0 ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit 0 ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit 0 ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit 0 ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit 0 ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 esac ;; esac fi if [ "${HP_ARCH}" = "" ]; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include #include int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac if [ ${HP_ARCH} = "hppa2.0w" ] then # avoid double evaluation of $set_cc_for_build test -n "$CC_FOR_BUILD" || eval $set_cc_for_build if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E -) | grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else HP_ARCH="hppa64" fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit 0 ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit 0 ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && $dummy && exit 0 echo unknown-hitachi-hiuxwe2 exit 0 ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit 0 ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit 0 ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit 0 ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit 0 ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit 0 ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit 0 ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit 0 ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit 0 ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit 0 ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit 0 ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit 0 ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; *:UNICOS/mp:*:*) echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit 0 ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit 0 ;; 5000:UNIX_System_V:4.*:*) FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit 0 ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit 0 ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit 0 ;; *:FreeBSD:*:*) echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` exit 0 ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit 0 ;; i*:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit 0 ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit 0 ;; x86:Interix*:[34]*) echo i586-pc-interix${UNAME_RELEASE}|sed -e 's/\..*//' exit 0 ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks exit 0 ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i586-pc-interix exit 0 ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin exit 0 ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin exit 0 ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit 0 ;; *:GNU:*:*) # the GNU system echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit 0 ;; *:GNU/*:*:*) # other systems with GNU libc and userland echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu exit 0 ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit 0 ;; arm*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; cris:Linux:*:*) echo cris-axis-linux-gnu exit 0 ;; crisv32:Linux:*:*) echo crisv32-axis-linux-gnu exit 0 ;; frv:Linux:*:*) echo frv-unknown-linux-gnu exit 0 ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; m32r*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips #undef mipsel #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mipsel #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips #else CPU= #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 ;; mips64:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips64 #undef mips64el #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mips64el #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips64 #else CPU= #endif #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^CPU=` test x"${CPU}" != x && echo "${CPU}-unknown-linux-gnu" && exit 0 ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit 0 ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu exit 0 ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit 0 ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-unknown-linux-gnu ;; PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac exit 0 ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu exit 0 ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit 0 ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit 0 ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu exit 0 ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. # Set LC_ALL=C to ensure ld outputs messages in English. ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" exit 0 ;; coff-i386) echo "${UNAME_MACHINE}-pc-linux-gnucoff" exit 0 ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" exit 0 ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 LIBC=gnu # else LIBC=gnulibc1 # endif # else LIBC=gnulibc1 # endif #else #ifdef __INTEL_COMPILER LIBC=gnu #else LIBC=gnuaout #endif #endif #ifdef __dietlibc__ LIBC=dietlibc #endif EOF eval `$CC_FOR_BUILD -E $dummy.c 2>/dev/null | grep ^LIBC=` test x"${LIBC}" != x && echo "${UNAME_MACHINE}-pc-linux-${LIBC}" && exit 0 test x"${TENTATIVE}" != x && echo "${TENTATIVE}" && exit 0 ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit 0 ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit 0 ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit 0 ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit 0 ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos exit 0 ;; i*86:syllable:*:*) echo ${UNAME_MACHINE}-pc-syllable exit 0 ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit 0 ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit 0 ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit 0 ;; i*86:*:5:[78]*) case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit 0 ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit 0 ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i386. echo i386-pc-msdosdjgpp exit 0 ;; Intel:Mach:3*:*) echo i386-pc-mach3 exit 0 ;; paragon:*:*:*) echo i860-intel-osf1 exit 0 ;; i860:*:4.*:*) # i860-SVR4 if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi exit 0 ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv exit 0 ;; mc68k:UNIX:SYSTEM5:3.51m) echo m68k-convergent-sysv exit 0 ;; M680?0:D-NIX:5.3:*) echo m68k-diab-dnix exit 0 ;; M68*:*:R3V[5678]*:*) test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;; 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && echo i486-ncr-sysv4.3${OS_REL} && exit 0 /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && echo i486-ncr-sysv4 && exit 0 ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} exit 0 ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 exit 0 ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} exit 0 ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} exit 0 ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} exit 0 ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} exit 0 ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 exit 0 ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 exit 0 ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` echo ${UNAME_MACHINE}-sni-sysv4 else echo ns32k-sni-sysv fi exit 0 ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says echo i586-unisys-sysv4 exit 0 ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes . # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 exit 0 ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 exit 0 ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos exit 0 ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} exit 0 ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 exit 0 ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi exit 0 ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos exit 0 ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos exit 0 ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos exit 0 ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} exit 0 ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} exit 0 ;; SX-6:SUPER-UX:*:*) echo sx6-nec-superux${UNAME_RELEASE} exit 0 ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit 0 ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} exit 0 ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown case $UNAME_PROCESSOR in *86) UNAME_PROCESSOR=i686 ;; unknown) UNAME_PROCESSOR=powerpc ;; esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit 0 ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` if test "$UNAME_PROCESSOR" = "x86"; then UNAME_PROCESSOR=i386 UNAME_MACHINE=pc fi echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} exit 0 ;; *:QNX:*:4*) echo i386-pc-qnx exit 0 ;; NSR-?:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} exit 0 ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux exit 0 ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv exit 0 ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} exit 0 ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. if test "$cputype" = "386"; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 exit 0 ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 exit 0 ;; *:TENEX:*:*) echo pdp10-unknown-tenex exit 0 ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 exit 0 ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 exit 0 ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 exit 0 ;; *:ITS:*:*) echo pdp10-unknown-its exit 0 ;; SEI:*:*:SEIUX) echo mips-sei-seiux${UNAME_RELEASE} exit 0 ;; *:DragonFly:*:*) echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` exit 0 ;; *:*VMS:*:*) UNAME_MACHINE=`(uname -p) 2>/dev/null` case "${UNAME_MACHINE}" in A*) echo alpha-dec-vms && exit 0 ;; I*) echo ia64-dec-vms && exit 0 ;; V*) echo vax-dec-vms && exit 0 ;; esac esac #echo '(No uname command or uname output not recognized.)' 1>&2 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 eval $set_cc_for_build cat >$dummy.c < # include #endif main () { #if defined (sony) #if defined (MIPSEB) /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, I don't know.... */ printf ("mips-sony-bsd\n"); exit (0); #else #include printf ("m68k-sony-newsos%s\n", #ifdef NEWSOS4 "4" #else "" #endif ); exit (0); #endif #endif #if defined (__arm) && defined (__acorn) && defined (__unix) printf ("arm-acorn-riscix"); exit (0); #endif #if defined (hp300) && !defined (hpux) printf ("m68k-hp-bsd\n"); exit (0); #endif #if defined (NeXT) #if !defined (__ARCHITECTURE__) #define __ARCHITECTURE__ "m68k" #endif int version; version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; if (version < 4) printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); else printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); exit (0); #endif #if defined (MULTIMAX) || defined (n16) #if defined (UMAXV) printf ("ns32k-encore-sysv\n"); exit (0); #else #if defined (CMU) printf ("ns32k-encore-mach\n"); exit (0); #else printf ("ns32k-encore-bsd\n"); exit (0); #endif #endif #endif #if defined (__386BSD__) printf ("i386-pc-bsd\n"); exit (0); #endif #if defined (sequent) #if defined (i386) printf ("i386-sequent-dynix\n"); exit (0); #endif #if defined (ns32000) printf ("ns32k-sequent-dynix\n"); exit (0); #endif #endif #if defined (_SEQUENT_) struct utsname un; uname(&un); if (strncmp(un.version, "V2", 2) == 0) { printf ("i386-sequent-ptx2\n"); exit (0); } if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ printf ("i386-sequent-ptx1\n"); exit (0); } printf ("i386-sequent-ptx\n"); exit (0); #endif #if defined (vax) # if !defined (ultrix) # include # if defined (BSD) # if BSD == 43 printf ("vax-dec-bsd4.3\n"); exit (0); # else # if BSD == 199006 printf ("vax-dec-bsd4.3reno\n"); exit (0); # else printf ("vax-dec-bsd\n"); exit (0); # endif # endif # else printf ("vax-dec-bsd\n"); exit (0); # endif # else printf ("vax-dec-ultrix\n"); exit (0); # endif #endif #if defined (alliant) && defined (i860) printf ("i860-alliant-bsd\n"); exit (0); #endif exit (1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && $dummy && exit 0 # Apollos put the system type in the environment. test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; } # Convex versions that predate uname can use getsysinfo(1) if [ -x /usr/convex/getsysinfo ] then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd exit 0 ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit 0 ;; c34*) echo c34-convex-bsd exit 0 ;; c38*) echo c38-convex-bsd exit 0 ;; c4*) echo c4-convex-bsd exit 0 ;; esac fi cat >&2 < in order to provide the needed information to handle your system. config.guess timestamp = $timestamp uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` /bin/uname -X = `(/bin/uname -X) 2>/dev/null` hostinfo = `(hostinfo) 2>/dev/null` /bin/universe = `(/bin/universe) 2>/dev/null` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` /bin/arch = `(/bin/arch) 2>/dev/null` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` UNAME_MACHINE = ${UNAME_MACHINE} UNAME_RELEASE = ${UNAME_RELEASE} UNAME_SYSTEM = ${UNAME_SYSTEM} UNAME_VERSION = ${UNAME_VERSION} EOF exit 1 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: gputils-0.13.7/libiberty/0000777000175000017500000000000011156521335012265 500000000000000gputils-0.13.7/libiberty/getopt.c0000644000175000017500000007270611156313066013663 00000000000000/* Getopt for GNU. NOTE: getopt is now part of the C library, so if you don't know what "Keep this file name-space clean" means, talk to drepper@gnu.org before changing it! Copyright (C) 1987, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98 Free Software Foundation, Inc. NOTE: This source is derived from an old version taken from the GNU C Library (glibc). This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* This tells Alpha OSF/1 not to define a getopt prototype in . Ditto for AIX 3.2 and . */ #ifndef _NO_PROTO # define _NO_PROTO #endif #ifdef HAVE_CONFIG_H # include #endif #if !defined __STDC__ || !__STDC__ /* This is a separate conditional since some stdc systems reject `defined (const)'. */ # ifndef const # define const # endif #endif #include /* Comment out all this code if we are using the GNU C Library, and are not actually compiling the library itself. This code is part of the GNU C Library, but also included in many other GNU distributions. Compiling and linking in this code is a waste when using the GNU C library (especially if it is a shared library). Rather than having every GNU program understand `configure --with-gnu-libc' and omit the object files, it is simpler to just do this in the source for each such file. */ #define GETOPT_INTERFACE_VERSION 2 #if !defined _LIBC && defined __GLIBC__ && __GLIBC__ >= 2 # include # if _GNU_GETOPT_INTERFACE_VERSION == GETOPT_INTERFACE_VERSION # define ELIDE_CODE # endif #endif #ifndef ELIDE_CODE /* This needs to come after some library #include to get __GNU_LIBRARY__ defined. */ #ifdef __GNU_LIBRARY__ /* Don't include stdlib.h for non-GNU C libraries because some of them contain conflicting prototypes for getopt. */ # include # include #endif /* GNU C library. */ #ifdef VMS # include # if HAVE_STRING_H - 0 # include # endif #endif #ifndef _ /* This is for other GNU distributions with internationalized messages. When compiling libc, the _ macro is predefined. */ # if (HAVE_LIBINTL_H && ENABLE_NLS) || defined _LIBC # include # define _(msgid) gettext (msgid) # else # define _(msgid) (msgid) # endif #endif /* This version of `getopt' appears to the caller like standard Unix `getopt' but it behaves differently for the user, since it allows the user to intersperse the options with the other arguments. As `getopt' works, it permutes the elements of ARGV so that, when it is done, all the options precede everything else. Thus all application programs are extended to handle flexible argument order. Setting the environment variable POSIXLY_CORRECT disables permutation. Then the behavior is completely standard. GNU application programs can use a third alternative mode in which they can distinguish the relative order of options and other arguments. */ #include "getopt.h" /* For communication from `getopt' to the caller. When `getopt' finds an option that takes an argument, the argument value is returned here. Also, when `ordering' is RETURN_IN_ORDER, each non-option ARGV-element is returned here. */ char *optarg = NULL; /* Index in ARGV of the next element to be scanned. This is used for communication to and from the caller and for communication between successive calls to `getopt'. On entry to `getopt', zero means this is the first call; initialize. When `getopt' returns -1, this is the index of the first of the non-option elements that the caller should itself scan. Otherwise, `optind' communicates from one call to the next how much of ARGV has been scanned so far. */ /* 1003.2 says this must be 1 before any call. */ int optind = 1; /* Formerly, initialization of getopt depended on optind==0, which causes problems with re-calling getopt as programs generally don't know that. */ int __getopt_initialized = 0; /* The next char to be scanned in the option-element in which the last option character we returned was found. This allows us to pick up the scan where we left off. If this is zero, or a null string, it means resume the scan by advancing to the next ARGV-element. */ static char *nextchar; /* Callers store zero here to inhibit the error message for unrecognized options. */ int opterr = 1; /* Set to an option character which was unrecognized. This must be initialized on some systems to avoid linking in the system's own getopt implementation. */ int optopt = '?'; /* Describe how to deal with options that follow non-option ARGV-elements. If the caller did not specify anything, the default is REQUIRE_ORDER if the environment variable POSIXLY_CORRECT is defined, PERMUTE otherwise. REQUIRE_ORDER means don't recognize them as options; stop option processing when the first non-option is seen. This is what Unix does. This mode of operation is selected by either setting the environment variable POSIXLY_CORRECT, or using `+' as the first character of the list of option characters. PERMUTE is the default. We permute the contents of ARGV as we scan, so that eventually all the non-options are at the end. This allows options to be given in any order, even with programs that were not written to expect this. RETURN_IN_ORDER is an option available to programs that were written to expect options and other ARGV-elements in any order and that care about the ordering of the two. We describe each non-option ARGV-element as if it were the argument of an option with character code 1. Using `-' as the first character of the list of option characters selects this mode of operation. The special argument `--' forces an end of option-scanning regardless of the value of `ordering'. In the case of RETURN_IN_ORDER, only `--' can cause `getopt' to return -1 with `optind' != ARGC. */ static enum { REQUIRE_ORDER, PERMUTE, RETURN_IN_ORDER } ordering; /* Value of POSIXLY_CORRECT environment variable. */ static char *posixly_correct; #ifdef __GNU_LIBRARY__ /* We want to avoid inclusion of string.h with non-GNU libraries because there are many ways it can cause trouble. On some systems, it contains special magic macros that don't work in GCC. */ # include # define my_index strchr #else # if HAVE_STRING_H # include # else # if HAVE_STRINGS_H # include # endif # endif /* Avoid depending on library functions or files whose names are inconsistent. */ #ifndef getenv extern char *getenv (); #endif static char * my_index (str, chr) const char *str; int chr; { while (*str) { if (*str == chr) return (char *) str; str++; } return 0; } /* If using GCC, we can safely declare strlen this way. If not using GCC, it is ok not to declare it. */ #ifdef __GNUC__ /* Note that Motorola Delta 68k R3V7 comes with GCC but not stddef.h. That was relevant to code that was here before. */ # if (!defined __STDC__ || !__STDC__) && !defined strlen /* gcc with -traditional declares the built-in strlen to return int, and has done so at least since version 2.4.5. -- rms. */ extern int strlen (const char *); # endif /* not __STDC__ */ #endif /* __GNUC__ */ #endif /* not __GNU_LIBRARY__ */ /* Handle permutation of arguments. */ /* Describe the part of ARGV that contains non-options that have been skipped. `first_nonopt' is the index in ARGV of the first of them; `last_nonopt' is the index after the last of them. */ static int first_nonopt; static int last_nonopt; #ifdef _LIBC /* Bash 2.0 gives us an environment variable containing flags indicating ARGV elements that should not be considered arguments. */ /* Defined in getopt_init.c */ extern char *__getopt_nonoption_flags; static int nonoption_flags_max_len; static int nonoption_flags_len; static int original_argc; static char *const *original_argv; /* Make sure the environment variable bash 2.0 puts in the environment is valid for the getopt call we must make sure that the ARGV passed to getopt is that one passed to the process. */ static void __attribute__ ((unused)) store_args_and_env (int argc, char *const *argv) { /* XXX This is no good solution. We should rather copy the args so that we can compare them later. But we must not use malloc(3). */ original_argc = argc; original_argv = argv; } # ifdef text_set_element text_set_element (__libc_subinit, store_args_and_env); # endif /* text_set_element */ # define SWAP_FLAGS(ch1, ch2) \ if (nonoption_flags_len > 0) \ { \ char __tmp = __getopt_nonoption_flags[ch1]; \ __getopt_nonoption_flags[ch1] = __getopt_nonoption_flags[ch2]; \ __getopt_nonoption_flags[ch2] = __tmp; \ } #else /* !_LIBC */ # define SWAP_FLAGS(ch1, ch2) #endif /* _LIBC */ /* Exchange two adjacent subsequences of ARGV. One subsequence is elements [first_nonopt,last_nonopt) which contains all the non-options that have been skipped so far. The other is elements [last_nonopt,optind), which contains all the options processed since those non-options were skipped. `first_nonopt' and `last_nonopt' are relocated so that they describe the new indices of the non-options in ARGV after they are moved. */ #if defined __STDC__ && __STDC__ static void exchange (char **); #endif static void exchange (argv) char **argv; { int bottom = first_nonopt; int middle = last_nonopt; int top = optind; char *tem; /* Exchange the shorter segment with the far end of the longer segment. That puts the shorter segment into the right place. It leaves the longer segment in the right place overall, but it consists of two parts that need to be swapped next. */ #ifdef _LIBC /* First make sure the handling of the `__getopt_nonoption_flags' string can work normally. Our top argument must be in the range of the string. */ if (nonoption_flags_len > 0 && top >= nonoption_flags_max_len) { /* We must extend the array. The user plays games with us and presents new arguments. */ char *new_str = malloc (top + 1); if (new_str == NULL) nonoption_flags_len = nonoption_flags_max_len = 0; else { memset (mempcpy (new_str, __getopt_nonoption_flags, nonoption_flags_max_len), '\0', top + 1 - nonoption_flags_max_len); nonoption_flags_max_len = top + 1; __getopt_nonoption_flags = new_str; } } #endif while (top > middle && middle > bottom) { if (top - middle > middle - bottom) { /* Bottom segment is the short one. */ int len = middle - bottom; register int i; /* Swap it with the top part of the top segment. */ for (i = 0; i < len; i++) { tem = argv[bottom + i]; argv[bottom + i] = argv[top - (middle - bottom) + i]; argv[top - (middle - bottom) + i] = tem; SWAP_FLAGS (bottom + i, top - (middle - bottom) + i); } /* Exclude the moved bottom segment from further swapping. */ top -= len; } else { /* Top segment is the short one. */ int len = top - middle; register int i; /* Swap it with the bottom part of the bottom segment. */ for (i = 0; i < len; i++) { tem = argv[bottom + i]; argv[bottom + i] = argv[middle + i]; argv[middle + i] = tem; SWAP_FLAGS (bottom + i, middle + i); } /* Exclude the moved top segment from further swapping. */ bottom += len; } } /* Update records for the slots the non-options now occupy. */ first_nonopt += (optind - last_nonopt); last_nonopt = optind; } /* Initialize the internal data when the first call is made. */ #if defined __STDC__ && __STDC__ static const char *_getopt_initialize (int, char *const *, const char *); #endif static const char * _getopt_initialize (argc, argv, optstring) int argc; char *const *argv; const char *optstring; { /* Start processing options with ARGV-element 1 (since ARGV-element 0 is the program name); the sequence of previously skipped non-option ARGV-elements is empty. */ first_nonopt = last_nonopt = optind; nextchar = NULL; posixly_correct = getenv ("POSIXLY_CORRECT"); /* Determine how to handle the ordering of options and nonoptions. */ if (optstring[0] == '-') { ordering = RETURN_IN_ORDER; ++optstring; } else if (optstring[0] == '+') { ordering = REQUIRE_ORDER; ++optstring; } else if (posixly_correct != NULL) ordering = REQUIRE_ORDER; else ordering = PERMUTE; #ifdef _LIBC if (posixly_correct == NULL && argc == original_argc && argv == original_argv) { if (nonoption_flags_max_len == 0) { if (__getopt_nonoption_flags == NULL || __getopt_nonoption_flags[0] == '\0') nonoption_flags_max_len = -1; else { const char *orig_str = __getopt_nonoption_flags; int len = nonoption_flags_max_len = strlen (orig_str); if (nonoption_flags_max_len < argc) nonoption_flags_max_len = argc; __getopt_nonoption_flags = (char *) malloc (nonoption_flags_max_len); if (__getopt_nonoption_flags == NULL) nonoption_flags_max_len = -1; else memset (mempcpy (__getopt_nonoption_flags, orig_str, len), '\0', nonoption_flags_max_len - len); } } nonoption_flags_len = nonoption_flags_max_len; } else nonoption_flags_len = 0; #endif return optstring; } /* Scan elements of ARGV (whose length is ARGC) for option characters given in OPTSTRING. If an element of ARGV starts with '-', and is not exactly "-" or "--", then it is an option element. The characters of this element (aside from the initial '-') are option characters. If `getopt' is called repeatedly, it returns successively each of the option characters from each of the option elements. If `getopt' finds another option character, it returns that character, updating `optind' and `nextchar' so that the next call to `getopt' can resume the scan with the following option character or ARGV-element. If there are no more option characters, `getopt' returns -1. Then `optind' is the index in ARGV of the first ARGV-element that is not an option. (The ARGV-elements have been permuted so that those that are not options now come last.) OPTSTRING is a string containing the legitimate option characters. If an option character is seen that is not listed in OPTSTRING, return '?' after printing an error message. If you set `opterr' to zero, the error message is suppressed but we still return '?'. If a char in OPTSTRING is followed by a colon, that means it wants an arg, so the following text in the same ARGV-element, or the text of the following ARGV-element, is returned in `optarg'. Two colons mean an option that wants an optional arg; if there is text in the current ARGV-element, it is returned in `optarg', otherwise `optarg' is set to zero. If OPTSTRING starts with `-' or `+', it requests different methods of handling the non-option ARGV-elements. See the comments about RETURN_IN_ORDER and REQUIRE_ORDER, above. Long-named options begin with `--' instead of `-'. Their names may be abbreviated as long as the abbreviation is unique or is an exact match for some defined option. If they have an argument, it follows the option name in the same ARGV-element, separated from the option name by a `=', or else the in next ARGV-element. When `getopt' finds a long-named option, it returns 0 if that option's `flag' field is nonzero, the value of the option's `val' field if the `flag' field is zero. The elements of ARGV aren't really const, because we permute them. But we pretend they're const in the prototype to be compatible with other systems. LONGOPTS is a vector of `struct option' terminated by an element containing a name which is zero. LONGIND returns the index in LONGOPT of the long-named option found. It is only valid when a long-named option has been found by the most recent call. If LONG_ONLY is nonzero, '-' as well as '--' can introduce long-named options. */ int _getopt_internal (argc, argv, optstring, longopts, longind, long_only) int argc; char *const *argv; const char *optstring; const struct option *longopts; int *longind; int long_only; { optarg = NULL; if (optind == 0 || !__getopt_initialized) { if (optind == 0) optind = 1; /* Don't scan ARGV[0], the program name. */ optstring = _getopt_initialize (argc, argv, optstring); __getopt_initialized = 1; } /* Test whether ARGV[optind] points to a non-option argument. Either it does not have option syntax, or there is an environment flag from the shell indicating it is not an option. The later information is only used when the used in the GNU libc. */ #ifdef _LIBC # define NONOPTION_P (argv[optind][0] != '-' || argv[optind][1] == '\0' \ || (optind < nonoption_flags_len \ && __getopt_nonoption_flags[optind] == '1')) #else # define NONOPTION_P (argv[optind][0] != '-' || argv[optind][1] == '\0') #endif if (nextchar == NULL || *nextchar == '\0') { /* Advance to the next ARGV-element. */ /* Give FIRST_NONOPT & LAST_NONOPT rational values if OPTIND has been moved back by the user (who may also have changed the arguments). */ if (last_nonopt > optind) last_nonopt = optind; if (first_nonopt > optind) first_nonopt = optind; if (ordering == PERMUTE) { /* If we have just processed some options following some non-options, exchange them so that the options come first. */ if (first_nonopt != last_nonopt && last_nonopt != optind) exchange ((char **) argv); else if (last_nonopt != optind) first_nonopt = optind; /* Skip any additional non-options and extend the range of non-options previously skipped. */ while (optind < argc && NONOPTION_P) optind++; last_nonopt = optind; } /* The special ARGV-element `--' means premature end of options. Skip it like a null option, then exchange with previous non-options as if it were an option, then skip everything else like a non-option. */ if (optind != argc && !strcmp (argv[optind], "--")) { optind++; if (first_nonopt != last_nonopt && last_nonopt != optind) exchange ((char **) argv); else if (first_nonopt == last_nonopt) first_nonopt = optind; last_nonopt = argc; optind = argc; } /* If we have done all the ARGV-elements, stop the scan and back over any non-options that we skipped and permuted. */ if (optind == argc) { /* Set the next-arg-index to point at the non-options that we previously skipped, so the caller will digest them. */ if (first_nonopt != last_nonopt) optind = first_nonopt; return -1; } /* If we have come to a non-option and did not permute it, either stop the scan or describe it to the caller and pass it by. */ if (NONOPTION_P) { if (ordering == REQUIRE_ORDER) return -1; optarg = argv[optind++]; return 1; } /* We have found another option-ARGV-element. Skip the initial punctuation. */ nextchar = (argv[optind] + 1 + (longopts != NULL && argv[optind][1] == '-')); } /* Decode the current option-ARGV-element. */ /* Check whether the ARGV-element is a long option. If long_only and the ARGV-element has the form "-f", where f is a valid short option, don't consider it an abbreviated form of a long option that starts with f. Otherwise there would be no way to give the -f short option. On the other hand, if there's a long option "fubar" and the ARGV-element is "-fu", do consider that an abbreviation of the long option, just like "--fu", and not "-f" with arg "u". This distinction seems to be the most useful approach. */ if (longopts != NULL && (argv[optind][1] == '-' || (long_only && (argv[optind][2] || !my_index (optstring, argv[optind][1]))))) { char *nameend; const struct option *p; const struct option *pfound = NULL; int exact = 0; int ambig = 0; int indfound = -1; int option_index; for (nameend = nextchar; *nameend && *nameend != '='; nameend++) /* Do nothing. */ ; /* Test all long options for either exact match or abbreviated matches. */ for (p = longopts, option_index = 0; p->name; p++, option_index++) if (!strncmp (p->name, nextchar, nameend - nextchar)) { if ((unsigned int) (nameend - nextchar) == (unsigned int) strlen (p->name)) { /* Exact match found. */ pfound = p; indfound = option_index; exact = 1; break; } else if (pfound == NULL) { /* First nonexact match found. */ pfound = p; indfound = option_index; } else /* Second or later nonexact match found. */ ambig = 1; } if (ambig && !exact) { if (opterr) fprintf (stderr, _("%s: option `%s' is ambiguous\n"), argv[0], argv[optind]); nextchar += strlen (nextchar); optind++; optopt = 0; return '?'; } if (pfound != NULL) { option_index = indfound; optind++; if (*nameend) { /* Don't test has_arg with >, because some C compilers don't allow it to be used on enums. */ if (pfound->has_arg) optarg = nameend + 1; else { if (opterr) { if (argv[optind - 1][1] == '-') /* --option */ fprintf (stderr, _("%s: option `--%s' doesn't allow an argument\n"), argv[0], pfound->name); else /* +option or -option */ fprintf (stderr, _("%s: option `%c%s' doesn't allow an argument\n"), argv[0], argv[optind - 1][0], pfound->name); nextchar += strlen (nextchar); optopt = pfound->val; return '?'; } } } else if (pfound->has_arg == 1) { if (optind < argc) optarg = argv[optind++]; else { if (opterr) fprintf (stderr, _("%s: option `%s' requires an argument\n"), argv[0], argv[optind - 1]); nextchar += strlen (nextchar); optopt = pfound->val; return optstring[0] == ':' ? ':' : '?'; } } nextchar += strlen (nextchar); if (longind != NULL) *longind = option_index; if (pfound->flag) { *(pfound->flag) = pfound->val; return 0; } return pfound->val; } /* Can't find it as a long option. If this is not getopt_long_only, or the option starts with '--' or is not a valid short option, then it's an error. Otherwise interpret it as a short option. */ if (!long_only || argv[optind][1] == '-' || my_index (optstring, *nextchar) == NULL) { if (opterr) { if (argv[optind][1] == '-') /* --option */ fprintf (stderr, _("%s: unrecognized option `--%s'\n"), argv[0], nextchar); else /* +option or -option */ fprintf (stderr, _("%s: unrecognized option `%c%s'\n"), argv[0], argv[optind][0], nextchar); } nextchar = (char *) ""; optind++; optopt = 0; return '?'; } } /* Look at and handle the next short option-character. */ { char c = *nextchar++; char *temp = my_index (optstring, c); /* Increment `optind' when we start to process its last character. */ if (*nextchar == '\0') ++optind; if (temp == NULL || c == ':') { if (opterr) { if (posixly_correct) /* 1003.2 specifies the format of this message. */ fprintf (stderr, _("%s: illegal option -- %c\n"), argv[0], c); else fprintf (stderr, _("%s: invalid option -- %c\n"), argv[0], c); } optopt = c; return '?'; } /* Convenience. Treat POSIX -W foo same as long option --foo */ if (temp[0] == 'W' && temp[1] == ';') { char *nameend; const struct option *p; const struct option *pfound = NULL; int exact = 0; int ambig = 0; int indfound = 0; int option_index; /* This is an option that requires an argument. */ if (*nextchar != '\0') { optarg = nextchar; /* If we end this ARGV-element by taking the rest as an arg, we must advance to the next element now. */ optind++; } else if (optind == argc) { if (opterr) { /* 1003.2 specifies the format of this message. */ fprintf (stderr, _("%s: option requires an argument -- %c\n"), argv[0], c); } optopt = c; if (optstring[0] == ':') c = ':'; else c = '?'; return c; } else /* We already incremented `optind' once; increment it again when taking next ARGV-elt as argument. */ optarg = argv[optind++]; /* optarg is now the argument, see if it's in the table of longopts. */ for (nextchar = nameend = optarg; *nameend && *nameend != '='; nameend++) /* Do nothing. */ ; /* Test all long options for either exact match or abbreviated matches. */ for (p = longopts, option_index = 0; p->name; p++, option_index++) if (!strncmp (p->name, nextchar, nameend - nextchar)) { if ((unsigned int) (nameend - nextchar) == strlen (p->name)) { /* Exact match found. */ pfound = p; indfound = option_index; exact = 1; break; } else if (pfound == NULL) { /* First nonexact match found. */ pfound = p; indfound = option_index; } else /* Second or later nonexact match found. */ ambig = 1; } if (ambig && !exact) { if (opterr) fprintf (stderr, _("%s: option `-W %s' is ambiguous\n"), argv[0], argv[optind]); nextchar += strlen (nextchar); optind++; return '?'; } if (pfound != NULL) { option_index = indfound; if (*nameend) { /* Don't test has_arg with >, because some C compilers don't allow it to be used on enums. */ if (pfound->has_arg) optarg = nameend + 1; else { if (opterr) fprintf (stderr, _("\ %s: option `-W %s' doesn't allow an argument\n"), argv[0], pfound->name); nextchar += strlen (nextchar); return '?'; } } else if (pfound->has_arg == 1) { if (optind < argc) optarg = argv[optind++]; else { if (opterr) fprintf (stderr, _("%s: option `%s' requires an argument\n"), argv[0], argv[optind - 1]); nextchar += strlen (nextchar); return optstring[0] == ':' ? ':' : '?'; } } nextchar += strlen (nextchar); if (longind != NULL) *longind = option_index; if (pfound->flag) { *(pfound->flag) = pfound->val; return 0; } return pfound->val; } nextchar = NULL; return 'W'; /* Let the application handle it. */ } if (temp[1] == ':') { if (temp[2] == ':') { /* This is an option that accepts an argument optionally. */ if (*nextchar != '\0') { optarg = nextchar; optind++; } else optarg = NULL; nextchar = NULL; } else { /* This is an option that requires an argument. */ if (*nextchar != '\0') { optarg = nextchar; /* If we end this ARGV-element by taking the rest as an arg, we must advance to the next element now. */ optind++; } else if (optind == argc) { if (opterr) { /* 1003.2 specifies the format of this message. */ fprintf (stderr, _("%s: option requires an argument -- %c\n"), argv[0], c); } optopt = c; if (optstring[0] == ':') c = ':'; else c = '?'; } else /* We already incremented `optind' once; increment it again when taking next ARGV-elt as argument. */ optarg = argv[optind++]; nextchar = NULL; } } return c; } } int getopt (argc, argv, optstring) int argc; char *const *argv; const char *optstring; { return _getopt_internal (argc, argv, optstring, (const struct option *) 0, (int *) 0, 0); } #endif /* Not ELIDE_CODE. */ #ifdef TEST /* Compile with -DTEST to make an executable for use in testing the above definition of `getopt'. */ int main (argc, argv) int argc; char **argv; { int c; int digit_optind = 0; while (1) { int this_option_optind = optind ? optind : 1; c = getopt (argc, argv, "abc:d:0123456789"); if (c == -1) break; switch (c) { case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': if (digit_optind != 0 && digit_optind != this_option_optind) printf ("digits occur in two different argv-elements.\n"); digit_optind = this_option_optind; printf ("option %c\n", c); break; case 'a': printf ("option a\n"); break; case 'b': printf ("option b\n"); break; case 'c': printf ("option c with value `%s'\n", optarg); break; case '?': break; default: printf ("?? getopt returned character code 0%o ??\n", c); } } if (optind < argc) { printf ("non-option ARGV-elements: "); while (optind < argc) printf ("%s ", argv[optind++]); printf ("\n"); } exit (0); } #endif /* TEST */ gputils-0.13.7/libiberty/vasprintf.c0000644000175000017500000001137511156313066014370 00000000000000/* Like vsprintf but provides a pointer to malloc'd storage, which must be freed by the caller. Copyright (C) 1994, 2003 Free Software Foundation, Inc. This file is part of the libiberty library. Libiberty is free software; you can redistribute it and/or modify it under the terms of the GNU Library General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. Libiberty is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Library General Public License for more details. You should have received a copy of the GNU Library General Public License along with libiberty; see the file COPYING.LIB. If not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifdef HAVE_CONFIG_H #include "config.h" #endif #include #ifdef ANSI_PROTOTYPES #include #else #include #endif #include #ifdef HAVE_STRING_H #include #endif #ifdef HAVE_STDLIB_H #include #else extern unsigned long strtoul (); extern PTR malloc (); #endif #include "libiberty.h" #ifdef TEST int global_total_width; #endif /* @deftypefn Extension int vasprintf (char **@var{resptr}, const char *@var{format}, va_list @var{args}) Like @code{vsprintf}, but instead of passing a pointer to a buffer, you pass a pointer to a pointer. This function will compute the size of the buffer needed, allocate memory with @code{malloc}, and store a pointer to the allocated memory in @code{*@var{resptr}}. The value returned is the same as @code{vsprintf} would return. If memory could not be allocated, minus one is returned and @code{NULL} is stored in @code{*@var{resptr}}. @end deftypefn */ static int int_vasprintf PARAMS ((char **, const char *, va_list)); static int int_vasprintf (result, format, args) char **result; const char *format; va_list args; { const char *p = format; /* Add one to make sure that it is never zero, which might cause malloc to return NULL. */ int total_width = strlen (format) + 1; va_list ap; #ifdef va_copy va_copy (ap, args); #else memcpy ((PTR) &ap, (PTR) &args, sizeof (va_list)); #endif while (*p != '\0') { if (*p++ == '%') { while (strchr ("-+ #0", *p)) ++p; if (*p == '*') { ++p; total_width += abs (va_arg (ap, int)); } else total_width += strtoul (p, (char **) &p, 10); if (*p == '.') { ++p; if (*p == '*') { ++p; total_width += abs (va_arg (ap, int)); } else total_width += strtoul (p, (char **) &p, 10); } while (strchr ("hlL", *p)) ++p; /* Should be big enough for any format specifier except %s and floats. */ total_width += 30; switch (*p) { case 'd': case 'i': case 'o': case 'u': case 'x': case 'X': case 'c': (void) va_arg (ap, int); break; case 'f': case 'e': case 'E': case 'g': case 'G': (void) va_arg (ap, double); /* Since an ieee double can have an exponent of 307, we'll make the buffer wide enough to cover the gross case. */ total_width += 307; break; case 's': total_width += strlen (va_arg (ap, char *)); break; case 'p': case 'n': (void) va_arg (ap, char *); break; } p++; } } #ifdef va_copy va_end (ap); #endif #ifdef TEST global_total_width = total_width; #endif *result = (char *) malloc (total_width); if (*result != NULL) return vsprintf (*result, format, args); else return -1; } int vasprintf (result, format, args) char **result; const char *format; #if defined (_BSD_VA_LIST_) && defined (__FreeBSD__) _BSD_VA_LIST_ args; #else va_list args; #endif { return int_vasprintf (result, format, args); } #ifdef TEST static void ATTRIBUTE_PRINTF_1 checkit VPARAMS ((const char *format, ...)) { char *result; VA_OPEN (args, format); VA_FIXEDARG (args, const char *, format); vasprintf (&result, format, args); VA_CLOSE (args); if (strlen (result) < (size_t) global_total_width) printf ("PASS: "); else printf ("FAIL: "); printf ("%d %s\n", global_total_width, result); free (result); } extern int main PARAMS ((void)); int main () { checkit ("%d", 0x12345678); checkit ("%200d", 5); checkit ("%.300d", 6); checkit ("%100.150d", 7); checkit ("%s", "jjjjjjjjjiiiiiiiiiiiiiiioooooooooooooooooppppppppppppaa\n\ 777777777777777777333333333333366666666666622222222222777777777777733333"); checkit ("%f%s%d%s", 1.0, "foo", 77, "asdjffffffffffffffiiiiiiiiiiixxxxx"); return 0; } #endif /* TEST */ gputils-0.13.7/libiberty/snprintf.c0000644000175000017500000000435511156313066014217 00000000000000/* Implement the snprintf function. Copyright (C) 2003 Free Software Foundation, Inc. Written by Kaveh R. Ghazi . This file is part of the libiberty library. This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. As a special exception, if you link this library with files compiled with a GNU compiler to produce an executable, this does not cause the resulting executable to be covered by the GNU General Public License. This exception does not however invalidate any other reasons why the executable file might be covered by the GNU General Public License. */ /* @deftypefn Supplemental int snprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, ...) This function is similar to sprintf, but it will print at most @var{n} characters. On error the return value is -1, otherwise it returns the number of characters that would have been printed had @var{n} been sufficiently large, regardless of the actual value of @var{n}. Note some pre-C99 system libraries do not implement this correctly so users cannot generally rely on the return value if the system version of this function is used. @end deftypefn */ #include "ansidecl.h" #ifdef ANSI_PROTOTYPES #include #include #else #include #define size_t unsigned long #endif int vsnprintf PARAMS ((char *, size_t, const char *, va_list)); int snprintf VPARAMS ((char *s, size_t n, const char *format, ...)) { int result; VA_OPEN (ap, format); VA_FIXEDARG (ap, char *, s); VA_FIXEDARG (ap, size_t, n); VA_FIXEDARG (ap, const char *, format); result = vsnprintf (s, n, format, ap); VA_CLOSE (ap); return result; } gputils-0.13.7/libiberty/README0000644000175000017500000000051411156313066013061 00000000000000This directory contains a subset of the GNU -liberty library. The intent is to provide functions that gputils needs without doubling the size of the gputils package. This directory may very well grow in the future. If it does please make every effort to conform with the content and configuration of libiberty included with gcc. gputils-0.13.7/libiberty/vsnprintf.c0000644000175000017500000001030511156313066014375 00000000000000/* Implement the vsnprintf function. Copyright (C) 2003 Free Software Foundation, Inc. Written by Kaveh R. Ghazi . This file is part of the libiberty library. This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. As a special exception, if you link this library with files compiled with a GNU compiler to produce an executable, this does not cause the resulting executable to be covered by the GNU General Public License. This exception does not however invalidate any other reasons why the executable file might be covered by the GNU General Public License. */ /* @deftypefn Supplemental int vsnprintf (char *@var{buf}, size_t @var{n}, const char *@var{format}, va_list @var{ap}) This function is similar to vsprintf, but it will print at most @var{n} characters. On error the return value is -1, otherwise it returns the number of characters that would have been printed had @var{n} been sufficiently large, regardless of the actual value of @var{n}. Note some pre-C99 system libraries do not implement this correctly so users cannot generally rely on the return value if the system version of this function is used. @end deftypefn */ #include "config.h" #include "ansidecl.h" #ifdef ANSI_PROTOTYPES #include #else #include #endif #ifdef HAVE_STRING_H #include #endif #ifdef HAVE_STDLIB_H #include #endif #include "libiberty.h" /* This implementation relies on a working vasprintf. */ int vsnprintf (s, n, format, ap) char * s; size_t n; const char *format; va_list ap; { char *buf = 0; int result = vasprintf (&buf, format, ap); if (!buf) return -1; if (result < 0) { free (buf); return -1; } result = strlen (buf); if (n > 0) { if ((long) n > result) memcpy (s, buf, result+1); else { memcpy (s, buf, n-1); s[n - 1] = 0; } } free (buf); return result; } #ifdef TEST /* Set the buffer to a known state. */ #define CLEAR(BUF) do { memset ((BUF), 'X', sizeof (BUF)); (BUF)[14] = '\0'; } while (0) /* For assertions. */ #define VERIFY(P) do { if (!(P)) abort(); } while (0) static int ATTRIBUTE_PRINTF_3 checkit VPARAMS ((char *s, size_t n, const char *format, ...)) { int result; VA_OPEN (ap, format); VA_FIXEDARG (ap, char *, s); VA_FIXEDARG (ap, size_t, n); VA_FIXEDARG (ap, const char *, format); result = vsnprintf (s, n, format, ap); VA_CLOSE (ap); return result; } extern int main PARAMS ((void)); int main () { char buf[128]; int status; CLEAR (buf); status = checkit (buf, 10, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "foobar:9\0XXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 9, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "foobar:9\0XXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 8, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "foobar:\0XXXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 7, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "foobar\0XXXXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 6, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "fooba\0XXXXXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 2, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "f\0XXXXXXXXXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 1, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "\0XXXXXXXXXXXXX\0", 15) == 0); CLEAR (buf); status = checkit (buf, 0, "%s:%d", "foobar", 9); VERIFY (status==8 && memcmp (buf, "XXXXXXXXXXXXXX\0", 15) == 0); return 0; } #endif /* TEST */ gputils-0.13.7/libiberty/bzero.c0000644000175000017500000000063211156313066013467 00000000000000/* Portable version of bzero for systems without it. This function is in the public domain. */ /* @deftypefn Supplemental void bzero (char *@var{mem}, int @var{count}) Zeros @var{count} bytes starting at @var{mem}. Use of this function is deprecated in favor of @code{memset}. @end deftypefn */ void bzero (to, count) char *to; int count; { while (count-- > 0) { *to++ = 0; } } gputils-0.13.7/libiberty/getopt1.c0000644000175000017500000001065011156313066013732 00000000000000/* getopt_long and getopt_long_only entry points for GNU getopt. Copyright (C) 1987,88,89,90,91,92,93,94,96,97,98 Free Software Foundation, Inc. NOTE: This source is derived from an old version taken from the GNU C Library (glibc). This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifdef HAVE_CONFIG_H #include #endif #include "getopt.h" #if !defined __STDC__ || !__STDC__ /* This is a separate conditional since some stdc systems reject `defined (const)'. */ #ifndef const #define const #endif #endif #include /* Comment out all this code if we are using the GNU C Library, and are not actually compiling the library itself. This code is part of the GNU C Library, but also included in many other GNU distributions. Compiling and linking in this code is a waste when using the GNU C library (especially if it is a shared library). Rather than having every GNU program understand `configure --with-gnu-libc' and omit the object files, it is simpler to just do this in the source for each such file. */ #define GETOPT_INTERFACE_VERSION 2 #if !defined _LIBC && defined __GLIBC__ && __GLIBC__ >= 2 #include #if _GNU_GETOPT_INTERFACE_VERSION == GETOPT_INTERFACE_VERSION #define ELIDE_CODE #endif #endif #ifndef ELIDE_CODE /* This needs to come after some library #include to get __GNU_LIBRARY__ defined. */ #ifdef __GNU_LIBRARY__ #include #endif #ifndef NULL #define NULL 0 #endif int getopt_long (argc, argv, options, long_options, opt_index) int argc; char *const *argv; const char *options; const struct option *long_options; int *opt_index; { return _getopt_internal (argc, argv, options, long_options, opt_index, 0); } /* Like getopt_long, but '-' as well as '--' can indicate a long option. If an option that starts with '-' (not '--') doesn't match a long option, but does match a short option, it is parsed as a short option instead. */ int getopt_long_only (argc, argv, options, long_options, opt_index) int argc; char *const *argv; const char *options; const struct option *long_options; int *opt_index; { return _getopt_internal (argc, argv, options, long_options, opt_index, 1); } #endif /* Not ELIDE_CODE. */ #ifdef TEST #include int main (argc, argv) int argc; char **argv; { int c; int digit_optind = 0; while (1) { int this_option_optind = optind ? optind : 1; int option_index = 0; static struct option long_options[] = { {"add", 1, 0, 0}, {"append", 0, 0, 0}, {"delete", 1, 0, 0}, {"verbose", 0, 0, 0}, {"create", 0, 0, 0}, {"file", 1, 0, 0}, {0, 0, 0, 0} }; c = getopt_long (argc, argv, "abc:d:0123456789", long_options, &option_index); if (c == -1) break; switch (c) { case 0: printf ("option %s", long_options[option_index].name); if (optarg) printf (" with arg %s", optarg); printf ("\n"); break; case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': if (digit_optind != 0 && digit_optind != this_option_optind) printf ("digits occur in two different argv-elements.\n"); digit_optind = this_option_optind; printf ("option %c\n", c); break; case 'a': printf ("option a\n"); break; case 'b': printf ("option b\n"); break; case 'c': printf ("option c with value `%s'\n", optarg); break; case 'd': printf ("option d with value `%s'\n", optarg); break; case '?': break; default: printf ("?? getopt returned character code 0%o ??\n", c); } } if (optind < argc) { printf ("non-option ARGV-elements: "); while (optind < argc) printf ("%s ", argv[optind++]); printf ("\n"); } exit (0); } #endif /* TEST */ gputils-0.13.7/libiberty/Makefile.am0000644000175000017500000000047511156313066014243 00000000000000## Process this file with automake to produce Makefile.in AM_CPPFLAGS = -I${top_srcdir}/include noinst_LIBRARIES = libiberty.a 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This list is in no particular order. gputils * grep the source for FIXME and fix. * Add a check for the version of flex. * Start migrating to the GNU coding style. * Prefix all visible library functions with gp_. Add _ to all others. * Switch to xmalloc and obstacks. * Use dejagnu for testing. gpasm * Implement nested while loops. * Clean up the byte verses word, data memory/program memory stuff. * Move opcode generator from /gpasm/directive.c to /libgputils/opcode.c. * Move COD file generation to library. * Add macro names to symbol table in listing file. * Undefined coff symbols are always at the end of the coff table. * Add relocations for the difference between symbols in the same section. * Allow multiple symbols with the same name in different sections of COFF asm files. * Allow expressions in .direct. Reduce to operators, numbers, and controls. gplink * Removed unnecessary page and bank switches. * Peep-like optimization. Consider using pcode from sdcc-pic14. * Partial linking. * Use extended COD file types. gpvc * Use the disassembler to decode the program memory sections. gpdasm * Generate human readable outputs. gputils-0.13.7/config.h.in0000644000175000017500000000541311156521302012234 00000000000000/* config.h.in. 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